KR102634181B1 - display device - Google Patents

Abstract

The present invention relates to a display device capable of displaying the same luminance in separate pixel areas in a heterogeneous display device having a pixel-free notch area. a substrate having a first pixel area, a second pixel area and a third pixel area that are spaced apart from each other and extend from the first pixel area, respectively, and have an area smaller than the first pixel area; first, second and third pixels provided in each of the first, second and third pixel areas; And the resistance of the lines supplying the initialization voltage (V _ini ) to the second pixels of the second pixel area and the third pixels of the third pixel area, respectively, is an initialization voltage (V ini ) to the first pixels of the first pixel area. It consists of a dummy line disposed between the second and third pixel areas that are spaced apart from each other to have the same resistance value as the lines supplying V _ini ), and is located in the middle by the notch area (B). In a structure where the wires are cut, the luminance compensation error can be solved due to the difference in the level of initialization voltage in the spaced apart areas.

Description

display device

The present invention relates to a display device, and more specifically, to a display device in which the luminance of separated pixel areas in a heterogeneous display device having a notch area is the same.

A display device includes a plurality of pixels including a display element, and each pixel has wires and a plurality of transistors connected to the wires and driving the display element. Wires may have different degrees of load depending on their length. In the final image provided by the display device, a difference in luminance may occur due to a difference in load value.

The purpose of the present invention is to provide a display device that can offset characteristic differences that may occur within the same panel.

Another object of the present invention is to provide a display device that can have uniform luminance regardless of area.

Another object of the present invention is to provide a display device that can solve the luminance deviation of a heterogeneous display device including a notch.

Another object of the present invention is to provide a display device capable of compensating for load variation in a heterogeneous display device.

To achieve this purpose, a display device according to the present invention has a first pixel area, a second pixel area and a third pixel area that are spaced apart from each other and extend from the first pixel area and have an area smaller than the first pixel area. Board; first, second and third pixels provided in each of the first, second and third pixel areas; The resistance of the line that supplies the initialization voltage (Vini) to the second pixels of the second pixel area and the third pixels of the third pixel area provides the initialization voltage (Vini) to the first pixels of the first pixel area. It is characterized by including a dummy line disposed between the second and third pixel areas spaced apart from each other to have the same resistance value as the supply line.

A detailed feature of the display device according to the present invention is that the second pixel areas spaced apart from each other have the same area.

A detailed feature of the display device according to the present invention is that the second pixel areas are spaced apart from each other with a pixel-free notch area in between where pixels are not formed.

A detailed feature of the display device according to the present invention is that the dummy line is formed along the inner edge of the pixel-free notch-shaped area.

A detailed feature of the display device according to the present invention is that the length of the initialization voltage supply lines of the first pixel area is longer than the length of the initialization voltage supply lines of the second and third pixel areas.

A detailed feature of the display device according to the present invention is that the dummy line connects the gate lines of the second and third pixel areas that are spaced apart from each other so that the dummy line has the same resistance value as the resistance value of the gate lines of the first pixel area.

A detailed feature of the display device according to the present invention is that the first, second and third pixels may include organic light emitting diodes.

A detailed feature of the display device according to the present invention is that the second pixel area and the third pixel area that are spaced apart from each other can exhibit the same luminance.

The display device according to the present invention can exhibit the following effects.

First, it is possible to resolve characteristic deviations caused by process deviations on the left and right sides of the panel.

Second, the load deviation of the heterogeneous display device can be compensated.

Third, the luminance deviation of the heterogeneous display device can be eliminated.

1 is a plan view showing a display device according to the present invention.
Figure 2 is a block diagram showing an example of pixels and a driver according to the present invention.
Figure 3 is an example diagram showing resistance components according to the initialization supply line disposed in each pixel area.
Figure 4 is an example diagram showing the luminance deviation of spaced apart pixel areas when a notch area is formed.
Figure 5 is an example diagram showing initialization supply lines arranged in each pixel area.
FIG. 6 is an enlarged illustration of portion “C” of FIG. 5.
Figure 7 is a cross-sectional view taken along line I-I' of "C1" in Figure 6.
Figure 8 is an exemplary diagram showing an arrangement area of a dummy line in a display device according to the present invention.
FIG. 9 is an enlarged example of portion “D” of FIG. 8.
Figure 10 is a cross-sectional view taken along line II-II' of "D1" in Figure 9.

Regarding the embodiments of the present invention disclosed in the text, specific structural and functional descriptions are merely illustrative for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms and are not included in the text. It should not be construed as limited to the described embodiments.

Since the present invention can be subject to various changes and can have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be referred to as a second component, and similarly, the second component may be referred to as a first component without departing from the scope of the present invention.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when a component is referred to as being “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly adjacent to" should be interpreted similarly.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprises” or “has” are intended to designate the presence of a disclosed feature, number, step, operation, component, part, or combination thereof, and are intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as indicating meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in the present application, should not be interpreted in an idealized or excessively formal sense. No.

Meanwhile, if an embodiment can be implemented differently, functions or operations specified within a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, or the blocks may be performed in reverse depending on the functions or operations involved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

1 is a plan view showing a display device according to an embodiment of the present invention. Referring to FIG. 1, a display device according to an embodiment of the present invention includes a substrate (SUB), pixels (PXL1, PXL2, PXL3; hereinafter referred to as PXL) provided on the substrate (SUB), and It is provided and includes a driver that drives the pixels (PXL), and a wiring portion (not shown) that connects the pixels (PXL) and the driver.

The substrate SUB includes a plurality of regions, at least two of which have different areas. In one example, the substrate SUB may have two regions, and the two regions may have different areas. Additionally, in one example, the substrate SUB may have three regions. In this case, all three areas may have different areas, or only two of the three areas may have different areas. In one example, the substrate SUB may have four or more regions.

In the following embodiment, for convenience of explanation, it is shown as an example that the substrate SUB includes three regions, that is, first to third regions A1, A2, and A3. The first to third areas (A1, A2, A3) each have an approximately rectangular shape, but can be formed into closed polygons, circles with curved sides, ovals, etc., straight lines and curves. It can be provided in various shapes, such as a semicircle or semiellipse including the sides.

The first to third areas A1, A2, and A3 each have pixel areas (PXA1, PXA2, PXA3; hereinafter referred to as PXA) and peripheral areas (PPA1, PPA2, and PPA3; hereinafter referred to as PPA). The pixel areas (PXA) are areas where pixels (PXL) that display images are provided. Each pixel (PXL) will be described later. The peripheral areas PPA are areas in which pixels PXL are not provided and no image is displayed. A driver for driving the pixels PXL and a portion of a wiring (not shown) connecting the pixels PXL and the driver are provided in the peripheral areas PPA. The peripheral areas (PPA) correspond to the bezel in the final display device, and the width of the bezel may be determined according to the width of the peripheral area.

Each of the first to third areas A1, A2, and A3 will be described as follows.

The first area A1 has the largest area among the first to third areas A1, A2, and A3. The first area A1 has a first pixel area PXA1 where an image is displayed and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1.

The first pixel area PXA1 is provided in a shape corresponding to the shape of the first area A1. In one embodiment of the present invention, the first pixel area (PXA1) has a first width (W1) in the first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). It may have a first length (L1).

The first peripheral area PPA1 is provided on at least one side of the first pixel area PXA1. In one embodiment of the present invention, the first peripheral area PPA1 surrounds the first pixel area PXA1, and the second area A2 and the third area A3, which will be described later, are It may be provided anywhere other than the part where it is placed. In one embodiment of the present invention, the first peripheral area PPA1 may include a horizontal portion extending in the width direction and a vertical portion extending in the longitudinal direction. The vertical portion of the first peripheral area PPA1 is provided as a pair spaced apart from each other along the width direction of the first pixel area PXA1.

The second area A2 has a smaller area than the first area A1. The second area A2 has a second pixel area PXA2 where an image is displayed and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2.

The second pixel area PXA2 is provided in a shape corresponding to the shape of the second area A2. In one embodiment of the present invention, the second pixel area PXA2 has a second width W2 that is smaller than the first width W1 of the first area A1. The second pixel area PXA2 may have a second length L2 that is smaller than the first length L1 of the first area A1. The second pixel area PXA2 protrudes from the first pixel area PXA1 and is directly connected to the first pixel area PXA1. In other words, in the second pixel area PXA2, the edge closest to the first pixel area PXA1 coincides with the edge of the first pixel area PXA1.

The second peripheral area PPA2 is provided on at least one side of the second pixel area PXA2. In one embodiment of the present invention, the second peripheral area PPA2 surrounds the second pixel area PXA2 and is connected to the first pixel area PXA1 and the second pixel area PXA2. Parts may not be provided. In one embodiment of the present invention, the second peripheral area PPA2 may also include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. The vertical portion of the second peripheral area PPA2 may be provided as a pair spaced apart from each other along the width direction of the second pixel area PXA2.

The third area A3 has a smaller area than the first area A1. The third area A3 may have the same area or a different area from the second area A2. The third area A3 has a third pixel area PXA3 where an image is displayed and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3.

The third pixel area PXA3 is provided in a shape corresponding to the shape of the third area A3. In one embodiment of the present invention, the third pixel area PXA3 has a third width W3 that is smaller than the first width W1 of the first area A1. The third pixel area PXA3 may have a third length L3 that is smaller than the first length L1 of the first area A1. The second width W2 and the third width W3 may be equal to each other, and the second length L2 and the third length L3 may be equal to each other. Additionally, the second width W2 and the third width W3 may be different from each other, and the second length L2 and the third length L3 may be different from each other.

The third pixel area PXA3 protrudes from the first pixel area PXA1 and is directly connected to the first pixel area PXA1. In other words, in the third pixel area PXA3, the edge closest to the third pixel area PXA3 coincides with the edge of the first pixel area PXA1.

The third peripheral area PPA3 is provided on at least one side of the third pixel area PXA3. In one embodiment of the present invention, the third peripheral area PPA3 surrounds the third pixel area PXA3 and is connected to the first pixel area PXA1 and the third pixel area PXA3. Parts may not be provided. In one embodiment of the present invention, the third peripheral area PPA3 may also include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. The vertical portion of the third peripheral area PPA3 may also be provided as a pair spaced apart from each other along the width direction of the first pixel area PXA1.

In one embodiment of the present invention, the third area (A3) may have a shape that is line symmetrical to the second area (A2), and in this case, each component provided in the third area (A3) The arrangement relationship may be substantially the same as in the second area A2 except for some wiring.

In one embodiment of the present invention, the vertical parts of the first peripheral area PPA1 may be connected to some of the vertical parts of the second peripheral area PPA2 and the third peripheral area PPA3, respectively. For example, the left vertical part of the first peripheral area PPA1 and the left vertical part of the second peripheral area PPA2 may be connected. The right vertical part of the first peripheral area PPA1 and the right vertical part of the third peripheral area PPA3 may be connected. Additionally, the width W4 of the left vertical portion of the first peripheral area PPA1 and the left vertical portion of the second peripheral area PPA2 may be the same. The width W5 of the right vertical part of the first peripheral area PPA1 and the right vertical part of the third peripheral area PPA3 may be the same.

The width W4 of the left vertical portion of the first peripheral area PPA1 and the second peripheral area PPA2 is the width W5 of the right vertical portion of the first peripheral area PPA1 and the third peripheral area PPA3. ), but may be different. For example, the width W4 of the left vertical portion of the first peripheral area PPA1 and the second peripheral area PPA2 is the right vertical portion of the first peripheral area PPA1 and the third peripheral area PPA3. It may be smaller than the negative width (W5).

The pixels PXL are provided in the pixel areas PXA on the substrate SUB, that is, in the first to third pixel areas PXA1, PXA2, and PXA3. Each pixel (PXL) is the minimum unit for displaying an image and may be provided in plural numbers. The pixels (PXL) may include organic light emitting devices that emit colored light. Each pixel (PXL) may emit one color among red, green, and blue, but is not limited thereto and may emit colors such as cyan, magenta, yellow, and white.

The pixels PXL include first pixels PXL1 arranged in the first pixel area PXA1, second pixels PXL2 arranged in the second pixel area PXA2, and third pixel area ( It includes third pixels (PXL3) arranged in PXA3). In one embodiment of the present invention, the first to third pixels PXL1, PXL2, and PXL3 are provided in plural numbers, respectively, in rows extending in the first direction DR1 and columns extending in the second direction DR2. It can be arranged in a row-column format. However, the arrangement form of the first to third pixels (PXL1, PXL2, and PXL3) is not particularly limited and may be arranged in various forms. For example, the first pixels PXL1 may be arranged so that the first direction DR1 is the row direction, but the second pixels PXL2 may be arranged in a direction other than the first direction DR1, for example. For example, the row direction may be arranged in a direction diagonal to the first direction DR1. Additionally, of course, the third pixels PXL3 may be arranged in the same direction or in different directions from the first pixels PXL1 and/or the second pixels PXL2. Alternatively, in another embodiment of the present invention, the row direction may be the second direction DR2 and the column direction may be the first direction DR1.

The driver provides a signal to each pixel through the wiring section and controls the driving of each pixel (PXL) accordingly. In Figure 1, the wiring portion is omitted for convenience of explanation.

The driving units include scan drivers (SDV1, SDV2, SDV3; hereinafter SDV) that provide scan signals to each pixel along the scan line, and light emission drivers (EDV1, EDV2) that provide light emission control signals to each pixel along the light emission control line. , EDV3 (hereinafter EDV), and a data driver (DDV) that provides a data signal to each pixel along the data line, and a timing control unit (not shown). The timing control unit controls the scan driver (SDV), the light emission driver (EDV), and the data driver (DDV).

In one embodiment of the present invention, the scan drivers SDV include a first scan driver SDV1 connected to the first pixels PXL1 and a second scan driver SDV2 connected to the second pixels PXL2. , may include a third scan driver (SDV3) connected to the third pixels (PXL3). In one embodiment of the present invention, the light emission drivers EDV include a first light emission driver EDV1 connected to the first pixels PXL1 and a second light emission driver EDV2 connected to the second pixels PXL2. , may include a third light emission driver (EDV3) connected to the third pixels (PXL3).

The first scan driver SDV1 may be disposed in a vertical portion of the first peripheral area PPA1. The vertical portion of the first peripheral area (PPA1) is provided as a pair spaced apart from each other along the width direction of the first pixel area (PXA1), and the first scan driver (SDV1) is connected to the first peripheral area (PPA1). ) can be placed on at least one side of the vertical part. The first scan driver SDV1 may extend long along the longitudinal direction of the first peripheral area PPA1.

In a similar manner, the second scan driver SDV2 may be disposed in the second peripheral area PPA2, and the third scan driver SDV3 may be disposed in the third peripheral area PPA3.

In one embodiment of the present invention, the scan drivers SDV may be directly mounted on the substrate SUB. When the scan drivers SDV are directly mounted on the substrate SUB, they may be formed together during the process of forming the pixels PXL. However, the location or method of providing the scan drivers SDV is not limited to this, and may be formed on a separate chip and provided in a chip-on-glass form on the substrate SUB, or a printed circuit board. It may be mounted on the board and connected to the board (SUB) through a connection member.

The first light emission driver EDV1 may also be disposed in the vertical portion of the first peripheral area PPA1, similar to the first scan driver SDV1. The first light emission driver EDV1 may be disposed on at least one of the vertical portions of the first peripheral area PPA1. The first light emission driver EDV1 may extend long along the longitudinal direction of the first peripheral area PPA1.

In a similar manner, the second light emission driver EDV2 may be disposed in the second peripheral area PPA2, and the third light emission driver EDV3 may be disposed in the third peripheral area PPA3.

In one embodiment of the present invention, the light emission drivers (EDV) may be directly mounted on the substrate (SUB). When the light emitting drivers EDV are directly mounted on the substrate SUB, they may be formed together during the process of forming the pixels PXL. However, the location or method of providing the light emitting drivers (EDV) is not limited to this, and may be formed on a separate chip and provided in the form of a chip on glass on the substrate (SUB), or a printed circuit board. It may be mounted on the board and connected to the board (SUB) through a connection member.

In one embodiment of the present invention, the scan drivers (SDV) and the light emission drivers (EDV) are adjacent to each other and are formed on only one side of a pair of vertical portions of the peripheral areas (PPA) as an example. , but is not limited to this, and the arrangement may be changed in various ways. For example, the first scan driver SDV1 is located on one side of the vertical portion of the first peripheral area PPA1 and the first light emission driver EDV1 is located on the other side of the vertical portion of the first peripheral area PPA1. can be provided. Alternatively, the first scan driver SDV1 may be provided on both sides of the vertical portion of the first peripheral area PPA1, and the first light emission driver EDV1 may be provided on both vertical portions of the first peripheral area PPA1. It can only be provided to one side.

The data driver DDV may be disposed in the first peripheral area PPA1. In particular, the data driver DDV may be disposed on a horizontal portion of the first peripheral area PPA1. The data driver DDV may extend long along the width direction of the first peripheral area PPA1.

In one embodiment of the present invention, the positions of the scan drivers (SDV), the light emission drivers (EDV), and/or the data drivers (DDV) may be changed as needed.

The timing control unit (not shown) may be configured to control the first to third scan drivers (SDV1, SDV2, SDV3), first to third light emission drivers (EDV1, EDV2, EDV3), and the data driver (DDV) in various ways. ) can be connected through wiring, and the placement location is not particularly limited. For example, the timing control unit is mounted on a printed circuit board, and the first to third scan drivers (SDV1, SDV2, SDV3) and the first to third light emission drivers (EDV1) are provided through the flexible printed circuit board. , EDV2, EDV3), and the data driver DDV, and the printed circuit board can be placed in various positions, such as one side of the substrate SUB or the back of the substrate SUB.

In various embodiments of the present invention, the shape of the substrate SUB may be changed in various ways. For example, it may have a polygonal shape, where each of the first to third areas A1, A2, and A3 is a closed polygon with straight sides, a circle, ellipse, etc. with curved sides, etc. It can be provided in various shapes such as a semicircle, semiellipse, etc. with sides made of straight lines and curves.

In various embodiments of the present invention, the first, second, and third pixels may include organic light emitting diodes.

According to various embodiments of the present invention, the second pixel area and the third pixel area spaced apart from each other may have the same area or different areas.

Figure 2 is a block diagram showing an example of pixels and a driver according to an embodiment of the present invention.

Referring to FIG. 2 , a display device according to an embodiment of the present invention may include pixels (PXL), a driver, and a wiring unit. The pixels PXL include first to third pixels PXL1, PXL2, and PXL3, and the driver units include first to third scan drivers SDV1, SDV2, and SDV3, and first to third light emission drivers EDV1. , EDV2, EDV3), a data driver (DDV), and a timing control unit (TC). In Figure 2, the positions of the first to third scan drivers (SDV1, SDV2, SDV3), first to third light emission drivers (EDV1, EDV2, EDV3), data driver (DDV), and timing control unit (TC) are It is set for convenience of explanation, and may be placed in a different location within the display device when implementing the actual display device. For example, the data driver DDV is disposed in an area adjacent to the second area A2 and the third area A3 rather than the first area A1, but is not limited thereto. For example, of course, the data driver DDV may be disposed in an area adjacent to the first area A1.

The wiring unit provides signals from the driver to each pixel (PXL) and may include scan lines, data lines, emission control lines, a power line, and an initialization power line (not shown). The scan lines include first to third scan lines (S11 to S1n, S21 and S22, S31 and S32) respectively connected to the first to third pixels (PXL1, PXL2, and PXL3), and the emission control lines are It may include first to third emission control lines (E11 to E1n, E21 and E22, E31 and E32) respectively connected to the first to third pixels (PXL1, PXL2, and PXL3). The data lines D1 to Dm and the power line may be connected to the first to third pixels PXL1, PXL2, and PXL3.

The first pixels PXL1 are located in the first pixel area PXA1. The first pixels PXL1 may be connected to the first scan lines S11 to S1n, the first emission control lines E11 to E1n, and the data lines D1 to Dm. The first pixels PXL1 receive data signals from the data lines D1 to Dm when scan signals are supplied from the first scan lines S11 to S1n. The first pixels (PXL1) that receive the data signal can control the amount of current flowing from the first power source (ELVDD) to the second power source (ELVSS) via an organic light emitting device (not shown).

The second pixels PXL2 are located in the second pixel area PXA2. The second pixels PXL2 are connected to the second scan lines S21 and S22, the second emission control lines E21 and E22, and the data lines D1 to D3. The second pixels PXL2 receive data signals from the data lines D1 to D3 when scan signals are supplied from the second scan lines S21 and S22. The second pixels PXL2 that receive the data signal control the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting device.

Additionally, in FIG. 2, the second pixel area PXA2 is formed by two second scan lines (S21, S22), two second emission control lines (E21, E22), and three data lines (D1 to D3). ), but the present invention is not limited thereto. That is, a plurality of second pixels PXL2 are disposed corresponding to the size of the second pixel area PXA2, and corresponding to the second pixels PXL2, second scan lines, second emission control lines, and the number of data lines can be set in various ways.

The third pixels PXL3 are a third pixel area partitioned by the third scan lines S31 and S32, the third emission control lines E31 and E32, and the data lines Dm-2 to Dm. It is located at PXA3). The third pixels PXL3 receive data signals from the data lines Dm-2 to Dm when scan signals are supplied from the third scan lines S31 and S32. The third pixels (PXL3) that receive the data signal can control the amount of current flowing from the first power source (ELVDD) to the second power source (ELVSS) via the organic light emitting device.

Additionally, in FIG. 2, the third pixel area is formed by two third scan lines (S31, S32), two third emission control lines (E31, E32), and three data lines (Dm-2 to Dm). Although it is shown that six third pixels (PXL3) are located at (PXA3), the present invention is not limited thereto. That is, a plurality of third pixels PXL3 are disposed corresponding to the size of the third pixel area PXA3, and corresponding to the third pixels PXL3, third scan lines, third emission control lines, and The number of data lines can be set in various ways.

The first scan driver SDV1 may supply a scan signal to the first scan lines S11 to S1n in response to the first gate control signal GCS1 from the timing controller TC. For example, the first scan driver SDV1 may sequentially supply scan signals to the first scan lines S11 to S1n. When scan signals are sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 may be sequentially selected in horizontal line units.

The second scan driver SDV2 may supply a scan signal to the second scan lines S21 and S22 in response to the second gate control signal GCS2 from the timing controller TC. For example, the second scan driver SDV2 may sequentially supply scan signals to the second scan lines S21 and S22. When scan signals are sequentially supplied to the second scan lines S21 and S22, the second pixels PXL2 may be sequentially selected on a horizontal line basis.

The third scan driver SDV3 may supply a scan signal to the third scan lines S31 and S32 in response to the third gate control signal GCS3 from the timing controller TC. For example, the third scan driver SDV3 may sequentially supply scan signals to the third scan lines S31 and S32. When scan signals are sequentially supplied to the third scan lines S31 and S32, the third pixels PXL3 may be sequentially selected on a horizontal line basis.

The first emission driver EDV1 may supply an emission control signal to the first emission control lines E11 to E1n in response to the fourth gate control signal GCS4 from the timing controller TC. For example, the first emission driver EDV1 may sequentially supply emission control signals to the first emission control lines E11 to E1n.

Here, the emission control signal can be set to have a wider width than the scan signal. For example, the light emission control signal supplied to the i (i is a natural number) first light emission control line (E1i) is the scan signal supplied to the i-1th first scan line (S1i-1) and the i-th first scan line It may be supplied to overlap at least a portion of the period with the scan signal supplied to (S1i).

The second emission driver EDV2 may supply an emission control signal to the second emission control lines E21 and E22 in response to the fifth gate control signal GCS5 from the timing controller TC. For example, the second emission driver EDV2 may sequentially supply emission control signals to the second emission control lines E21 and E22.

The third emission driver EDV3 may supply an emission control signal to the third emission control lines E31 and E32 in response to the sixth gate control signal GCS6 from the timing controller TC. For example, the third emission driver EDV3 may sequentially supply emission control signals to the third emission control lines E31 and E32.

Additionally, the emission control signal is set to a gate-off voltage (e.g., high voltage) so that the transistor included in the pixels PXL is turned off, and the scan signal is set to a gate-off voltage (e.g., high voltage) so that the transistor included in the pixel PXL is turned off. It may be set to a gate-on voltage (eg, low voltage) so that it can be turned on.

The data driver DDV may supply a data signal to the data lines D1 to Dm in response to the data control signal DCS. The data signal supplied to the data lines D1 to Dm may be supplied to the pixels PXL selected by the scan signal.

The timing control unit (TC) supplies gate control signals (GCS1 to GCS6) generated based on externally supplied timing signals to the scan drivers (SDV) and emission drivers (EDV), and a data control signal (DCS). ) can be supplied to the data driver (DDV). Each of the gate control signals GCS1 to GCS6 may include a start pulse and clock signals. The start pulse may control the timing of the first scan signal or the first emission control signal. Clock signals can be used to shift the start pulse.

The data control signal (DCS) may include source start pulse and clock signals. The source start pulse can control the starting point of data sampling. Clock signals can be used to control sampling operation.

Meanwhile, when the display device is driven sequentially, the first scan driver SDV1 may receive the last output signal of the second scan driver SDV2 as a start pulse. In this case, the first scan driver SDV1 and the second scan driver SDV2 may share control signals, and accordingly, the timing controller TC may send the gate control signal GCS2 to the second scan driver SDV2. and the gate control signal (GSC1) may not be supplied to the first scan driver (SDV1).

Similarly, when a separate scan driver for driving the first pixels (PXL1) is added below the third scan driver (SDV3), the added scan driver and the third scan driver (SDV3) may share a control signal. You can. Additionally, the added scan driver may receive the last scan signal of the third scan driver SDV3 as a start pulse.

Additionally, when the display device is driven sequentially, the first light emission driver EDV1 may receive the last output signal of the second light emission driver EDV2 as a start pulse. In this case, the first light emission driver (EDV1) and the second light emission driver (EDV2) may share control signals, and accordingly, the timing control unit (TC) may send the gate control signal (GCS5) to the second light emission driver (EDV2). may be supplied, and the gate control signal GCS4 may not be supplied to the first light emission driver EDV1.

Similarly, when a separate light emission driver for driving the first pixels (PXL1) is added to the lower part of the third light emission driver (EDV3), the added light emission driver and the third light emission driver (EDV3) may share a control signal. You can. Additionally, the added light emission driver may receive the last light emission control signal of the third light emission driver EDV3 as a start pulse.

Meanwhile, as shown in FIG. 3, compared to the length of the initialization voltage supply line of the first pixel area (PXA1), the length of the initialization voltage supply line of the second pixel area (PXA2) and the third pixel area (PXA3) is relatively long. short. Since the intermediate wiring is cut by the notch area (B), luminance compensation reflecting the sampled value cannot be properly performed due to the difference in the level of the initialization voltage.

In addition, a heterogeneous display device with a pixel-free notch area (B) has a wiring cut off in the center by the notch area (B), so as shown in FIG. 4, left and right process deviations occur. As a result, the deviation in driving characteristics of the second pixels arranged in the second pixel area PXA2 and the third pixels arranged in the third pixel area PXA3 may not be offset, thereby causing a luminance deviation. That is, in order to sense the threshold voltage of the driving transistor included in each pixel area, the line width or thickness of the initialization voltage (Vini) supply line that supplies initialization power through the gate electrode of the driving transistor of each pixel area is determined by the second pixel area. A difference can be shown in (PXA2) and the third pixel area (PXA2). Accordingly, a difference may occur in the level of the initialization voltage (V _ini ) in the second pixel area (PXA2) and the third pixel area (PXA2), and a deviation may occur in the compensation values of the pixels included in each area.

5 shows initialization through the gate electrode of the driving transistor of each pixel region to sense the threshold voltage of the driving transistor included in the first to third pixel regions (PXA1, PXA2, and PXA3) and each pixel disposed in each region. This is an example diagram showing an initialization voltage (Vini) supply line that supplies power, and FIG. 6 is an example diagram showing an enlarged portion of “C” in FIG. 5. As shown, a metal line identical to the source/drain electrode of the driving transistor is disposed on the upper part of the initialization supply line (Vini). FIG. 7 is a cross-sectional view taken along line I-I' of the "C1" portion of FIG. 6. As shown, a first interlayer insulating film (ILD1: 102) is disposed on top of the gate insulating film (GI: 101), and an initialization voltage is applied to the same layer and the same metal as the gate electrode on top of the first interlayer insulating film (GI) 102. A supply line (Vini: 105) is deployed. A second interlayer insulating layer (ILD2: 103) is disposed on the initialization voltage supply line 105. A metal line (SD: 106) identical to the source/drain electrodes of the driving transistor is disposed on the second interlayer insulating film 103, and a protective layer (PAS: 104) is formed on the top.

In a preferred embodiment of the present invention, it is possible to prevent deviations in the compensation values of the pixels included in each area due to the level difference in the initialization voltage (V _ini ) between the second and third pixel areas (PXA2) and PXA2. To this end, as shown in FIG. 8, a dummy line disposed between the two pixel areas (PXA2 and PXA3) may be included. That is, the resistance of the line that supplies the initialization voltage (V _ini ) to the second pixels of the second pixel area (A2) and the third pixels of the third pixel area (PXA3) is the resistance of the first pixel of the first pixel area (PXA3). Dummy lines are placed along the inner edges of the second pixel area (PXA2) and the third pixel area (PXA3) spaced apart from each other to have the same resistance value as the line that supplies the initialization voltage (V _ini ) to the lines. . The dummy line is connected between the second pixel area (PXA2) and the second peripheral area (PPA2) and reaches the panel portion near the side notch area of the third pixel area (PXA3) opposite thereto. .

FIG. 9 is an enlarged illustration of portion “D” of FIG. 8. As shown, unlike the example diagram of FIG. 6, it can be seen that the initialization voltage supply line (V _ini line) of the second pixel area (PXA2) extends from the pixel area toward the notch area, and is disposed on a dummy line above it. there is.

Figure 10 is a cross-sectional view taken along line II-II' in the area "D1" in Figure 9. As shown, a first interlayer insulating film (ILD1: 102) is disposed on top of the gate insulating film (GI: 101), and an initialization voltage is applied to the same layer and the same metal as the gate electrode on top of the first interlayer insulating film (GI) 102. A supply line (V _ini : 105) is arranged to extend from the pixel area toward the notch area. A second interlayer insulating layer (ILD2: 103) is disposed on the extended initialization voltage supply line 105. A metal line (SD: 106) identical to the source/drain electrodes of the driving transistor is disposed on the second interlayer insulating film 103. At this time, on the upper part of the extended initialization voltage supply line 105, a dummy line 107 made of the same metal is disposed on the same layer as the metal line 106 through a contact hole, and a protective layer ( PAS: 104) is formed.

As shown through the above description, the difference in driving characteristics due to the left and right process deviation in the two pixel areas where the horizontal wiring is cut off at the center due to the formation of the notch and spaced apart from each other can be offset by the left and right luminance deviation through the dummy line.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art may make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can do it.

101: gate insulating film 102: first interlayer insulating film
103: second interlayer insulating film 104: protective layer
105: initialization voltage supply line 106: metal line
107: Dummy line

Claims (9)

A first pixel area, a second pixel area and a third pixel area that are spaced apart from each other and each extend from the first pixel area, have a smaller area than the first pixel area, and face each other with a notch-shaped area without pixels in between. A substrate having a;
a plurality of first initialization voltage supply lines supplying an initialization voltage to first pixels of the first pixel area;
a plurality of second initialization voltage supply lines electrically connected to the first initialization voltage supply lines and supplying the initialization voltage to second pixels in the second pixel area;
a plurality of third initialization voltage supply lines electrically connected to the first initialization voltage supply lines and supplying the initialization voltage to third pixels of the third pixel area; and
It includes one dummy line electrically connecting the second initialization voltage supply lines and the third initialization voltage supply lines,
The dummy line is extended and disposed in the first border area, the second border area, and the third border area,
The first border area is a border area of the first pixel area that contacts the first side of the notch-shaped area,
The second border area is a border area of the second pixel area that contacts the notch-shaped area and the second side, and in the second border area, the second initialization voltage supply lines are commonly connected to the dummy line,
The third border area is a border area of the third pixel area that contacts the notch-shaped area and a third side, and in the third border area, the third initialization voltage supply lines are commonly connected to the dummy line. The display device according to claim 1, wherein the second pixel area and the third pixel area spaced apart from each other have the same area. delete delete The display device of claim 1, wherein the length of the first initialization voltage supply line is longer than the length of the second initialization voltage supply line and the length of the third initialization voltage supply line. The method of claim 5, wherein the total resistance value of any one of the dummy line, the second initialization voltage supply lines, and the third initialization voltage supply lines is one of the first initialization voltage supply lines. A display device with the same resistance value. The display device of claim 1, wherein the first, second and third pixels include organic light emitting diodes. The display device according to claim 1, wherein the second pixel area and the third pixel area spaced apart from each other exhibit the same luminance. The display device of claim 1, wherein the second and third initialization voltage supply lines are located on a different layer from the dummy line with an insulating film interposed therebetween, and are in contact with the dummy line through contact holes penetrating the insulating film.