KR20200071014A - Semiconductor package and fabricating method thereof - Google Patents

Abstract

Disclosed are a semiconductor package structure and a manufacturing method of a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide a variety of semiconductor package structures including a connection die for routing an electrical signal between a plurality of different semiconductor dies and, a manufacturing method thereof. An electronic device comprises: a first signal redistribution structure; a first vertical interconnection structure; a connection die; a first connection die interconnection structure; a second signal redistribution structure; and a first electronic component.

Description

Semiconductor package and its manufacturing method{SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF}

This application is filed on September 18, 2017, and is a continuing application of US Patent Application No. 15/707,646, entitled "Semiconductor Package and Method for Manufacturing It," filed May 12, 2017, " Partially continued application of U.S. Patent Application No. 15/594,313, entitled "Semiconductor package and manufacturing method thereof," /207,186, which is currently in U.S. Patent No. 9,653,428, which is filed January 27, 2016 and refers to U.S. Provisional Application No. 62/287,544, entitled "Semiconductor Package and Method for Manufacturing It," Priority claims, and benefit from, each of which is incorporated herein by reference in its entirety.

This application was filed on April 14, 2015, entitled US Patent Application No. 14/686,725 entitled “Semiconductor Package with High Routing Density Patch”; United States Patent Application Serial No. 14/823,689, filed August 11, 2015, named "Semiconductor Package and Method for Manufacturing It," and is currently US Patent No. 9,543,242; United States Patent Application No. 15/400,041, filed January 6, 2017 and entitled "Semiconductor Package and Method for Manufacturing It"; And United States Patent Application Serial No. 15/066,724, filed March 10, 2016, entitled "Semiconductor Package and Manufacturing Method," each of which is incorporated herein by reference in its entirety.

The present invention relates to a semiconductor package and a method for manufacturing the same.

Current semiconductor packages and methods of forming semiconductor packages are inadequate, such as excessive cost, reduced reliability, or package size too large. Additional limitations and disadvantages of the conventional and traditional methods will become apparent to those skilled in the art by comparing these methods of the invention presented in the rest of the application with reference to the drawings.

The present invention provides a semiconductor package and a method for manufacturing the same.

A semiconductor device (package) according to the present invention includes a first signal redistribution structure; A first vertical interconnect structure on a first side of the first signal redistribution structure; A connection die including a rear surface and a front surface, the rear surface facing and connected to a first side surface of the first signal redistribution structure; A first connection die interconnect structure coupled to the front surface of the connection die; A second signal redistribution structure on the first vertical interconnect structure and the first connection die interconnect structure; And a first electronic component, wherein the first electronic component comprises: A first interconnect structure connected to the second signal redistribution structure such that the first electronic component is electrically connected to the first vertical interconnect structure through at least the second signal redistribution structure; And And a second interconnect structure connected to the second signal redistribution structure such that the first electronic component is electrically connected to the first connection die interconnect structure through at least the second signal redistribution structure.

The present invention provides a second vertical interconnect structure on a first side of the first signal redistribution structure; A second connection die interconnect structure connected to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure; And a second electronic component, wherein the second electronic component is connected to the second signal redistribution structure such that the second electronic component is electrically connected to the second vertical interconnect structure through at least the second signal redistribution structure. A first interconnect structure connected; And a second interconnect structure connected to the second signal redistribution structure such that the second electronic component is electrically connected to the second connection die interconnect structure through at least the second signal redistribution structure.

In a vertical direction between the first electronic component and the second signal redistribution structure, in a vertical direction between the second electronic component and the second signal redistribution structure, and in a lateral direction between the first and second electronic components. It may include a layer of underfill material positioned.

And a first encapsulating material covering a first side of the first signal redistribution structure and surrounding the first vertical interconnect structure and the first connection die interconnect structure in a lateral direction.

The first encapsulating material may surround the connection die in the side direction.

The first side of the first encapsulating material may be coplanar with the end surface of the first vertical interconnect structure and the end surface of the first connection die interconnect structure.

The first side side of the first signal redistribution structure, the first side side of the second signal redistribution structure and the first side side of the first encapsulating material may be coplanar.

And a second encapsulating material surrounding the second signal redistribution structure and surrounding the first electronic component in a lateral direction.

The first side side of the first signal redistribution structure, the first side side of the second signal redistribution structure, the first side side of the first encapsulating material and the first side side of the second encapsulating material are It can be in the same plane.

There may be no electrical connection to the back of the connection die.

At least a portion of the connection die may be on the top surface of the first signal redistribution structure.

A semiconductor device according to the present invention includes a first signal redistribution structure; A first vertical interconnect structure on a first side of the first signal redistribution structure; A second vertical interconnect structure on a first side of the first signal redistribution structure; A rear surface and a front surface, wherein the rear surface is connected to a first side of the first signal redistribution structure; A first connection die interconnect structure connected to the front surface of the connection die; A second connection die interconnect structure, connected to the front surface of the connection die, electrically connected to the first connection die interconnect structure; A first encapsulation on a first side of the first signal redistribution structure and surrounding the first and second vertical interconnect structures, the first and second connection die interconnect structures and the connection die in a lateral direction material; A second signal redistribution structure on the first encapsulating material, the first and second vertical interconnect structures, and the first and second connecting die interconnect structures; A first functional die, wherein the first functional die is: to the second signal redistribution structure such that the first functional die is electrically connected to the first vertical interconnect structure through at least the second signal redistribution structure. A first interconnect structure connected; And a second interconnect structure connected to the second signal redistribution structure such that the first functional die is electrically connected to the first connection die interconnect structure through at least the second signal redistribution structure; And a second functional die, wherein the second functional die is: the second signal redistribution structure such that the second functional die is electrically connected to the second vertical interconnect structure through at least the second signal redistribution structure. A first interconnect structure connected to; And a second interconnect structure connected to the second signal redistribution structure such that the second functional die is electrically connected to the second connection die interconnect structure through at least the second signal redistribution structure.

The present invention may include a second encapsulating material covering the second signal redistribution structure and surrounding the first and second functional die in a lateral direction without contacting the first encapsulating material.

The first side of the first encapsulating material may be coplanar with an end face of each of the first and second vertical interconnect structures and an end face of each of the first and second connecting die interconnect structures. .

The first side side of the first signal redistribution structure, the first side side of the second signal redistribution structure, the first side side of the first encapsulating material and the first side side of the second encapsulating material are It can be in the same plane.

An underfill positioned vertically between the first functional die and the second signal redistribution structure, vertically between the second functional die and the second signal redistribution structure and laterally between the first and second functional die. It may include a material layer.

There may be no active electronic components in the volume in the vertical direction directly between the first and second signal redistribution structures.

A semiconductor device according to the present invention includes a first signal redistribution structure; A first vertical interconnect structure on a first side of the first signal redistribution structure; A connection die including a rear surface and a front surface, the rear surface facing and connected to a first side surface of the first signal redistribution structure; A first connection die interconnect structure connected to the front surface of the connection die; And a first electronic component, wherein the first electronic component comprises: a first interconnect structure electrically connected to the first vertical interconnect structure; And a second interconnect structure electrically connected to the first connection die interconnect structure.

The present invention provides a second signal redistribution structure positioned in a vertical direction between the first electronic component and the first vertical interconnect structure and positioned in a vertical direction between the first electronic component and the first connection die interconnect structure. It can contain.

The first and second interconnect structures of the first electronic component may be directly connected to the second signal redistribution structure.

The first and second signal redistribution structures may be coreless (coreless).

The present invention provides a second vertical interconnect structure on a first side of the first signal redistribution structure; A second connection die interconnect structure connected to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure; And a second electronic component, wherein the second electronic component comprises: a first interconnect structure electrically connected to the second vertical interconnect structure; And a second interconnect structure electrically connected to the second connection die interconnect structure.

A method for manufacturing a semiconductor device according to the present invention includes a first signal redistribution structure; A first vertical interconnect structure on a first side of the first signal redistribution structure; A rear surface and a front surface, wherein the rear surface is connected to a first side of the first signal redistribution structure; And receiving an assembly comprising a first connection die interconnect structure coupled to the front surface of the connection die; Forming a second signal redistribution structure on the first vertical interconnect structure and the first connection die interconnect structure; And connecting a first electronic component to the second signal redistribution structure, wherein combining the first electronic component comprises: connecting a first interconnection structure of the first electronic component to the second signal redistribution structure. The first interconnection structure of the first electronic component is electrically connected to the first vertical interconnection structure through at least the second signal redistribution structure; And connecting the second interconnection structure of the first electronic component to the second signal redistribution structure such that the second interconnection structure of the first electronic component is at least the first connection die through the second signal redistribution structure. And electrically connecting to the interconnect structure.

The received assembly includes: a second vertical interconnect structure on a first side of the first signal redistribution structure; And a second connection die interconnect structure coupled to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure. And the method includes connecting a second electronic component to the second signal redistribution structure, wherein connecting the second electronic component comprises: connecting the first interconnection structure of the second electronic component to the second signal. Connecting to a redistribution structure, the first interconnection structure of the second electronic component being electrically connected to the second vertical interconnection structure through at least the second signal redistribution structure; And connecting the second interconnection structure of the second electronic component to the second signal redistribution structure such that the second interconnection structure of the second electronic component is at least a second interconnection die interconnection through the second signal redistribution structure. It may include the step of being electrically connected to the connection structure.

The present invention is a first covering the first side of the first signal redistribution structure and surrounding the first and second vertical interconnection structures, the first and second connection die interconnection structures and the connection die in a lateral direction. And forming an encapsulating material.

The present invention may include forming a second encapsulating material covering the second signal redistribution structure and surrounding the first and second electronic components laterally without contacting the first encapsulating material. have.

The present invention provides a semiconductor package and a method for manufacturing the same.

1 shows a flow diagram of an example method of manufacturing an electronic device in accordance with various aspects of the present disclosure.
2A-2Q illustrate cross-sectional views illustrating example electronic devices and example methods of manufacturing example electronic devices in accordance with various aspects of the present disclosure.
3 shows a flow diagram of an example method of manufacturing an electronic device in accordance with various aspects of the present disclosure.
4A-4N illustrate cross-sectional views illustrating exemplary electronic devices and example methods of manufacturing exemplary electronic devices in accordance with various aspects of the present disclosure.
5 shows a flow diagram of an example method of manufacturing an electronic device in accordance with various aspects of the present disclosure.
6A-6M show cross-sectional views illustrating an example electronic device and an example method of manufacturing the example electronic device according to various aspects of the present disclosure.
7 shows a flow diagram of an example method of manufacturing an electronic device in accordance with various aspects of the present disclosure.
8A-8N show cross-sectional views illustrating an example electronic device and an example method of manufacturing the example electronic device according to various aspects of the present disclosure.
9 shows a top view of an example electronic device in accordance with various aspects of the present disclosure.
10 shows a top view of an example electronic device in accordance with various aspects of the present disclosure.

Various aspects of the present disclosure provide a semiconductor package structure and a method of manufacturing the semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures including a connection die that routes electrical signals between a plurality of different semiconductor dies and methods of manufacturing the same.

The following discussion presents various aspects of the present disclosure by providing examples of various aspects. As these examples are non-limiting, the scope of the various aspects of the present disclosure should not be limited by any particular characteristics of the examples provided. In the following discussion, the phrases “for example”, “eg,” and “exemplary” are non-restrictive and generally "by way" of example and not limitation", "for example and not limitation," and the like.

As used herein, “and/or” means any one or more items in a list joined by “and/or”. For example, "x and/or y" means any element of the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y." In another example, "x, y and/or z" is a set of 7 elements {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y and z”.

The terminology used herein is for describing specific examples and is not intended to limit the present disclosure. As used herein, singular expression includes plural expression unless the context clearly indicates otherwise. As used herein, "comprises", "includes", "comprising", "including", "has", "has ( The terms “have””, “having”, and the like will be understood to specify the presence of the stated feature, integer, step, action, element, and/or component, and one or more other features, integer, step, action. , Does not exclude the presence or addition of elements, elements and/or groups thereof.

It will be understood that terms such as first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, for example, a first element, first component, or first section discussed below may be referred to as a second element, second component, or second section without departing from the teachings of this disclosure. Similarly, various spatial terms such as "top", "bottom", "side", etc. can be used to distinguish one element from another in a relative manner. However, the parts can be oriented in different ways, for example, without departing from the teachings of the present disclosure, a semiconductor device or package can be rotated sideways such that the “top” surface is horizontal and the “side” surface is vertical. You must understand that there is.

Various aspects of the present disclosure provide a semiconductor device or package and a method of manufacturing (or manufacturing) the same, which can reduce cost, increase reliability, and/or increase the manufacturability of the semiconductor device or package.

The above and other aspects of the present disclosure will be described or apparent in the following description of various exemplary implementations. Various aspects of the present disclosure will now be presented with reference to the accompanying drawings so that those skilled in the art can easily implement the various aspects.

1 shows a flow diagram of an exemplary method 100 of manufacturing an electronic device (eg, a semiconductor package, etc.). Exemplary method 100 may share any or all properties with, for example, any other exemplary method(s) discussed herein (eg, exemplary method 300 of FIG. 3, FIG. 5, the exemplary method 500, the exemplary method 700 of FIG. 7, etc.). 2A-2Q illustrate cross-sectional views illustrating exemplary electronic devices (eg, semiconductor packages, etc.) and exemplary methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure. 2A-2Q may, for example, illustrate example electronic devices in various blocks (or steps) of the method 100 of FIG. 1. Figures 1 and 2a-2q will now be discussed together. It should be noted that the order of the exemplary blocks of method 100 may vary without departing from the scope of the present disclosure.

The exemplary method 100 can begin executing at block 105. Method 100 can initiate execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, method 100 automatically executes in response to one or more signals received from one or more upstream and/or downstream manufacturing stations in response to signals from a central manufacturing line controller upon arrival and/or manufacturing of components. Can start. Also, for example, the method 100 can start execution in response to an operator command to start. Additionally, for example, method 100 may initiate execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Exemplary method 100 may include receiving, manufacturing, and/or preparing a plurality of functional dies at block 110. Block 110 may include receiving, manufacturing and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 110 may share any or all characteristics with any of the receiving, manufacturing and/or preparatory operations of the functional die discussed herein. Various exemplary aspects of block 110 are presented in FIG. 2A.

Block 110 may include, for example, receiving a plurality of functional dies (or portions thereof) from an upstream manufacturing process at the same facility or geographic location. Block 110 may also include, for example, receiving a functional die (or portion thereof) from a supplier (eg, from a foundry, etc.).

The functional die received, manufactured and/or manufactured may include any of a variety of properties. For example, although not shown, the received die may include a plurality of different dies on the same wafer (eg, Multi-Project Wafer (MPW)). An example of such a configuration is shown in example 210A in FIG. 2A of U.S. Patent Application No. 15/594,313, which is incorporated herein by reference in its entirety for all purposes. In this MPW configuration, the wafer can include a plurality of different types of functional die. For example, the first die may include a processor, and the second die may include a memory chip. Also, for example, the first die may include a processor, and the second die may include a co-processor. Additionally, for example, both the first die and the second die may include memory chips. Generally, the die may include active semiconductor circuitry. The various examples presented herein generally place or attach individualized functional dies, but these dies may also be connected to each other prior to placement (eg, as part of the same semiconductor wafer, as part of a reconstructed wafer).

Block 110 may include, for example, receiving a functional die in one or more individual wafers dedicated to a single type of die. For example, as shown in FIG. 2A, example 200A-1 represents a wafer dedicated to the entire wafer of die 1, an exemplary die is illustrated at label 211, and an exemplary wafer 200A-3 is here While the various examples shown in general relate to the first and second functional dies (e.g., die 1 and die 2), the entire wafer of the die (the entire wafer of die 2, shown on label 212) should be understood. The present disclosure extends to any number of functional dies of the same or different type (eg, 3 dies, 4 dies, etc.). The scope of the present disclosure is also extended to passive electronic components (eg, resistors, capacitors, inductors, etc.) in addition to or instead of, for example, functional semiconductor die.

The functional dies 211 and 212 can include die interconnect structures. For example, as shown in FIG. 2A, the first functional die 211 includes a first set of one or more die interconnect structures 213 and a second set of one or more die interconnect structures 214. . Similarly, the second functional die 212 can include such a structure. Die interconnect structures 213 and 214 can include any of a variety of die interconnect structure characteristics, and non-limiting examples of these are provided herein.

The first die interconnect structure 213 may include, for example, metal (eg, copper, aluminum, etc.) pillars or lands. The first die interconnect structure 213 may also include, for example, conductive bumps (eg, C4 bumps, etc.) or balls, wires, pillars, and the like.

The first die interconnect structure 213 can be formed in any of a variety of ways. For example, the first die interconnect structure 213 can be plated on the die pad of the functional die 211. Also, for example, the first die interconnect structure 213 can be printing and reflow, wire bonding, and the like. Note that in some example implementations, the first die interconnect structure 213 can be a die pad of the first functional die 211.

The first die interconnect structure 213 can be capped, for example. For example, the first die interconnect structure 213 can be solder capped. Also, for example, the first die interconnect structure 213 can be capped with a metal layer (eg, a metal layer other than solder forming a substituted solid solution or an intermetallic compound with copper). For example, the first die interconnect structure 213 is filed December 8, 2015 and is described in US Patent Application No. 14/963,037 entitled "Temporary Interface Gradient Bonding for Metal Bonding" Can be formed and/or linked, the contents of which are incorporated herein by reference. Additionally, for example, the first die interconnect structure 213 is filed on January 6, 2016 and is entitled US Patent Application No. 14/989,455 entitled "Semiconductor Products Having Metal-Metal Bonds and Methods of Manufacturing them" Can be formed and/or linked as described in the entire contents of which are incorporated herein by reference.

The first die interconnect structure 213 can include, for example, any of a variety of dimensional characteristics. For example, in an exemplary implementation, first die interconnect structure 213 may include a pitch of 30 microns (eg, an inter-center spacing) and a diameter of 17.5 microns (or width, shortening, or long axis width, etc.). Can be. Also, for example, in the exemplary implementation, the first die interconnect structure 213 has a pitch in the range of 20-40 (or 30-40) microns and a diameter in the range of 10-25 microns (or width, shortening, or long axis width) Etc.). The first die interconnect structure 213 can be, for example, 15-20 microns high.

The second die interconnect structure 214 can, for example, share any or all properties with the first die interconnect structure 213. Some or all of the second die interconnect structure 214 may be substantially different from the first die interconnect structure 213, for example.

The second die interconnect structure 214 can include, for example, metal (eg, copper, aluminum, etc.) pillars or lands. The second die interconnect structure 214 may also include, for example, conductive bumps (eg, C4 bumps, etc.) or balls, wires, and the like. The second die interconnect structure 214 may, for example, need not be, but may be the same general type of interconnect structure as the first die interconnect structure 213. For example, both the first die interconnect structure 213 and the second die interconnect structure 214 can include copper pillars. Further, for example, the first die interconnect structure 213 may include metal lands, and the second die interconnect structure 214 may also include copper pillars.

The second die interconnect structure 214 can be formed in any of a variety of ways. For example, the second die interconnect structure 214 can be plated on the die pad of the functional die 211. Also, for example, the second die interconnect structure 214 can be printing and reflow, wire bonding, and the like. Although formed in the same process step as the first die interconnect structure 213, such die interconnect structures 213 and 214 may also be formed in separate individual steps and/or overlapping steps.

For example, in the first exemplary scenario, the first portion of each second die interconnect structure 214 (eg, first half, 1/3, etc.) is the first die interconnect structure 213 ) May be formed by the same first plating operation. Continuing with the first exemplary scenario, a second portion of each of the second die interconnect structures 214 (eg, the second half, the remaining 2/3, etc.) may be formed in the second plating operation. . For example, during the second plating operation, the first die interconnect structure 213 may be inhibited from further plating (eg, by removing a dielectric or protective mask layer formed thereon, removing electroplating signals, etc.). In another exemplary scenario, the second die interconnect structure 214 can be formed in a second plating process that is completely independent of the first plating process used to form the first die interconnect structure 213, which is an example. For example, it may be covered by a protective mask layer during the second plating process.

The second die interconnect structure 214 may not be capped, for example. For example, the second die interconnect structure 214 may not be solder capped. In an exemplary scenario, the first die interconnect structure 213 may be capped (eg, solder-capping, metal layer capping, etc.), and the second die interconnect structure 214 may not be capped. In another example scenario, neither the first die interconnect structure 213 nor the second die interconnect structure 214 is capped.

The second die interconnect structure 214 can include, for example, any of a variety of dimensional characteristics. For example, in an exemplary implementation, the second die interconnect structure 214 can include a 80 micron pitch (eg, an inter-center spacing) and a diameter (or width) of 25 microns or more. Also, for example, in an exemplary implementation, the second die interconnect structure 214 can include a pitch in the range of 50-80 microns and a diameter in the range of 20-30 microns (or width, short or long axis width, etc.). . Additionally, for example, in an exemplary implementation, the second die interconnect structure 214 may have a pitch in the 80-150 (or 100-150) micron range and a diameter in the 25-40 micron range (or width, shortening, or Long axis width, and the like). The second die interconnect structure 214 can be, for example, 40-80 microns high.

It should be noted that functional dies (eg, in the form of a wafer, etc.) can already be received with and have one or more die interconnect structures 213/214 formed thereon (or portions thereof).

The functional die (eg, in the form of a wafer) can be thinned (eg, by grinding, mechanical and/or chemical thinning, etc.) from the original die thickness at this point, but this is not necessary. For example, a functional die wafer (eg, wafers depicted in embodiments 200A-1, 200A-2, 200A-3 and/or 200A-4) can be full thickness wafers. In addition, for example, functional die wafers (e.g., wafers shown in embodiments (200A-1, 200A-2, 200A-3, 200A-4), etc.) provide safe handling of the wafer while still providing the final package thickness. It can be thinned at least partially to reduce.

Generally, block 110 may include receiving, manufacturing and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of such reception and/or manufacturing or any specific nature of such a functional die.

Exemplary method 100 may include, at block 115, receiving, manufacturing, and/or preparing a connection die. Block 115 may include receiving and/or manufacturing a plurality of connection dies in any of a variety of ways, non-limiting examples of which are provided herein. Various exemplary aspects of block 115 are shown in Examples 200B-1 to 200B-7 shown in FIG. 2B (FIGS. 2B-1 and 2B-2).

Block 115 may include, for example, receiving a plurality of connection dies from an upstream manufacturing process at the same facility or geographic location. Block 115 may also include, for example, receiving a connection die from a supplier (eg, from a foundry, etc.).

The receiving, manufactured and/or prepared connecting die can include any of a variety of characteristics. For example, a received, fabricated, and/or prepared die can include a plurality of connecting dies on a wafer (eg, silicon or other semiconductor wafer, glass wafer or panel, metal wafer or panel, etc.). For example, as shown in FIG. 2B-1, example 200B-1 includes the entire wafer of connecting die, and the connecting die of that example is shown with label 216a. While the various examples shown herein generally relate to the use of a single connection die in a package, it should be understood that multiple connection dies (eg, the same or different designs) can be used in a single electronic device package. Non-limiting examples of such configurations are provided herein.

In the example shown here (e.g., 200B-1 to 200B-4), the connection die may include only electrical routing circuitry (e.g., without active semiconductor components and/or passive components). Can be. Note, however, that the scope of the present disclosure is not limited thereto. For example, the connection dies shown here can include passive electronic components (e.g., resistors, capacitors, inductors, integrated passive devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductors) Processing components, semiconductor memory components, etc.) and/or optical components.

The connecting die can include a connecting die interconnect structure. For example, the exemplary connection die 216a shown in FIG. 200B-1 includes a connection die interconnect structure 217. The connecting die interconnect structure 217 can include any of a variety of interconnect structure characteristics, and non-limiting examples of these are provided herein. This discussion generally suggests that all connecting die interconnect structures 217 are identical to each other, but may be different from each other. For example, referring to FIG. 2B-1, the left portion of the connecting die interconnect structure 217 may be the same or different from the right portion of the connecting die interconnect structure 217.

The connection die interconnect structure 217 and/or formation thereof may be any or all of the characteristics of the first die interconnect structure 213 and/or the second die interconnect structure 214 and/or its formation discussed herein. To share. In an exemplary implementation, the first portion of the connecting die interconnect structure 217 provides a gap to provide such a first portion to match each first die interconnect structure 213 of the first functional die 211, Layout, shape, size, and/or material properties. The second portion of the connecting die interconnect structure 217 provides the spacing, layout, shape, size to provide such a second portion to match each first die interconnect structure 213 of the second functional die 212. And/or material properties.

The connecting die interconnect structure 217 can include, for example, metal (eg, copper, aluminum, etc.) pillars or lands. The connecting die interconnect structure 217 may also include, for example, conductive bumps (eg, C4 bumps, etc.) or balls, wires, pillars, and the like.

The connecting die interconnect structure 217 can be formed in any of a variety of ways. For example, the connection die interconnect structure 217 can be plated on the die pad of the connection die 216a. Further, for example, the connection die interconnect structure 217 can be printing and reflow, wire bonding, and the like. Note that in some example implementations, the connection die interconnect structure 217 can be a die pad of the connection die 216a.

The connecting die interconnect structure 217 can be capped, for example. For example, the connecting die interconnect structure 217 can be solder capped. Also, for example, the connecting die interconnect structure 217 can be capped with a metal layer (eg, a substituted solid solution or a metal layer forming an intermetallic compound with copper). For example, the connection die interconnect structure 217 is filed December 8, 2015, and is formed and/or as described in US Patent Application No. 14/963,037, "Temporary Interface Gradient Bonding for Metal Bonding" Can be linked, the entire contents of which are incorporated herein by reference. Additionally, for example, the connection die interconnect structure 217 is filed in US Patent Application No. 14/989,455 filed on January 6, 2016 and entitled "Semiconductor Products with Metal-Metal Bonds and Methods of Manufacturing them" It can be formed and/or linked as described, the entire contents of which are incorporated herein by reference.

The connecting die interconnect structure 217 can include, for example, any of a variety of dimensional characteristics. For example, in an exemplary implementation, connecting die interconnect structure 217 may include a pitch of 30 microns (eg, an inter-center spacing) and a diameter of 17.5 microns (or width, shortening, or long axis width, etc.). have. Also, for example, in an exemplary implementation, the connecting die interconnect structure 217 may have a pitch in the range of 20-40 (or 30-40) microns and a diameter in the range of 10-25 microns (or width, short or long axis width, etc.). It may include. The connecting die interconnect structure 217 can be, for example, 15-20 microns high.

In an exemplary scenario, the connection die interconnect structure 217 is a first functional die 211 and a second functional die 212 of each of the first die interconnect structure 213 (e.g., metal land, conductive Bumps, copper pillars, and the like).

The connecting die 216a (or its wafer 200B-1) can be formed in any of a variety of ways, non-limiting examples of which are discussed herein. For example, referring to FIG. 2B-1, connecting die 216a (eg, shown in example 200B-3) or its wafer (eg, shown in example 200B-1) May include, for example, a support layer 290a (eg, silicon or other semiconductor layer, glass layer, metal layer, plastic layer, etc.). Redistribution (RD) structure 298 may be formed on support layer 290. The RD structure 298 is, for example, a base dielectric layer 291, a first dielectric layer 293, a first conductive trace 292, a second dielectric layer 296, a second conductive trace 295 and a connecting die interconnect structure (217).

The base dielectric layer 291 can be on the support layer 290, for example. The base dielectric layer 291 may include, for example, an oxide layer, a nitride layer, any of various inorganic dielectric materials, and the like. The base dielectric layer 291 can be formed according to specifications and/or can be basic, for example. The base dielectric layer 291 may be referred to as a passivation layer. The base dielectric layer 291 can be or include a silicon dioxide layer formed using, for example, a low pressure chemical vapor deposition (LPCVD) process. In other example implementations, the base dielectric layer 291 can be formed of any of a variety of organic dielectric materials, many of which are provided herein.

The connecting die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in example 200B-1) may also have a first conductive trace 292, for example. And a first dielectric layer 293. For example, it may include deposited conductive metals (eg, copper, aluminum, tungsten, etc.). The first conductive trace 292 may be formed, for example, by sputtering, electroplating, electroless plating, or the like. The first conductive trace 292 may be formed, for example, of submicron or submicron pitch (or inter-center spacing). The first dielectric layer 293 may include, for example, an inorganic dielectric material (eg, silicon oxide, silicon nitride, etc.). In various implementations, the first dielectric layer 293 can be formed before the first conductive trace 292, for example, an opening filled with the first conductive trace 292 or a portion thereof. In an exemplary implementation including, for example, copper conductive traces, a dual damascene process can be used to deposit the traces.

In an alternative assembly, the first dielectric layer 293 can include an organic dielectric material. For example, the first dielectric layer 293 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy and equivalents thereof, and These compounds may be included, but the present invention is not limited thereto. Organic dielectric materials can be formed in a variety of ways, such as chemical vapor deposition (CVD). In this alternative assembly, the first conductive trace 292 can be, for example, a 2-5 micron pitch (or center-to-center spacing).

The connecting die 216a (e.g., shown in example 200B-3) or its wafer (e.g., shown in 200B-1), for example, a second conductive trace 295 and a second dielectric layer (296). The conductive trace 295 can include, for example, a deposited conductive metal (eg, copper, etc.). The second conductive trace 295 can be connected to each first conductive trace 292, for example (eg, in the first dielectric layer 293) through each conductive via 294 or opening. The second dielectric layer 296 can include, for example, an inorganic dielectric material (eg, silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 296 can include an organic dielectric material. For example, the second dielectric layer 296 includes bismaleimide triazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy and equivalents thereof, and These compounds may be included, but the present invention is not limited thereto. The second dielectric layer 296 may be formed using, for example, a CVD process, but is not limited thereto. Various dielectric layers (eg, first dielectric layer 293, second dielectric layer 296, etc.) can be formed of the same dielectric material and/or can be formed using the same process, but this is not required. For example, the first dielectric layer 293 can be formed of any inorganic dielectric material discussed herein, and the second dielectric layer 296 can be formed of any organic dielectric material discussed herein, and vice versa. It is the same.

Two sets of dielectric layers and conductive traces are shown in FIG. 2B-1, but of the connection die 216a (eg, shown in 200B-3) or its wafer (eg, shown in 200B-1) It should be understood that the RD structure 298 can include any number of such layers and traces. For example, RD structure 298 may include only one set of dielectric layers and/or conductive traces, three sets of dielectric layers and/or conductive traces, and the like.

Connection die interconnect structures 217 (eg, conductive bumps, conductive balls, conductive pillars or posts, conductive lands or pads, etc.) may be formed on the surface of the RD structure 298. An example of such a connection die interconnect structure 217 is shown in FIGS. 2B-1 and 2B-2, where a connection die interconnect structure 217 is formed on the front (or top) side of the RD structure 298 and is formed. It is shown as being electrically connected to each second conductive trace 295 through the conductive vias of the two dielectric layers. Such connecting die interconnect structures 217 include, for example, RD structures 298, for example, various electronic components, including the first functional die 211 and the second functional die 212 discussed herein. (Eg, active semiconductor components or dies, passive components, etc.).

The connecting die interconnect structure 217 may include, for example, various conductive materials (eg, any one of copper, nickel, gold, and the like, or combinations thereof). The connecting die interconnect structure 217 may also include solder, for example. In addition, for example, the connection die interconnect structure 217 is plated with a solder ball or bump, a multi-ball solder column, a long solder ball, a metal (eg copper) core ball with a layer of solder covering the metal core Pillar structures (eg, copper pillars, etc.), wire structures (eg, wire bonding wires), and the like.

Referring to FIG. 2B-1, an example 200B-1 showing a wafer of the connection die 216a shows a thin connection die wafer of the thin connection die 216b, for example, as shown in Example 200B-2. It can be thinned to produce. For example, a thin connecting die wafer (eg, as shown in 200B-2 for example) can still be thin enough to safely handle thin (eg grinding, chemical and/or By mechanical thinning, etc.). The connecting die wafer and/or its individual thin connecting die 216b provides a low profile. For example, referring to FIG. 2B-1, in an exemplary implementation where the support layer 290 comprises silicon, the thin connecting die 216b may still include at least a portion of the silicon support layer 290. The lower surface (or back side) of the thin connection die 216b may include a non-conductive support layer 290, a base dielectric layer 291, and the like, to prevent conductive access from the lower support layer 290 to the upper conductive layer. . In other examples, the thin connecting die 216b can be thinned to substantially or completely remove the support layer 290. In such examples, conductive access at the lower side of the connection die 216b may still be blocked by the base dielectric layer 291.

For example, in an exemplary implementation, a thin connecting die wafer (eg, as shown in example 200B-2) or its thin connecting die 216b can have a thickness of 50 microns or less. In another exemplary implementation, the thin connecting die wafer (or its thin connecting die 216b) can have a thickness in the range of 20 to 40 microns. As discussed herein, the thickness of the thin connection die 216b is, for example, the first die 211 and the second, so that the thin connection die 216b can be sandwiched between the carrier and the functional die 211, 212. It may be less than the length of the second die interconnect structure 214 of the two die 212.

Two implementations of the connection die labeled "Connect Die Example 1" and "Connect Die Example 2" are shown in 200B-5 of FIG. 2B-2. Connect Die Example 1 can use, for example, an inorganic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and the semiconductor support layer 290. For example, Connect Die Example 1 can be manufactured by using Amkor Technology's SLIM ^TM (Silicon-Less Integrated Module) technology. The semiconductor support layer can be, for example, 30-100 um (eg, 70 um) thick, and each level (or sub-layer or layer) of the RD structure (eg, including at least a dielectric layer and a conductive layer) is For example, the thickness may be 1-3um (eg, 3um, 5um, etc.). The total thickness of the exemplary resulting structures can be, for example, in the range of 33-109 um (eg, <80 um, etc.). Note that the scope of the present disclosure is not limited to any particular dimension.

Connect Die Example 2 can use, for example, an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and the semiconductor support layer 290. For example, Connect Die Example 2 may be manufactured using Amkor Technology's Silicon Wafer Integrated Fan-out (SWIFT ^TM ) technology. The semiconductor support layer can be, for example, 30-100 um (eg, 70 um) thick and each level (or sub-layer or layer) of the RD structure (eg, including at least a dielectric layer and a conductive layer) Silver, for example, the total thickness of the resulting structure can be, for example, in the range of 41-121 um (eg, <80 um, 100 um, 110 um, etc.). Note that the scope of the present disclosure is not limited to any particular dimension. Also, note that in various example implementations, the support layer 290 of Connect Die Example 2 can be thinned (eg, compared to Connect Die Example 1), resulting in the same or similar thickness overall.

The example implementation presented herein generally relates to a one-sided connection die that may have, for example, interconnect structures on only one side. However, it should be noted that the scope of the present disclosure is not limited to this one-sided structure. For example, as shown in examples 200B-6 and 200B-7, connecting die 216c may include interconnect structures on both sides. Such connection die 216c (eg, as shown in example 200B-7) and its wafer (eg, as shown in example 200B-6), which may also be referred to as a double-sided connection die An exemplary implementation of) is shown in Figure 2B-2. Exemplary wafers (e.g., 200B-6, for example) are optional with example wafers (e.g., (200B-1 and/or 200B-2)) shown in FIG. 2B and discussed herein, for example. Let's or share all the characteristics. Also, for example, the example connection die 216c can share any or all of the characteristics with the example connection dies 216a and/or 216b shown in FIG. 2B-1 and discussed herein. For example, the connection die interconnect structure 217b can share any or all properties with the connection die interconnect structure 217 shown in FIG. 2B-1 and discussed herein. Also, for example, redistribution (RD) structure 298b, base dielectric layer 291b, first conductive trace 292b, first dielectric layer 293b, conductive via 294b, second conductive trace 295b, and Any or all of the second dielectric layers 296b are shown in FIGS. 2B-1 and redistributed (RD) structures 298, base dielectric layers 291, first conductive traces 292, first, respectively, discussed herein. Any or all of the features of dielectric layer 293, conductive vias 294, second conductive traces 295, and second dielectric layers 296 may be shared. The exemplary connection die 216c also includes a second set of connection die interconnect structures 299 received and/or manufactured on the side of the connection die 216c opposite the connection die interconnect structure 217b. This second connecting die interconnect structure 299 can share any or all properties with the connecting die interconnect structure 217. In an exemplary implementation, the second connecting die interconnect structure 299 may be formed first as the RD structure 298b is formed on the support structure (eg, removed and thinned, such as the support structure 290). Planarized (eg, by grinding, peeling, stripping, etching, etc.).

Similarly, any or all of the exemplary methods and structures shown in U.S. Patent Application No. 15/594,313, incorporated herein by reference in its entirety, are performed with any of these connecting dies 216a, 216b and/or 216c. Can be.

One or more of the second connection die interconnect structures 299 may be isolated from other electrical circuits of the connection die 216c, which will also be referred to herein as dummy structures (eg, dummy pillars, etc.), anchoring structures. Note that you can. For example, any or all of the second connecting die interconnect structures 299 can be formed to secure the connecting die 216c to a carrier or RD structure or metal pattern in a later step. Further, the one or more second connecting die interconnect structures 299 may be electrically connected to an electrical trace, which may be connected to, for example, electronic device circuitry of the die attached to the connecting die 216c. Such a structure may be referred to as an active structure (eg, active pillar, etc.), for example.

Generally, block 115 may include receiving, manufacturing, and/or preparing a connection die. Accordingly, the scope of the present disclosure should not be limited by any particular manner of such reception, fabrication and/or preparation, or by any particular nature of such a connection die.

Exemplary method 100 may include receiving, manufacturing and/or preparing a first carrier at block 120. Block 120 may include receiving, manufacturing and/or preparing carriers in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 120 may share any or all characteristics with other carrier reception, manufacturing and/or preparation steps discussed herein, for example. Various exemplary aspects of block 120 are shown in example 200C of FIG. 2C.

Block 120 may include, for example, receiving a carrier from an upstream manufacturing process at the same facility or geographic location. Block 120 may also include, for example, receiving a carrier from a supplier (eg, foundry, etc.).

The received, manufactured and/or prepared carrier 221 can include any of a variety of characteristics. For example, the carrier 221 may include a semiconductor wafer or panel (eg, a typical semiconductor wafer, a lower grade semiconductor wafer using lower grade silicon than those used in the functional die discussed herein, etc.). Further, for example, the carrier 221 may include metal, glass, plastic, and the like. The carrier 221 may be reusable or breakable, for example (single use, multiple use, etc.).

The carrier 221 can include any of a variety of shapes. For example, the carrier can be in the shape of a wafer (eg, circular, etc.) and can be in the form of a panel (eg, square, rectangular, etc.). The carrier 221 can have any of a variety of side dimensions and/or thickness. For example, the carrier 221 can have the same or similar side dimensions and/or thickness of the wafers of the functional die and/or connecting die discussed herein. Further, for example, the carrier 221 may have the same or similar thickness to the wafer of the functional die and/or connecting die discussed herein. The scope of the present disclosure is not limited by any particular carrier properties (eg, material, shape, dimensions, etc.).

The example 200C shown in FIG. 2C includes an adhesive material layer 223. The adhesive material 223 can include any of a variety of types of adhesives. For example, the adhesive can be a liquid, paste, tape, or the like.

The adhesive 223 can include any of a variety of dimensions. For example, the adhesive 223 may cover the entire upper surface of the first carrier 221. Further, for example, the adhesive may cover the central portion of the upper surface of the first carrier 221 without covering the peripheral edge of the upper side of the first carrier 221. In addition, for example, the adhesive can cover each portion of the top surface of the first carrier 221, which corresponds to the future location of the functional die of a single electronic package.

The adhesive 223 can have a thickness greater than the height of the second die interconnect structure 214, and thus, greater than the height of the first die interconnect structure 213 (eg, 5% larger, 10% bigger, 20% bigger, etc.).

Exemplary carrier 221 may share any or all properties with any carrier discussed herein. For example, and without limitation, the carrier may not have a signal distribution layer, but may include one or more signal distribution layers. Examples of such structures and their formation are shown in example 600A in FIG. 6A and discussed herein.

Generally, block 120 may include receiving, manufacturing and/or preparing a carrier. Accordingly, the scope of the present disclosure should not be limited by the particular conditions under which the carrier is received, any particular manner of manufacturing the carrier and/or the nature of any particular manner of preparing such carrier for use.

Exemplary method 100 couples (or mounts) a functional die to a carrier (e.g., to the top surface of a non-conductive carrier, to a metal pattern on the top surface of the carrier, to the RD structure on top of the carrier, etc.) at block 125. )). Block 125 may include performing such a combination in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 125 may share any or all properties with other die mounting steps discussed herein, for example. Various exemplary aspects of block 125 are shown in example 200D shown in FIG. 2D.

The functional dies 201-204 (eg, any of the functional dies 211 and 212) can be accommodated, for example, as individual dies. Also, for example, one or more of the functional dies 201-204 can be accommodated on a single wafer, and one or more of the functional dies 201-204 (e.g., 200A-1) and functional In a scenario where one or both of the dies are accommodated in wafer form, the functional die can be singulated from the wafer If one of the functional dies 201-204 is received on a single MPW, these functional dies are attached to the set Note that it can singulate from the wafer (eg, connected to bulk silicon).

Block 125 may include placing functional die 201-204 in adhesive layer 223. For example, the second die interconnect structure 214 and the first die interconnect structure 213 can be completely (or partially) inserted into the adhesive layer 223. The adhesive layer 223 is formed of the second die interconnect structure 214 when the lower surface of the die 201 to 204 contacts the upper surface of the adhesive layer 223, such as the lower end of the second die interconnect structure. It can be thicker than the height. In an alternative implementation, the adhesive layer 223 may be thinner than the height of the second die interconnect structure 214, but when the dies 201 to 204 are disposed on the adhesive layer 223, the first die interconnect structure It is thick enough to cover at least a portion of (213).

Block 125 may include placing functional dies 201-204 using, for example, a die pick and place machine.

It should be noted that although the examples herein are generally presented with functional dies 201-204 (and their interconnect structures) in similar sizes and shapes, such symmetry is not required. For example, the functional dies 201-204 can be each different shape and size, and can have different types and/or numbers of interconnect structures. The functional die 201-204 (or so-called any functional die discussed herein) can also be a semiconductor die, but can also be a variety of electronic components, such as passive electronic components, active electronic components, bare dies, packaged dies, etc. Can be. Accordingly, the scope of the present disclosure is limited by the properties of the functional die 201-204 (or any so-called functional die discussed herein).

In general, block 125 may include coupling (or mounting) a functional die to a carrier. Accordingly, the scope of the present disclosure should not be limited by any particular way of performing such bonding, or by any particular properties such as such functional dies, interconnect structures (water), carriers, attachment means, and the like.

Exemplary method 100 may include encapsulation at block 130. Block 130 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Various exemplary aspects of block 130 are shown in example 200E shown in FIG. 2E. Block 130 may share any or all properties with other encapsulations discussed herein, for example.

Block 130 may, for example, include performing a wafer (or panel) level molding process. As discussed herein, before individualizing individual modules, any or all of the process steps discussed herein can be performed at the panel or wafer level. Referring to the exemplary implementation 200E shown in FIG. 2E, the encapsulating material 226' is the top surface of the adhesive 223, the top surface of the functional die 201-204, the functional die 201-204 It may cover at least a part (or all) of the side. The encapsulating material 226' can also cover any portion of the second die interconnect structure 214, the first die interconnect structure 213, and the functional die 201-204, for example (such as Any of the components are exposed).

The encapsulating material 226' can include various types of encapsulating materials, such as molding materials, any dielectric materials presented herein, and the like.

Although encapsulating material 226' (as shown in FIG. 2E) is shown covering the top surface of functional die 201-204, this top surface (or any respective portion of this top surface) Can be exposed from the encapsulating material 226 (as shown in Figure 2F). The block 130 may be formed using, for example, a process of initially forming the encapsulating material 226 with the die top surface exposed (eg, film assisted molding technology, die-seal molding technology, etc.). ), forming encapsulating material 226' and then encapsulating material 226' sufficient to expose the top surface of any or all functional dies 201-204 of functional dies 201 to 204. The thinning process (e.g., performed at block 135), forming the encapsulating material 226', and then the top surface of any or all of the functional dies 201 to 204 (or the And a thinning process (eg, performed at block 135) to thin the encapsulation material to still leave a portion of the encapsulating material 226' to cover each portion.

In general, block 130 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way or any particular type of encapsulating material or construction thereof to perform such encapsulation.

Exemplary method 100 may include grinding encapsulating material at block 135. Block 135 may include performing such grinding (or any thinning or planarization) in any of the various ways a non-limiting example is provided herein. Block 135 may, for example, share any or all properties with other grinding (or thinning) blocks (or steps) discussed herein. Various exemplary aspects of block 135 are shown in example 200F shown in FIG. 2F.

As discussed herein, in various exemplary implementations, encapsulating material 226' may be formed to a thickness that is greater than originally desired ultimately. In this exemplary implementation, block 135 may be performed to grind (or otherwise thin or planarize) encapsulating material 226'. In example 200F, shown in FIG. 2F, encapsulating material 226 ′ was ground to produce encapsulating material 226. The top surface of the ground (or thin or planarized) encapsulating material 226 is coplanar with the top surface of the functional die. Note that in various example implementations, one or more functional dies 201-204 can be exposed and one or more functional dies 201-204 can be exposed from covering material 226. Note that when performed, such grinding operations do not need to expose the top surface of the functional die 201-204.

In an exemplary implementation, block 135 may include grinding (or thinning or flattening) the back of either or both of encapsulating material 226' and functional die 201-204, thus , The encapsulating material 226 and the top surfaces of the one or more functional dies 201 to 204 are coplanar.

In general, block 135 may include grinding the encapsulating material. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

The exemplary method 100 can include attaching a second carrier at block 140. Block 140 may include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 140 may share any or all properties with any carrier attachment discussed herein. Various exemplary aspects of block 140 are shown in FIG. 2G.

2G, the second carrier 231 can be attached to the top surface of the encapsulating material 226 and/or the top surface of the functional die 201-204. At this point, the assembly can still be in the form of a wafer (or panel). The second carrier 231 can include any of a variety of properties. For example, the second carrier 231 may include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, and the like. Block 140 may include attaching (or joining or mounting) second carrier 231 in any of a variety of ways. For example, block 140 may include attaching the second carrier 231 using an adhesive, using a mechanical attachment mechanism, or using a vacuum attachment.

Generally, block 140 may include attaching a second carrier. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of carrier attaching or the properties of any particular type of carrier.

The exemplary method 100 can include removing the first carrier at block 145. Block 145 can include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 145 can share any or all properties with any carrier removal process discussed herein. Various exemplary aspects of block 145 are shown in example 200H shown in FIG. 2H.

For example, the example 200H in FIG. 2H shows the removed first carrier 221 (eg, compared to the example 200G in FIG. 2G ). Block 145 can include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical-mechanical planarization, peeling, shearing, heat or laser emission, etc.).

Also, for example, block 145 may include removing the adhesive layer 223 used in block 125 to couple functional die 201-204 to first carrier 221. . The adhesive layer 223 may be removed together with the first carrier 221 in a single-step or multi-step process, for example. For example, in an exemplary implementation, block 145 pulls first carrier 221 from functional die 201-204 and encapsulating material 226, and adhesive (or a portion thereof) is applied to first carrier ( 221). Also, for example, block 145 may be functional die 201-204 (eg, from the underside of functional die 201-204, from the first and/or second die interconnect structures, etc.) And the adhesive layer 223 from the encapsulating material 226 (eg, any portion of the adhesive layer 223 remaining after removing the entire adhesive layer 223 and/or the first carrier 221, etc.) It may include using a solvent, thermal energy, light energy, or other cleaning techniques to remove the.

In general, block 145 can include removing the first carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular type of carrier removal or the nature of any particular type of carrier.

Exemplary method 100 may include attaching (or joining or mounting) a connection die to a functional die at block 150. Block 150 may include performing this attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 150 can share any or all properties with any die attach process discussed herein, for example. Various exemplary aspects of block 150 are shown in FIG. 2I.

For example, the die interconnect structure 217 of the first connection die 216b (eg, any or all of those connection dies) is the first functional die 201 and the second functional die 202. Can be mechanically and electrically connected to each of the first die interconnect structures 213.

These interconnect structures can be connected in a variety of ways. For example, the connection can be performed by solder. In an exemplary implementation, the first die interconnect structure 213 and/or the connection die interconnect structure 217 can include a solder cap (or other solder structure) that can be reflowed to perform the connection. Such solder caps can be reflowed, for example, by mass reflow, thermal compression bonding (TCB), or the like. In other example implementations, the connection may be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding, instead of using solder. Examples of such connections are filed on December 8, 2015 and filed on US Patent Application No. 14/963,037 filed "Transient Interface Gradient Bonding for Metal Bonding" and January 6, 2016 and "Interlocking Metals- A semiconductor product having a metal bond and a method for manufacturing the same are provided in US Patent Application No. 14/989,455, the entire contents of each of which are incorporated herein by reference. Any of a variety of techniques can be used to attach the first die interconnect structure 213 to the connection die interconnect structure 217 (eg, mass reflow, thermocompression bonding (TCB), direct metal to metal). Direct metal-to-metal intermetallic bonding, conductive adhesives, etc.).

As shown in example 200I, the first die interconnect structure 213 of the first connection die 201 is connected to each connection die interconnect structure 217 of the connection die 216b, and the second The first die interconnect structure 213 of the connection die 202 can be connected to each connection die interconnect structure 217 of the connection die 216b. As connected, connection die 216b provides electrical connection between various die interconnect structures of first functional die 201 and second functional die 202 via RD structure 298 (eg For example, as shown in Example 2B-1 (200B-3), etc.).

In the example 200I shown in FIG. 2I, the height of the second die interconnect structure 214 is, for example, the first die interconnect structure 213, the connection die interconnect structure 217, the RD structure 298 and It may be greater than or equal to the combined height of any support layer 290b of the connecting die 216b. This height difference may be, for example, a buffer material (eg, underfill, etc.) between the connection die 216b and the other substrate (eg, as shown in FIG. 2N example 200N and discussed herein). ).

Although the exemplary connecting die 216b is shown as a one-sided connecting die (eg, as the exemplary connecting die 216b of FIG. 2B-1 ), the scope of the present disclosure is not limited thereto. For example, any or all of these exemplary connecting dies 216b may be double-sided (eg, as the exemplary connecting die 216c of FIG. 2B-2).

In general, block 150 may include attaching (or joining or mounting) a connecting die to a functional die. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing this attachment or the nature of any particular type of attachment structure.

The example method 100 can include underfilling the connecting die at block 155. Block 155 may include performing this underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 155 may share any or all of the characteristics with any underfill process discussed herein, for example. Various exemplary aspects of block 155 are shown in example 200J shown in FIG. 2J.

An underfill may be applied between the connecting die 216b and the functional die 201-204. In scenarios where pre-applied underfill (PUF) is used, such PUF is prior to joining the connecting die interconnect structure 217 to the first die interconnect structure 213 of the functional die 201-204 (e.g. , At block 150) functional die 201-204 and/or connecting die 216b.

Block 155 may include forming an underfill after attachment performed at block 150 (eg, capillary underfill, etc.). As shown in the exemplary implementation 200J of FIG. 2J, the underfill material 223 (eg, any underfill material discussed herein, etc.) is connected (eg, as oriented in FIG. 2J). The bottom surface of the die 216b may be fully or partially covered and/or at least a portion (if not all) of the sides of the connecting die 216b. The underfill material 223 may also, for example, surround the connection die interconnect structure 217 and the first die interconnect structure 213 of the functional die 201-204. The underfill material 223 may additionally cover the top surface of the functional die 201-204 (as oriented in FIG. 2J ), for example in an area corresponding to the first die interconnect structure 213. .

Note that in various example implementations of example method 100, underfilling performed at block 155 may be omitted. For example, the underfill of the connecting die can be performed in another block (eg, block 175, etc.). Also, for example, this underfilling can be omitted entirely.

In general, block 155 may include underfilling the connecting die. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular type of underfill or the nature of any particular type of underfill that performs this underfill.

The exemplary method 100 can include removing the second carrier at block 160. Block 160 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 160 may share any or all properties with any carrier removal process discussed herein (eg, with respect to block 145, etc.). Various exemplary aspects of block 160 are presented by example 200K shown in FIG. 2K.

For example, the example implementation 200K shown in FIG. 2K does not include the second carrier 231 of the example implementation 200J shown in FIG. 2J. Note that such removal may include, for example, surface cleaning, adhesive removal when used, and the like.

In general, block 160 may include removing the second carrier. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of carrier or carrier material being removed or any particular way of performing such carrier removal.

Exemplary method 100 may include singulation at block 165. Block 165 may include performing this singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 165 may share any or all characteristics with any singulation discussed herein, for example. Various exemplary aspects of block 165 are presented by example 200L shown in FIG. 2L.

As discussed herein, the exemplary assembly shown herein can be formed on a wafer or panel that includes a plurality of such assemblies (or modules). For example, example 200K shown in FIG. 2K has two assemblies (left and right) joined together by encapsulating material 226. In this exemplary implementation, the wafer or panel can be singulated (or diced) to form individual assemblies (or modules). In the example 200L of FIG. 2L, encapsulating material 226 is sawed (or cut, split, snapped, diced, cut into two encapsulating material portions 226a and 226b corresponding to each electronic device. Etc).

In the exemplary implementation 200L shown in FIG. 2L, only the encapsulating material 226 needs to be cut. However, block 165 may include cutting any of a variety of materials when present along a singulation street (or cut line). For example, block 165 may include cutting underfill material, carrier material, functional and/or connecting die material, substrate material, and the like.

In general, block 165 may include singulation. Therefore, the scope of the present disclosure should not be limited by any particular singulation scheme.

Exemplary method 100 may include mounting to a substrate at block 170. Block 170 can include, for example, performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 170 can share any or all of the properties discussed herein with mounting (or attaching) steps discussed herein (eg, attaching interconnect structures, attaching die backs, etc.). Various exemplary aspects of block 170 are shown in example 400M shown in FIG. 4M.

The substrate 288 can include any of a variety of properties, non-limiting examples of which are provided herein. For example, the substrate 288 may include packaging substrates, interposers, motherboards, printed wire boards, functional semiconductor dies, build-up redistribution structures of other devices, and the like. Substrate 288 may include, for example, a coreless substrate. The substrate 288 may include, for example, a conductive layer formed on one or more dielectric layers (eg, organic and/or inorganic dielectric layers) and/or semiconductor (eg, silicon, etc.) substrates, glass or metal substrates, ceramic substrates, etc. It can contain. The substrate 288 may share any or all properties with, for example, the RD structure 298 of FIG. 2B-1 and the RD structure 298b of FIG. 2B-2. Substrate 288 may include, for example, individual packaged substrates, or may include a plurality of substrates (eg, in a panel or wafer) that can be singulated together, which can be singulated later.

In the example 200M shown in FIG. 2M, block 170 provides a second die interconnect structure 214 of the functional die 201-202 to each pad (eg, bond pads, traces, lands, etc.). Or soldering (eg, using mass reflow, thermal compression bonding, laser soldering, etc.) to other interconnect structures of the substrate 288 (eg, pillars, pillars, balls, bumps, etc.) have.

In an exemplary implementation where the connecting die 216b is a double-sided connecting die, such as the connecting die 216c, block 170 can also provide a second set of connecting die interconnect structures 299 to each pad or substrate 288. Note that it may include connecting to other interconnect structures. However, in the example 200M of FIG. 2M, the connection die 216b is a one side connection die. As discussed herein, the second die interconnect structure 214 of the functional die 201-202 includes the first die interconnect structure 213, the connection die interconnect structure 217 and the connection die 216b. Note that since there is higher than the combined height of the support layer 290b, there is a gap between the back side of the connection die 216b (the bottom of the connection die 216b in FIG. 2M) and the top of the substrate 288. As shown in Fig. 2N, this gap can be filled with an underfill.

In general, block 170 includes mounting (or attaching or joining) the individualized assembly (or module) at block 165 to the substrate. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular type of mounting (or attachment) or any particular mounting (or attachment) structure.

Exemplary method 100 may include performing an underfill between a substrate at block 175 and an assembly (or module) mounted to block 170. Block 175 may include performing underfilling in any of a variety of ways, and non-limiting examples are provided herein. Block 175 can share any or all properties with any underfill (or encapsulating) process discussed herein (eg, with respect to block 155, etc.). Various aspects of block 175 are shown in example 200N shown in FIG. 2N.

Block 175 may include, for example, performing a capillary or injected underfill process after mounting performed in block 170. Also, for example, in a scenario where a pre-applied underfill (PUF) is used, such PUF can be applied to the substrate, the metal pattern of the substrate, and/or their interconnect structures prior to such mounting. Block 175 may also include performing this underfill using a molded underfill process.

As shown in the exemplary implementation 200N of FIG. 2N, the underfill material 291 (eg, any underfill material discussed herein, etc.) can completely or partially cover the top surface of the substrate 288. have. The underfill material 291 also surrounds the second die interconnect structure 214 (and/or the corresponding substrate pad) of the functional die 201-202, for example. The underfill material 291 may, for example, cover the lower surface of the functional die 201-202, the lower surface of the connecting die 216b and the lower surface of the encapsulating material 226a. The underfill material 291 may also, for example, cover the side surface of the side of the connecting die 216b and/or the exposed side of the underfill 223 between the connecting die 216b and the functional die 201-202. . The underfill material 291 may, for example, cover the side sides (eg, all or part) of the encapsulating material 226a and/or the functional die 201-202.

In an exemplary implementation where underfill 223 is not formed, underfill material 291 may be formed in place of underfill 223. For example, referring to example 200N, underfill material 223 may be replaced with more underfill material 291 in example 200N.

In the example implementation in which the underfill 223 is formed, the underfill material 291 can be a different type of underfill material than the underfill material 223. In other example implementations, the underfill materials 223 and 291 may be of the same type of material.

Like block 155, block 175 can also be omitted, leaving space to be filled with another underfill (eg, a molded underfill, etc.) in another block, for example.

Generally, block 175 includes an underfill. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of underfill or any particular underfill material.

Exemplary method 100 may include performing a continuous process at block 190. Such a continuous process can include any of a variety of properties, non-limiting examples of which are provided herein. For example, block 190 may include returning the execution flow of example method 100 to any block. Also, for example, block 190 may include sending the execution flow of example method 100 to any other method block (or step) discussed herein (eg, the example of FIG. 3. Method 300, in connection with the exemplary method 500 of FIG. 5, and the like).

For example, block 190 may include forming interconnect structures 299 (eg, conductive balls, bumps, pillars, etc.) on the bottom surface of substrate 288.

In addition, for example, as shown in example 200O of FIG. 20, block 190 may include forming encapsulating material 225. Such encapsulating material 225 may be, for example, the top surface of substrate 288, the side surface of underfill 224, the side surface of encapsulating material 226a, and/or the side surface of functional die 201-202. Can cover. In the example 200O shown in FIG. 2O, the top surface of the encapsulating material 225, the top surface of the encapsulating material 226a and/or the top surface of the functional die 201-202 may be coplanar have.

As discussed herein, underfill 224 (eg, formed at block 175) may not be formed. In such a case, the encapsulating material 225 can take its place as an underfill. An example 200P of such a structure and method is provided in FIG. 2P. For example implementation 200O shown in FIG. 2O, in example implementation 200P, underfill 224 of example implementation 200O is replaced with encapsulating material 225 as underfill.

As discussed herein, underfill 223 (eg, formed at block 155) and underfill 224 may not be formed. In such cases, encapsulating material 225 may be substituted. An exemplary implementation 200Q of this structure and method is provided in FIG. 2Q. Compared to the exemplary implementation 200P shown in FIG. 2P, in the exemplary implementation 200Q, the underfill 223 of the exemplary implementation 200P is replaced with an encapsulating material 225.

In any example implementations 200O, 200P and 200Q shown in FIGS. 2O, 2P and 2Q, the sides of the encapsulating material 225 and the substrate 288 can be coplanar.

In the exemplary method 100 shown in FIGS. 1 and 2A-2Q, various die interconnect structures (eg, first die interconnect structures 213, second die interconnect structures 214, dies) Interconnection structures 217 (and/or 299, etc.) were present. For example, these various die interconnect structures may generally be formed before each die is incorporated into an assembly, but the scope of the present disclosure is not limited by timing. For example, any or all of the various die interconnect structures can be formed after each die is incorporated into the assembly. An exemplary method 300 of forming a die interconnect structure at another stage will now be discussed.

3 shows a flow diagram of an exemplary method 300 of manufacturing an electronic device (eg, a semiconductor package, etc.). Exemplary method 300 may share any or all properties with, for example, any other exemplary method(s) discussed herein (eg, exemplary method 100 of FIG. 1, FIG. 5, the exemplary method 500, the exemplary method 700 of FIG. 7, etc.). 4A-4N illustrate cross-sectional views illustrating exemplary electronic devices (eg, semiconductor packages, etc.) and exemplary methods of manufacturing exemplary electronic devices, in accordance with various aspects of the present disclosure. 4A-4N can illustrate an example electronic device at various blocks (or steps) of the method 300 of FIG. 3, for example. 3 and 4a-4n will now be discussed together. It should be noted that the order of the exemplary blocks of method 300 may vary without departing from the scope of the present disclosure.

The exemplary method 300 can begin executing at block 305. Method 300 can initiate execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, the method 300 can automatically initiate execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations in response to signals from a central manufacturing line controller or the like. 300 may start execution in response to an operator command to start. Additionally, for example, method 300 can initiate execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Exemplary method 300 may include receiving, manufacturing, and/or preparing a plurality of functional dies at block 310. Block 310 may include receiving, manufacturing and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 310 can share any or all properties with block 110 of the example method 100 shown in FIG. 1 and discussed herein. Various aspects of block 310 are shown in the examples 400A-1 to 400A-4 shown in FIG. 4A.

Block 310 can include, for example, receiving a plurality of functional dies from an upstream manufacturing process at the same facility or geographic location. Block 310 may also include, for example, receiving a functional die from a supplier (eg, from a foundry). Block 310 may also include, for example, forming any or all features of a plurality of functional dies.

In an example implementation, block 310 may share any or all properties with block 110 of example method 100 of FIG. 1, but first and second die interconnect structures 213, 214 There is no. As can be seen, such die interconnect structures can be formed later in the exemplary method 300 (eg, in block 347, etc.). Although not shown in FIG. 4A, each of the functional dies 411-412 can include, for example, die pads and/or under bump metallization structures on which such die interconnect structure can be formed.

The functional die 411-412 shown in FIG. 4A can share any or all properties with, for example, the functional die 211-212 shown in FIG. 2A (eg, first and first) 2 without die interconnect structures 213,214). For example and without limitation, functional dies 411-412 can be used in a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.) It can include any property.

In general, block 310 may include receiving, manufacturing and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by any particular way of performing such reception, manufacturing and/or preparation, or by any particular characteristic of such a functional die.

Exemplary method 300 may include receiving, manufacturing, and/or preparing a connection die at block 315. Block 315 can include receiving, manufacturing and/or preparing one or more connection dies in any of a variety of ways, non-limiting examples of which are provided herein. Block 315 may share any or all properties with block 115 of the example method 100 shown and discussed herein, for example, in FIG. 1. Various exemplary aspects of block 315 are shown in examples 400B-1 and 400B-2 shown in FIG. 4B.

The connecting die 416a and/or 416b (or wafer thereof) may include, for example, a connecting die interconnect structure 417. The connecting die interconnect structure 417 can include any of a variety of properties. For example, the formation of a connection die interconnect structure 417 and/or any aspect thereof is illustrated in FIGS. 2B-1-2B-2 and discussed herein with a connection die interconnect structure 217 and/or formation thereof Can share any or all characteristics.

The connection dies 416a and/or 416b (or wafers thereof) are non-limiting examples provided herein in connection with, for example, the connection dies 216a, 216b, and/or 216c of FIGS. 2B-1 to 2B-2 It can be formed in any of a variety of ways.

Generally, block 315 may include receiving, manufacturing, and/or preparing a connection die. Accordingly, the scope of the present disclosure should not be limited by any particular way of performing such reception, manufacturing and/or preparation, or by any particular nature of such a connection die.

Exemplary method 300 may include receiving, manufacturing and/or preparing the first carrier at block 320. Block 320 may include receiving, manufacturing and/or preparing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. Block 320 may have any or all of the characteristics of, for example, other carrier receiving, manufacturing and/or preparation steps discussed herein (e.g., block 120 of exemplary method 100 of FIG. 1, etc.). Share it.

Various exemplary aspects of block 320 are shown in example 400C shown in FIG. 4C. For example, the carrier 421 can share any or all of the characteristics with the carrier 221 of FIG. 2C. In addition, for example, the adhesive 423 can share any or all properties with the adhesive 223 of FIG. 2C. However, note that the adhesive 423 need not be as thick as the adhesive 223 (e.g., at block 325) because the adhesive 423 does not receive the die interconnect structure of the functional die.

In general, block 320 may include receiving, manufacturing and/or preparing the first carrier. Accordingly, the scope of the present disclosure should not be limited by the particular conditions under which the carrier is received, any particular manner of manufacturing the carrier and/or the nature of any particular manner of preparing such carrier for use.

The exemplary method 300 couples the functional die to the carrier at block 325 (e.g., to the top surface of the non-conductive carrier, to the metal pattern on the top surface of the carrier, to the RD structure on top of the carrier, etc.) Or mounting). Block 325 may include performing such a combination in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 325 can share any or all properties with other die mounting steps discussed in, for example (eg, block 125 of example method 100 of FIG. 1 ). have.

Various exemplary aspects of block 325 are shown in example 400D shown in FIG. 4D. Example 400D may share any or all properties with example 200D in FIG. 2D. For example, an instance of a functional die 401-404 (e.g., die 411 and/or 412) is a functional die 201-204 of FIG. 2D (e.g., die 211 and/or 212) ) And any or all properties (eg, die interconnect structures 213 and 214 do not extend into adhesive 223 ).

In example 400D, each active surface of functional die 401-404 is shown as bonded to adhesive 423, but the scope of the present disclosure is not limited to such orientation. In an alternative implementation, each inactive side of the functional die 401-404 can be mounted to the adhesive 423 (eg, the functional die 404-404 is later connected via a silicon via or other structure to the die). Can be connected to, etc.).

In general, block 325 may include bonding a functional die to a carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing such binding.

Exemplary method 300 may include an encapsulating step at block 330. Block 330 may include performing this encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 330 can share any or all properties with other encapsulants discussed herein (eg, block 130, etc., of exemplary method 100 of FIG. 1).

Various exemplary aspects of block 330 are shown in example 400E shown in FIG. 4E. For example, the encapsulating material 426' (and/or its formation) may share any or all properties with the encapsulating material 226' (and/or its formation) of FIG. 2E.

In general, block 330 may include an encapsulation step. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such encapsulation, any particular type of encapsulating material, and the like.

Exemplary method 300 may include grinding (or otherwise thinning (thinning) or planarizing) the encapsulating material at block 335. Block 335 may include performing such grinding (or any thinning or planarization process) in any of the various ways a non-limiting example is provided herein. For example, block 335 may share any or all properties with other grinding (or thinning or planarization) discussed herein (eg, block 135 of exemplary method 100 of FIG. 1 ). ) Etc).

Various exemplary aspects of block 335 are shown in example 400F shown in FIG. 4F. An example of grinding (or thinning or flattening, etc.) the encapsulating material 426 (and/or its formation) shares any or all properties with the encapsulant material 226 (and/or its formation) of FIG. 2F can do.

In general, block 335 may include grinding (or otherwise thinning or flattening) the encapsulating material. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

The exemplary method 300 can include attaching a second carrier at block 340. Block 340 can include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 340 can share any or all properties with any carrier attachments discussed herein (eg, block 140, etc. of the exemplary method 100 of FIG. 1).

Various exemplary aspects of block 340 are shown in example 400G shown in FIG. 4G. The second carrier 431 (and/or attachment thereof) may share any or all properties with the second carrier 231 of FIG. 2G, for example.

In general, block 340 may include attaching a second carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way and/or any particular type of second carrier to perform this attachment.

The exemplary method 300 can include removing the first carrier at block 345. Block 345 can include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 345 can share any or all properties with any carrier removal discussed herein (eg, block 145 of example method 100 shown in FIG. 1, etc.). have.

Various exemplary aspects of block 345 are shown in example 400H shown in FIG. 4H (FIG. 4H-1). For example, with respect to example 400G, the first carrier 421 has been removed.

In general, block 345 may include removing the first carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing such removal.

Exemplary method 300 may include forming an interconnect structure at block 347. Block 347 can include forming interconnect structures in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 347 can share any or all properties with other interconnect structure forming processes (or steps or blocks) discussed herein (eg, shown in FIG. 1 and discussed herein). With respect to block 110 of the exemplary method 100).

Various exemplary aspects of block 347 are shown in example 400H-2 of FIG. 4H (FIG. 4H-2). The first die interconnect structure 413 (and/or formation thereof) of FIG. 4H-2 will share any or all properties with the first die interconnect structure 213 (and/or formation thereof) of FIG. 2A. Can be. Similarly, the second die interconnect structure 414 (and/or formation thereof) of FIG. 4H-2 is any or all of the characteristics of the second die interconnect structure 214 (and/or formation thereof) of FIG. 2A. To share.

Exemplary implementation 400H-2 includes passivation layer 417 (or repassivation layer). Although not shown in the example implementations of FIG. 2A and/or other example implementations presented herein, such example implementations may also include such a passivation layer 417 (eg, functional die and die interconnection). Between the base of the structure and/or die interconnect structure, between the connection die and the base of the connection die interconnect structure and/or the connection die interconnect structure, etc.). Block 347 can include, for example, forming such a passivation layer 417 in a scenario where such a passivation layer 417 has not yet been formed prior to block 347. Note that the passivation layer 417 can also be omitted.

For example, in an exemplary implementation where a functional die is received or formed with an external inorganic dielectric layer, the passivation layer 417 can include an organic dielectric layer (eg, including any organic dielectric layer discussed herein). have.

The passivation layer 417 (and/or formation thereof) can include the properties of any (and/or formation thereof) of the passivation (or dielectric) layer discussed herein. The first die interconnect structure 413 and the second die interconnect structure 414 can be electrically connected to the functional dies 401-404 through, for example, each opening of the passivation layer 417.

Although passivation layer 417 is shown formed on molding layer 426 and functional dies 401-404, passivation layer 417 can also be directly above functional die 401-404 (e.g., block 310 In) can be formed. In this exemplary implementation, the outer surface of the passivation layer 417 (eg, the surface of the passivation layer 417 faces up in FIG. 4H-2) is coplanar with the corresponding surface of the encapsulating material 426. May be present (eg, the surface of the encapsulating material 426 faces up in FIG. 4H-2).

In general, block 347 can include forming an interconnect structure. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of forming or any specific nature of the interconnect structure.

Exemplary method 300 may include attaching (or joining or mounting) a connection die to a functional die at block 350. Block 350 may include performing this attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 350 shares any or all properties with, for example, any die attachment discussed herein (e.g., block 150 of exemplary method 100 of FIG. 1, etc.). can do.

Various exemplary aspects of block 350 are shown in example 400I shown in FIG. 4I. Connecting die 416b, functional die 401-404, and/or connecting these die to each other is, for example, connecting die 216b, functional die 201-204 and/or the example shown in FIG. 2I The connection of these dies to each other of 200I and any or all characteristics may be shared.

In general, block 350 may include attaching a connecting die to the functional die. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of performing such attachment and/or any particular structure used to perform such attachment.

The example method 300 can include underfilling the connecting die at block 355. Block 355 may include performing this underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 355 is for example any underfill discussed herein (e.g., block 155 and/or block 175 of exemplary method 100 of FIG. 1, etc.) and any or all properties To share.

Various exemplary aspects of block 355 are shown in example 400J shown in FIG. 4J. For example, the underfill 423 of FIG. 4J (and/or its formation) may share any or all properties with the underfill 223 of FIG. 2J (and/or its formation). It is noted that, as with any of the underfills discussed herein, various example implementations may omit performing such underfills.

In general, block 355 may include underfilling the connecting die. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of underfill material or any particular way of performing this underfill.

The exemplary method 300 can include removing the second carrier at block 360. Block 360 may include removing the second carrier in any of a variety of ways, a non-limiting example of which is provided herein. For example, block 360 (eg, block 145 and/or block 160 of example method 100 of FIG. 1, block 160, block 345, etc.) can be used with any carrier removal or All characteristics can be shared.

Various exemplary aspects of block 360 are present in example 400K shown in FIG. 4K. For example, comparing Figure 4K with Figure 4J, the second carrier 431 is removed.

In general, block 360 may include removing the second carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing such removal.

Exemplary method 300 may include a singulation step at block 365. Block 365 may include performing such singulation in any of a variety of ways, the non-limiting examples of which are discussed herein. Block 365 may include any singulation and any or all properties discussed herein (eg, as discussed in relation to block 165 of example method 100 of FIG. 1, etc.). Share it.

Various exemplary aspects of block 365 are shown in example 400L shown in FIG. 4L. The singulated structure (e.g., corresponding to the two encapsulant material portions 426a and 426b), for example, the singulated structure of FIG. 2L (e.g., two encapsulant material portions 226a And 226b).

In general, block 365 may include singulation. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular singulation scheme.

Exemplary method 300 may include mounting to a substrate at block 370. Block 370 can include, for example, performing such mounting (or joining or attaching) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 370 may be any of any of the mounting (or coupling or attaching) discussed herein (eg, with respect to block 170, etc. of the exemplary method 100 shown in FIG. 1 ). Let's or share all the characteristics.

Various exemplary aspects of block 370 are shown in example 400M shown in FIG. 4M. For example, the substrate 488 (and/or attachment to such substrate 288) may be any or all of the substrate 288 (and/or attachment to such substrate 288) of the example 200M of FIG. 2M. Share characteristics.

In general, block 370 may include mounting to a substrate. Accordingly, the scope of the present disclosure should not be limited by the nature of the substrate or any particular manner of mounting to any particular type of substrate.

The example method 300 can include, at block 375, performing an underfill between the substrate and the assembly (or module) mounted to the block 370. Block 375 may include performing underfilling in any of a variety of ways, non-limiting examples of which are provided herein as follows. Block 375 can share any or all properties with, for example, the underfilling (or encapsulation) process discussed herein (eg, with respect to block 355, FIG. 1 ). Blocks (155 and 175, etc.) of the exemplary method 100).

Various aspects of block 375 are shown in example 400N shown in FIG. 4N. The underfill 424 (and/or formation thereof) may share any or all properties with the example underfill 224 (and/or formation thereof) shown in example 200N in FIG. 2N, for example. Note that, as with any underfill discussed herein, the underfill of block 375 can be omitted or performed at another point in the method.

Generally, block 375 may include underfilling between the substrate and the assembly mounted on the substrate. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of mounting on a substrate or any particular type of substrate.

Exemplary method 300 may include performing continuous processing at block 390. Such continuous processing can include any of a variety of properties, non-limiting examples of which are provided herein. For example, block 390 can share any or all properties with block 190 of the exemplary method 100 of FIG. 1 discussed herein.

For example, block 390 can include returning the execution flow of the example method 300 to any block. Also, for example, block 390 may include sending the execution flow of example method 300 to any other method block (or step) discussed herein (eg, the example of FIG. 1. Method 100, exemplary method 500 of FIG. 5, exemplary method 700 of FIG. 7, and the like).

For example, block 390 can include forming interconnect structures 499 (eg, conductive balls, bumps, pillars, etc.) on the bottom surface of the substrate 488.

Also, for example, as shown in the example 200O of FIG. 2O, the example 200P of FIG. 2P, and the example 200Q of FIG. 2Q, block 390 forms the encapsulant material and/or underfill. And (or skipping formation).

In various example implementations discussed herein, the functional die is mounted to the carrier before the connecting die is attached to the functional die. The scope of the present disclosure is not limited to this mounting order. A non-limiting example will now be presented in which the connecting die is mounted to the carrier before being attached to the functional die.

5 shows a flow diagram of an example method 500 of manufacturing an electronic device in accordance with various aspects of the present disclosure. Exemplary method 500 may share any or all properties with, for example, any other exemplary method(s) discussed herein (eg, exemplary method 100 of FIG. 1, FIG. The exemplary method 300 of 3, the exemplary method 700 of FIG. 7, etc.). 6A-6M illustrate cross-sectional views illustrating exemplary electronic devices (eg, semiconductor packages, etc.) and exemplary methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure. 6A-6M can illustrate an example electronic device at various blocks (or steps) of the method 500 of FIG. 5, for example. 5 and 6a-6m will now be discussed together. It should be noted that the order of example blocks of method 500 may vary without departing from the scope of the present disclosure.

The exemplary method 500 can begin executing at block 505. Method 500 can initiate execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, the method 500 can automatically initiate execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations in response to signals from a central manufacturing line controller or the like. 500 may start execution in response to an operator command to start. Additionally, for example, method 500 can initiate execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Exemplary method 500 may include receiving, manufacturing, and/or preparing a plurality of functional dies at block 510. Block 510 can include receiving, manufacturing and/or preparing a plurality of functional dies in any of a variety of ways, where non-limiting examples are provided herein. For example, block 510 can share any or all properties with block 310 of the example method 300 shown in FIG. 3 and discussed herein. Various aspects of block 510 are shown in the examples 400A-1 to 400A-4 shown in FIG. 4A. It is noted that block 510 can also share any or all properties with block 110 of the exemplary method 100 shown and discussed herein, for example, in FIG. 1.

The functional dies 611a and 612a (and/or their formation) shown in the majority of FIGS. 6A-6M can share any or all properties with, for example, the functional dies 411 and 412 (and/or Teeth formation). For example and without limitation, functional dies 611 and 612 can include the properties of any of a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies or components) Etc).

In general, block 510 may include receiving, manufacturing and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by any particular way of performing such reception and/or manufacturing, or by any particular nature of such a functional die.

Exemplary method 500 may include receiving, manufacturing, and/or preparing a connection die at block 515. Block 515 can include receiving and/or manufacturing a plurality of connection dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 515 can share any or all properties with block 115 of the exemplary method 100 shown in FIG. 1 and discussed herein. Various exemplary aspects of block 515 are presented in the examples 200B-1 and 200B-7 shown in FIGS. 2B-1-2B-2. It is noted that block 515 can also share any or all properties with block 315 of the example method 300 shown in FIG. 3 and discussed herein, for example.

A number of connection dies 616b and connection die interconnect structures 617 (and/or formations thereof) as shown in FIGS. 6A-6M are, for example, the connection dies of FIGS. 2B-1-2B-2 ( 216b) and any or all properties with connecting die interconnect structures 217 (and/or formation thereof).

Note that the connecting die interconnect structure 617 (and/or formation thereof) can share any or all properties with, for example, the first die interconnect structure 213 (and/or formation thereof). For example, in an implementation example, instead of the first die interconnect structure, such as the first die interconnect structure 213 of FIG. 2A formed on the functional die 211/212, the same or similar on the connection die 616b A connecting die interconnect structure 617 can be formed.

In general, block 515 can include receiving, manufacturing and/or preparing a connection die. Accordingly, the scope of the present disclosure should not be limited by any particular manner of such reception, fabrication and/or preparation, or by any particular nature of such a connection die.

Exemplary method 500 may include, at block 520, receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure) thereon. Block 520 may include performing such receiving, manufacturing and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 520 is, for example, with respect to block 320 of the exemplary method 300 of FIG. 3 (eg, with respect to block 120 of the exemplary method 100 of FIG. 1 ), Etc.) Any or all of the characteristics can be shared with any or all of the characteristics of carrier reception, manufacture and/or preparation discussed herein. Various exemplary aspects of block 520 are provided in example 600A of FIG. 6A. do.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (eg, bulk silicon, bulk glass, bulk metal, etc.). Any or all of these carriers may include (or instead) a signal redistribution (RD) structure on the bulk material. Block 520 provides an example of receiving, manufacturing and/or preparing such a carrier.

Block 520 can include forming RD structure 646a on bulk carrier 621a in any of a variety of ways, non-limiting examples of which are presented herein. In an exemplary implementation, one or more to distribute electrical connections in a lateral and/or vertical direction to a second die interconnect structure 614 (formed later) that will ultimately be connected to functional dies 611 and 612 (connected later). A dielectric layer and one or more conductive layers can be formed.

6A shows an example in which the RD structure 646a includes three dielectric layers 647 and three conductive layers 648. This number of layers is merely an example, and the scope of the present disclosure is not limited thereto. In other exemplary implementations, the RD structure 646a can include a single dielectric layer 647 and a single conductive layer 648, two of each layer, and the like. An exemplary redistribution (RD) structure 646a is formed on the bulk carrier 621a material.

The dielectric layer 647 can be formed of any of a variety of materials (eg, Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy or other insulating materials). The dielectric layer 647 can be formed using any of a variety of processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layer 647 can be patterned, for example, to expose various surfaces (eg, to expose the bottom traces or pads of conductive layer 648).

The conductive layer 648 can be formed of any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, and the like). The conductive layer 648 can be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

Redistribution structure 646a can include, for example, a conductor exposed on an outer surface (eg, exposed on the top surface of example 600A). Such exposed conductors can be used, for example, to attach (or form) die interconnect structures (eg, block 525, etc.). In this implementation, the exposed conductor can include a pad, for example, a low bump metal (UBM) formed thereon to enhance the attachment (or formation) of the die interconnect structure. Such under bump metals may include, for example, one or more Ti, Cr, Al, TiW, TiN layers or other electrically conductive materials.

Examples of redistribution structures and/or their formation are filed August 11, 2015 and named "Semiconductor Package and Method for Manufacturing It", US Patent Application No. 14/823,689 and "Semiconductor Package and Method for Manufacturing It" U.S. Patent No. 8,362,612, the content of each of which is incorporated herein by reference in its entirety.

Redistribution structure 646a may, for example, perform fan-out redistribution of at least some electrical connections, such as die interconnect structures (e.g., from at least a portion of die interconnect structure 614 (to be formed)). 614) the electrical connection in the lateral direction out of the footprint of the functional dies 611 and 612 to be attached. Redistribution structure 646a, for example, can also perform fan-in redistribution of at least some electrical connections, for example, connection die 616b from at least a portion of die interconnect structure 614 (to be formed). The electrical connection is transferred to the location inside the footprint of (to be connected) and/or the location inside the footprint of the functional dies 611 and 612 (to be connected). Redistribution structure 646a may also provide, for example, a connection of various signals between functional dies 611 and 612 (eg, in addition to the connection provided by connection die 616b).

In various example implementations, block 520 may include forming only the first portion 646a of the entire RD structure 646, where the second portion 646b of the entire RD structure 646 is later ( For example, at block 570).

In general, block 520 may include receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure thereon. Accordingly, the scope of the present disclosure should not be limited by any particular way of making such a carrier and/or signal redistribution structure or by any particular property of such a carrier and/or signal redistribution structure.

Exemplary method 500 may include forming a tall (high) die interconnect structure on the RD structure at block 525 (eg, as provided at block 520). . Block 525 can include forming a toll die interconnect structure on the RD structure in any of a variety of non-limiting examples provided herein.

Block 525 provides, for example, any or all and any or all of the properties of the functional die receiving, manufacturing and/or preparation discussed herein (eg, the properties of forming the second die interconnect structure, etc.). Can be shared (e.g., with the formation of block 110 and second die interconnect structure 214 of exemplary method 100 of FIG. 1 and/or formation of first die interconnect structure 213). , With the formation of block 347 and second die interconnect structure 414 of the exemplary method 300 of FIG. 3, etc.).

Various exemplary aspects of block 525 are provided in example 600B in FIG. 6B. The tall (tall) interconnect structure 614 (and/or its formation) is the second die interconnect structure 214 (and/or its formation) of FIG. 2A and/or the second of FIG. 4H-2. Any or all properties may be shared with the two die interconnect structure 414 (and/or formation thereof).

In general, block 525 may include forming a toll die interconnect structure on the RD structure (eg, as provided at block 520). Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of forming such a toll die interconnect structure and/or any particular type of toll interconnect structure.

Exemplary method 500 may include mounting the connection die to the RD structure at block 530 (eg, as provided at block 520). Block 530 can include performing such mounting (or attachment or engagement) in any of a variety of ways, non-limiting examples of which are provided herein. Block 530 can share any or all properties with, for example, any die attachment discussed herein (eg, a block of the exemplary method 300 shown in FIG. 3 and discussed herein ( 325), to block 125 of the exemplary method 100 shown in FIG. 1 and discussed herein, etc.) Various exemplary aspects of block 530 are presented in example 600C shown in FIG. 6C. have.

Block 530 can include attaching the back side of connection die 616b to RD structure 646a, for example, using a die-adhesive adhesive (eg, tape, liquid, paste, etc.). . In FIG. 6C, connecting die 616b is shown coupled to the dielectric layer of RD structure 646a, but in other exemplary embodiments, the back side of connecting die 616b may be coupled to a conductive layer (eg For enhanced heat dissipation and to provide additional structural support).

Also, as discussed herein, any connecting die discussed herein can be two-sided. In this exemplary implementation, the back interconnect structure can be electrically connected to the corresponding interconnect structure of the RD structure 646a (eg, pads, lands, bumps, etc.).

Generally, block 530 may include mounting a connection die to an RD structure (eg, as provided in block 520). Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of mounting the connection die.

Exemplary method 500 may include an encapsulating step at block 535. Block 535 can include performing this encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Block 535 can, for example, share any or all properties with other encapsulating blocks (or steps) discussed herein (eg, of the exemplary method 100 of FIG. 1 ). Block 130, block 330 of the exemplary method 300 of FIG. 3, etc.)). Various exemplary aspects of block 535 are shown in FIG. 6D.

Block 535 can include, for example, performing a wafer (or panel) level molding process. As discussed herein, before individualizing individual modules, any or all of the process steps discussed herein can be performed at the panel or wafer level. Referring to the exemplary implementation 600D shown in FIG. 6D, the encapsulating material 651' is the top surface of the RD structure 646a, toll pillar 614, connecting die interconnect structure 617, connecting die At least a portion (or both) of the top (or active or front) side of 166b and the side side of connection die 616b.

Encapsulating material 651 ′ (as shown in FIG. 6D) is shown as covering the top of toll interconnect structure 614 and connecting die interconnect structure 617, but either of these ends or All can be exposed from the encapsulating material 651' (as shown in Figure 6E). Block 535 may include, for example, initially forming the upper ends of the various interconnects that are exposed or projected with encapsulant material 651' (eg, film assisted molding technology, die- Using seal forming technology, etc.). Alternatively, block 535 is sufficiently susceptible to expose the top surface of some or all of the toll interconnect structure 614 and connecting die interconnect structure 617 after forming the encapsulant material 651'. Encapsulant material (651')? To do so, it can include a thinning (thinning) (or planarizing or grinding) process (eg, performed at block 540).

In general, block 535 may include an encapsulation step. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way or any particular type of encapsulating material or construction thereof to perform such encapsulation.

Exemplary method 500 may include grinding encapsulating material and/or various interconnect structures at block 540. Block 540 can include, by way of non-limiting example, performing such grinding (or any thinning or planarization) in any of a variety of ways provided herein. Various exemplary aspects of block 540 are shown in example 600E shown in FIG. 6E. Block 540 can, for example, share any or all properties with other grinding (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various exemplary implementations, encapsulant material 651' may initially be formed to a thickness greater than desired and/or toll interconnect structure 614 and connect die interconnect Structure 617 may initially be formed to a thickness greater than desired. In this exemplary implementation, block 540 is performed to grind (or otherwise thin or planarize) encapsulant material 651', toll interconnect structure 614 and/or connecting die interconnect structure 617. Can be. The encapsulant material 651, the toll interconnect structure 614 and/or the connection die interconnect structure 617 (as shown in FIG. 6E), the encapsulant material 651 and the interconnect structure 613 and 617). The top surface of the ground encapsulant material 651, the top surface of the toll interconnect structure 614 and/or the top surface of the connection die interconnect structure 617 can be, for example, coplanar.

In various exemplary implementations, the top surface of the toll interconnect structure 614 and/or the top surface of the connection die interconnect structure 617 may be formed of encapsulating material 651 using, for example, a chemical or mechanical process. Note that it may protrude from the top surface. The encapsulating material 651 is thinner than the wiring structures 614 and/or 617 using a film assisted and/or sealed molding process, etc., at block 535.

In general, block 540 may include grinding (or thinning or planarizing) the encapsulating material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

Exemplary method 500 may include attaching (or joining or mounting) a functional die to a toll interconnect structure and a connect die interconnect structure at block 545. Block 545 can include performing this attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 545 can share any or all properties with, for example, any die attach process discussed herein. Various exemplary aspects of block 545 are presented in example 600F shown in FIG. 6F.

For example, the die interconnect structures (eg, pads, bumps, etc.) of the first functional die 611a are mechanically attached to each tall interconnect structure 614 and each connecting die interconnect structure 617. And it can be electrically connected. The pads, bumps, etc. of the second functional die 612a may be mechanically and electrically connected to each tall interconnect structure 614 and each connecting die interconnect structure 617.

These interconnect structures can be connected in a variety of ways. For example, the connection can be performed by solder. In an exemplary implementation, each interconnection structure of the toll die interconnection structure 614, the connection die interconnection structure 617 and/or the first 611a and second 612a functional dies is configured to perform a connection. And a solder cap (or other solder structure) that can be reflowed. Such solder caps can be reflowed, for example, by mass reflow, thermal compression bonding (TCB), or the like. In another exemplary implementation, the connection can be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding instead of using solder. Examples of such connections are US Patent Application No. 14/963,037, filed December 8, 2015 and named "Temporary Interface Gradient Bonding for Metal Bonding," and January 6, 2016, "Interlocking Metals- A semiconductor product having a metal bond and a method for manufacturing the same are provided in US Patent Application No. 14/989,455, the entire contents of each of which are incorporated herein by reference. Any of a variety of techniques can be used to attach the functional die interconnect structure to the toll interconnect structure 614 and the connection die interconnect structure 617 (eg, mass reflow, thermocompression bonding (TCB). , Direct metal-to-metal metal bonding, conductive adhesives, etc.).

As shown in the exemplary implementation 600F, the first connecting die interconnect structure 617 of the connecting die 616b is connected to each interconnect structure of the first functional die 611a, and the connecting die 616b )'S second connecting die interconnect structure 617 is connected to each interconnect structure of the second functional die 612a. As connected, the connection die 616b provides an electrical connection between the various die interconnect structures of the first functional die 611a and the second functional die 612a through the RD structure 298 of the connection die 616b. (For example, as shown in the example of FIG. 2B-1 (200B-4), etc.).

In the example 600F shown in FIG. 6F, the height of the toll interconnect structure 614 may include, for example, the support layer 290b and the connection die 616b of the connection die interconnect structure 217 and the connection die 616b. It can be equal to or greater than the combined height of the adhesive or other means used to attach to the RD structure 646a.

In general, block 545 can include attaching (or joining or mounting) a functional die to a toll interconnect structure and a connection die interconnect structure. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing this attachment or the nature of any particular type of attachment structure.

The example method 500 can include underfilling the functional die at block 550. Block 550 can include performing this underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 550 is, for example, any underfill discussed herein (e.g., block 155 and/or block 175 of example method 100 of FIG. 1 and block 175 of example method of FIG. 3) (300, block 355 and/or block 375, etc.) may share any or all properties. Various exemplary aspects of block 550 are shown in example 600G shown in FIG. 6G.

An underfill may be applied between functional dies 611a and 612a and encapsulating material 651. In scenarios where pre-applied underfill (PUF) is used, such PUF may be applied to functional dies 611a and 612a and/or prior to bonding of the functional die, encapsulating material 651 and/or Can be coupled to the top exposed ends of the interconnect structures 614 and 617.

Block 550 may include forming an underfill after attachment performed at block 545 (eg, capillary underfill, injected underfill, etc.). As shown in the exemplary implementation 600G of FIG. 6G, the underfill material 661 (e.g., any underfill material discussed herein, etc.) is provided with the bottom and/or functionality of the functional dies 611a and 612a. The underfill material 661 can also fully or partially cover at least a portion (if not all) of the sides of the dies 611a and 612a (eg, as oriented in FIG. 6G ), for example encapsulating. Most (or all) of the top surface of material 651 may be covered. Underfill material 661 may, for example, surround each interconnection structure of functional dies 611a and 612a to which toll interconnection structure 614 and connection die interconnection structure 617 are attached. In an exemplary implementation where the ends of the toll interconnect structure 614 and/or the connection die interconnect structure 617 protrude from the encapsulant material 651, the underfill material 661 can also surround such protrusions. have.

In various example implementations of the example method 500, the underfill step performed at block 550 may be omitted. For example, underfill of the functional die may be performed in another block (eg, block 555, etc.). Also, for example, this underfill can be omitted entirely.

In general, block 550 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of underfill material or any particular way of performing this underfill.

Exemplary method 500 may include an encapsulating step at block 555. Block 555 can include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 555 can share any or all properties with other encapsulating blocks (or steps) discussed herein (eg, with block 535, the exemplary method of FIG. 1 ). (At block 130 of 100, and at block 330 of the exemplary method 300 of FIG. 3, etc.).

Various exemplary aspects of block 555 are shown in example 600H shown in FIG. 6H. For example, the encapsulating material 652' (and/or its formation) comprises the encapsulating material 226' (and/or its formation) of Figure 2E and the encapsulating material 426 of Figure 4K. (And/or formation thereof), and the encapsulating material 651 (and/or formation thereof) of FIG. 6D and the like, or any or all properties.

The encapsulating material 652' covers the top surface of the encapsulating material 651, covers the side sides of the underfill 661, and at least a portion of the side sides of the functional dies 611a and 612b (if not all) And the top surfaces of the functional dies 611a and 612b, and the like.

As discussed herein with respect to other encapsulant materials (e.g., encapsulant material 226', etc. of Figure 2E), encapsulant material 652' is a functional die of 611a and 612a. It need not be initially formed to cover the top surface. For example, block 555 can include using film assisted molding, sealing molding, and the like to form encapsulating material 652'.

In general, block 555 may include an encapsulation step. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such encapsulation, any particular type of encapsulating material, and the like.

Exemplary method 500 may include grinding (or running thinning or planarizing) the encapsulant material at block 560. Block 560 can include performing this grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 560 can share any or all properties with, for example, other grinding (or thinning) blocks (or steps) discussed herein (eg, the exemplary method of FIG. 1 ( Block 135 of block 100, block 335 of example method 300 of FIG. 3, block 540, etc.).

Various exemplary aspects of block 560 are presented in example 600I shown in FIG. 6I. An example of grinding (or thinning or flattening, etc.) the encapsulating material 652 (and/or forming thereof), along with the encapsulating material 226 (and/or forming thereof) of FIG. Together with the encapsulating material 426 (and/or formation thereof), any or all properties may be shared with the encapsulating material 651 of FIG. 6E (and/or formation thereof) and the like.

Block 560 may include, for example, grinding encapsulating material 652 and/or functional dies 611a and 612a, such that the top surface of encapsulating material 652 is a functional die It may be coplanar with the top surface of 611a and/or the top surface of functional die 612a.

In general, block 560 may include grinding (or thinning or flattening running) the encapsulating material. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

Exemplary method 500 may include removing a carrier at block 565. Block 565 can include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 565 can share any or all properties with any carrier removal process discussed herein (eg, block 145 and/or in exemplary method 100 of FIG. 1 and/or Or block 160, block 345 and/or block 360 of the exemplary method 300 of FIG. 3, etc.). Various exemplary aspects of block 565 are shown in example 600J in FIG. 6J.

For example, the example 600J in FIG. 6J shows that the first carrier 621a has been removed (eg, compared to the example 600I in FIG. 6I ). Block 565 can include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical-mechanical planarization, peeling, shearing, heat or laser emission, etc.). In addition, for example, block 565 may include removing the adhesive layer, if, for example, an adhesive layer is used during the formation of RD structure 646a at block 520.

Note that in various exemplary implementations, a second carrier can be used, as shown and discussed herein with respect to the exemplary methods 100 and 300 of FIGS. 1 and 3 (eg, encapsulation). Rating material 652 and/or bonded to functional dies 611a and 612a). In other example implementations, various tooling structures can be used in place of the carrier.

In general, block 565 may include removing the carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular type of carrier removal or the nature of any particular type of carrier.

Exemplary method 500 may include completing the signal redistribution (RD) structure at block 570. Block 570 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 570 can share any or all properties with, for example, block 520 (eg, with respect to RD structures forming aspects of block 520). Various aspects of block 570 are shown in example 600K shown in FIG. 6K.

As discussed herein, for example, with respect to block 520, the carrier may receive (or be manufactured or prepared) with only a portion of the desired RD structure formed. In this example scenario, block 570 may include completing the formation of the RD structure.

Referring to FIG. 6K, block 570 forms a second portion of the RD structure 646b on the first portion of the RD structure 646a (eg, the first portion of the RD structure 646a is Block 520, including those received, manufactured, or prepared). Block 570 can include, for example, forming a second portion of RD structure 646b in the same way that a first portion of RD structure 646a is formed.

Note that in various implementations, the first portion of the RD structure 646a and the second portion of the RD structure 646b can be formed using different materials and/or different processes. For example, the first portion of the RD structure 646a can be formed using an inorganic dielectric layer, and the second portion of the RD structure 646b can be formed using an organic dielectric layer. Also, for example, the first portion of the RD structure 646a may be formed to have a finer pitch (or thinner trace, etc.), and the second portion of the RD structure 646b may have a larger pitch (or thicker) Traces, etc.). ). Also, for example, the first portion of the RD structure 646a can be formed using a back end of line (BEOL) semiconductor wafer fabrication (fab) process, and the second portion of the RD structure 646b is post- It may be formed using a fab electronic device packaging process. Also, the first portion of the RD structure 646a and the second portion of the RD structure 646b can be formed in different geographic locations.

Like the first portion of the RD structure 646a, the second portion of the RD structure 646b can have any number of dielectric and/or conductive layers.

As discussed herein, the interconnect structure can be formed on the RD structure 646b. In this exemplary implementation, block 565 can include forming under bump metallization (UBM) on the exposed pads to enhance the formation (or attachment) of this interconnect structure.

In general, block 570 may include completing a signal redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of signal distribution structure or any particular type of signal distribution structure.

The exemplary method 500 can include forming an interconnect structure on the redistribution structure at block 575. Block 575 can include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 575 can share any or all properties with any interconnect structures discussed herein.

Various exemplary aspects of block 575 are shown in example 600L shown in FIG. 6L. Exemplary interconnect structures 652 (eg, package interconnect structures, etc.) can include any of a variety of interconnect structures. For example, the package interconnect structure 652 can include conductive balls (eg, solder balls, etc.), conductive bumps, conductive pillars, wires, and the like.

Block 575 can include forming interconnect structure 652 in any of a variety of ways. For example, the interconnect structure 652 can be pasted and/or printed on the RD structure 646b (eg, into each pad 651 and/or UBM) and then reflowed. Also, for example, it can be pre-formed before attaching the interconnect structures 652 (eg, conductive balls, conductive bumps, pillars, wires, etc.) and then, for example, reflow, plating , Epoxide, wire bond, etc., to the RD structure 646b.

As discussed above, the pad 651 of the RD structure 646b may be used to assist in the formation of interconnect structures (e.g., building, attachment, bonding, deposition, etc.) under bump metal (UBM) or Note that it can be formed by any metallization. Such UBM formation can be performed at block 570 and/or block 575, for example.

In general, block 575 may include forming an interconnect structure on the redistribution structure. Accordingly, the scope of the present disclosure should not be limited by any particular way of forming these interconnect structures or by any particular properties of the interconnect structures.

Exemplary method 500 may include a singulation step at block 580. Block 580 may include performing such singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 580 can share any or all properties with, for example, any singulation discussed herein (eg, with respect to block 365 of example method 300 of FIG. 3 ). As discussed, in relation to block 165 of the exemplary method 100 of FIG. 1 ).

Various exemplary aspects of block 580 are shown in example 600M shown in FIG. 6M. The singulated structure (e.g., corresponding to the encapsulant material portion 652a) is, for example, with the singulated structure of FIG. 2L (e.g., two encapsulant material portions 226a) And 226b), together with the singulated structure of FIG. 4L (eg, corresponding to two encapsulant material portions 426a and 426b).

In general, block 580 may include singulation. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular singulation scheme.

Exemplary method 500 may include performing continuous processing at block 590. Such continuous processing can include any of a variety of properties, non-limiting examples of which are provided herein. For example, block 590 may share any or all of the characteristics of block 190 of example method 100 of FIG. 1, block 390 of example method 300 of FIG. 3, and the like.

For example, block 590 can include returning the execution flow of the exemplary method 500 to any block. Also, for example, block 590 can include sending the execution flow of example method 500 to any other method block (or step) discussed herein (eg, the example of FIG. 1. With method 100, with example method 300 in FIG. 3, with example method 700 in FIG. 7, etc.).

For example, as shown in the example 200 of FIG. 2O, the example 200P of FIG. 2P, and the example 200Q of FIG. 2Q, block 590 forms an encapsulant material and/or an underfill ( Or skipping formation).

As discussed herein, the functional die and connecting die can be mounted to a substrate, for example in a multi-chip module configuration. Non-limiting examples of such a configuration are shown in FIGS. 9 and 10.

7 shows a flow diagram of an example method 700 of manufacturing an electronic device in accordance with various aspects of the present disclosure. Exemplary method 700 can share any or all properties with, for example, any other exemplary method(s) discussed herein (eg, exemplary method 100 of FIG. 1, FIG. The exemplary method 300 of 3, the exemplary method 500 of FIG. 5, etc.). 8A-8N illustrate cross-sectional views illustrating exemplary electronic devices (eg, semiconductor packages, etc.) and exemplary methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure. 8A-8N can illustrate an example electronic device at various blocks (or steps) of the method 700 of FIG. 7, for example. 7 and 8a-8n will now be discussed together. It should be noted that the order of example blocks of method 700 may vary without departing from the scope of the present disclosure. In an exemplary implementation, the method 700 of FIG. 7 can be considered similar to the method of FIG. 5 by adding block 742 to form a second redistribution structure.

The example method 700 can begin executing at block 705. Method 700 can initiate execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, the method 700 can automatically initiate execution in response to one or more signals received from one or more upstream and/or downstream manufacturing stations in response to signals from a central manufacturing line controller or the like. Method 700 can begin execution in response to an operator command to start. Additionally, for example, method 700 can initiate execution in response to receiving an execution flow from any other method block (or step) discussed herein.

The example method 700 can include receiving, manufacturing and/or preparing a plurality of functional dies at block 710. Block 710 can include receiving, manufacturing, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 710 is block 310 of the exemplary method 300 shown in FIG. 3 and discussed herein, block 510 of the exemplary method 500 shown in FIG. 5 and discussed herein. And any or all characteristics. Various aspects of block 710 are shown in examples 400A-1 to 400A-4 shown in FIG. 4A. It is noted that block 710 can also share any or all properties with block 110 of the example method 100 shown and discussed herein, for example, in FIG. 1.

The plurality of functional dies 811a and 812a (and/or their formation) shown in FIGS. 8A-8N are, for example, functional dies 611a and 612a (and/or formations thereof), functional dies 411 and 412 (And/or formation thereof), functional dies 211 and 212 (and/or formation thereof), and any or all other properties. For example and without limitation, functional dies 811a and 812a may include the properties of any of a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies). Or components, etc.).

In general, block 710 may include receiving, manufacturing and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by any particular way of performing such reception and/or manufacturing, or by any particular nature of such a functional die.

Exemplary method 700 may include receiving, manufacturing, and/or preparing a connection die at block 715. Block 715 can include receiving and/or manufacturing a plurality of connection dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 715 can share any or all properties with block 115 of the example method 100 shown in FIG. 1 and discussed herein. Various exemplary aspects of block 715 are presented in the examples 200B-1 and 200B-7 shown in FIGS. 2B-1-2B-2. Block 715 may also be any block with block 315 of the exemplary method 100 illustrated in FIG. 3 and discussed herein, and with block 515 of the exemplary method 500 illustrated in FIG. 5, for example. Or note that you can share all the characteristics.

A number of connection dies 816b and connection die interconnect structures 817 (and/or formations thereof) as shown in FIGS. 8A-8N are for example the connection dies 216B of FIGS. 2B-1-2B-2 ) And connecting die interconnect structures 217 (and/or formations thereof).

Note that the connecting die interconnect structure 817 (and/or formation thereof) can share any or all properties with, for example, the first die interconnect structure 213 (and/or formation thereof). For example, in an implementation example, instead of a first die interconnect structure such as the first die interconnect structure 213 of FIG. 2A formed on the functional die 211/212, the same or similar on the connection die 816b A connecting die interconnect structure 817 can be formed.

In general, block 715 may include receiving, manufacturing and/or preparing a connection die. Accordingly, the scope of the present disclosure should not be limited by any particular manner of such reception, fabrication and/or preparation, or by any particular nature of such a connection die.

Exemplary method 700 may include, at block 720, receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure). Block 720 may include performing such receive manufacturing and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 720 may, for example, share any or all characteristics with any or all carriers during reception, manufacture and/or preparation discussed herein (eg, the exemplary method of FIG. 1 ( With respect to block 120 of 100), with respect to block 320 of exemplary method 300 of FIG. 3, and with respect to block 520 of exemplary method 500 of FIG. 5, etc.) . Various exemplary aspects of block 720 are provided in example 800A in FIG. 8A.

As discussed herein, any or all carriers discussed herein may include, for example, only bulk materials (eg, bulk silicon, bulk glass, bulk metal, etc.). Any or all of these carriers may include (or instead) a signal redistribution (RD) structure on the bulk material. Block 720 provides an example of receiving, manufacturing and/or preparing such a carrier.

Block 720 can include forming RD structure 846a in any of a variety of ways on bulk carrier 821a, non-limiting examples of which are presented herein. In an exemplary implementation, the one or more dielectric layers and the one or more conductive layers make electrical connections to the second redistribution structures 896 and/or the vertical interconnect structures 814 that will be electrically connected to the functional dies 811 and 812 (later connected). It can be formed to distribute in the lateral direction and/or in the vertical direction. RD structure 846a may thus be coreless. However, in various alternative implementations, the RD structure 846a can be a core structure.

8A shows an example in which the RD structure 846a includes three dielectric layers 847 and three conductive layers 848. This number of layers is merely an example, and the scope of the present disclosure is not limited thereto. In other exemplary implementations, the RD structure 846a can include a single dielectric layer 847 and a single conductive layer 848, two of each layer, and the like. An exemplary redistribution (RD) structure 846a is formed on the bulk carrier 821a material.

Dielectric layer 847 can be formed of any of a variety of materials (eg, Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy or other insulating materials). Dielectric layers 847 can be formed using various processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layers 847 can be patterned, for example, to expose various surfaces (eg, to expose the bottom trace or pad of conductive layer 848).

The conductive layer 848 can be formed on any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 848 can be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

Redistribution structure 846a can include, for example, a conductor exposed to an outer surface (eg, exposed to the top surface of example 800A). Such exposed conductors can be used, for example, to attach (or form) die interconnect structures (eg, block 725, etc.). In this implementation, the exposed conductor can include a pad, for example, an underbump metal (UBM) formed thereon to enhance the attachment (or formation) of the die interconnect structure. Such underbump metals may include, for example, one or more Ti, Cr, Al, TiW, TiN layers or other electrically conductive materials.

Examples of redistribution structures and/or their formation are US Patent Application Nos. 14/823,689, filed August 11, 2015 and entitled "Semiconductor Package and Method for Manufacturing It"; And U.S. Patent 8,362,612, entitled "Semiconductor Device and Method for Manufacturing It"; Each of these is incorporated herein by reference in its entirety.

Redistribution structure 846a may, for example, perform fan-out redistribution of at least some electrical connections, such as vertical interconnect structure 814 from at least a portion of vertical interconnect structure 814 (to be formed), for example. ) Through the electrical connection in the lateral direction to a location outside the footprint of the functional dies 811 and 812 to be attached. Also, for example, the redistribution structure 846a may perform fan-in redistribution of at least some electrical connections, for example, the connection die 816b from at least a portion of the vertical interconnect structure 814 (to be formed). The electrical connection is shifted laterally to the inner position of the footprint of the (to be connected) and/or the inner position of the footprint of the functional dies (811, 812) (to be connected). Redistribution structure 846a may also provide connections for various signals, for example, between functional dies 811 and 812 (eg, in addition to the connections provided by connection dies 816b).

In various example implementations, block 720 may include forming only the first portion 846a of the entire RD structure 846, where the second portion 846b of the entire RD structure 846 is later Can be formed (eg, at block 770).

In general, block 720 may include receiving, manufacturing and/or preparing a carrier having a signal redistribution (RD) structure thereon. Accordingly, the scope of the present disclosure should not be limited by any particular way of making such carrier and/or signal redistribution structures or by any particular property of such carrier and/or signal redistribution structures.

The exemplary method 700 can include forming a vertical interconnect structure on the RD structure at block 725 (eg, as provided at block 720 ). Block 725 can include forming a vertical interconnect structure on the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Note that vertical interconnect structures may also be referred to herein as toll bumps, toll pillars, toll posts, die interconnect structures, functional die interconnect structures, and the like.

Block 725 shares, for example, any or all properties (eg, second die interconnect structure formation properties, etc.) with any or all of the functional die reception, manufacture, and/or preparation discussed herein. (E.g., in connection with the formation of block 110 and second die interconnect structure 214 of exemplary method 100 of FIG. 1 and/or formation of first die interconnect structure 213) In connection with the formation of block 347 and second die interconnect structure 414 of the exemplary method 347 of FIG. 3, with respect to block 525 of the exemplary method 500 of FIG. 5) .

Various exemplary aspects of block 725 are provided in example 800B in FIG. 8B. The vertical interconnect structure 814 (and/or formation thereof) is the second die interconnect structure 214 of FIG. 2A (and/or formation thereof) and/or the second die interconnect structure 414 of FIG. 4H-2. ) (And/or its formation) and any or all properties. Further, the vertical interconnect structure 814 (and/or formation thereof) may share any or all properties with the interconnect structure 614 (and/or formation thereof) of FIG. 6B.

In general, block 725 may include forming a vertical interconnect structure on the RD structure (eg, as provided at block 720). Accordingly, the scope of the present disclosure should not be limited by the properties of any particular manner of forming such vertical interconnect structures and/or any particular type of vertical interconnect structures.

Exemplary method 700 may include mounting a connection die to an RD structure at block 730 (eg, as provided at block 720 ). Block 730 may include performing such mounting (or attaching or joining) in any of a variety of ways, non-limiting examples of which are provided herein. Block 730 can share any or all properties with, for example, any die attachment discussed herein (eg, a block of the exemplary method 500 shown in FIG. 5 and discussed herein ( With respect to block 325 of the exemplary method 300 shown and discussed herein in connection with FIG. 3, block 125 of the exemplary method 100 shown in FIG. 1 and discussed herein In relation to). Various exemplary aspects of block 730 are shown in example 800C shown in FIG. 8C.

Block 730 may include attaching the back side of connection die 816b to RD structure 846a using, for example, a die-adhesive adhesive (eg, tape, liquid, paste, etc.). . In FIG. 8C, connecting die 816b is shown coupled to the dielectric layer of RD structure 846a, but in other exemplary implementations, the back of connecting die 816b (eg, enhances heat dissipation, adds It can be coupled to the conductive layer) to provide structural support.

Also, as discussed herein, any connecting die discussed herein can be two-sided. In this exemplary implementation, the rear interconnection structure can be electrically connected to the corresponding interconnection structure (eg, pad, land, bump, etc.) of the RD structure 846a.

In general, block 730 may include mounting a connection die to the RD structure (eg, as provided in block 720). Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of mounting the connection die.

Exemplary method 700 may include an encapsulating step at block 735. Block 735 can include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Block 735 can, for example, share any or all properties with other encapsulating blocks (or steps) discussed herein (eg, with block 130 of exemplary method 100 of FIG. 1 ). , To block 330 of the exemplary method 300 of FIG. 3, to block 530 of the exemplary method 500 of FIG. 5, etc.). Various exemplary aspects of block 735 are shown in FIG. 8D.

Block 735 can include, for example, performing a wafer (or panel) level molding process. As discussed herein, before individualizing individual modules, any or all of the process steps discussed herein can be performed at the panel or wafer level. Referring to the example implementation 800D shown in FIG. 8D, the encapsulating material 851 ′ is an upper surface of the RD structure 846a, a vertical interconnect structure 814, a connection die interconnect structure 817, It may cover the top (or active or front) of the connecting die 816b, and at least a portion (or both) of the side sides of the connecting die 816b.

Although encapsulating material 851' (as shown in FIG. 8D) is shown covering the top of vertical interconnect structure 814 and connecting die interconnect structure 817, some or all of these ends It can be exposed from the encapsulating material 851' (as shown in Figure 8e). Block 735 may include, for example, initially forming an encapsulating material 851' with the tops of various interconnects exposed or projected (eg, film assisted molding technology, die-seal) Using molding techniques, etc.). Alternatively, block 735 forms encapsulating material 851', and then encapsulating material 851', such as vertical interconnect structure 814 and connecting die interconnect structure 817, is optional. Or performing a thinning (or planarizing or grinding) process (eg, performed at block 740) to be thin enough to expose the entire top surface.

In general, block 735 may include an encapsulation step. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way or any particular type of encapsulating material or construction thereof to perform such encapsulation.

Exemplary method 700 may include grinding encapsulating material and/or various interconnect structures at block 740. Block 740 can include performing such grinding (or any thinning or flattening) in any of a variety of ways, non-limiting examples of which are provided herein. Various exemplary aspects of block 740 are shown in example 800E shown in FIG. 8E. Block 740 can, for example, share any or all properties with other grinding (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various exemplary implementations, encapsulating material 851' may initially be formed to a thickness thicker than ultimately desired, and/or interconnection of vertical interconnect structures 814 and connecting dies. The connecting structure 817 can ultimately be formed with an initial thickness that is thicker than desired. In this exemplary implementation, block 740 may be performed to grind (or otherwise thin or planarize) encapsulating material 851', vertical interconnect structure 814 and/or connection die interconnect structure 817. Can be. In the example 800E shown in FIG. 8E, the encapsulating material 851, vertical interconnect structure 814 and/or connecting die interconnect structure 817 are encapsulated (as shown in FIG. 8E). Grinded to result in material 851 and vertical interconnect structure 814 and connecting die interconnect structure 817. The upper surface of the ground encapsulating material 851, the upper surface of the vertical interconnect structure 814 and/or the upper surface of the connecting die interconnect structure 817 can be, for example, coplanar.

In various exemplary implementations, the top surface of the vertical interconnect structure 814 and/or the top surface of the connection die interconnect structure 817 is, for example, the top of the encapsulating material 851 using a chemical or mechanical process. Note that it may protrude from the surface. The encapsulating material 851 is thinner than the vertical interconnect structure 814 and/or the connection die interconnect structure 817 using a film assist and/or seal forming process, etc., at block 735.

In general, block 740 may include grinding (or thinning or planarizing) the encapsulating material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

The exemplary method 700 can include forming a second signal redistribution (RD) structure (or distribution structure) at block 742. Block 742 can include performing this formation in any of a variety of ways, non-limiting examples of which are provided herein.

Block 742 can, for example, share any or all properties with any or all signal distribution structures discussed herein (eg, block 120 of the exemplary method 100 of FIG. 1 ). ), with respect to block 320 of exemplary method 300 of FIG. 3, with respect to block 520 of exemplary method 500 of FIG. 5, with respect to block 720, etc.). Various exemplary aspects of block 742 are provided in example 800F in FIG. 8F.

As discussed herein, the exemplary structure 800E generated from block 740 is the top surface of encapsulating material 851, vertical interconnect structure 814 and/or connecting die interconnect structure 817. It may include an exposed top surface, a vertical interconnect structure 814 and / or an upper surface including the exposed upper side of the connection die interconnect structure 817, and the like. Block 742 can include, for example, forming a second signal redistribution structure on any or all of those surfaces.

Block 742 can include, for example, forming a second RD structure in any of a variety of ways on top of structure 800E, non-limiting examples of which are provided herein. In an exemplary implementation, the one or more dielectric layers and the one or more conductive layers side electrical connections between vertical interconnect structures 814 and/or connecting die interconnect structures 817 to electrical components mounted therein. It can be formed to distribute in the direction and/or in the vertical direction (eg, semiconductor dies, eg dies 811 and 812, passive electrical components, shielding components, etc.). 8F shows an example in which the second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. The number of such layers is only an example, and the scope of the present invention is not limited thereto. In another example implementation, the second RD structure 896 can include a single dielectric layer 897 and a single conductive layer 898, two of each layer, and the like. Thus, the second RD structure 896 may be coreless. However, it is noted that in various alternative implementations, the second RD structure 896 can be a core structure. In another exemplary implementation, the second redistribution (or distribution) structure 896 can include only a single vertical metal structure (eg, one or more layers), eg, an under bump metallization structure.

Dielectric layer 997 can be formed of any of a variety of materials (eg, Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy or other insulating materials). Dielectric layer 997 can be formed using any of a variety of processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). The dielectric layer 997 can be patterned, for example, to expose various surfaces (eg, to expose the bottom traces or pads of the conductive layer 898).

The conductive layer 898 can be formed of any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 898 can be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

The second RD structure 896 can include, for example, a conductor exposed on the outer surface (eg, exposed on the top surface of example 800F). Such exposed conductors can be used, for example, for attachment (or formation) of electrical components and/or attachment structures thereof (eg, block 745, etc.). Such exposed conductors may include, for example, pad structures, bump metallization structures, and the like. In this implementation, the exposed conductor can include a pad, for example, a low bump metal (UBM) formed thereon to enhance adhesion (or formation) of components and/or their interconnect structures. can do. Such under bump metals may include, for example, one or more Ti, Cr, Al, TiW, TiN layers or other electrically conductive materials.

Examples of redistribution structures and/or their formation are US Patent Application No. 14/823,689, filed August 11, 2015 and entitled "Semiconductor Package and Forming Method"; And U.S. Patent No. 8,362,612, entitled "Semiconductor Device and Method for Manufacturing It," each of which is incorporated herein by reference in its entirety.

The second RD structure 896 can, for example, perform at least some electrical connection or fan-out redistribution of the signal, which at least part of the connection die interconnect structure 817 and/or vertical interconnect structure 814 From (to the bottom surface of the second RD structure 896) to the connection die interconnect structure 817 (or connection die 816b) and/or to locations outside the footprint of the vertical interconnect structure 814 Place electrical connections or signals in the lateral direction. Also, for example, the second RD structure 896 may perform at least some electrical connection or fan-in redistribution of the signal, which may include at least the connection die interconnect structure 817 and/or the vertical interconnect structure 814. The electrical connection or signal is moved laterally from some of the connecting die interconnect structures 817 (or connecting die 816b) and/or the vertical interconnect structures 814 into the footprint interior locations. The second RD structure 896 can also provide connection of various signals between, for example, functional dies 811 and 812 (eg, in addition to the connection provided by the RD structure 846a, the connection die (In addition to the connection provided by 816b)

Exemplary block 742 is described as forming a second RD structure layer by layer, but the second RD structure may be received in a pre-formed format and then attached (eg, soldering, epoxy, etc.) at block 742. It should be noted that there is.

In general, block 742 may include forming a second redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by any particular way of making such a carrier and/or signal redistribution structure or by any particular property of such a carrier and/or signal redistribution structure.

Exemplary method 700 may include, at block 745, attaching (or bonding or mounting) a functional die to a second redistribution (RD) structure (eg, formed at block 742). have. Block 745 can include performing this attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 745 can share any or all properties with, for example, any die attach process discussed herein. Various exemplary aspects of block 745 are shown in example 800G shown in FIG. 8G.

For example, the die interconnect structures (eg, pads, bumps, etc.) of the first functional die 811a may include respective conductors (eg, pads, under bump metals) of the second RD structure 896, Mechanically and electrically to exposed traces, etc.). For example, the die interconnect structure of the first functional die 811a is through the conductors of the second RD structure 896, respectively, each vertical interconnect structure 814 and/or each connecting die interconnect structure 817. ). Similarly, the die interconnect structures of the second functional die 812a (eg, pads, bumps, etc.) are exposed to each conductor of the second RD structure 896 (eg, pads, under bump metal, exposed) Traces, etc.) mechanically and electrically. For example, the die interconnect structure of the second functional die 812a may be through the conductors of the second RD structure 896, respectively, each vertical interconnect structure 814 and/or each connecting die interconnect structure 817. ).

These interconnect structures of the functional die can be connected in any of a variety of ways. For example, the connection can be performed by solder. In an exemplary implementation, the interconnect structures of the functional dies 811a and 812a can include solder caps (or other solder structures) that can be reflowed by mass reflow, thermal compression bonding (TCB), or the like. Similarly, the pad or under bump metal of the second RD structure 896 can be re-flowed into a solder cap (or other solder structure) that can be reflowed by mass reflow, thermal compression bonding (TCB), etc. 742)). In other exemplary implementations, the connection may be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding instead of using solder and/or using one or more intervening non-solder metal layers. Examples of such connections are filed on December 8, 2015 and filed on US Patent Application No. 14/963,037 filed "Transient Interface Gradient Bonding for Metal Bonding" and June 6, 2016 and "Interlocking Metal-Metal A semiconductor product having a bond and a method for manufacturing the same are provided in US Patent Application No. 14/989,455, the entire contents of each of which are incorporated herein by reference. Any of a variety of techniques can be used to attach the functional die interconnect structure to the second RD structure 896 (eg, mass reflow, thermocompression bonding (TCB), direct metal-to-metal metal bonding, Conductive adhesive, etc.).

As shown in the exemplary implementation 800G, the first connection die interconnect structure 817 of the connection die 816b is through the second RD structure 896 each interconnection of the first functional die 811a. Connected to the structure, the second connecting die interconnect structure 817 of the connecting die 816b is connected to each interconnect structure of the second functional die 812a through the second RD structure 896. As connected, the connection die 816b (eg, together with the second RD structure 896) is connected through the RD structure 298 of the connection die 816b to the first functional die 811a and the second functional die. Electrical connections between the various die interconnect structures of 812a are provided (eg, as shown in the example 200B-4 of FIG. 2B-1, etc.).

In the example 800G shown in FIG. 8F, the height of the vertical interconnect structure 814 may include, for example, the support layer 290b and the connection die 816b of the connection die interconnect structure 217 and the connection die 816b. It may be equal to or greater than the combined height of the adhesive or other means used to attach to the RD structure 846a. Thus, the second RD structure 896 can include, for example, a generally planar lower surface, a generally uniform thickness, and a generally planar upper surface.

In general, block 745 may include attaching (or joining or mounting) a functional die to the second RD structure. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular way of performing this attachment or the nature of any particular type of attachment structure.

The exemplary method 700 can include underfilling the functional die at block 750. Block 750 may include performing this underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 750 may share any or all properties with, for example, underfilling discussed herein (eg, block 155 and/or block 175 of example method 100 of FIG. 1 ). ), to block 355 and/or block 375 of example method 300 of FIG. 3, to block 550 of example method 500 of FIG. 5, etc.). Various exemplary aspects of block 750 are shown in example 800H shown in FIG. 8H.

Note that the underfill can be applied between functional dies 811a, 812a and second RD structure 896. In scenarios where a pre-applied underfill (PUF) is utilized, such PUF may be added to functional dies 811a and 812a and/or to second RD structure 896 and/or prior to bonding of functional dies 811a and 812a. 2 can be applied to the top exposed conductor of the RD structure 896 (eg, pads, under bump metal, exposed traces, etc.).

Block 750 may include forming an underfill after attachment is performed at block 745 (eg, capillary underfill, injected underfill, etc.). As shown in the exemplary implementation 800H of FIG. 8H, underfill material 861 (eg, any underfill material discussed herein, etc.) is a bottom surface of functional dies 811a and 812a (eg, , As oriented in FIG. 8H) and/or at least partially (if not all) the side surfaces of the functional dies 811a and 812a. The underfill material 861 may also cover most (or all) of the top surface of the second RD structure 896, for example. The underfill material 861 is also, for example, each of the functional dies 811a and 812a to which the interconnect structures of each of the second RD structures 896 (eg, pads, lands, traces, under bump metals, etc.) are attached. It can surround interconnect structures (eg, pads, bumps, etc.). In an exemplary implementation where the ends of the interconnect structures of the second RD structure 896 protrude from the top surface of the second RD structure 896 (eg, the top dielectric layer surface), the underfill material 861 also provides such protrusions. You can surround the part.

In various example implementations of the example method 700, underfilling performed at block 750 may be omitted. For example, the underfill of the functional die can be performed in another block (eg, block 755, etc.). Also, for example, this underfill can be omitted entirely.

Generally, block 750 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of underfill material or any particular way of performing this underfill.

The exemplary method 700 can include an encapsulating step at block 755. Block 755 can include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 755 can share any or all properties with other encapsulating blocks (or steps) discussed herein (eg, block 735, the exemplary of FIG. 1 ). To block 130 of method 100, to block 330 of example method 300 of FIG. 3, to blocks 535 and 555 of example method 500 of FIG. 5, etc.).

Various exemplary aspects of block 755 are shown in example 800I shown in FIG. 8I. For example, the encapsulating material 852' (and/or its formation), together with the encapsulating material 226' (and/or its formation) of FIG. 2E, and the encapsulating material 426 of FIG. 4K ) (And/or its formation), with the encapsulating materials 651 and 652' of FIGS. 6D and 6H (and/or their formation), with the encapsulating material 851 of FIG. 8E, etc., any Let's or share all the characteristics.

The encapsulating material 852' covers the top surface of the second RD structure 896, covers the side surface of the underfill 861, and covers the top surface of the underfill 861 (e.g., die 811a). (Between 812a), covering at least a portion (if not all) of the side surfaces of the functional dies 811a and 812a, and the top surface of the functional dies 811a and 812a, and the like. In another example, encapsulant material 852' can replace underfill 861, thus providing an underfill between functional die 811a and/or 812a and second RD structure 896.

As discussed herein with respect to other encapsulating materials (e.g., the encapsulating material 226' of FIG. 2E, etc.), the encapsulating material 852' is a functional die 811a and 812a. It need not be formed originally to cover the top surface. For example, block 755 can include using film assisted molding, sealing molding, and the like to form encapsulating material 852'.

In general, block 755 may include an encapsulation step. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such encapsulation, any particular type of encapsulating material, and the like.

Exemplary method 700 can include grinding (or running thinning or planarizing) the encapsulant material at block 760. Block 760 can include performing such grinding (or any thinning or planarization process) in any of the various ways a non-limiting example is provided herein. For example, block 760 can share any or all properties, for example with other grinding (or thinning) blocks (or steps) discussed herein (eg, the exemplary method of FIG. 1 ). With block 135 of 100, with block 335 of example method 300 of FIG. 3, with blocks 540 and 555 of example method 500 of FIG. 5, block 735 ) Together, etc.).

Various exemplary aspects of block 760 are shown in example 800J shown in FIG. 8J. An example of grinding (or thinning or flattening, etc.) the encapsulating material 852 (and/or forming thereof), along with the encapsulating material 226 (and/or forming thereof) of FIG. With encapsulating material 426 (and/or formation thereof), with encapsulating materials 651 and 652 (and/or formation thereof) of FIGS. 6E and 6I, with encapsulating material 851, etc. , Any or all characteristics can be shared.

Block 760 may be, for example, encapsulating material (e.g., such that the top surface of encapsulating material 852 is coplanar with the top surface of functional die 811a and/or the top surface of functional die 812a. 852) and/or grinding functional dies 811a and 812a.

In general, block 760 may include grinding (or thinning or flattening running) the encapsulating material. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular way of performing such grinding (or thinning or flattening).

The exemplary method 700 can include removing the carrier at block 765. Block 765 can include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 765 can share any or all properties with any carrier removal process discussed herein (eg, block 145 of exemplary method 100 of FIG. 1 and And/or with block 160, with block 345 and/or block 360 of example method 300 of FIG. 3, with block 565 of example method 500 of FIG. 5, Etc). Various exemplary aspects of block 765 are shown in example 800K in FIG. 8K.

For example, example 800K in FIG. 8K shows the removed first carrier 821a (eg, compared to example 800J in FIG. 8J ). Block 765 can include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical-mechanical planarization, peeling, shearing, heat or laser emission, etc.). In addition, for example, block 765 may include removing the adhesive layer, for example, if an adhesive layer was used during formation of RD structure 846a at block 720.

In various exemplary implementations, a second carrier can be used (eg, encapsulating material 852, as shown and discussed herein in connection with the exemplary methods 100 and 300 of FIGS. 1 and 3 ). ) And/or in combination with functional dies 811a and 812a) In other example implementations, various tooling structures can be used in place of the carrier.

In general, block 765 can include removing the carrier. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular type of carrier removal or the nature of any particular type of carrier.

The example method 700 can include completing the signal redistribution (RD) structure at block 770 (eg, if the RD structure 846a is not fully formed at block 820). Block 770 can include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 770 can share any or all properties with, for example, block 720 (eg, with respect to RD structures forming aspects of block 720). Various aspects of block 770 are shown in example 800L shown in FIG. 8L.

As discussed herein, for example, with respect to block 720, the carrier can receive (or be manufactured or prepared) with only a portion of the desired RD structure formed. In this example scenario, block 770 can include completing the formation of the RD structure.

Referring to FIG. 8L, block 770 may include forming a second portion of RD structure 846b on a first portion of RD structure 846a (eg, RD structure 846a) The first part of is received or manufactured or prepared at block 720). Block 770 can include, for example, forming a second portion of RD structure 846b in the same way that a first portion of RD structure 846a is formed.

Note that in various implementations, the first portion of the RD structure 846a and the second portion of the RD structure 846b can be formed using different materials and/or different processes. For example, the first portion of the RD structure 846a can be formed using an inorganic dielectric layer, and the second portion of the RD structure 846b can be formed using an organic dielectric layer. Also, for example, the first portion of the RD structure 846a may be formed to have a finer pitch (or thinner trace, etc.), and the second portion of the RD structure 846b may have a coarser pitch (or thicker) Trace, etc.). Further, for example, the first portion of the RD structure 846a can be formed using a back end of line (BEOL) semiconductor wafer manufacturing process, and the second portion of the RD structure 846b is a post-fab electronic device. It can be formed using a packaging process. Also, the first portion of the RD structure 846a and the second portion of the RD structure 846b can be formed at different geographic locations.

Like the first portion of RD structure 846a, the second portion of RD structure 846b may have any number of dielectric and/or conductive layers.

As discussed herein, the interconnect structure can be formed on the RD structure 846b. In this exemplary implementation, block 765 can include forming under bump metallization (UBM) on the exposed pad to enhance the formation (or attachment) of this interconnect structure.

Generally, block 770 may include completing (complete) the signal redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular type of signal distribution structure or any specific type of signal distribution structure.

The exemplary method 700 can include forming an interconnect structure on the redistribution structure at block 775. Block 775 can include forming interconnect structures in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 775 can share any or all properties with any of the interconnect structures discussed herein.

Various exemplary aspects of block 775 are shown in example 800M shown in FIG. 8M. Exemplary interconnect structures 852 (eg, package interconnect structures, etc.) may include any of a variety of interconnect structures. For example, the package interconnect structure 852 can include conductive balls (eg, solder balls, etc.), conductive bumps, conductive pillars, wires, and the like.

Block 775 can include forming interconnect structure 852 in any of a variety of ways. For example, the interconnect structure 852 can be pasted and/or printed and reflowed onto the RD structure 846b (eg, to each pad 851 and/or UBM). Also, for example, interconnect structures 852 (eg, conductive balls, conductive bumps, pillars, wires, etc.) are pre-formed prior to attachment, such as to the RD structure 846b, It can be reflowed, plated, epoxidized, wire bonded.

As discussed above, the pad 851 of the RD structure 846b is an under bump metal (UBM) or any metal to aid in the formation of the interconnect structure (eg, building, attachment, bonding, deposition, etc.) Note that it can be formed in a furnace. Such UBM formation can be performed, for example, at block 770 and/or block 775.

Generally, block 775 can include forming an interconnect structure on the redistribution structure. Accordingly, the scope of the present disclosure should not be limited by any particular way of forming these interconnect structures or by any particular properties of the interconnect structures.

Exemplary method 700 may include a singulation step at block 780. Block 780 may include performing this singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 780 can share any or all characteristics with, for example, any singulation discussed herein (eg, discussed with respect to block 165 of example method 100 of FIG. 1 ). As discussed with respect to block 365 of the exemplary method 300 of FIG. 3, as discussed with respect to block 580 of the exemplary method 500 of FIG. 5 ).

Various exemplary aspects of block 780 are shown in example 800N shown in FIG. 8N. The individualized structure (e.g., corresponding to the encapsulating material portion 852a) corresponds, for example, with the individualized structure of FIG. 2L (e.g., two encapsulating material portions 226a and 226b) ), with the individualized structure of FIG. 4L (e.g., corresponding to two encapsulating material portions 426a and 426b), a single structure of FIG. 6m (600M), etc., can share any or all properties have.

In general, block 780 may include a singulation step. Accordingly, the scope of the present disclosure should not be limited by the properties of any particular singulation scheme.

The exemplary method 700 can include performing a continuous process at block 790. Such a continuous process can include any of a variety of properties, non-limiting examples of which are provided herein. For example, block 790 is illustrated with block 190 of example method 100 of FIG. 1, with block 390 of example method 300 of FIG. 3, example method of FIG. 5 ( Any or all of the characteristics can be shared with block 590 of 500).

For example, block 790 can include returning the execution flow of the example method 700 to any block. Also, for example, block 790 may include sending the execution flow of example method 700 to any other method block (or step) discussed herein (eg, the example of FIG. 1. Method 100, with respect to the exemplary method 300 of FIG. 3, with respect to the exemplary method 500 of FIG. 5, etc.).

For example, as shown in example 200O of FIG. 2O, example 200P of FIG. 2P, and example 200Q of FIG. 2Q, block 790 forms an encapsulating material and/or underfill (or Formation omitted).

As discussed herein, the functional die and connecting die can be mounted to a substrate, for example in a multi-chip module configuration. Non-limiting examples of such a configuration are shown in FIGS. 9 and 10.

9 shows a top view of an example electronic device 900 according to various aspects of the present disclosure. The example electronic device 900 can share any or all properties with any or all of the electronic devices discussed herein, for example. For example, functional dies 911 and 912 may be any and all of the functional dies discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, etc.) Let's or share all the characteristics. In addition, for example, the connection die 916 can be any or all of the properties and any or all of the connection dies (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.) discussed herein. Share it. Additionally, for example, the substrate 930 may share any or all properties with any or all substrates and/or RD structures (288, 488, 646, 846, 896, etc.) discussed herein.

10 shows a top view of an example electronic device in accordance with various aspects of the present disclosure. The example electronic device 1000 can share any or all characteristics with any or all electronic devices discussed herein, for example. For example, functional dies (functional die 1 to functional die 10) are functional dies 211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a discussed herein. , 911, 912, etc.). Also, for example, the connection dies (connection dies 1 to 10) may be any or all of the properties discussed herein, any or all of the connection dies 216a, 216b, 216c, 290a, 290b, 416a , 416b, 616b, 816b, 916, etc.). Additionally, for example, substrate 1030 may share any or all properties with any or all substrates and/or RD structures (288, 488, 646, 846, 896, 930, etc.) discussed herein. You can.

The examples discussed herein generally include a connecting die between two functional dies, but the scope of the present disclosure is not limited thereto. For example, as shown in FIG. 10, the connecting die 9 is connected to three functional dies (e.g., functional die 2, functional die 9 and functional die 10), e.g. For example, each of these functional dies is electrically connected to each other. Thus, a single connecting die can join multiple functional dies (eg, two functional dies, three functional dies, four functional dies, etc.).

Further, the examples discussed herein generally include functional dies connected to only one connecting die, but the scope of the present disclosure is not limited thereto. For example, a single functional die can be connected to two or more connecting dies. For example, as shown in FIG. 10, functional die 1 is connected to many different functional dies through a number of respective connecting dies.

The discussion herein includes a number of exemplary drawings showing various parts of a semiconductor device assembly (assembly) (or package) and/or method of manufacturing the same. For clarity, such drawings have not shown all aspects of each example assembly. Any example assembly presented herein may share any or all properties with any or all other assemblies presented herein.

In summary, various aspects of the present disclosure provide a semiconductor package structure and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures including a connection die that routes electrical signals between a plurality of different semiconductor dies and methods of manufacturing the same. Although the foregoing has been described with reference to specific aspects and examples, those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the invention. Therefore, the present disclosure is not limited to the specific example(s) disclosed, and the present disclosure is intended to include all examples falling within the scope of the appended claims.

Claims (26)

A first signal redistribution structure;
A first vertical interconnect structure on a first side of the first signal redistribution structure;
A connection die including a rear surface and a front surface, the rear surface facing and connected to a first side surface of the first signal redistribution structure;
A first connection die interconnect structure coupled to the front surface of the connection die;
A second signal redistribution structure on the first vertical interconnect structure and the first connection die interconnect structure; And
The first electronic component includes:
A first interconnect structure connected to the second signal redistribution structure such that the first electronic component is electrically connected to the first vertical interconnect structure through at least the second signal redistribution structure; And
And a second interconnect structure connected to the second signal redistribution structure such that the first electronic component is electrically connected to the first connection die interconnect structure through at least the second signal redistribution structure. According to claim 1,
A second vertical interconnect structure on a first side of the first signal redistribution structure;
A second connection die interconnect structure connected to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure; And
A second electronic component, wherein the second electronic component is
A first interconnect structure connected to the second signal redistribution structure such that the second electronic component is electrically connected to the second vertical interconnect structure through at least the second signal redistribution structure; And
And a second interconnect structure connected to the second signal redistribution structure such that the second electronic component is electrically connected to the second connection die interconnect structure through at least the second signal redistribution structure. According to claim 2,
In a vertical direction between the first electronic component and the second signal redistribution structure, in a vertical direction between the second electronic component and the second signal redistribution structure, and in a lateral direction between the first and second electronic components. An electronic device comprising a layer of underfill material positioned. According to claim 1,
And a first encapsulating material covering a first side of the first signal redistribution structure and surrounding the first vertical interconnect structure and the first connection die interconnect structure in a lateral direction. The method of claim 4,
Wherein the first encapsulating material surrounds the connection die in a lateral direction. The method of claim 4,
Wherein the first side of the first encapsulating material is coplanar with the end surface of the first vertical interconnect structure and the end surface of the first connecting die interconnect structure. The method of claim 6,
An electronic device wherein a first side side of the first signal redistribution structure, a first side side of the second signal redistribution structure and a first side side of the first encapsulating material are coplanar. The method of claim 4,
And a second encapsulating material surrounding the second signal redistribution structure and surrounding the first electronic component in a lateral direction. The method of claim 8,
The first side side of the first signal redistribution structure, the first side side of the second signal redistribution structure, the first side side of the first encapsulating material and the first side side of the second encapsulating material are An electronic device that is coplanar. According to claim 1,
An electronic device having no electrical connection to the back of the connection die. According to claim 1,
At least a portion of the connection die is above the top surface of the first signal redistribution structure. A first signal redistribution structure;
A first vertical interconnect structure on a first side of the first signal redistribution structure;
A second vertical interconnect structure on a first side of the first signal redistribution structure;
A rear surface and a front surface, wherein the rear surface is connected to a first side of the first signal redistribution structure;
A first connection die interconnect structure connected to the front surface of the connection die;
A second connecting die interconnect structure connected to the front surface of the connecting die, the second connecting die interconnect structure being electrically connected to the first connecting die interconnect structure;
A first encapsulation on a first side of the first signal redistribution structure and surrounding the first and second vertical interconnect structures, the first and second connection die interconnect structures and the connection die in a lateral direction material;
A second signal redistribution structure on the first encapsulating material, the first and second vertical interconnect structures, and the first and second connecting die interconnect structures;
A first functional die, wherein the first functional die comprises:
A first interconnect structure connected to the second signal redistribution structure such that the first functional die is electrically connected to the first vertical interconnect structure through at least the second signal redistribution structure; And
A second interconnect structure connected to the second signal redistribution structure such that the first functional die is electrically connected to the first connection die interconnect structure through at least the second signal redistribution structure; And
A second functional die, wherein the second functional die comprises:
A first interconnect structure connected to the second signal redistribution structure such that the second functional die is electrically connected to the second vertical interconnect structure through at least the second signal redistribution structure; And
And a second interconnect structure connected to the second signal redistribution structure such that the second functional die is electrically connected to the second connection die interconnect structure through at least the second signal redistribution structure. The method of claim 12,
And a second encapsulating material covering the second signal redistribution structure and surrounding the first and second functional die in a lateral direction without contacting the first encapsulating material. The method of claim 13,
The first side of the first encapsulating material is co-planar with the end faces of each of the first and second vertical interconnect structures and the end faces of each of the first and second connecting die interconnect structures. device. The method of claim 14,
The first side side of the first signal redistribution structure, the first side side of the second signal redistribution structure, the first side side of the first encapsulating material and the first side side of the second encapsulating material are An electronic device that is coplanar. The method of claim 12,
An underfill located in a vertical direction between the first functional die and the second signal redistribution structure, in a vertical direction between the second functional die and the second signal redistribution structure, and laterally between the first and second functional die. An electronic device comprising a material layer. The method of claim 12,
An electronic device, wherein there is no active electronic component in the volume in the vertical direction directly between the first and second signal redistribution structures. A first signal redistribution structure;
A first vertical interconnect structure on a first side of the first signal redistribution structure;
A connection die including a rear surface and a front surface, the rear surface facing and connected to a first side surface of the first signal redistribution structure;
A first connection die interconnect structure connected to the front surface of the connection die; And
The first electronic component includes:
A first interconnect structure electrically connected to the first vertical interconnect structure; And
And a second interconnect structure electrically connected to the first connection die interconnect structure. The method of claim 18,
A second signal redistribution structure positioned vertically between the first electronic component and the first vertical interconnect structure and vertically located between the first electronic component and the first connection die interconnect structure, Electronic device. The method of claim 19,
And the first and second interconnect structures of the first electronic component are directly connected to the second signal redistribution structure. The method of claim 19,
The first and second signal redistribution structures are coreless (coreless), electronic devices. The method of claim 18,
A second vertical interconnect structure on a first side of the first signal redistribution structure;
A second connection die interconnect structure connected to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure; And
A second electronic component, wherein the second electronic component is:
A first interconnect structure electrically connected to the second vertical interconnect structure; And
And a second interconnect structure electrically connected to the second connection die interconnect structure. A first signal redistribution structure;
A first vertical interconnect structure on a first side of the first signal redistribution structure;
A rear surface and a front surface, wherein the rear surface is connected to a first side of the first signal redistribution structure; And
Receiving an assembly comprising a first connection die interconnect structure coupled to the front surface of the connection die;
Forming a second signal redistribution structure on the first vertical interconnect structure and the first connection die interconnect structure;
Connecting a first electronic component to the second signal redistribution structure, wherein combining the first electronic component comprises:
Connecting the first interconnection structure of the first electronic component to the second signal redistribution structure such that the first interconnection structure of the first electronic component is at least the first vertical interconnection through the second signal redistribution structure. Electrically connected to the structure; And
Connecting the second interconnection structure of the first electronic component to the second signal redistribution structure such that the second interconnection structure of the first electronic component at least interconnects the first connection die through the second signal redistribution structure A method of manufacturing an electronic device comprising the step of being electrically connected to a connection structure. The method of claim 23,
The received assembly is:
A second vertical interconnect structure on a first side of the first signal redistribution structure; And
A second connection die interconnect structure coupled to the front surface of the connection die, the second connection die interconnect structure electrically connected to the first connection die interconnect structure; And
The method includes connecting a second electronic component to the second signal redistribution structure, wherein connecting the second electronic component comprises:
Connecting the first interconnection structure of the second electronic component to the second signal redistribution structure such that the first interconnection structure of the second electronic component is at least the second vertical interconnection through the second signal redistribution structure. Electrically connected to the structure; And
Connecting the second interconnection structure of the second electronic component to the second signal redistribution structure such that the second interconnection structure of the second electronic component at least connects a second connection die through the second signal redistribution structure A method of manufacturing an electronic device comprising the step of being electrically connected to a structure. The method of claim 24,
A first encapsulation covering a first side of the first signal redistribution structure, and surrounding the first and second vertical interconnect structures, the first and second connection die interconnect structures and the connection die in a lateral direction A method of manufacturing an electronic device comprising forming a material. The method of claim 25,
Forming a second encapsulating material covering the second signal redistribution structure and surrounding the first and second electronic components laterally without contacting the first encapsulating material; Manufacturing method.

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