TWI815521B - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Description

Semiconductor packaging and manufacturing method thereof

The present invention relates to semiconductor packages and methods of manufacturing semiconductor packages. Cross-Reference / Incorporation by Reference of Related Applications

This application is a continuation-in-part of U.S. Patent Application No. 15/707,646, titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF", filed on September 18, 2017. U.S. Patent Application No. 15/594,313 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on May 12, 2017 is a continuation-in-part of U.S. Patent Application No. 15/ U.S. Patent Application No. 594,313 is U.S. Patent Application No. 15/207,186 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on July 11, 2016 (now U.S. Patent No. 9,653,428 Continuation of the patent case), U.S. Patent Application No. 15/207,186 cites U.S. Provisional No. 62/287,544 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on January 27, 2016 Applications, claiming priority and claiming the benefit thereof, each of which is hereby incorporated by reference in its entirety.

This application is related to the following application: U.S. Patent Application No. 14/686,725 titled "SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH" filed on April 14, 2015; U.S. Patent Application No. 14/823,689 (now U.S. Patent No. 9,543,242) entitled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on August 11, 2015; 2017 January U.S. Patent Application No. 15/400,041 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on March 6; and filed on March 10, 2016 titled "Semiconductor Packaging and Fabricating Methods Therefor" U.S. Patent Application No. 15/066,724 "SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF", each of which is hereby incorporated by reference in its entirety.

Current semiconductor packages and methods for forming semiconductor packages are inadequate, resulting in, for example, excessive cost, reduced reliability, or excessive package size. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure as set forth in the remainder of this application with reference to the accompanying drawings.

Various aspects of the present disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As non-limiting examples, aspects of the present disclosure provide various semiconductor package structures including connection dies that route electrical signals between multiple other semiconductor dies and methods of fabricating the same.

The following discussion presents various aspects of this disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure is not necessarily limited by any specific features of the examples provided. In the following discussion, the terms "such as" and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "for example and not limiting."

As used herein, "and/or" refers to any one or more items in a list connected by "and/or". For example, "x and/or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y and/or z" means a seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), ( any element in x, y, z)}. In other words, "x, y, and/or z" means "one or more of x, y, and z."

The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprising," "comprising," "having" and the like, when used in this specification, mean that the presence of stated features, integers, steps, operations, elements and/or components does not exclude the presence of one or more The presence or addition of other features, integers, steps, operations, elements, parts and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the present disclosure. Similarly, various spatial terms such as "upper," "lower," "sides," etc. may be used to distinguish one element from another element in a relative manner. However, it is understood that the components may be oriented differently, for example, a semiconductor device or package may be turned sideways such that its "top" surface faces horizontally and its "sides" without departing from the teachings of this disclosure. The surface faces vertically.

Various aspects of the present disclosure provide a semiconductor device or package and a method of fabricating the same that may reduce cost, increase reliability, and/or improve manufacturability of the semiconductor device or package.

The above and other aspects of the present disclosure will be described in and will be apparent from the following description of various example embodiments. Various aspects of the present disclosure will now be presented with reference to the accompanying drawings so that those skilled in the art can readily practice the various aspects.

1 illustrates a flow diagram of an example method 100 of manufacturing an electronic device (eg, semiconductor package, etc.). Example method 100 may, for example, share any or all features with any other example method discussed herein (eg, example method 300 of FIG. 3, example method 500 of FIG. 5, example method 700 of FIG. 7, etc.). 2A-2Q illustrate cross-sectional views illustrating example electronic devices (eg, semiconductor packages, etc.) and example methods of fabricating the example electronic devices in accordance with various aspects of the present disclosure. 2A-2Q may illustrate an example electronic device, such as in various blocks (or steps) of the method 100 of FIG. 1 . Figures 1 and 2A-2Q will now be discussed together. It should be noted that the order of the example blocks of method 100 may vary without departing from the scope of the present disclosure.

Execution of the instance method 100 may begin at block 105 . Method 100 may begin execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, method 100 may be responsive to one or more signals received from one or more upstream and/or downstream manufacturing stations upon the arrival of components and/or manufacturing materials used during execution of method 100 , in response to input from a central manufacturing line control. The signal from the controller starts to execute automatically. As another example, method 100 may begin execution in response to an operator command to begin. Additionally, for example, method 100 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 100 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 110 . Block 110 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 110 may share any or all characteristics with any of the functional die receipt, fabrication, and/or preparation operations discussed herein. Various example aspects of block 110 are presented in Figure 2A.

Block 110 may include, for example, receiving multiple functional dies (or any portion thereof) from an upstream manufacturing process at the same facility or geographic location. Block 110 may also include, for example, receiving the functional die (or any portion thereof) from a supplier (eg, from a foundry, etc.).

Functional dies received, fabricated, and/or prepared may include any of a variety of features. For example, although not shown, the received dies may include multiple different dies on the same wafer (eg, a multi-project wafer (MPW)). An example of such a configuration is shown in Example 210A of Figure 2A of US Patent Application No. 15/594,313, which is hereby incorporated by reference in its entirety for all purposes. In such MPW configurations, the wafer can contain multiple functional dies of different types. For example, a first die may include a processor and a second die may include a memory die. As another example, a first die may include a processor and a second die may include a coprocessor. Additionally, for example, both the first die and the second die may include memory dies. Typically, a die may include active semiconductor circuitry. Although the various examples presented herein typically place or attach diced functional dies, such dies may also be interconnected prior to placement (e.g., as part of the same semiconductor wafer, as part of a reconstituted wafer, etc. ).

Block 110 may include, for example, receiving functional dies in one or more corresponding wafers dedicated to a single type of die. For example, as shown in Figure 2A, example 200A-1 shows a wafer dedicated to an entire wafer of die 1, example die of which is shown at element numeral 211, and example wafer 200A-3 shows An entire wafer is shown dedicated to die 2, an example die of which is shown with reference numeral 212. It should be understood that while the various examples shown herein generally relate to first and second functional dies (eg, die 1 and die 2), the scope of the present disclosure extends to any number of the same or different types. Functional die (e.g., three die, four die, etc.). For example, the scope of the present disclosure extends to passive electronic components (eg, resistors, capacitors, inductors, etc.) in addition to or instead of functional semiconductor dies.

Functional dies 211 and 212 may include die interconnect structures. For example, as shown in FIG. 2A , the first functional die 211 includes a first set of one or more die interconnect structures 213 and a second set of one or more die interconnect structures 214 . Similarly, the second functional die 212 may include such structures. Die interconnect structures 213 and 214 may include any of a variety of die interconnect structure features, non-limiting examples of which are provided herein.

The first die interconnect structure 213 may include, for example, metal (eg, copper, aluminum, etc.) pillars or lands. The first die interconnect structure 213 may also include, for example, conductive bumps (eg, C4 bumps, etc.) or balls, leads, pillars, etc.

The first die interconnect structure 213 may be formed in any of a variety of ways. For example, first die interconnect structure 213 may be plated on the die pad of functional die 211 . As another example, the first die interconnect structure 213 may be printed and reflowed, wire bonded, or the like. It should be noted that in some example implementations, first die interconnect structure 213 may be a die pad for first functional die 211 .

The first die interconnect structure 213 may be capped, for example. For example, the first die interconnect structure 213 may be capped by solder. As another example, the first die interconnect structure 213 may be capped with a metal layer (eg, a metal layer other than solder that forms a substituted solid solution or an intermetallic compound with copper). For example, the first die interconnect structure 213 may be as described in U.S. Patent No. 14/963,037 titled "Transient Interface Gradient Bonding for Metal Bonds" filed on December 8, 2015. formed and/or connected as explained in the application, the entire contents of which are hereby incorporated by reference. Additionally, for example, the first die interconnect structure 213 may be as described in a paper filed on January 6, 2016 titled "Semiconductor Product with Interlocking Metal-to-Metal Bonding and Methods of Manufacturing the Same" Bonds and Method for Manufacturing Thereof", U.S. Patent Application No. 14/989,455, the entire contents of which are hereby incorporated by reference.

The first die interconnect structure 213 may include any of a variety of dimensional features, for example. For example, in example embodiments, first die interconnect structure 213 may include a pitch (eg, center-to-center spacing) of 30 microns and a diameter (or width, minor or major axis width, etc.) of 17.5 microns. As another example, in example embodiments, first die interconnect structure 213 may include a pitch in the range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor axis) in the range of 10 to 25 microns. or spindle width, etc.). The first die interconnect structure 213 may be, for example, 15 to 20 microns tall.

The second die interconnect structure 214 may share any or all features with the first die interconnect structure 213 , for example. Some or all of the second die interconnect structures 214 may be substantially different than the first die interconnect structures 213 , for example.

The second die interconnect structure 214 may include, for example, metal (eg, copper, aluminum, etc.) pillars or pads. The second die interconnect structure 214 may also include conductive bumps (eg, C4 bumps, etc.) or balls, leads, etc., for example. The second die interconnect structure 214 may, for example, be the same general type of interconnect structure as the first die interconnect structure 213, but need not be. For example, both the first die interconnect structure 213 and the second die interconnect structure 214 may include copper pillars. As another example, the first die interconnect structure 213 may include metal lands, and the second die interconnect structure 214 may include copper pillars.

The second die interconnect structure 214 may be formed in any of a variety of ways. For example, second die interconnect structure 214 may be plated on the die pad of functional die 211 . As another example, the second die interconnect structure 214 may be printed and reflowed, wire bonded, or the like. The second die interconnect structure 214 may be formed in the same process step as the first die interconnect structure 213, but such die interconnect structures 213 and 214 may also be formed in separate respective steps and/or in overlapping layers. formed in the steps.

For example, in a first example scenario, a first portion of each of the second die interconnect structures 214 (eg, a first half, first third). Continuing with the first example scenario, a second portion (eg, second half, remaining two-thirds, etc.) of each of the second die interconnect structures 214 may then be formed in a second plating operation. For example, during the second plating operation, the first die interconnect structure 213 may be inhibited from additional plating (eg, by a dielectric or protective mask layer formed thereon, by removing plating signals, etc.). In another example scenario, the second die interconnect structure 214 may be formed in a second plating process that is completely independent of the first plating process used to form the first die interconnect structure 213 during the second plating process. The first die interconnect structure may be covered by a protective mask layer, for example.

The second die interconnect structure 214 may be uncapped, for example. For example, the second die interconnect structure 214 may not be capped by solder. In an example scenario, the first die interconnect structure 213 may be capped (eg, capped by solder, capped by a metal layer, etc.) while the second die interconnect structure 214 is not capped. In another example scenario, neither the first die interconnect structure 213 nor the second die interconnect structure 214 is capped.

The second die interconnect structure 214 may include any of a variety of dimensional features, for example. For example, in example embodiments, second die interconnect structure 214 may include a pitch (eg, center-to-center spacing) of 80 microns and a diameter (or width) of 25 microns or greater. As another example, in example embodiments, the second die interconnect structure 214 may include a pitch in the range of 50 to 80 microns and a diameter (or width, minor or major axis width, etc.) in the range of 20 to 30 microns. Additionally, for example, in example embodiments, the second die interconnect structure 214 may include a pitch in the range of 80 to 150 (or 100 to 150) microns and a diameter (or width, short diameter) in the range of 25 to 40 microns. axis or spindle width, etc.). The second die interconnect structure 214 may be, for example, 40 to 80 microns tall.

It should be noted that functional dies (eg, in wafer form, etc.) may be received that already have one or more die interconnect structures 213/214 (or any portion thereof) formed thereon.

It should also be noted that the functional die (eg, in wafer form) can be thinned at this point from its original die thickness (eg, by grinding, mechanical and/or chemical thinning, etc.), but does not have to be. For example, functional die wafers (eg, the wafers shown in Examples 200A-1, 200A-2, 200A-3, and/or 200A-4) may be full thickness wafers. As another example, functional die wafers (eg, the wafers shown in Examples 200A-1, 200A-2, 200A-3, 200A-4, etc.) can be at least partially thinned to reduce the thickness of the resulting package while still Enables safe wafer handling.

Generally, block 110 may include receiving, fabricating, and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such is received and/or manufactured, nor by any particular characteristics of such functional dies.

The example method 100 may include receiving, fabricating, and/or preparing the connection die at block 115 . Block 115 may include receiving, fabricating, and/or preparing a plurality of connection dies in any of a variety of manners, non-limiting examples of which are provided herein. Various example aspects of block 115 are presented in Examples 200B-1 through 200B-7 shown in Figures 2B-1 and 2B-2.

Block 115 may include, for example, receiving multiple connection dies from an upstream manufacturing process at the same facility or geographic location. Block 115 may also include, for example, receiving connection dies from a supplier (eg, from a foundry, etc.).

The connection dies received, fabricated, and/or prepared may include any of a variety of features. For example, the dies received, fabricated, and/or prepared may include multiple connected dies on a wafer (eg, silicon or other semiconductor wafer, glass wafer or panel, metal wafer or panel, etc.). For example, as shown in FIG. 2B-1 , example 200B-1 includes an entire wafer of connection dies, an example connection die of which is shown at symbol 216a. It should be understood that although the various examples shown herein generally involve the utilization of a single connection die in a package, multiple connection dies may be utilized in a single electronic device package (e.g., multiple connection dies with the same or different designs) . This article provides non-limiting examples of such configurations.

In the examples illustrated herein (eg, 200B-1 through 200B-4), the connection die may, for example, only contain electrical routing circuitry (eg, no active semiconductor components and/or passive components). Note, however, that the scope of the present disclosure is not limited in this regard. For example, the connection dies shown herein may include passive electronic components (e.g., resistors, capacitors, inductors, integrated passive devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductors, etc.) processing components, semiconductor memory components, etc.) and/or optical components, etc.

Connecting the dies may include connecting dies interconnect structures. For example, the example connection die 216a shown in FIG. 200B-1 includes a connection die interconnect structure 217. The connecting die interconnect structure 217 may include any of a variety of interconnect structure features, non-limiting examples of which are provided herein. Although this discussion generally presents all connected die interconnect structures 217 as being identical to each other, they may also differ from each other. For example, referring to FIG. 2B-1 , the left portion of the connecting die interconnect structure 217 may be the same as or different from the right portion of the connecting die interconnect structure 217 .

The connecting die interconnect structure 217 and/or its formation may share any or all characteristics with the first die interconnect structure 213 and/or the second die interconnect structure 214 and/or its formation discussed herein. In example embodiments, connecting the first portions of the die interconnect structures 217 may include providing spacing, layout, shape, size, mating of such first portions to corresponding first die interconnect structures 213 of the first functional die 211 and/or material characteristics, and connecting the second portions of the die interconnect structures 217 may include providing spacing, layout, mating of such second portions to corresponding first die interconnect structures 213 of the second functional die 212 , Shape, size and/or material characteristics.

The connection die interconnect structure 217 may include, for example, metal (eg, copper, aluminum, etc.) pillars or lands. The connection die interconnect structure 217 may also include, for example, conductive bumps (eg, C4 bumps, etc.) or balls, leads, posts, etc.

The connecting die interconnect structure 217 may be formed in any of a variety of ways. For example, connection die interconnect structure 217 may be plated on the die pad of connection die 216a. As another example, the connecting die interconnect structure 217 may be printed and reflowed, wire bonded, or the like. It should be noted that in some example embodiments, connecting die interconnect structure 217 may be a die pad connecting die 216a.

The connection die interconnect structure 217 may be capped, for example. For example, connecting die interconnect structure 217 may be covered by solder. As another example, the connecting die interconnect structure 217 may be capped with a metal layer (eg, a metal layer forming a substituted solid solution or an intermetallic compound with copper). For example, the connecting die interconnect structure 217 may be as described in U.S. Patent Application No. 14/963,037 entitled "Transient Interface Gradient Bonding for Metal Bonds" filed on December 8, 2015. Formed and/or connected as herein explained, the entire contents of said U.S. patent application are hereby incorporated by reference. Additionally, for example, the connecting die interconnect structure 217 may be used as described in a paper filed on January 6, 2016 titled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Methods of Making the Same" and Method for Manufacturing Thereof," U.S. Patent Application No. 14/989,455, the entire contents of which are hereby incorporated by reference.

The connecting die interconnect structure 217 may include any of a variety of dimensional features, for example. For example, in example embodiments, connecting die interconnect structures 217 may include a pitch (eg, center to center spacing) of 30 microns and a diameter (or width, minor or major axis width, etc.) of 17.5 microns. As another example, in example embodiments, the connecting die interconnect structure 217 may include a pitch in the range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor axis, or diameter) in the range of 10 to 25 microns. Spindle width, etc.). The connecting die interconnect structure 217 may be, for example, 15 to 20 microns tall.

In an example scenario, connecting die interconnect structures 217 may include corresponding first die interconnect structures 213 (eg, metal lands, conductive bumps, copper pillars, etc.) matching copper pillars.

Connection die 216a (or wafer 200B-1 thereof) may be formed in any of a variety of ways, non-limiting examples of which are discussed herein. For example, referring to FIG. 2B-1 , connection die 216a (eg, shown in Example 200B-3) or its wafer (eg, shown in Example 200B-1) may, for example, include a support layer 290a (eg, silicon Or other semiconductor layers, glass layers, metal layers, plastic layers, etc.). A redistribution (RD) structure 298 may be formed on the support layer 290 . RD structure 298 may include, for example, a base dielectric layer 291, a first dielectric layer 293, a first conductive trace 292, a second dielectric layer 296, a second conductive trace 295, and a connecting die interconnect structure 217 .

Base dielectric layer 291 may be, for example, on support layer 290. The base dielectric layer 291 may include, for example, an oxide layer, a nitride layer, any one of various inorganic dielectric materials, and the like. Base dielectric layer 291 may, for example, be formed to specifications and/or may be natural. Base dielectric layer 291 may be referred to as a passivation layer. The base dielectric layer 291 may be or include, for example, a silicon dioxide layer formed using a low pressure chemical vapor deposition (LPCVD) process. In other example embodiments, base dielectric layer 291 may be formed from any of a variety of organic dielectric materials, many examples of which are provided herein.

Connection die 216a (eg, shown in Example 200B-3) or wafer thereof (eg, shown in Example 200B-1) may also include, for example, first conductive traces 292 and first dielectric layer 293 . First conductive trace 292 may, for example, include deposited conductive metal (eg, copper, aluminum, tungsten, etc.). First conductive trace 292 may be formed, for example, by sputtering, electroplating, electroless plating, or the like. The first conductive traces 292 may be formed, for example, with sub-micron or sub-two micron spacing (or center-to-center spacing). The first dielectric layer 293 may, for example, include an inorganic dielectric material (eg, silicon oxide, silicon nitride, etc.). It should be noted that in various embodiments, first dielectric layer 293 may be formed before first conductive trace 292, such as by forming a hole, and then filling the hole with first conductive trace 292 or a portion thereof. In example embodiments that include, for example, copper conductive traces, the traces may be deposited using a dual damascene process.

In alternative components, first dielectric layer 293 may include an organic dielectric material. For example, the first dielectric layer 293 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB) , polybenzoxazole (PBO), epoxy resin and equivalents and compounds thereof, but the aspects of the present disclosure are not limited thereto. The organic dielectric material can be formed in any of a variety of ways, such as chemical vapor deposition (CVD). In such alternative components, the first conductive traces 292 may be spaced, for example, from 2 to 5 microns (or center to center).

Connection die 216a (eg, shown in Example 200B-3) or its wafer 200B-1 (eg, shown in Example 200B-1) may also include, for example, second conductive traces 295 and a second dielectric Quality layer 296. Second conductive trace 295 may, for example, include deposited conductive metal (eg, copper, etc.). The second conductive trace 295 may be connected to the corresponding first conductive trace 292 , such as through a corresponding conductive via 294 or hole (eg, in the first dielectric layer 293 ). The second dielectric layer 296 may include, for example, an inorganic dielectric material (eg, silicon oxide, silicon nitride, etc.). In alternative components, second dielectric layer 296 may include an organic dielectric material. For example, the second dielectric layer 296 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) ), epoxy resins and equivalents thereof and compounds thereof, but the aspects of the present disclosure are not limited thereto. The second dielectric layer 296 may be formed using a CVD process, for example, but the scope of the present disclosure is not limited thereto. It should be noted that various dielectric layers (eg, first dielectric layer 293, second dielectric layer 296, etc.) may be formed of the same dielectric material and/or formed using the same process, but this not necessary. For example, first dielectric layer 293 may be formed from any inorganic dielectric material discussed herein and second dielectric layer 296 may be formed from any organic dielectric material discussed herein, or vice versa.

Although two sets of dielectric layers and conductive traces are shown in Figure 2B-1, it should be understood that the RD structure 298 connecting die 216a (eg, shown in Example 200B-3) or its die A circle (eg, as shown in Example 200B-1) may include any number of such layers and traces. For example, RD structure 298 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, etc.

Connection die interconnect structures 217 (eg, conductive bumps, conductive balls, conductive posts or pillars, conductive lands or pads, etc.) may be formed on the surface of the RD structure 298 . Examples of such connecting die interconnect structures 217 are shown in Figures 2B-1 and 2B-2, where the connecting die interconnect structures 217 are shown formed on the front (or top) surface of the RD structure 298, and Electrical connections are made to corresponding second conductive traces 295 through conductive vias in the second dielectric layer 296 . Such connecting die interconnect structures 217 may, for example, be used to couple the RD structure 298 to various electronic components (eg, active semiconductor components or dies, passive components, etc.), including, for example, the first functional die 211 and the first functional die 211 discussed herein. Dual-function die 212.

The connecting die interconnect structure 217 may, for example, include any of a variety of conductive materials (eg, any one or combination of copper, nickel, gold, etc.). The connecting die interconnect structure 217 may also include solder, for example. As another example, the connection die interconnect structure 217 may include solder balls or bumps, multi-ball solder posts, elongated solder balls, metal (eg, copper) core balls with a solder layer on the metal core, plated post structures (eg, copper pillars, etc.), lead structures (e.g. wire bond leads), etc.

Referring to FIG. 2B-1 , example 200B-1 of a wafer showing connection die 216a may be thinned, for example, to produce a thin connection die wafer of thin connection die 216b as shown in example 200B-2. For example, a thin tie die wafer (e.g., as shown in Example 200B-2) may be thinned (e.g., by grinding, chemical and/or mechanical thinning, etc.) to a level that still allows safe handling of the thin tie die wafer and / or to the extent that it has a single thin connecting die 216b but provides a low profile. For example, referring to Figure 2B-1, in example embodiments in which support layer 290 includes silicon, thin connection die 216b may still include at least a portion of silicon support layer 290. For example, the bottom surface (or backside) of thin connection die 216b may include sufficient non-conductive support layer 290, base dielectric layer 291, etc. to prohibit conductive contact on the bottom surface of the remaining support layer 290 with the conductive layer on the top surface. In other examples, thin connection die 216b may be thinned to substantially or completely remove support layer 290. In such instances, the conductive contact connecting the bottom surface of die 216b may still be blocked by base dielectric 291.

For example, in example embodiments, a thin tie die wafer (eg, as shown in Example 200B-2) or thin tie die 216b thereof may have a thickness of 50 microns or less. In another example embodiment, the thin tie die wafer (or thin tie die 216b thereof) may have a thickness in the range of 20 to 40 microns. As will be discussed herein, the thickness of the thin connection die 216b may be less than the length of the second die interconnect structure 214 of the first die 211 and the second die 212, for example, such that the thin connection die 216b may be mounted on a carrier and between functional dies 211 and 212.

Two example connection die embodiments labeled "Connection Die Example 1" and "Connection Die Example 2" are shown at 200B-5 of Figure 2B-2. Connection die Example 1 may, for example, utilize an inorganic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in the RD structure 298 and the semiconductor support layer 290 . Connection die Example 1 may be produced, for example, using Amkor Technology's Silicon-less Integrated Module (SLIM™) technology. The semiconductor support layer may be, for example, 30 to 100 μm (eg, 70 μm) thick, and each level (or sub-layer or layer) of the RD structure (eg, including at least a dielectric layer and a conductive layer) may be, for example, 1 to 3 μm (e.g. 3 μm, 5 μm, etc.) thick. The total thickness of the resulting structures of examples may, for example, range from 33 to 109 μm (eg, <80 μm, etc.). It should be noted that the scope of this disclosure is not limited to any specific dimensions.

Connecting die Example 2 may, for example, utilize RD structure 298 and an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers) in semiconductor support layer 290 . Connection Die Example 2 may be produced, for example, using Amkor Technology's Silicon Wafer Integrated Fan-Out (SWIFT™) technology. The semiconductor support layer may be, for example, 30 to 100 μm (eg, 70 μm) thick, and each level (or sub-layer or layer) of the RD structure (eg, including at least a dielectric layer and a conductive layer) may be, for example, 4 to 7 μm thick, 10 μm thick, etc. The total thickness of the resulting structures of examples may, for example, be in the range of 41 to 121 μm (eg, <80 μm, 100 μm, 110 μm, etc.). It should be noted that the scope of this disclosure is not limited to any specific dimensions. It should also be noted that in various example embodiments, the support layer 290 of Connection Die Example 2 may be thinned (eg, relative to Connection Die Example 1 ) to achieve the same or similar overall thickness.

Example embodiments presented herein generally involve single-sided connected dies, which may, for example, have interconnect structures on only one side. However, it should be noted that the scope of the present disclosure is not limited to such single-sided structures. For example, as shown in Examples 200B-6 and 200B-7, connection die 216c may include interconnect structures on both sides. An example implementation of such a connection die 216c (e.g., as shown in Example 200B-7) and its wafer (e.g., as shown in Example 200B-6), which may also be referred to as a double-sided connection die, is shown in Figure 2B- 2 is shown. Example wafers (eg, Example 200B-6) may, for example, share any or all features with example wafers (eg, Examples 200B-1 and/or 200B-2) shown in FIG. 2B and discussed herein. As another example, example connection die 216c may share any or all features with example connection dies 216a and/or 216b shown in FIG. 2B-1 and discussed herein. For example, connection die interconnect structure 217b may share any or all features with connection die interconnect structure 217 shown in FIG. 2B-1 and discussed herein. As another example, the redistribution (RD) structure 298b, the base dielectric layer 291b, the first conductive trace 292b, the first dielectric layer 293b, the conductive via 294b, the second conductive trace 295b and the second dielectric Any or all of layer 296b may be associated with redistribution (RD) structure 298, base dielectric layer 291, first conductive trace 292, first dielectric, respectively, shown in FIG. 2B-1 and discussed herein. Material layer 293, conductive via 294, second conductive trace 295, and second dielectric layer 296 share any or all characteristics. Example bonding die 216c also includes a second set of bonding die interconnect structures 299 received and/or fabricated on a side of bonding die 216c opposite bonding die interconnect structures 217b. Such second connection die interconnect structure 299 may share any or all characteristics with connection die interconnect structure 217 . In an example embodiment, the second connection die interconnect structure 299 may be first formed as the RD structure 298b is built up on the support structure (eg, similar to the support structure 290 ) and then removed or thinned or planarized (eg, similar to the support structure 290 ). , by grinding, stripping, removing, etching, etc.).

Similarly, any or all of the example methods and structures illustrated in U.S. Patent Application No. 15/594,313, which is hereby incorporated by reference in its entirety, may be implemented with any such connection dies 216a, 216b, and/or 216c. are incorporated into this article.

It should be noted that one or more or all of the second connection die interconnect structures 299 may be isolated from other circuits of the connection die 216c, which may also be referred to herein as dummy structures (e.g., dummy structures). columns, etc.), anchoring structures (e.g., anchor columns, etc.). For example, any or all of the second connection die interconnect structures 299 may be formed solely for anchoring the connection die 216c to the carrier or RD structure or metal pattern at a later step. It should also be noted that one or more or all of second connection die interconnect structures 299 may be electrically connected to electrical traces, which may, for example, be connected to the die attached to connection die 216c electronic device circuit. Such structures may, for example, be referred to as active structures (eg active columns, etc.) or the like.

Generally, block 115 may include receiving, fabricating, and/or preparing the die for attachment. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such is received, manufactured, and/or prepared or by any particular characteristics of such connected dies.

Example method 100 may include receiving, manufacturing, and/or preparing a first carrier at block 120 . Block 120 may include receiving, manufacturing, and/or preparing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 120 may share any or all features with other carrier receiving, manufacturing, and/or preparation steps discussed herein, for example. Various example aspects of block 120 are presented at instance 200C of Figure 2C.

Block 120 may include, for example, receiving the carrier from the upstream manufacturing process at the same facility or geographic location. Block 120 may also include, for example, receiving a carrier from a supplier (eg, from a foundry, etc.).

The received, manufactured and/or prepared carrier 221 may include any of a variety of features. For example, carrier 221 may include a semiconductor wafer or panel (eg, a typical semiconductor wafer, a lower-grade semiconductor wafer utilizing lower-grade silicon than that used for the functional dies discussed herein, etc.). For another example, the carrier 221 may include metal, glass, plastic, etc. The carrier 221 may be, for example, reusable or destructible (eg, single use, multiple use, etc.).

The carrier 221 may include any of a variety of shapes. For example, the carrier may be wafer-shaped (eg, circular, etc.), may be panel-shaped (eg, square, rectangular, etc.), etc. Carrier 221 may have any of a variety of lateral dimensions and/or thicknesses. For example, carrier 221 may have the same or similar lateral dimensions and/or thickness of the functional dies and/or wafers connecting the dies discussed herein. As another example, carrier 221 may have the same or similar thickness as the functional dies and/or wafers to which the dies are connected as discussed herein. The scope of the present disclosure is not limited by any specific carrier characteristics (eg, material, shape, size, etc.).

Example 200C shown in Figure 2C includes a layer of adhesive material 223. Adhesive material 223 may include any of various types of adhesives. For example, the adhesive may be liquid, paste, tape, etc.

Adhesive 223 may include any of a variety of sizes. For example, the adhesive 223 may cover the entire top surface of the first carrier 221 . As another example, the adhesive may cover a central portion of the top surface of the first carrier 221 while leaving the peripheral edges of the top surface of the first carrier 221 uncovered. For another example, the adhesive may cover a portion of the top surface of the first carrier 221 in place. corresponding portions corresponding to the future location of the functional die of a single electronic package.

The thickness of adhesive 223 may be greater than the height of second die interconnect structure 214, and thus also greater than the height of first die interconnect structure 213 (eg, 5% larger, 10% larger, 20% larger, etc.).

Example vector 221 may share any or all characteristics with any vector discussed herein. For example, but not limited to, the carrier may have no signal distribution layer, but may also include one or more signal distribution layers. Examples of such structures and their formation are shown in example 600A of Figure 6A and discussed herein.

Generally, block 120 may include receiving, manufacturing, and/or preparing the carrier. Accordingly, the scope of the present disclosure should not be limited by any particular conditions under which the vectors are received, by any particular manner of making the vectors, and/or by the characteristics of any particular manner of preparing such vectors for use.

The example method 100 may include coupling (or mounting) the functional die to the carrier (eg, coupling to a top surface of the non-conductive carrier, coupling to a metal pattern on the top surface of the carrier, coupling to a top surface of the carrier, at block 125 RD structure, etc.). Block 125 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 125 may share any or all features with other die mounting steps discussed herein, for example. Various example aspects of block 125 are presented in example 200D shown in Figure 2D.

For example, functional dies 201-204 (eg, any of functional dies 211 and 212) may be received as individual dies. As another example, one or more functional dies 201 - 204 may be received on a single wafer, and one or more of the functional dies 201 - 204 may be received on multiple corresponding wafers (e.g., as in the example 200A-1 and 200A-3, etc.), etc. Where one or both of the functional dies are received in wafer form, the functional dies may be cut from the wafer. It should be noted that if any of the functional dies 201-204 are received on a single MPW, such functional dies may be cut out of the wafer as attachment means (e.g., connected to bulk silicon) .

Block 125 may include placing functional dies 201 - 204 in adhesive layer 223 . For example, the second die interconnect structure 214 and the first die interconnect structure 213 may be fully (or partially) inserted into the adhesive layer 223 . As discussed herein, adhesive layer 223 may be thicker than the height of second die interconnect structure 214 such that when the bottom surfaces of dies 201 - 204 contact the top surface of adhesive layer 223 , the second die interconnect structure The bottom end of 214 does not contact the carrier 221. However, in alternative embodiments, the adhesive layer 223 may be thinner than the height of the second die interconnect structure 214 but still thick enough to cover the first die when the dies 201 - 204 are placed on the adhesive layer 223 At least a portion of interconnect structure 213 .

Block 125 may include placing functional dies 201-204 using, for example, a die pick and place machine.

It should be noted that although the illustrations herein generally set functional dies 201-204 (and their interconnect structures) to be similar in size and shape, such symmetry is not required. For example, functional dies 201-204 may have different corresponding shapes and sizes, may have different types and/or numbers of interconnect structures, etc. It should also be noted that functional dies 201-204 (or any so-called functional dies discussed herein) may be semiconductor dies, but may also be any of a variety of electronic components, such as passive electronic components, active electronic components , bare die, packaged die, etc. Accordingly, the scope of the present disclosure should not be limited by the characteristics of functional dies 201-204 (or any so-called functional dies discussed herein).

Generally, block 125 may include coupling (or mounting) the functional die to the carrier. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such coupling or by any specific features of such functional dies, interconnect structures, carriers, attachment members, or the like.

Example method 100 may include encapsulation at block 130 . Block 130 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 130 are presented in example 200E shown in Figure 2E. Block 130 may, for example, share any or all features with other capsules discussed herein.

Block 130 may include, for example, performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level before individual modules are diced. Referring to the example embodiment 200E shown in FIG. 2E , the encapsulation material 226 ′ may cover at least part (or all) of the top surface of the adhesive 223 , the top surfaces of the functional dies 201 - 204 , and the side surfaces of the functional dies 201 - 204 )wait. The encapsulation material 226' may also, for example, cover any portion of the second die interconnect structure 214, the first die interconnect structure 213, and the bottom surface of the functional dies 201-204 exposed from 223 if any such components are exposed outside).

Encapsulating material 226' may include any of various types of encapsulating materials, such as molding materials, any dielectric material presented herein, etc.

Although encapsulation material 226' (shown in Figure 2E) is shown covering the top surfaces of functional dies 201-204, any or all such top surfaces (or any corresponding portions of such top surfaces) may be removed from the encapsulation material 226' (shown in Figure 2E). The sealing material 226 is exposed (as shown in Figure 2F). Block 130 may include, for example, initially forming encapsulation material 226 with die top surfaces exposed (e.g., using film-assisted molding techniques, die seal molding techniques, etc.); forming encapsulation material 226', followed by a thinning process ( For example, performed at block 135 ) to thin encapsulation material 226 ′ sufficiently to expose the top surfaces of any or all functional dies 201 - 204 ; forming encapsulation material 226 ′, followed by a thinning process (e.g., at block 135 ) Performed at 135) to thin the encapsulation material but still retain a portion of the encapsulation material 226' covering the top surface of any or all functional dies 201-204 (or any corresponding portion thereof); etc.

Generally, block 130 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or by the characteristics of any particular type of encapsulation material or configuration thereof.

Example method 100 may include grinding the encapsulation material at block 135 . Block 135 may include performing such grinding (or any thinning or planarizing) in any of a variety of ways, non-limiting examples of which are provided herein. Block 135 may, for example, share any or all features with other grinding (or thinning) blocks (or steps) discussed herein. Various example aspects of block 135 are presented in example 200F shown in Figure 2F.

As discussed herein, in various example embodiments, the encapsulation material 226' may initially be formed to a thickness greater than the final desired thickness. In such example embodiments, block 135 may be performed to grind (or otherwise thin or planarize) the encapsulation material 226'. In the example 200F shown in Figure 2F, encapsulation material 226' has been ground to form encapsulation material 226. The top surface of the ground (or thinned or planarized) encapsulation material 226 is coplanar with the top surfaces of the functional die 201 - 204 and, therefore, the functional die are exposed from the encapsulation material 226 . It should be noted that in various example embodiments, one or more of functional dies 201 - 204 may be exposed, while one or more of functional dies 201 - 204 may remain covered by encapsulation material 226 . It should be noted that, if performed, such grinding operations need not expose the top surfaces of functional dies 201-204.

In an example embodiment, block 135 may include grinding (or thinning or planarizing) the encapsulation material 226 ′ and the backside of any or all functional dies 201 - 204 , thereby achieving a top surface of the encapsulation material 226 that is consistent with the functional dies 201 - 204 . Coplanarity of one or more of 201-204.

Generally, block 135 may include grinding encapsulation material. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 100 may include attaching a second carrier at block 140 . Block 140 may include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 140 may share any or all features with any carrier attachment discussed herein. Figure 2G illustrates various example aspects of block 140.

As shown in example 200G of Figure 2G, second carrier 231 may be attached to the top surface of encapsulation material 226 and/or the top surface of functional dies 201-204. It should be noted that the component may still be in wafer (or panel) form at this point. The second carrier 231 may include any of a variety of features. For example, the second carrier 231 may include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, etc. Block 140 may include attaching (or coupling or mounting) the second carrier 231 in any of a variety of ways. For example, block 140 may include attaching the second carrier 231 using an adhesive, using a mechanical attachment mechanism, using vacuum attachment, or the like.

Generally, block 140 may include attaching a second carrier. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of attaching the carrier or by the features of any particular type of carrier.

Example method 100 may include removing the first carrier at block 145 . Block 145 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 145 may share any or all features with any of the carrier removal processes discussed herein. Various example aspects of block 145 are presented in example 200H shown in Figure 2H.

For example, example 200H of Figure 2H shows first carrier 221 removed (eg, compared to example 200G of Figure 2G). Block 145 may include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical mechanical planarization, lift-off, shearing, thermal release or laser release, etc.).

As another example, block 145 may include removing the adhesive layer 223 used at block 125 to couple the functional dies 201 - 204 to the first carrier 221 . For example, such adhesive layer 223 can be removed together with the first carrier 221 in a single-step or multi-step process. For example, in an example embodiment, block 145 may include pulling first carrier 221 from functional dies 201 - 204 and encapsulation material 226 , with the adhesive (or a portion thereof) being removed along with first carrier 221 . As another example, block 145 may include utilizing solvents, thermal energy, light energy, or other cleaning techniques to clean the functional die 201-204 (e.g., from the bottom surface of the functional die 201-204, from the first die 213 and/or the second die 214 interconnect structure, etc.) and encapsulation material 226 remove adhesive layer 223 (eg, the entire adhesive layer 223 and/or any portion of the adhesive layer 223 remaining after removal of the first carrier 221 , etc.).

Generally, block 145 may include removing the first carrier. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of removing the carrier or by the characteristics of any particular type of carrier.

The example method 100 may include attaching (or coupling or mounting) a connection die to a functional die at block 150 . Block 150 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 150 may, for example, share any or all features with any of the die attach processes discussed herein. Various example aspects of block 150 are presented at Figure 2I.

For example, die interconnect structure 217 of first connection die 216b (eg, any or all of such connection dies) may be mechanically and electrically connected to first functional die 201 and second functional die 202 corresponding first die interconnect structure 213 .

Such interconnect structures may be connected in any of a variety of ways. For example, the connection can be performed by soldering. In example embodiments, first die interconnect structure 213 and/or connecting die interconnect structure 217 may include a solder cap (or other solder structure) that may be resoldered to perform the connection. Such solder caps can be resoldered, for example, by mass reflow, thermocompression bonding (TCB), etc. In another example embodiment, the connection may be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding without utilizing solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037 titled "Transient Interface Gradient Bonding for Metal Bonds" filed on December 8, 2015 and in January 2016. U.S. Patent Application No. 14/989,455 titled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof" filed on March 6 are provided in , the entire contents of each of said U.S. patent applications is hereby incorporated by reference. The first die interconnect structure 213 may be attached to the connecting die interconnect structure 217 using any of a variety of techniques (eg, mass reflow, thermocompression bonding (TCB), direct metal-to-metal metal indirect. compounds, conductive adhesives, etc.).

As shown in example 200I, the first die interconnect structure 213 of the first connection die 201 is connected to the corresponding connection die interconnect structure 217 of the connection die 216b, and the first die interconnect structure 217 of the second connection die 202 is connected to each other. Bond structures 213 are connected to corresponding bond die interconnect structures 217 of bond die 216b. When connected, connection die 216b provides electrical connections between various die interconnect structures of first functional die 201 and second functional die 202 via RD structures 298 (e.g., example 200B- of FIG. 2B-1 3 etc.).

In the example 200I shown in FIG. 2I , the height of the second die interconnection structure 214 may be, for example, greater than (or equal to) the first die interconnection structure 213 , the connection die interconnection structure 217 , the RD structure 298 and the connection die interconnection structure 217 . The combined height of any support layer 290b of particle 216b. Such height differences may, for example, provide space for buffer material (eg, underfill, etc.) connecting die 216b to another substrate (eg, as shown in example 200N of FIG. 2N and discussed herein).

It should be noted that although example connection die (216b) is shown as a single-sided connection die (eg, similar to example connection die 216b of Figure 2B-1), the scope of the present disclosure is not limited in this regard. For example, any or all such example connection die 216b may be double-sided (eg, similar to example connection die 216c of Figure 2B-2).

Generally, block 150 may include attaching (or coupling or mounting) a connection die to a functional die. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or by the features of any particular type of attachment structure.

The example method 100 may include underfilling the connection die at block 155 . Block 155 may include performing such underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 155 may, for example, share any or all features with any of the underfill processes discussed herein. Various example aspects of block 155 are presented in example 200J shown in Figure 2J.

It should be noted that underfill may be applied between connection die 216b and functional dies 201-204. In scenarios utilizing pre-applied underfill (PUF), the connection die interconnect structure 217 may be coupled to the first die interconnect structure 213 of the functional dies 201 - 204 (eg, at block 150 ) Such PUF is applied to functional dies 201-204 and/or to connection die 216b.

Following the attachment performed at block 150, block 155 may include forming an underfill (eg, capillary underfill, etc.). As shown in the example embodiment 200J of Figure 2J, underfill material 223 (e.g., any underfill material discussed herein, etc.) may fully or partially cover the bottom surface of connection die 216b (e.g., oriented as shown in Figure 2J), and/or connect at least a portion, if not all, of the sides of die 216b. The underfill material 223 may also surround the connecting die interconnect structure 217 , for example, and surround the first die interconnect structure 213 of the functional dies 201 - 204 . Underfill material 223 may additionally cover the top surfaces of functional dies 201 - 204 , such as in areas corresponding to first die interconnect structures 213 (the orientation shown in FIG. 2J ).

It should be noted that in various example implementations of example method 100, the underfill performed at block 155 may be skipped. For example, underfilling the connection die may be performed at another block (eg, at block 175 , etc.). As another example, such bottom padding can be omitted entirely.

Generally, block 155 may include underfilling the connection die. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or by the characteristics of any particular type of underfill.

Example method 100 may include removing the second carrier at block 160 . Block 160 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 160 may share any or all features with any carrier removal process discussed herein (eg, with respect to block 145, etc.). Example 200K shown in FIG. 2K presents various example aspects of block 160.

For example, the example implementation 200K shown in Figure 2K does not include the second carrier 231 of the example implementation 200J shown in Figure 2J. It should be noted that such removal may include, for example, cleaning the surface, removing adhesive (if used), etc.

Generally, block 160 may include removing the second carrier. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such carrier removal or by the characteristics of any particular type of carrier or carrier material that is removed.

Example method 100 may include singulation cutting at block 165 . Block 165 may include performing such singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 165 may, for example, share any or all characteristics with any of the singulation cuts discussed herein. Example 200L shown in FIG. 2L presents various example aspects of block 165.

As discussed herein, example components shown herein may be formed on a wafer or panel containing a plurality of such components (or modules). For example, the example 200K shown in FIG. 2K has two components (left and right) joined together by encapsulation material 226 . In such example embodiments, the wafers or panels may be singulated (or diced) to form individual components (or modules). In example 200L of Figure 2L, encapsulating material 226 is sawed (or trimmed, broken, pulled, diced, or otherwise trimmed, etc.) into two encapsulating material portions 226a and 226b, each portion corresponding to Corresponding electronic device.

In the example embodiment 200L shown in Figure 2L, only encapsulation material 226 needs to be trimmed. However, block 165 may include cutting any of the various materials if present along a singulation cut line (or cut line). For example, block 165 may include tailoring underfill material, carrier material, functional and/or connection die material, substrate material, etc.

Generally, block 165 may include singulation cutting. Accordingly, the scope of the present disclosure should not be limited by any particular manner of singulation.

The example method 100 may include mounting to a substrate at block 170 . Block 170 may, for example, include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 170 may share any or all features with any of the mounting (or attaching) steps discussed herein (eg, attaching interconnect structures, attaching die backside, etc.). Various example aspects of block 170 are presented in example 400M shown in FIG. 4M.

Substrate 288 may include any of a variety of features, non-limiting examples of which are provided herein. For example, substrate 288 may include a packaging substrate, an interposer, a motherboard, a printed lead board, a functional semiconductor die, a stacked redistribution structure of another device, or the like. The substrate 288 may include, for example, a coreless substrate, an organic substrate, a ceramic substrate, or the like. Substrate 288 may, for example, include one or more dielectric layers (eg, organic and/or inorganic dielectric layers) and/or be formed on a semiconductor (eg, silicon, etc.) substrate, a glass or metal substrate, a ceramic substrate, etc. conductive layer. Substrate 288 may share any or all features, for example, with RD structure 298 of Figure 2B-1, RD structure 298b of Figure 2B-2, any RD structure discussed herein, and the like. Substrate 288 may include, for example, a single package substrate, or may include multiple substrates that are coupled together (eg, in a panel or wafer) and may be subsequently cut.

In the example 200M shown in FIG. 2M , block 170 may include soldering (eg, using quality reflow, thermocompression bonding, laser welding, etc.) the second die interconnect structure 214 of the functional dies 201 - 202 to corresponding pads (eg, bonding pads, traces, lands, etc.) or other interconnect structures of the substrate 288 (eg, pillars, posts, balls, bumps, etc.).

It should be noted that in example embodiments in which connection die 216b is a double-sided connection die similar to connection die 216c, block 170 may also include connecting a second set of connection die interconnect structures 299 to the substrate 288 corresponding pads or other interconnect structures. However, in example 200M of Figure 2M, connection die 216b is a single-sided connection die. It should be noted that, as discussed herein, since the second die interconnect structure 214 of the functional dies 201-202 is more supportive than the first die interconnect structure 213, the connection die interconnect structure 217, and the connection die 216b The combined height of layer 290b is high so that there is a gap between the backside of connection die 216b (underside of connection die 216b in Figure 2M) and the top surface of substrate 288. This gap can be filled with underfill as shown in Figure 2N.

Generally, block 170 includes mounting (or attaching or coupling) the components (or modules) singulated at block 165 to a substrate. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular type of mounting (or attachment) or by the characteristics of any particular mounting (or attachment) structure.

The example method 100 may include, at block 175 , underfilling between the substrate and the component (or module) mounted thereto at block 170 . Block 175 may include performing underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 175 may, for example, share any or all features with any underfill (or encapsulation) process discussed herein (eg, with respect to block 155 , etc.). Various aspects of block 175 are presented in example 200N shown in Figure 2N.

Block 175 may include, for example, performing a capillary underfill or injected underfill process after performing the installation at block 170 . As another example, in scenarios utilizing pre-applied underfill (PUF), such PUF may be applied to the substrate, its metal pattern, and/or its interconnect structure prior to such mounting. Block 175 may also include performing such underfill using a molded underfill process.

As shown in example embodiment 200N of FIG. 2N, underfill material 291 (eg, any of the underfill materials discussed herein, etc.) may fully or partially cover the top surface of substrate 288. The underfill material 291 may also surround the second die interconnect structure 214 (and/or the corresponding substrate pad) of the functional dies 201 - 202 , for example. Underfill material 291 may, for example, cover the bottom surfaces of functional dies 201-202, the bottom surfaces of connection die 216b, and the bottom surfaces of encapsulation material 226a. Underfill material 291 may also cover, for example, side surfaces of connection die 216b and/or exposed lateral surfaces of underfill 223 between connection die 216b and functional dies 201-202. Underfill material 291 may, for example, cover encapsulation material 226a and/or side surfaces (eg, all or a portion) of functional dies 201 - 202 .

In example embodiments in which underfill 223 is not formed, underfill material 291 may be formed in place of underfill 223 . For example, referring to Example 200N, underfill material 223 may be replaced with more underfill material 291 in Example 200N.

In example embodiments in which underfill 223 is formed, underfill material 291 may be a different type of underfill material than underfill material 223 . In another example embodiment, both underfill materials 223 and 291 may be the same type of material.

As with block 155, block 175 may also be skipped, such as leaving a space at another block to be filled with another underfill (eg, molded underfill, etc.).

Typically, block 175 involves performing an underfill. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular type of underfill or the characteristics of any particular underfill material.

The example method 100 may include performing a continuation process at block 190 . Such continued processing may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 190 may include returning execution flow of example method 100 to any block thereof. As another example, block 190 may include directing execution flow of example method 100 to any other method block (or step) discussed herein (eg, with respect to example method 300 of Figure 3, example method 500 of Figure 5, etc.).

For example, block 190 may include forming interconnect structures 299 (eg, conductive balls, bumps, pillars, etc.) on the bottom surface of substrate 288 .

As another example, as shown in example 200O of FIG. 2O , block 190 may include forming encapsulation material 225 . Such encapsulation material 225 may, for example, cover the top surface of substrate 288, the sides of underfill 224, the sides of encapsulation material 226a, and/or the sides of functional dies 201-202. In the example 200O shown in FIG. 2O, the top surface of the encapsulation material 225, the top surface of the encapsulation material 226a, and/or the top surfaces of the functional dies 201-202 may be coplanar.

As discussed herein, underfill 224 may not be formed (eg, as formed at block 175 ). In this case, encapsulating material 225 may replace the underfill. An example 200P of such structures and methods is provided at Figure 2P. Relative to example embodiment 200O shown in FIG. 20 , in example embodiment 200P, underfill 224 of example embodiment 200O is replaced with encapsulation material 225 as the underfill.

As discussed herein, underfill 223 (eg, as formed at block 155) and underfill 224 may not be formed. In this case, encapsulating material 225 may replace them. An example implementation 200Q of such structures and methods is provided at Figure 2Q. Relative to example embodiment 200P shown in Figure 2P, in example embodiment 200Q, encapsulation material 225 is used in place of underfill 223 of example embodiment 200P.

It should be noted that in any of the example embodiments 200O, 200P, and 200Q shown in Figures 2O, 2P, and 2Q, the sides of the encapsulation material 225 and the substrate 288 may be coplanar.

In the example method 100 shown in FIGS. 1 and 2A-2Q , various die interconnect structures (eg, first die interconnect structure 213 , second die interconnect structure 214 , connecting die interconnect structure 217 (and/or 299), etc.) are typically formed during the die receiving, fabrication, and/or preparation processes. For example, such various die interconnect structures may often be formed prior to integration of their corresponding die into the component. However, the scope of the present disclosure should not be limited by the timing of such example implementations. For example, any or all of the various die interconnect structures may be formed after their corresponding die are integrated into the assembly. An example method 300 illustrating forming a die interconnect structure at different stages will now be discussed.

3 illustrates a flow diagram of an example method 300 of manufacturing an electronic device (eg, semiconductor package, etc.). Example method 300 may, for example, share any or all features with any other example method discussed herein (eg, example method 100 of FIG. 1 , example method 500 of FIG. 5 , example method 700 of FIG. 7 , etc.). 4A-4N illustrate cross-sectional views illustrating example electronic devices (eg, semiconductor packages, etc.) and example methods of fabricating the example electronic devices in accordance with various aspects of the present disclosure. 4A-4N may illustrate an example electronic device, such as in various blocks (or steps) of method 300 of FIG. 3 . Figures 3 and 4A-4N will now be discussed together. It should be noted that the order of the example blocks of method 300 may vary without departing from the scope of the present disclosure.

Example method 300 may begin execution at block 305. Method 300 may begin execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, method 300 may begin automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, or the like. As another example, method 300 may begin execution in response to an operator command to begin. Additionally, for example, method 300 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 300 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 310 . Block 310 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 310 may share any or all features with block 110 of example method 100 shown in FIG. 1 and discussed herein. Various aspects of block 310 are presented in examples 400A-1 through 400A-4 shown in Figure 4A.

Block 310 may include, for example, receiving multiple functional dies from an upstream manufacturing process at the same facility or geographic location. Block 310 may also include, for example, receiving functional dies from a supplier (eg, from a foundry, etc.). Block 310 may also include, for example, any or all features that form a plurality of functional dies.

In an example implementation, block 310 may share any or all features with block 110 of example method 100 of FIG. 1 but does not have first die interconnect structure 213 and second die interconnect structure 214 . It will be seen that such die interconnect structures may be formed later in example method 300 (eg, at block 347, etc.). Although not shown in FIG. 4A , each of the functional dies 411 - 412 may, for example, include die pads and/or under-bump metallization structures on which such die interconnect structures may be formed.

Functional die 411-412 shown in Figure 4A may, for example, share any or all features with functional die 211-212 shown in Figure 2A (e.g., not having first die interconnect structure 213 and second die interconnect Structure 214). For example, and without limitation, functional dies 411 - 412 may include features of any of a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Generally, block 310 may include receiving, fabricating, and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such receiving, fabrication, and/or preparation is performed, nor by any specific characteristics of such functional die.

The example method 300 may include receiving, fabricating, and/or preparing the connection die at block 315 . Block 315 may include receiving, fabricating, and/or preparing one or more connection dies in any of a variety of ways, non-limiting examples of which are provided herein. Block 315 may, for example, share any or all features with block 115 of the example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 315 are presented in examples 400B-1 and 400B-2 shown in Figure 4B.

Connection die 416a and/or 416b (or wafers thereof) may include, for example, connection die interconnect structures 417 . The connecting die interconnect structure 417 may include any of a variety of features. For example, the connection die interconnect structure 417 and/or the formation of any aspects thereof may have any characteristics similar to the connection die interconnect structure 217 and/or the formation thereof shown in FIGS. 2B-1 through 2B-2 and discussed herein. or all features.

Connection dies 416a and/or 416b (or wafers thereof) may be formed in any of a variety of manners, for example as provided herein with respect to connection dies 216a, 216b, and/or 216c of Figures 2B-1 through 2B-2. Restricted examples.

Generally, block 315 may include receiving, fabricating, and/or preparing the die for attachment. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such receiving, fabrication, and/or preparation is performed, nor by any particular characteristics of such connected dies.

Example method 300 may include receiving, manufacturing, and/or preparing a first carrier at block 320 . Block 320 may include receiving, manufacturing, and/or preparing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. Block 320 may, for example, share any or all features with other carrier receiving, manufacturing, and/or preparation steps discussed herein (eg, with block 120 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 320 are presented in example 400C shown in Figure 4C. For example, carrier 421 may share any or all features with carrier 221 of Figure 2C. As another example, adhesive 423 may share any or all features with adhesive 223 of Figure 2C. However, it should be noted that since adhesive 423 does not receive the die interconnect structure of the functional die (eg, at block 325 ), adhesive 423 does not have to be as thick as adhesive 223 .

Generally, block 320 may include receiving, manufacturing, and/or preparing a first carrier. The scope of the disclosure should therefore not be limited by any particular conditions under which the carriers are received, by any particular manner of making the carriers, and/or by the characteristics of any particular manner of preparing such carriers for use.

The example method 300 may include coupling (or mounting) the functional die to the carrier (eg, coupling to a top surface of the non-conductive carrier, coupling to a metal pattern on the top surface of the carrier, coupling to a top surface of the carrier, at block 325 RD structure, etc.). Block 325 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 325 may share any or all features, such as with other die mounting steps discussed herein (eg, at block 125 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 325 are presented in example 400D shown in Figure 4D. Instance 400D may share any or all features with instance 200D of Figure 2D. For example, functional die 401-404 (eg, instances of die 411 and/or 412) may share any or all features with functional die 201-204 of Figure 2D (eg, instances of die 211 and/or 212) (For example, die interconnect structures 213 and 214 do not extend into adhesive 223.

In example 400D, the respective active faces of functional dies 401 - 404 are shown coupled to adhesive 423 , but the scope of the present disclosure is not limited to such orientations. In alternative embodiments, the respective non-active sides of functional dies 401-404 may be mounted to adhesive 423 (e.g., where functional dies 404-404 may have through-silicon vias or other structures for later connection to bonding dies, etc. ).

Generally, block 325 may include coupling the functional die to the carrier. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such coupling.

Example method 300 may include encapsulation at block 330 . Block 330 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 330 may share any or all features with other encapsulations discussed herein (eg, with block 130 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 330 are presented in example 400E shown in Figure 4E. For example, encapsulation material 426' (and/or its formation) may share any or all features with encapsulation material 226' (and/or its formation) of Figure 2E.

Generally, block 330 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulating material, or the like.

Example method 300 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 335 . Block 335 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 335 may share any or all features with other grinding (or thinning or planarizing) discussed herein (eg, with block 135 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 335 are presented in example 400F shown in Figure 4F. Example ground (or thinned or planarized, etc.) encapsulation material 426 (and/or its formation) may share any or all characteristics with encapsulation material 226 (and/or its formation) of Figure 2F.

Generally, block 335 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 300 may include attaching a second carrier at block 340 . Block 340 may include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 340 may share any or all features with any carrier attachment discussed herein (eg, with block 140 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 340 are shown in example 400G shown in Figure 4G. The second carrier 431 (and/or its attachment) may share any or all features with the second carrier 231 of Figure 2G, for example.

Generally, block 340 may include attaching a second carrier. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment and/or by the features of any particular type of second carrier.

Example method 300 may include removing the first carrier at block 345 . Block 345 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 345 may share any or all features with any of the vector removals discussed herein (eg, with block 145 of example method 100 shown in FIG. 1 , etc.).

Various example aspects of block 345 are shown in example 400H shown in Figure 4H-1. For example, relative to example 400G, first carrier 421 has been removed.

Generally, block 345 may include removing the first carrier. Accordingly, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such removal is performed.

Example method 300 may include forming an interconnect structure at block 347 . Block 347 may include forming an interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 347 may share any or all features with other interconnect structure formation processes (or steps or blocks) discussed herein (eg, block 110 with respect to the example method 100 shown in FIG. 1 and discussed herein, etc.).

Various example aspects of block 347 are shown at instance 400H-2 of Figure 4H-2. The first die interconnect structure 413 (and/or its formation) of FIG. 4H-2 may share any or all features with the first die interconnect structure 213 (and/or its formation) of FIG. 2A. Similarly, the second die interconnect structure 414 of FIG. 4H-2 (and/or its formation) may share any or all features with the second die interconnect structure 214 (and/or its formation) of FIG. 2A.

Example implementation 400H-2 includes a passivation layer 417 (or re-passivation layer). Although not shown in the example embodiment of FIG. 2A and/or other example embodiments presented herein, such example embodiments may also include such passivation layers 417 (e.g., between functional die and die interconnect structures). between and/or around the base of the die interconnect structures, between the connecting dies and the connecting die interconnect structures and/or around the base of the connecting die interconnect structures, etc.). For example, block 347 may include forming such passivation layer 417 where such passivation layer 417 has not been formed prior to block 347 . It should be noted that passivation layer 417 may also be omitted.

In example embodiments, such as where functional grains are received or formed through an external inorganic dielectric layer, passivation layer 417 may include an organic dielectric layer (eg, including any of the organic dielectric layers discussed herein).

Passivation layer 417 (and/or its formation) may include features of any passivation (or dielectric) layer (and/or its formation) discussed herein. The first die interconnect structure 413 and the second die interconnect structure 414 may be electrically connected to the functional dies 401 - 404 , such as through corresponding holes in the passivation layer 417 .

Although passivation layer 417 is shown on mold layer 426 and functional dies 401 - 404 , passivation layer 417 may also be formed only on functional dies 401 - 404 (eg, at block 310 ). In such example embodiments, the outer surface of passivation layer 417 (eg, the upwardly facing surface of passivation layer 417 in FIG. 4H-2 ) may be consistent with a corresponding surface of encapsulation material 426 (eg, in FIG. 4H-2 The upwardly facing surfaces of the encapsulation material 426 are coplanar.

Generally, block 347 may include forming an interconnect structure. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of such formation or by any particular characteristics of the interconnection structures.

The example method 300 may include attaching (or coupling or mounting) a connection die to a functional die at block 350 . Block 350 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 350 may share any or all features, such as with any die attachment discussed herein (eg, with block 150 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 350 are presented in example 400I shown in Figure 4I. Connections of connection die 416b, functional dies 401-404, and/or such dies to each other may be, for example, similar to connection die 216b, functional dies 201-204, and/or such dies of example 200I shown in FIG. 2I Connections to each other share any or all characteristics.

Generally, block 350 may include attaching a connection die to a functional die. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachments and/or by the features of any particular structure for performing such attachments.

The example method 300 may include underfilling the connection die at block 355 . Block 355 may include performing such underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 355 may, for example, share any or all features with any of the underfills discussed herein (eg, with block 155 and/or block 175 of example method 100 of FIG. 1 , etc.).

Various example aspects of block 355 are presented in example 400J shown in Figure 4J. For example, underfill 423 (and/or its formation) of FIG. 4J may share any or all features with underfill 223 (and/or its formation) of FIG. 2J . It should be noted that, as with any underfill discussed herein, various example implementations may omit to perform such underfill.

Generally, block 355 may include underfilling the connection die. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or by the characteristics of any particular type of underfill material.

Example method 300 may include removing the second carrier at block 360 . Block 360 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 360 may share any or all features with any of the carrier components discussed herein (eg, with block 145 and/or block 160 of example method 100 of FIG. 1 , with block 345 , etc.).

Various example aspects of block 360 are presented in example 400K shown in Figure 4K. For example, comparing Figure 4K to Figure 4J, the second carrier 431 has been removed.

Generally, block 360 may include removing the second carrier. Accordingly, the scope of this disclosure should not be limited by the characteristics of any particular manner in which such removal is performed.

Example method 300 may include singulation cutting at block 365 . Block 365 may include performing such singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 365 may, for example, share any or all features with any of the singulation cuts discussed herein (eg, as discussed with respect to block 165 of the example method 100 of FIG. 1 , etc.).

Various example aspects of block 365 are presented in example 400L shown in Figure 4L. The singulated-cut structure (eg, corresponding to the two encapsulating material portions 426a and 426b) may, for example, share any or all features.

Generally, block 365 may include singulation cutting. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of singulation.

Example method 300 may include mounting to a substrate at block 370 . Block 370 may, for example, include performing such mounting (or coupling or attaching) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 370 may share any or all features with any installation (or coupling or attachment) discussed herein (eg, block 170 with respect to the example method 100 shown in FIG. 1 , etc.).

Various example aspects of block 370 are presented in example 400M shown in FIG. 4M. For example, substrate 488 (and/or attachment to such substrate 288) may share any or all features with substrate 288 (and/or attachment to such substrate 288) of example 200M of FIG. 2M.

Generally, block 370 may include mounting to a substrate. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of mounting to a substrate or by the features of any particular type of substrate.

The example method 300 may include, at block 375 , underfilling between the substrate and the component (or module) mounted thereto at block 370 . Block 375 may include performing underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 375 may, for example, share any or all features with any of the underfill (or encapsulation) processes discussed herein (eg, with respect to block 355 , with respect to blocks 155 and 175 of the example method 100 of FIG. 1 , etc.).

Various aspects of block 375 are presented in example 400N shown in Figure 4N. Underfill 424 (and/or its formation) may, for example, share any or all features with example underfill 224 (and/or its formation) shown in example 200N of FIG. 2N. It should be noted that, as with any underfill discussed herein, the underfill of block 375 may be skipped or may be performed at different points in the method.

Generally, block 375 may include underfilling between the substrate and components mounted to the substrate. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of mounting to a substrate or by the features of any particular type of substrate.

The example method 300 may include performing a continuation process at block 390 . Such continued processing may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 390 may share any or all features with block 190 of the example method 100 of FIG. 1 discussed herein.

For example, block 390 may include returning execution flow of example method 300 to any block thereof. As another example, block 390 may include directing execution flow of example method 300 to any other method block (or step) discussed herein (e.g., with respect to example method 100 of FIG. 1 , example method 500 of FIG. 5 , the example method of FIG. 7 700 etc.).

For example, block 390 may include forming interconnect structures 499 (eg, conductive balls, bumps, pillars, etc.) on the bottom surface of substrate 488 .

As another example, as shown in example 200O of FIG. 2O , example 200P of FIG. 2P , and example 200Q of FIG. 2Q , block 390 may include forming the encapsulation material and/or underfill (or skip forming the encapsulation material and/or underfill). filling).

In various example embodiments discussed herein, the functional die is mounted to the carrier prior to attaching the connection die to the functional die. The scope of this disclosure is not limited to such installation sequences. A non-limiting example will now be presented where the connection die is mounted to the carrier prior to attaching the connection die to the functional die.

5 illustrates a flowchart of an example method 500 of manufacturing an electronic device in accordance with various aspects of the present disclosure. Example method 500 may, for example, share any or all features with any other example method discussed herein (eg, example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 700 of FIG. 7 , etc.). 6A-6M illustrate cross-sectional views illustrating example electronic devices (eg, semiconductor packages, etc.) and example methods of fabricating the example electronic devices in accordance with various aspects of the present disclosure. 6A-6M may illustrate an example electronic device, such as in various blocks (or steps) of method 500 of FIG. 5 . Figures 5 and 6A-6M will now be discussed together. It should be noted that the order of the example blocks of method 500 may vary without departing from the scope of the present disclosure.

Execution of instance method 500 may begin at block 505. Method 500 may begin execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, method 500 may begin automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, or the like. As another example, method 500 may begin execution in response to an operator command to begin. Additionally, for example, method 500 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 500 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 510 . Block 510 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 510 may share any or all features with block 310 of example method 300 shown in FIG. 3 and discussed herein. Various aspects of block 510 are presented in examples 400A-1 through 400A-4 shown in Figure 4A. It should be noted that block 510 may also share any or all features, for example, with block 110 of the example method 100 shown in FIG. 1 and discussed herein.

Functional dies 611a and 612a (and/or their formation) as shown in many of FIGS. 6A-6M may, for example, be the same as functional dies 411 and 412 (and/or their formation) of FIG. 4A , with the function of FIG. 2A Grains 211-212 (and/or their formation) etc. share any or all characteristics. For example, and without limitation, functional dies 611 and 612 may include features of any of a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Generally, block 510 may include receiving, fabricating, and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such receiving and/or fabrication, nor by any specific features of such functional dies.

The example method 500 may include receiving, fabricating, and/or preparing the connection die at block 515 . Block 515 may include receiving and/or fabricating a plurality of connection dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 515 may share any or all features with block 115 of the example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 515 are presented in examples 200B-1 and 200B-7 shown in Figures 2B-1 through 2B-2. It should be noted that block 515 may also share any or all features with block 315 of the example method 300 shown in FIG. 3 and discussed herein.

The connection die 616b and connection die interconnect structures 617 (and/or their formation) as shown in many of the figures in Figures 6A-6M may, for example, be related to the connection die 216b and connection die 216b of Figures 2B-1 through 2B-2. Granular interconnect structures 217 (and/or their formation) share any or all characteristics.

It should be noted that connecting die interconnect structure 617 (and/or its formation) may share any or all features with first die interconnect structure 213 (and/or its formation), for example. For example, in an example embodiment, instead of forming a first die interconnect structure such as first die interconnect structure 213 of FIG. 2A on functional die 211/212, the same may be formed on connection die 616b. or similar connecting die interconnect structure 617.

Generally, block 515 may include receiving, fabricating, and/or preparing the die for attachment. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such is received, manufactured, and/or prepared or by any particular characteristics of such connected dies.

Example method 500 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure) thereon at block 520 . Block 520 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 520 may, for example, share any or all features with any or all of the carrier receiving, manufacturing, and/or preparing discussed herein (eg, block 120 with respect to the example method 100 of FIG. 1 , block 320 with respect to the example method 300 of FIG. 3 , etc.) . Various example aspects of block 520 are provided in example 600A of Figure 6A.

As discussed herein, any or all of the supports discussed herein may, for example, include only bulk materials (eg, bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or in place of) the bulk material. Block 520 provides an example of the receipt, manufacture, and/or preparation of such carriers.

Block 520 may include forming RD structure 646a on bulk carrier 621a in any of a variety of ways, non-limiting examples of which are presented herein. In example embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to the second die interconnect structure 614 (which is later formed), The second die interconnect structure will eventually connect to functional dies 611 and 612 (which will be connected later).

FIG. 6A shows an example in which RD structure 646a includes three dielectric layers 647 and three conductive layers 648. Such numbers of layers are merely examples, and the scope of this disclosure is not limited thereto. In another example embodiment, RD structure 646a may include only a single dielectric layer 647 and a single conductive layer 648, two dielectric layers and two conductive layers, etc. Example redistribution (RD) structures 646a are formed on bulk carrier 621a material.

Dielectric layer 647 may be formed from any of a variety of materials (eg, Si ₃ N ₄ , SiO ₂ , SiON, PI, BCB, PBO, WPR, epoxy, or other insulating materials). The dielectric layer 647 may be formed using any of various processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layer 647 may, for example, be patterned to expose various surfaces (eg, exposing lower traces or pads of conductive layer 648, etc.).

Conductive layer 648 may be formed from any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). Conductive layer 648 may be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

Redistribution structure 646a may, for example, include conductors exposed at its outer surface (eg, exposed at the top surface of example 600A). Such exposed conductors may be used, for example, for attachment (or formation) of die interconnect structures (eg, at block 525 , etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metallization (UBM) formed thereon to enhance attachment (or formation) of the die interconnect structure. Such under-bump metal may include, for example, one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

U.S. Patent Application No. 14/823,689 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on August 11, 2015; and titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF"; Example redistribution structures and/or formations thereof are provided in U.S. Patent No. 8,362,612, DEVICE AND MANUFACTURING METHOD THEREOF; each of which is hereby incorporated by reference in its entirety.

The redistribution structure 646a may, for example, perform a fan-out redistribution of at least some electrical connections, such as laterally moving the electrical connections to at least a portion of the die interconnect structure 614 (to be formed) to where it will be via such die interconnect structure. 614 attaches functional dies 611 and 612 at a location outside the footprint. As another example, redistribution structure 646a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of die interconnect structure 614 (to be formed) to connected dies (to be connected). within the footprint of die 616b and/or to a location within the footprint of functional die 611 and 612 (to be connected). Redistribution structure 646a may also, for example, provide connectivity for various signals between functional die 611 and 612 (eg, in addition to the connections provided by connection die 616b).

In various example embodiments, block 520 may include forming only a first portion 646a of the entire RD structure 646, wherein a second portion 646b of the entire RD structure 646 may be formed later (eg, at block 570).

Generally, block 520 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure thereon. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of making such carriers and/or signal redistribution structures or by any specific features of such carriers and/or signal redistribution structures.

The example method 500 may include, at block 525 , forming a high-grain interconnect structure on an RD structure (eg, as provided at block 520 ). Block 525 may include forming a high-grain interconnect structure on the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

Block 525 may, for example, be associated with the receipt, fabrication, and/or preparation of any or all of the functional dies discussed herein (e.g., with respect to block 110 of the example method 100 of FIG. 1 and the formation of the second die interconnect structure 214 and/or the first Formation of die interconnect structure 213, block 347 with respect to example method 347 of FIG. 3, formation of second die interconnect structure 414, etc.) share any or all features (eg, second die interconnect structure formation features, etc. ).

Various example aspects of block 525 are provided in example 600B of Figure 6B. High interconnect structure 614 (and/or its formation) may be associated with second die interconnect structure 214 (and/or its formation) of FIG. 2A and/or with second die interconnect structure 414 (of FIG. 4H-2 and/or its formation) share any or all characteristics.

Generally, block 525 may include forming a high-grain interconnect structure on an RD structure (eg, as provided at block 520 ). Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming such high-grain interconnect structures and/or by the characteristics of any particular type of high-grain interconnect structures.

The example method 500 may include mounting the connection die to the RD structure at block 530 (eg, as provided at block 520 ). Block 530 may include performing such mounting (or attaching or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. Block 530 may, for example, share any or all features with any die attachment discussed herein (e.g., block 325 with respect to example method 300 shown in FIG. 3 and discussed herein, block 325 with respect to the example method 300 shown in FIG. 1 and discussed herein 100 squares 125 etc.). Various example aspects of block 530 are presented in example 600C shown in Figure 6C.

Block 530 may include, for example, attaching the backside of connection die 616b to RD structure 646a using a die attach adhesive (eg, tape, liquid, paste, etc.). Although connection die 616b is shown coupled to the dielectric layer of RD structure 646a in FIG. 6C, in other example implementations, the backside of connection die 616b may be coupled to a conductive layer (eg, to enhance heat dissipation, providing additional structural supports, etc.).

Additionally, as discussed herein, any connection die discussed herein may be bi-sided. In such example embodiments, the backside interconnect structures may be electrically connected to corresponding interconnect structures (eg, pads, lands, bumps, etc.) of RD structure 646a.

Generally, block 530 may include mounting the connection die to the RD structure (eg, as provided at block 520). Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of mounting the connection die.

Example method 500 may include encapsulation at block 535 . Block 535 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Block 535 may, for example, share any or all features with other encapsulated blocks (or steps) discussed herein (eg, with block 130 of example method 100 of FIG. 1 , with block 330 of example method 300 of FIG. 3 , etc.). Various example aspects of block 535 are presented at Figure 6D.

Block 535 may include, for example, performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level before individual modules are singulated. Referring to the example embodiment 600D shown in Figure 6D, the encapsulation material 651' may cover the top surface of the RD structure 646a, the tall pillars 614, the connecting die interconnect structure 617, the top surface (or active surface or front), and at least part (or all) of the side surface of the connecting die 616b.

Although encapsulation material 651 ′ (shown in FIG. 6D ) is shown as covering the top ends of high interconnect structure 614 and the top end of connecting die interconnect structure 617 , any or all of these ends may be removed from encapsulation material 651 'exposed (as shown in Figure 6E). Block 535 may, for example, include initially forming the encapsulation material 651' with the top ends of the various interconnects exposed or protruding (e.g., using film-assisted molding techniques, die seal molding techniques, etc.). Alternatively, block 535 may include forming the encapsulation material 651', followed by a thinning (or planarization or grinding) process (eg, performed at block 540) to thin the encapsulation material 651' sufficiently to expose the high-interference The top surface of any or all of the connection structure 614 and the connection die interconnect structure 617, etc.

Generally, block 535 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or by the characteristics of any particular type of encapsulation material or configuration thereof.

The example method 500 may include grinding the encapsulation material and/or various interconnect structures at block 540 . Block 540 may include performing such grinding (or any thinning or planarizing) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 540 are presented in example 600E shown in Figure 6E. Block 540 may, for example, share any or all features with other grinding (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, the encapsulation material 651 ′ may be initially formed to be thicker than the final desired thickness, and/or the high interconnect structure 614 and the connecting die interconnect structure 617 may be initially formed to be thicker than the final desired thickness. required thickness. In such example embodiments, block 540 may be performed to grind (or otherwise thin or planarize) encapsulation material 651 ′, high interconnect structure 614 , and/or connect die interconnect structure 617 . In example 600E shown in Figure 6E, encapsulation material 651, high interconnect structure 614 and/or connection die interconnect structure 617 have been milled to produce encapsulation material 651 and interconnect structures 613 and 617 (Figure 6E shown). The top surface of the ground encapsulation material 651, the top surface of the high interconnect structure 614, and/or the top surface of the connecting die interconnect structure 617 may be coplanar, for example.

It should be noted that in various example embodiments, film assist and/or sealing molding is utilized at block 535, such as using chemical or mechanical processes that thin the encapsulation material 651 more than the interconnect structures 614 and/or 617. Due to manufacturing processes, etc., the top surface of the high interconnect structure 614 and/or the top surface of the connecting die interconnect structure 617 may protrude from the top surface of the encapsulation material 651 .

Generally, block 540 may include grinding (or thinning or planarizing) the encapsulation material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 500 may include attaching (or coupling or mounting) the functional die to the high interconnect structure and connecting the die interconnect structure at block 545 . Block 545 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 545 may, for example, share any or all features with any of the die attach processes discussed herein. Various example aspects of block 545 are presented in example 600F shown in Figure 6F.

For example, die interconnect structures (eg, pads, bumps, etc.) of first functional die 611a may be mechanically and electrically connected to corresponding high interconnect structures 614 and to corresponding connected die interconnect structures 617 . Similarly, the die interconnect structures (eg, pads, bumps, etc.) of the second functional die 612a may be mechanically and electrically connected to the corresponding high interconnect structures 614 and to the corresponding connecting die interconnect structures 617.

Such interconnect structures may be connected in any of a variety of ways. For example, the connection can be performed by soldering. In example embodiments, the high die interconnect structure 614, the connecting die interconnect structure 617, and/or the corresponding interconnect structures of the first functional die 611a and the second functional die 612a may include components that may be reflowed to perform Attached solder cap (or other solder structure). Such solder caps can be resoldered, for example, by mass reflow, thermocompression bonding (TCB), etc. In another example embodiment, the connection may be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding without utilizing solder. Examples of such connections are provided in U.S. Patent Application No. 14/963,037 titled "Transient Interface Gradient Bonding for Metal Bonds" filed on December 8, 2015 and in January 2016. U.S. Patent Application No. 14/989,455 titled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof" filed on March 6 are provided in , the entire contents of each of said U.S. patent applications is hereby incorporated by reference. Any of a variety of techniques may be utilized to attach the functional die interconnect structure to the high interconnect structure 614 and connect the die interconnect structure 617 (eg, mass reflow, thermocompression bonding (TCB), direct metal pair Metal-to-metal joining of metals, conductive adhesives, etc.).

As shown in example embodiment 600F, a first connection die interconnect structure 617 of connection die 616b is connected to a corresponding interconnect structure of first functional die 611a, and a second connection die interconnect structure of connection die 616b 617 is connected to the corresponding interconnect structure of the second functional die 612a. When connected, connection die 616b provides electrical connections between the various die interconnect structures of the first functional die 611a and the second functional die 612a via the RD structure 298 of the connection die 616b (eg, as shown in FIG. 2B - Examples of 1 are shown in 200B-4, etc.).

In the example 600F shown in FIG. 6F , the height of the tall interconnect structure 614 may be, for example, equal to (or greater than) the connection die interconnect structure 217 and the support layer 290 b for attaching the connection die 616 b. The combined height of adhesive or other components to RD structure 646a.

Generally, block 545 may include attaching (or coupling or mounting) the functional die to the high interconnect structure and connecting the die to the interconnect structure. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or by the features of any particular type of attachment structure.

The example method 500 may include underfilling the functional die at block 550 . Block 550 may include performing such underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 550 may, for example, share any or All features. Various example aspects of block 550 are presented in example 600G shown in Figure 6G.

It should be noted that underfill may be applied between functional dies 611a and 612a and encapsulation material 651. In scenarios utilizing pre-applied underfill (PUF), such PUF may be applied to the functional dies 611a and 612a, and/or to the encapsulation material 651 and/or the interconnect structure prior to coupling the functional dies. The top exposed ends of 614 and 617.

Following the attachment performed at block 545, block 550 may include forming an underfill (eg, capillary underfill, injected underfill, etc.). As shown in example embodiment 600G of Figure 6G, underfill material 661 (e.g., any of the underfill materials discussed herein, etc.) may fully or partially cover the bottom surfaces of functional dies 611a and 612a (e.g., as shown in Figure 6G orientation), and/or at least a portion, if not all, of the sides of functional dies 611a and 612a. Underfill material 661 may also, for example, cover most (or all) of the top surface of encapsulation material 651 . Underfill material 661 may also surround, for example, high interconnect structures 614 and corresponding interconnect structures of functional dies 611a and 612a to which connecting die interconnect structures 617 are attached. In example embodiments where the ends of high interconnect structures 614 and/or connecting die interconnect structures 617 protrude from encapsulation material 651 , underfill material 661 may also surround such protrusions.

It should be noted that in various example implementations of example method 500, the underfill performed at block 550 may be skipped. For example, underfilling the functional die may be performed at another block (eg, at block 555, etc.). As another example, such bottom padding can be omitted entirely.

Generally, block 550 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or by the characteristics of any particular type of underfill material.

Example method 500 may include encapsulation at block 555 . Block 555 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 555 may, for example, share any information with other encapsulated blocks (or steps) discussed herein (eg, with block 535, with block 130 of example method 100 of FIG. 1, with block 330 of example method 300 of FIG. 3, etc.) or all features.

Various example aspects of block 555 are presented in example 600H shown in Figure 6H. For example, encapsulation material 652' (and/or its formation) may be the same as encapsulation material 226' (and/or its formation) of FIG. 2E, with encapsulation material 426 (and/or its formation) of FIG. 4K, with FIG. 6D's encapsulation material 651 (and/or its formation) etc. share any or all characteristics.

Encapsulation material 652' covers the top surface of encapsulation material 651, covers the side surfaces of underfill 661, covers at least some, if not all, of the side surfaces of functional die 611a and 612b, covers functional die 611a and The top surface of 612b etc.

As discussed herein with respect to other encapsulation materials (eg, encapsulation material 226' of Figure 2E, etc.), encapsulation material 652' does not necessarily need to be initially formed to cover the top surfaces of functional dies 611a and 612a. For example, block 555 may include forming encapsulation material 652' using film-assisted molding, seal molding, or the like.

Generally, block 555 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulation material, or the like.

Example method 500 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 560 . Block 560 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 560 may be used, for example, with other grinding (or thinning) blocks (or steps) discussed herein (eg, with block 135 of the example method 100 of FIG. 1 , with block 335 of the example method 300 of FIG. 3 , with block 540 etc.) share any or all characteristics.

Various example aspects of block 560 are presented in example 600I shown in Figure 6I. Example ground (or thinned or planarized, etc.) encapsulation material 652 (and/or its formation) may be the same as encapsulation material 226 (and/or its formation) of FIG. and/or its formation), shares any or all features with the encapsulation material 651 (and/or its formation) of FIG. 6E, and the like.

Block 560 may include, for example, grinding encapsulation material 652 and/or functional die 611a and 612a such that a top surface of encapsulation material 652 is coplanar with a top surface of functional die 611a and/or with a top surface of functional die 612a.

Generally, block 560 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 500 may include removing the carrier at block 565 . Block 565 may include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 565 may be shared with any carrier removal process discussed herein (eg, with block 145 and/or block 160 of example method 100 of FIG. 1 , with block 345 and/or block 360 of example method 300 of FIG. 3 , etc.) Any or all characteristics. Various example aspects of block 565 are shown in example 600J of Figure 6J.

For example, example 600J of Figure 6J shows first carrier 621a removed (eg, compared to example 600I of Figure 6I). Block 565 may include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical mechanical planarization, lift-off, shearing, thermal release or laser release, etc.). As another example, if an adhesive layer was utilized during the formation of RD structure 646a, such as at block 520, block 565 may include removing the adhesive layer.

It should be noted that in various example embodiments, as shown and discussed herein with respect to the example methods 100 and 300 of FIGS. 1 and 3 , a second carrier (eg, coupled to the encapsulating material 652 and/or coupled to the functional Grains 611a and 612a). In other example embodiments, various tool structures may be utilized in place of the carrier.

Generally, block 565 may include removing the carrier. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of removal of carriers or by the characteristics of any particular type of carrier.

The example method 500 may include completing a signal redistribution (RD) structure at block 570 . Block 570 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 570 may, for example, share any or all features with block 520 (eg, with respect to the RD structure forming aspect of block 520). Various aspects of block 570 are shown in example 600K shown in Figure 6K.

As discussed herein, for example, with respect to block 520, the carrier may have been (but need not have been) received (or manufactured or prepared) forming only a portion of the desired RD structure. In such example scenarios, block 570 may include completing formation of the RD structure.

Referring to Figure 6K, block 570 may include forming a second portion 646b of the RD structure on the first portion 646a of the RD structure (eg, the first portion 646a of the RD structure that has been received or fabricated or prepared at block 520). Block 570 may, for example, include forming the second portion 646b of the RD structure in the same manner as forming the first portion 646a of the RD structure.

It should be noted that in various embodiments, the first portion 646a of the RD structure and the second portion 646b of the RD structure may be formed using different materials and/or different processes. For example, the first portion 646a of the RD structure may be formed using an inorganic dielectric layer, while the second portion 646b of the RD structure may be formed using an organic dielectric layer. As another example, the first portion 646a of the RD structure may be formed with finer pitches (or thinner traces, etc.), while the second portion 646b of the RD structure may be formed with thicker pitches (or thicker traces, etc.) wait). As another example, the first portion 646a of the RD structure may be formed using a back-end-of-line (BEOL) semiconductor wafer fabrication (fab) process, and the second portion 646b of the RD structure may be formed using a post-fab electronic device packaging process. Additionally, the first portion 646a of the RD structure and the second portion 646b of the RD structure may be formed at different geographical locations.

Like the first portion 646a of the RD structure, the second portion 646b of the RD structure may have any number of dielectric and/or conductive layers.

As discussed herein, interconnect structures may be formed on RD structure 646b. In such example embodiments, block 565 may include forming under-bump metallization (UBM) on the exposed pads to enhance the formation (or attachment) of such interconnect structures.

Generally, block 570 may include completing a signal redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming signal redistribution structures or by the characteristics of any particular type of signal distribution structure.

The example method 500 may include forming an interconnect structure on the redistribution structure at block 575 . Block 575 may include forming an interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 575 may share any or all features with any interconnect structure discussed herein.

Various example aspects of block 575 are presented in example 600L shown in Figure 6L. Example interconnect structures 652 (eg, package interconnect structures, etc.) may include features of any of a variety of interconnect structures. For example, package interconnect structure 652 may include conductive balls (eg, solder balls, etc.), conductive bumps, conductive pillars, leads, etc.

Block 575 may include forming interconnect structure 652 in any of a variety of ways. For example, interconnect structure 652 may be adhered and/or printed on RD structure 646b (eg, adhered and/or printed to its corresponding pad 651 and/or UBM) and then reflowed. As another example, interconnect structures 652 (e.g., conductive balls, conductive bumps, pillars, leads, etc.) may be preformed prior to attachment and then attached, e.g., via reflow, plating, epoxy gluing, wire bonding, etc. RD structure 646b (eg, attached to its corresponding pad 651).

It should be noted that, as discussed above, the pads 651 of the RD structure 646b may be formed from under-bump metallization (UBM) or any metallization to assist in the formation (e.g., build, attach, couple, deposit, etc.) of the interconnect structure 652 ). Such UBM formation may be performed at block 570 and/or block 575, for example.

Generally, block 575 may include forming interconnect structures on the redistribution structure. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming such interconnect structures or by any particular characteristics of the interconnect structures.

Example method 500 may include singulation cutting at block 580 . Block 580 may include performing such singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 580 may, for example, share any or all features with any of the singulated cuts discussed herein (eg, as discussed with respect to block 165 of the example method 100 of FIG. 1 , as discussed with respect to the block 365 of the example method 300 of FIG. 3 , etc.) .

Various example aspects of block 580 are presented in example 600M shown in Figure 6M. The singulated cut structure (eg, corresponding to the encapsulating material portion 652a) may be the same as the singulated cut structure of FIG. 2L (eg, corresponding to the two encapsulating material portions 226a and 226b), or the same as the singulated cut structure of FIG. 4L. Granulated cut structures (eg, corresponding to the two encapsulating material portions 426a and 426b) and the like share any or all characteristics.

Generally, block 580 may include singulation cutting. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of singulation.

The example method 500 may include performing a continuation process at block 590 . Such continued processing may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 590 may share any or all features with block 190 of the example method 100 of FIG. 1, with block 390 of the example method 300 of FIG. 3, and so on.

For example, block 590 may include returning execution flow of example method 500 to any block thereof. As another example, block 590 may include directing execution flow of the example method 500 to any other method block (or step) discussed herein (e.g., with respect to the example method 100 of FIG. 1 , the example method 300 of FIG. 3 , the example method of FIG. 7 700 etc.).

As another example, as shown in example 200O of FIG. 2O, example 200P of FIG. 2P, and example 200Q of FIG. 2Q, block 590 may include forming the encapsulation material and/or underfill (or skip forming the encapsulation material and/or underfill). filling).

As discussed herein, functional dies and connection dies may be mounted to a substrate, for example, in a multi-die module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

7 illustrates a flowchart of an example method 700 of manufacturing an electronic device in accordance with various aspects of the present disclosure. Example method 700 may, for example, share any or all features with any other example method discussed herein (eg, example method 100 of FIG. 1 , example method 300 of FIG. 3 , example method 500 of FIG. 5 , etc.). 8A-8N illustrate cross-sectional views illustrating example electronic devices (eg, semiconductor packages, etc.) and example methods of fabricating the example electronic devices in accordance with various aspects of the present disclosure. 8A-8N may illustrate an example electronic device, such as in various blocks (or steps) of method 700 of FIG. 7 . Figures 7 and 8A-8N will now be discussed together. It should be noted that the order of the example blocks of method 700 may vary without departing from the scope of the present disclosure. In an example embodiment, the method 700 of Figure 7 can be considered similar to the method of Figure 5, but with the addition of block 742 for forming the second redistribution structure.

Example method 700 may begin execution at block 705. Method 700 may begin execution in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, method 700 may begin automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, or the like. As another example, method 700 may begin execution in response to an operator command to begin. Additionally, for example, method 700 may begin execution in response to receiving an execution flow from any other method block (or step) discussed herein.

Example method 700 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 710 . Block 710 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 710 may share any or all features with block 510 of example method 500 shown in FIG. 5 and discussed herein, with block 310 of example method 300 shown in FIG. 3 and discussed herein, and so on. Various aspects of block 710 are presented in examples 400A-1 through 400A-4 shown in Figure 4A. It should be noted that block 710 may also share any or all features, for example, with block 110 of the example method 100 shown in FIG. 1 and discussed herein.

Functional die 811a and 812a (and/or their formation), as shown in many of the figures in Figures 8A-8N, may, for example, be combined with functional die 611a and 612a (and/or their formation), functional die 411 and 412 (and /or their formation), functional grains 211 and 212 (and/or their formation), etc. share any or all characteristics. For example, and without limitation, functional dies 811a and 812a may include features of any of a variety of electronic components (eg, passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

Generally, block 710 may include receiving, fabricating, and/or preparing a plurality of functional dies. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such receiving and/or fabrication, nor by any specific features of such functional dies.

Example method 700 may include receiving, fabricating, and/or preparing a connection die at block 715 . Block 715 may include receiving, fabricating, and/or preparing a plurality of connection dies in any of a variety of manners, non-limiting examples of which are provided herein. For example, block 715 may share any or all features with block 115 of the example method 100 shown in FIG. 1 and discussed herein. Various example aspects of block 715 are presented in examples 200B-1 and 200B-7 shown in Figures 2B-1 through 2B-2. It should be noted that block 715 may also share any or all features, for example, with block 315 of the example method 100 shown in FIG. 3 and discussed herein, with block 515 of the example method 500 shown in FIG. 5 , and the like.

The connection die 816b and connection die interconnect structures 817 (and/or their formation) as shown in many of the figures in Figures 8A-8N may, for example, be related to the connection die 216b and connection die 216b of Figures 2B-1 through 2B-2. Granular interconnect structures 217 (and/or their formation) share any or all characteristics.

It should be noted that connecting die interconnect structure 817 (and/or its formation) may share any or all features with first die interconnect structure 213 (and/or its formation), for example. For example, in an example embodiment, instead of forming a first die interconnect structure such as first die interconnect structure 213 of FIG. 2A on functional die 211/212, the same may be formed on connection die 816b. or similar connecting die interconnect structure 817.

Generally, block 715 may include receiving, fabricating, and/or preparing the die for attachment. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner in which such is received, manufactured, and/or prepared or by any particular characteristics of such connected dies.

Example method 700 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure (or distribution structure) thereon at block 720 . Block 720 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 720 may be received, manufactured, and/or prepared, for example, with any or all of the carriers discussed herein (e.g., block 120 with respect to the example method 100 of FIG. 1 , block 320 with respect to the example method 300 of FIG. 3 , block 320 with respect to the example method 300 of FIG. 5 500's box 520 etc.) share any or all characteristics. Various example aspects of block 720 are provided in example 800A of Figure 8A.

As discussed herein, any or all of the supports discussed herein may, for example, include only bulk materials (eg, bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal redistribution (RD) structures on (or in place of) the bulk material. Block 720 provides an example of the receipt, manufacture, and/or preparation of such carriers.

Block 720 may include forming RD structure 846a on bulk carrier 821a in any of a variety of ways, non-limiting examples of which are presented herein. In example embodiments, one or more dielectric layers and one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to vertical interconnect structure 814 (which is later formed). The interconnect structure will eventually connect to the second redistribution structure 896 and/or functional dies 811 and 812 (which will be connected later). Therefore, RD structure 846a may be coreless. However, it should be noted that in various alternative embodiments, RD structure 846a may be a cored structure.

FIG. 8A shows an example in which RD structure 846a includes three dielectric layers 847 and three conductive layers 848. Such numbers of layers are merely examples, and the scope of this disclosure is not limited thereto. In another example embodiment, RD structure 846a may include only a single dielectric layer 847 and a single conductive layer 848, two dielectric layers and two conductive layers, etc. Example redistribution (RD) structure 846a is formed on bulk carrier 821a material.

Dielectric layer 847 may be formed from any of a variety of materials (eg, Si ₃ N ₄ , SiO ₂ , SiON, PI, BCB, PBO, WPR, epoxy, or other insulating materials). The dielectric layer 847 may be formed using any of various processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layer 847 may, for example, be patterned to expose various surfaces (eg, exposing lower traces or pads of conductive layer 848, etc.).

Conductive layer 848 may be formed from any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). Conductive layer 848 may be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

Redistribution structure 846a may, for example, include conductors exposed at its outer surface (eg, exposed at the top surface of example 800A). Such exposed conductors may be used, for example, for attachment (or formation) of die interconnect structures (eg, at block 725 , etc.). In such embodiments, the exposed conductors may include pads and may include, for example, under-bump metallization (UBM) formed thereon to enhance attachment (or formation) of the die interconnect structure. Such under-bump metal may include, for example, one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

U.S. Patent Application No. 14/823,689 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on August 11, 2015; and titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF"; Example redistribution structures and/or formations thereof are provided in U.S. Patent No. 8,362,612 "DEVICE AND MANUFACTURING METHOD THEREOF"; each of the foregoing applications is hereby incorporated by reference in its entirety.

The redistribution structure 846a may, for example, perform a fan-out redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of the vertical interconnect structures 814 (to be formed) to those that will be attached via such vertical interconnect structures 814 . The connected functional dies 811 and 812 are located outside the coverage area. As another example, redistribution structure 846a may perform fan-in redistribution of at least some electrical connections, such as laterally moving electrical connections to at least a portion of vertical interconnect structure 814 (to be formed) to connection dies (to be connected). 816b and/or to a location within the footprint of functional dies 811 and 812 (to be connected). Redistribution structure 846a may also, for example, provide connectivity for various signals between functional dies 811 and 812 (eg, in addition to the connections provided by connection die 816b).

In various example embodiments, block 720 may include forming only a first portion 846a of the entire RD structure 846, wherein a second portion 846b of the entire RD structure 846 may be formed later (eg, at block 770).

Generally, block 720 may include receiving, manufacturing, and/or preparing a carrier having a signal redistribution (RD) structure thereon. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of making such carriers and/or signal redistribution structures or by any specific features of such carriers and/or signal redistribution structures.

The example method 700 may include, at block 725 , forming a vertical interconnect structure on an RD structure (eg, as provided at block 720 ). Block 725 may include forming a vertical interconnect structure on the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. It should be noted that vertical interconnect structures may also be referred to herein as tall bumps, tall pillars, tall pillars, die interconnect structures, functional die interconnect structures, etc.

Block 725 may, for example, relate to the receipt, fabrication, and/or preparation of any or all functional die discussed herein (e.g., with respect to block 110 of the example method 100 of FIG. 1 and the formation of the second die interconnect structure 214 and/or the first Formation of die interconnect structure 213 , block 347 with respect to example method 347 of FIG. 3 and formation of second die interconnect structure 414 with respect to block 525 of example method 500 of FIG. 5 , etc.) share any or all features (e.g., , second grain interconnection structure formation characteristics, etc.).

Various example aspects of block 725 are provided in example 800B of Figure 8B. Vertical interconnect structure 814 (and/or its formation) may be associated with second die interconnect structure 214 (and/or its formation) of FIG. 2A and/or with second die interconnect structure 414 (of FIG. 4H-2 and/or its formation) share any or all characteristics. Additionally, vertical interconnect structure 814 (and/or its formation) may share any or all features with interconnect structure 614 (and/or its formation) of FIG. 6B .

Generally, block 725 may include forming a vertical interconnect structure on the RD structure (eg, as provided at block 720). Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming such vertical interconnect structures and/or by the characteristics of any particular type of vertical interconnect structures.

The example method 700 may include mounting the connection die to the RD structure at block 730 (eg, as provided at block 720). Block 730 may include performing such mounting (or attaching or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. Block 730 may, for example, share any or all features with any die attachment discussed herein (e.g., block 530 with respect to example method 500 shown in FIG. 5 and discussed herein, block 530 with respect to the example method 500 shown in FIG. 3 and discussed herein 300, block 125 with respect to the example method 100 shown in FIG. 1 and discussed herein, etc.). Various example aspects of block 730 are presented in example 800C shown in Figure 8C.

Block 730 may include, for example, attaching the backside of connection die 816b to RD structure 846a using a die attach adhesive (eg, tape, liquid, paste, etc.). Although connection die 816b is shown coupled to the dielectric layer of RD structure 846a in FIG. 8C, in other example embodiments, the backside of connection die 816b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural supports, etc.).

Additionally, as discussed herein, any connection die discussed herein may be bi-sided. In such example embodiments, the backside interconnect structures may be electrically connected to corresponding interconnect structures (eg, pads, lands, bumps, etc.) of RD structure 846a.

Generally, block 730 may include mounting the connection die to the RD structure (eg, as provided at block 720). Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of mounting the connection die.

Example method 700 may include encapsulation at block 735 . Block 735 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 735 may be used, for example, with other encapsulated blocks (or steps) discussed herein (eg, with block 130 of the example method 100 of FIG. 1 , with block 330 of the example method 300 of FIG. 3 , with the example method 500 of FIG. 5 of block 530, etc.) share any or all characteristics. Various example aspects of block 735 are presented at Figure 8D.

Block 735 may include, for example, performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein can be performed at the panel or wafer level before individual modules are singulated. Referring to the example embodiment 800D shown in Figure 8D, the encapsulation material 851' may cover the top surface of the RD structure 846a, the vertical interconnect structure 814, the connecting die interconnect structure 817, the top surface (or active surface) of the connecting die 816b or front), and at least part (or all) of the side surface of connecting die 816b.

Although encapsulation material 851 ′ (shown in FIG. 8D ) is shown covering the top ends of vertical interconnect structures 814 and the top ends of connecting die interconnect structures 817 , any or all of these ends may be removed from the encapsulation material 851 'exposed (as shown in Figure 8E). Block 735 may, for example, include initially forming the encapsulation material 851&apos; with the top ends of the various interconnects exposed or protruding (e.g., using film-assisted molding techniques, die seal molding techniques, etc.). Alternatively, block 735 may include forming the encapsulation material 851', followed by a thinning (or planarization or grinding) process (eg, performed at block 740) to thin the encapsulation material 851' sufficiently to expose the vertical interconnects. The top surface of any or all of the connection structure 814 and the connection die interconnect structure 817, etc.

Generally, block 735 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation or by the characteristics of any particular type of encapsulation material or configuration thereof.

The example method 700 may include grinding the encapsulation material and/or various interconnect structures at block 740 . Block 740 may include performing such grinding (or any thinning or planarizing) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 740 are presented in example 800E shown in Figure 8E. Block 740 may, for example, share any or all features with other grinding (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, the encapsulation material 851' may be initially formed to be thicker than the final desired thickness, and/or the vertical interconnect structures 814 and the connecting die interconnect structures 817 may be initially formed to be thicker than the final desired thickness. required thickness. In such example embodiments, block 740 may be performed to grind (or otherwise thin or planarize) the encapsulation material 851&apos;, the vertical interconnect structure 814, and/or the connection die interconnect structure 817. In example 800E shown in FIG. 8E , encapsulation material 851 , vertical interconnect structures 814 and/or connection die interconnect structures 817 have been milled to produce encapsulation material 851 and vertical interconnect structures 814 and connection die interconnect structures. Connect structure 817 (shown in Figure 8E). The top surface of the ground encapsulation material 851, the top surface of the vertical interconnect structures 814, and/or the top surface of the connecting die interconnect structures 817 may be coplanar, for example.

It should be noted that in various example embodiments, such as using a chemical or mechanical process that thins the encapsulation material 851 more than the vertical interconnect structures 814 and/or the connecting die interconnect structures 817 , at block 735 . The top surface of the vertical interconnect structure 814 and/or the top surface of the connecting die interconnect structure 817 may protrude from the top surface of the encapsulation material 851 due to film-assisted and/or sealing molding processes.

Generally, block 740 may include grinding (or thinning or planarizing) the encapsulation material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 700 may include forming a second signal redistribution (RD) structure (or distribution structure) at block 742 . Block 742 may include performing such formation in any of a variety of ways, non-limiting examples of which are provided herein.

Block 742 may be formed, for example, with any or all of the signal distribution structures discussed herein (eg, block 120 with respect to the example method 100 of FIG. 1 , block 320 with respect to the example method 300 of FIG. 3 , block 520 with respect to the example method 500 of FIG. 5 , regarding block 720, etc.) share any or all characteristics. Various example aspects of block 742 are provided in example 800F of Figure 8F.

As discussed herein, example structure 800E produced by block 740 may include a top surface that includes a top surface of encapsulation material 851 , vertical interconnect structures 814 , and/or exposed tips of connecting die interconnect structures 817 surface, the vertical interconnect structure 814 and/or the exposed top side surface of the connecting die interconnect structure 817, etc. Block 742 may include, for example, forming a second signal redistribution structure on any or all such surfaces.

Block 742 may include forming a second RD structure in any of a variety of ways, such as forming a second RD structure on top of structure 800E, non-limiting examples of which are presented herein. In example embodiments, one or more dielectric layers and one or more conductive layers may be formed to connect electrical connections between vertical interconnect structures 814 and/or connecting die interconnect structures 817 laterally and/or Vertically distributed to electrical components mounted therein (eg, distributed to semiconductor dies such as dies 811 and 812, passive electrical components, shielding components, etc.). 8F shows an example in which the second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. Such numbers of layers are merely examples, and the scope of this disclosure is not limited thereto. In another example embodiment, the second RD structure 896 may include only a single dielectric layer 897 and a single conductive layer 898, two dielectric layers and two conductive layers, etc. Therefore, the second RD structure 896 may be coreless. However, it should be noted that in various alternative embodiments, the second RD structure 896 may be a cored structure. In another example embodiment, the second redistribution (or distribution) structure 896 may include only a single vertical metal structure (eg, one or more layers), such as an under-bump metallization structure.

Dielectric layer 897 may be formed from any of a variety of materials (eg, Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy, or other insulating materials). The dielectric layer 897 may be formed using any of a variety of processes (eg, PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layer 897 may, for example, be patterned to expose various surfaces (eg, exposing lower traces or pads of conductive layer 898, etc.).

Conductive layer 898 may be formed from any of a variety of materials (eg, copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). Conductive layer 898 may be formed using any of a variety of processes (eg, electrolytic plating, electroless plating, CVD, PVD, etc.).

The second RD structure 896 may, for example, include a conductor exposed at its outer surface (eg, exposed at the top surface of example 800F). Such exposed conductors may be used, for example, for attachment (or formation) of electrical components and/or attachment structures thereof (eg, at block 745 , etc.). Such exposed conductors may include, for example, pad structures, under-bump metallization structures, and the like. In such embodiments, the exposed conductors may include pads, and may include, for example, under-bump metallization (UBM) formed thereon to enhance attachment (or formation) of the component and/or its interconnect structure. Such under-bump metal may include, for example, one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive materials.

U.S. Patent Application No. 14/823,689 titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF" filed on August 11, 2015; and titled "SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF"; Example redistribution structures and/or formations thereof are provided in U.S. Patent No. 8,362,612 "DEVICE AND MANUFACTURING METHOD THEREOF"; each of the foregoing applications is hereby incorporated by reference in its entirety.

The second RD structure 896 may, for example, perform fan-out redistribution of at least some electrical connections or signals from the connecting die interconnect structure 817 and/or the vertical interconnect structure 814 (attached to the second RD structure 896 At least a portion of the bottom surface of the connecting die interconnect structure 817 (or the connecting die 816 b ) and/or the vertical interconnect structure 814 is laterally moved to a position outside the footprint of the connecting die interconnect structure 817 (or the connecting die 816 b ). As another example, the second RD structure 896 may perform fan-in redistribution of at least some electrical connections or signals, moving the electrical connections or signals laterally from at least a portion of the connecting die interconnect structure 817 and/or the vertical interconnect structure 814 to Locations within the footprint of connection die interconnect structure 817 (or connection die 816b) and/or vertical interconnect structure 814. Second RD structure 896 may also, for example, provide connectivity for various signals between functional dies 811 and 812 (eg, in addition to the connections provided by connection die 816b, in addition to the connections provided by RD structure 846a, etc.) .

Although example block 742 has been described as forming the second RD structure layer by layer, it should be noted that the second RD structure may be received in a preformed format and then attached at block 742 (eg, welded, epoxy glued, etc.) Second RD structure.

Generally, block 742 may include forming a second redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of making such carriers and/or signal redistribution structures or by any specific features of such carriers and/or signal redistribution structures.

Example method 700 may include attaching (or coupling or mounting) the functional die to a second redistribution (RD) structure (eg, as formed at block 742 ) at block 745 . Block 745 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 745 may, for example, share any or all features with any of the die attach processes discussed herein. Various example aspects of block 745 are presented in example 800G shown in Figure 8G.

For example, the die interconnect structures (eg, pads, bumps, etc.) of the first functional die 811a may be mechanically and electrically connected to corresponding conductors (eg, pads, under-bump metal, etc.) of the second RD structure 896 exposed traces, etc.). For example, the die interconnect structure of the first functional die 811a may be electrically connected to the corresponding vertical interconnect structure 814 and/or to the corresponding connecting die interconnect structure 817 through the conductors of the second RD structure 896. Similarly, the die interconnect structures (eg, pads, bumps, etc.) of the second functional die 812a may be mechanically and electrically connected to corresponding conductors (eg, pads, under-bump metallization) of the second RD structure 896 , exposed traces, etc.). For example, the die interconnect structure of the second functional die 812a may be electrically connected to the corresponding vertical interconnect structure 814 and/or to the corresponding connecting die interconnect structure 817 through the conductors of the second RD structure 896.

Such interconnect structures of functional dies can be connected in any of a variety of ways. For example, the connection can be performed by soldering. In example embodiments, the interconnect structures of functional dies 811a and 812a may include solder caps (or other solder structures) that may be resoldered by mass reflow, thermocompression bonding (TCB), or the like. Similarly, the pad or under-bump metal of the second RD structure 896 may have been formed (eg, at block 742 ) with a solder cap (or other solder structure). In another example embodiment, the connection may be performed by direct metal-to-metal (eg, copper-to-copper, etc.) bonding without utilizing solder and/or by utilizing one or more intermediate non-solder metal layers. Examples of such connections are provided in U.S. Patent Application No. 14/963,037 titled "Transient Interface Gradient Bonding for Metal Bonds" filed on December 8, 2015 and in January 2016. U.S. Patent Application No. 14/989,455 titled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof" filed on March 6 are provided in , the entire contents of each of said U.S. patent applications is hereby incorporated by reference. The functional die interconnect structure may be attached to the second RD structure 896 using any of a variety of techniques (e.g., mass reflow, thermocompression bonding (TCB), direct metal-to-metal metal-to-metal bonding, conductive bonding agents, etc.).

As shown in example embodiment 800G, first connecting die interconnect structures 817 of connecting die 816b are connected to corresponding interconnect structures of first functional die 811a through second RD structures 896, and second connecting die 816b The connecting die interconnect structure 817 is connected to the corresponding interconnect structure of the second functional die 812a through the second RD structure 896. When connected, connection die 816b (eg, combined with second RD structure 896) is among the various die interconnect structures of first functional die 811a and second functional die 812a via RD structure 298 of connection die 816b. Provide electrical connections between them (for example, as shown in example 200B-4 of Figure 2B-1, etc.).

In the example 800G shown in FIG. 8F , the height of the vertical interconnect structure 814 may be, for example, equal to (or greater than) the connection die interconnect structure 217 and the support layer 290 b for attaching the connection die 816 b. The combined height of adhesive or other components to RD structure 846a. Thus, the second RD structure 896 may, for example, include a generally planar lower surface, a generally uniform thickness, and a generally planar upper surface.

Generally, block 745 may include attaching (or coupling or mounting) the functional die to the second RD structure. Accordingly, the scope of the present disclosure should not be limited by the features of any particular manner of performing such attachment or by the features of any particular type of attachment structure.

Example method 700 may include underfilling the functional die at block 750 . Block 750 may include performing such underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 750 may, for example, be consistent with any of the underfills discussed herein (eg, with block 155 and/or block 175 of example method 100 of FIG. 1 , with block 355 and/or block 375 of example method 300 of FIG. 3 , with block 375 of example method 300 of FIG. 5 Instance method 500, block 550, etc.) share any or all characteristics. Various example aspects of block 750 are presented in example 800H shown in Figure 8H.

It should be noted that underfill may be applied between functional dies 811a and 812a and second RD structure 896. In scenarios utilizing pre-applied underfill (PUF), such PUF may be applied to functional dies 811a and 812a, and/or to second RD structures 896 and/or prior to coupling functional dies 811a and 812a. or the top exposed conductor of the second RD structure 896 (eg, pad, under-bump metallization, exposed trace, etc.).

Following the attachment performed at block 745, block 750 may include forming an underfill (eg, capillary underfill, injected underfill, etc.). As shown in example embodiment 800H of Figure 8H, underfill material 861 (eg, any of the underfill materials discussed herein, etc.) may fully or partially cover the bottom surfaces of functional dies 811a and 812a (eg, as shown in Figure 8H orientation), and/or at least a portion, if not all, of the sides of functional dies 811a and 812a. The underfill material 861 may also cover most (or all) of the top surface of the second RD structure 896 , for example. Underfill material 861 may also surround, for example, corresponding portions of functional dies 811a and 812a to which respective interconnect structures (eg, pads, lands, traces, under-bump metallization, etc.) of second RD structure 896 are attached. Interconnect structures (e.g., pads, bumps, etc.). In example embodiments in which the ends of the interconnect structures of second RD structure 896 protrude from the top surface (eg, the top dielectric layer surface) of second RD structure 896 , underfill material 861 may also surround such protrusions. part.

It should be noted that in various example implementations of example method 700, the underfill performed at block 750 may be skipped. For example, underfilling the functional die may be performed at another block (eg, at block 755, etc.). As another example, such bottom padding can be omitted entirely.

Generally, block 750 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such underfill or by the characteristics of any particular type of underfill material.

Example method 700 may include encapsulation at block 755 . Block 755 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 755 may be used, for example, with other encapsulated blocks (or steps) discussed herein (eg, with block 735 , with block 130 of example method 100 of FIG. 1 , with block 330 of example method 300 of FIG. 3 , with block 330 of example method 300 of FIG. 5 The instance methods 500 of blocks 535 and 555 etc.) share any or all characteristics.

Various example aspects of block 755 are presented in example 800I shown in Figure 8I. For example, encapsulation material 852' (and/or its formation) may be the same as encapsulation material 226' (and/or its formation) of FIG. 2E, with encapsulation material 426 (and/or its formation) of FIG. 4K, with FIG. The encapsulation materials 651 and 652' of 6D and 6H (and/or their formation) share any or all characteristics with the encapsulation material 851 of Figure 8E and the like.

Encapsulation material 852' covers the top surface of second RD structure 896, covers the side surfaces of underfill 861, covers the top surface of underfill 861 (eg, between die 811a and 812a), covers functional die 811a and 812a, cover the top surfaces of functional dies 811a and 812a, etc. In other examples, encapsulation material 852' may replace underfill 861, thus providing underfill between functional die 811a and/or 812a and second RD structure 896.

As discussed herein with respect to other encapsulation materials (eg, encapsulation material 226' of Figure 2E, etc.), encapsulation material 852' does not necessarily need to be initially formed to cover the top surfaces of functional dies 811a and 812a. For example, block 755 may include forming encapsulation material 852' using film-assisted molding, seal molding, or the like.

Generally, block 755 may include encapsulation. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such encapsulation, the characteristics of any particular type of encapsulating material, or the like.

Example method 700 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 760 . Block 760 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 760 may be used, for example, with other grinding (or thinning) blocks (or steps) discussed herein (eg, with block 135 of example method 100 of FIG. 1 , with block 335 of example method 300 of FIG. 3 , with block 335 of example method 300 of FIG. 5 The example method 500 shares any or all features of blocks 540 and 555, with block 735, etc.).

Various example aspects of block 760 are presented in example 800J shown in Figure 8J. Example ground (or thinned or planarized, etc.) encapsulation material 852 (and/or its formation) may be the same as encapsulation material 226 (and/or its formation) of FIG. 2F , same as encapsulation material 426 ( and/or their formation), share any or all characteristics with encapsulation materials 651 and 652 (and/or their formation) of Figures 6E and 6I, with encapsulation material 851, etc.

Block 760 may include, for example, grinding encapsulation material 852 and/or functional die 811a and 812a such that a top surface of encapsulation material 852 is coplanar with a top surface of functional die 811a and/or with a top surface of functional die 812a.

Generally, block 760 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 700 may include removing the carrier at block 765 . Block 765 may include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 765 may be associated with any of the carrier removal processes discussed herein (eg, with block 145 and/or block 160 of the example method 100 of FIG. 1 , with block 345 and/or block 360 of the example method 300 of FIG. 3 , with FIG. Instances of 5, methods 500, blocks 565, etc.) share any or all characteristics. Various example aspects of block 765 are shown in example 800K of Figure 8K.

For example, example 800K of Figure 8K shows first carrier 821a removed (eg, compared to example 800J of Figure 8J). Block 765 may include performing such carrier removal in any of a variety of ways (eg, grinding, etching, chemical mechanical planarization, lift-off, shearing, thermal release or laser release, etc.). As another example, if an adhesive layer was utilized during the formation of RD structure 846a, such as at block 720, block 765 may include removing the adhesive layer.

It should be noted that in various example embodiments, as shown and discussed herein with respect to the example methods 100 and 300 of FIGS. 1 and 3 , a second carrier (eg, coupled to the encapsulating material 852 and/or coupled to the functional Grains 811a and 812a). In other example embodiments, various tool structures may be utilized in place of the carrier.

Generally, block 765 may include removing the carrier. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of removing the carrier or by the characteristics of any particular type of carrier.

The example method 700 may include completing the signal redistribution (RD) structure at block 770 (eg, if the RD structure 846a is not fully formed at block 820). Block 770 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 770 may, for example, share any or all features with block 720 (eg, with respect to the RD structure forming aspect of block 720). Various aspects of block 770 are presented in example 800L shown in Figure 8L.

As discussed herein, for example, with respect to block 720, the carrier may have been (but need not have been) received (or manufactured or prepared) forming only a portion of the desired RD structure. In such example scenarios, block 770 may include completing formation of the RD structure.

Referring to Figure 8L, block 770 may include forming a second portion 846b of the RD structure on the first portion 846a of the RD structure (eg, the first portion 846a of the RD structure that has been received or fabricated or prepared at block 720). Block 770 may, for example, include forming the second portion 846b of the RD structure in the same manner as forming the first portion 846a of the RD structure.

It should be noted that in various embodiments, the first portion 846a of the RD structure and the second portion 846b of the RD structure may be formed using different materials and/or different processes. For example, the first portion 846a of the RD structure may be formed using an inorganic dielectric layer, while the second portion 846b of the RD structure may be formed using an organic dielectric layer. As another example, the first portion 846a of the RD structure may be formed with finer pitches (or thinner traces, etc.), while the second portion 846b of the RD structure may be formed with thicker pitches (or thicker traces, etc.) wait). As another example, the first portion 846a of the RD structure may be formed using a back-end-of-line (BEOL) semiconductor wafer fabrication (fab) process, and the second portion 846b of the RD structure may be formed using a post-fab electronic device packaging process. Additionally, the first portion 846a of the RD structure and the second portion 846b of the RD structure may be formed at different geographic locations.

Like the first portion 846a of the RD structure, the second portion 846b of the RD structure may have any number of dielectric and/or conductive layers.

As discussed herein, interconnect structures may be formed on RD structure 846b. In such example embodiments, block 765 may include forming under-bump metallization (UBM) on the exposed pads to enhance the formation (or attachment) of such interconnect structures.

Generally, block 770 may include completing a signal redistribution (RD) structure. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming signal redistribution structures or by the characteristics of any particular type of signal distribution structure.

Example method 700 may include forming an interconnect structure on the redistribution structure at block 775 . Block 775 may include forming an interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 775 may share any or all features with any interconnect structure discussed herein.

Various example aspects of block 775 are presented in example 800M shown in Figure 8M. Example interconnect structures 852 (eg, package interconnect structures, etc.) may include features of any of a variety of interconnect structures. For example, package interconnect structure 852 may include conductive balls (eg, solder balls, etc.), conductive bumps, conductive pillars, leads, etc.

Block 775 may include forming interconnect structure 852 in any of a variety of ways. For example, interconnect structure 852 may be adhered and/or printed on RD structure 846b (eg, adhered and/or printed to its corresponding pad 851 and/or UBM) and then reflowed. As another example, interconnect structure 852 (e.g., conductive balls, conductive bumps, pillars, leads, etc.) may be pre-formed prior to attachment and then attached to RD structure 846b, such as via reflow, plating, epoxy, wire bonding, etc. (e.g., attached to its corresponding pad 851).

It should be noted that, as discussed above, the pads 851 of the RD structure 846b may be formed from under-bump metallization (UBM) or any metallization to assist in the formation (e.g., build, attach, couple, deposit, etc.) of the interconnect structure 852 ). For example, such UBM formation may be performed at block 770 and/or block 775.

Generally, block 775 may include forming interconnect structures on the redistribution structure. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming such interconnect structures or by any particular characteristics of the interconnect structures.

Example method 700 may include singulation cutting at block 780 . Block 780 may include performing such singulation in any of a variety of ways, non-limiting examples of which are discussed herein. Block 780 may, for example, be associated with any of the singulation cuts discussed herein (eg, as discussed with respect to block 165 of the example method 100 of FIG. 1 , as discussed with respect to block 365 of the example method 300 of FIG. 3 , as with respect to the example of FIG. 5 (discussed in block 580 of method 500, etc.) share any or all characteristics.

Various example aspects of block 780 are presented in example 800N shown in Figure 8N. The singulated cut structure (eg, corresponding to the encapsulating material portion 852a) may be the same as the singulated cut structure of FIG. 2L (eg, corresponding to the two encapsulating material portions 226a and 226b), or the same as the singulated cut structure of FIG. 4L. The granulated cut structure (eg, corresponding to the two encapsulating material portions 426a and 426b) shares any or all features with the single granulated cut structure 600M of FIG. 6M, and the like.

Generally, block 780 may include cutting. Accordingly, the scope of the present disclosure should not be limited by the characterization of any particular manner of cutting.

Example method 700 may include performing continuation processing at block 790 . Such continued processing may include any of a variety of features, non-limiting examples of which are provided herein. For example, block 790 may share any or all features with block 190 of the example method 100 of FIG. 1 , with block 390 of the example method 300 of FIG. 3 , with block 590 of the example method 500 of FIG. 5 , etc.

For example, block 790 may include returning execution flow of example method 700 to any block thereof. As another example, block 790 may include directing execution flow of the example method 700 to any other method block (or step) discussed herein (e.g., with respect to the example method 100 of FIG. 1 , the example method 300 of FIG. 3 , the example method of FIG. 5 500 etc.).

As another example, as shown in example 200O of FIG. 2O , example 200P of FIG. 2P , and example 200Q of FIG. 2Q , block 790 may include forming the encapsulation material and/or underfill (or skip forming the encapsulation material and/or underfill). filling).

As discussed herein, functional dies and connection dies may be mounted to a substrate, for example, in a multi-die module configuration. Non-limiting examples of such configurations are shown in Figures 9 and 10.

9 illustrates a top view of an example electronic device 900 in accordance with various aspects of the present disclosure. Example electronic device 900 may, for example, share any or all features with any or all electronic devices discussed herein. For example, functional dies 911 and 912 may share any or all characteristics with any or all of the functional dies discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, etc.) . As another example, connection die 916 may share any or all characteristics with any or all connection dies discussed herein (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.). Additionally, for example, substrate 930 may share any or all features with any or all substrates and/or RD structures discussed herein (288, 488, 646, 846, 896, etc.).

10 illustrates a top view of an example electronic device in accordance with various aspects of the present disclosure. Example electronic device 1000 may, for example, share any or all features with any or all electronic devices discussed herein. For example, functional die (functional die 1 through functional die 10) may be associated with any or all of the functional die discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, 911, 912, etc.) share any or all characteristics. As another example, the connection dies (connection die 1 through connection die 10) may be associated with any or all of the connection dies discussed herein (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, 916, etc.) Share any or all characteristics. Additionally, for example, substrate 1030 may share any or all features with any or all substrates and/or RD structures discussed herein (288, 488, 646, 846, 896, 930, etc.).

Although the illustrations discussed herein generally include connecting dies between two functional dies, the scope of the present disclosure is not limited thereto. For example, as shown in Figure 10, connection die 9 is connected to three functional die (eg, functional die 2, functional die 9, and functional die 10), such as each such functional die being electrically connected to each other . Therefore, a single connection die can couple multiple functional die (eg, two functional die, three functional die, four functional die, etc.).

Additionally, although the illustrations discussed herein generally include functional dies connected to only one connection die, the scope of the present disclosure is not limited in this regard. For example, a single functional die can be connected to two or more connecting dies. For example, as shown in Figure 10, functional die 1 is connected to many other functional die via many corresponding connection die.

The discussion herein contains a number of illustrative figures illustrating various portions of a semiconductor device assembly (or package) and/or a method of fabricating the same. For purposes of clarity of illustration, the drawings do not show all aspects of each example component. Any example component presented herein may share any or all characteristics with any or all other components presented herein.

In summary, aspects of the present disclosure provide a semiconductor package structure and methods for fabricating semiconductor packages. As non-limiting examples, aspects of the present disclosure provide various semiconductor package structures including connection dies that route electrical signals between multiple other semiconductor dies and methods of fabricating the same. Although the foregoing has been described with reference to certain aspects and examples, those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the disclosure. Therefore, it is intended that this disclosure not be limited to the particular examples disclosed, but that this disclosure will include all examples falling within the scope of the appended claims.

100:Instance method/method 105:square 110: Square 115:square 120:square 125:square 130:block 135:square 140:block 145:square 150:block 155:block 160:block 165:square 170:block 175:block 190:block 200A-1:Examples 200A-2:Examples 200A-3: Example/Example Wafer 200A-4:Examples 200B-1: Example/Wafer 200B-2:Examples 200B-3:Examples 200B-4:Examples 200B-5:Examples 200B-6:Examples 200B-7:Examples 200C:Example 200D:Example 200E:Example 200F:Example 200G:Instance 200H:Example 200I:Example 200J:Example 200K:Instances 200L:Example 200M:Instance 200N:Example 200O: Example/Example Implementation Plan 200P: Example/Example Implementation Plan 200Q: Example/Example Implementation Plan 201: Functional grain 202: Functional grain 203: Functional grain 204: Functional grain 211: Instance die/functional die/first functional die/first die 212: Instance die/Function die/Second function die/Second die 213: Die interconnection structure/first die interconnection structure 214: Die interconnection structure/second die interconnection structure 216a: Instance connection die/connection die 216b: Thin connecting die/connecting die 216c: connecting die 217: Connecting die interconnect structure 217b: Connecting die interconnect structure 221: Carrier 223: Adhesive material/adhesive layer/underfill 224: Bottom filling 225: Encapsulation material 226: Encapsulation material 226’: encapsulation material 226a: Encapsulation material part 226b: Encapsulation material part 231:Second carrier 288:Substrate 290:Support layer 290a: Support layer 290b: Support layer 291:Basic dielectric layer 291b: Basic dielectric layer 292: First conductive trace 292b: First conductive trace 293: First dielectric layer 293b: first dielectric layer 294:Conductive via 294b: Conductive via 295: Second conductive trace 295b: Second conductive trace 296: Second dielectric layer 296b: Second dielectric layer 298:Redistribution (RD) structure 298b: Redistribution (RD) structure 299: The second group of connected die interconnect structures/second connected die interconnect structures 300:Instance method/method 305: Square 310:block 315:square 320:block 325:square 330:block 335:block 340:block 345:block 347:Block 350:block 355:block 360:block 365:block 370:block 375:block 390:block 400A-1: Example 400A-2: Example 400A-3: Example 400A-4: Example 400B-1: Example 400B-2:Example 400C: Example 400D:Example 400E:Example 400F:Example 400G:Instance 400H: Example 400H-2: Example/Example Implementation Plan 400I:Instance 400J:Example 400K:Instances 400L:Example 400M:Instance 400N:Example 401: Functional grain 402: Functional grain 403: Functional grain 404: Functional grain 411: Functional grain 412: Functional grain 413: First die interconnect structure 414: Second die interconnection structure 416a: connecting die 416b: connecting die 417: Connecting die interconnect structure/passivation layer 421: Carrier 423: Adhesive/underfill 424: Bottom filling 426: Encapsulation material 426’: Encapsulation material 426a: Encapsulation material part 426b: Encapsulation material part 431:Second carrier 488:Substrate 500:Instance method/method 505:block 510:block 515:square 520:block 525:square 530:block 535:block 540:block 545:block 550:block 555:block 560:block 565:block 570:block 575:block 580:block 590:block 600A:Example 600B:Example 600C: Example 600D:Example 600E:Example 600F:Example 600G:Instance 600H: Example 600I:Instance 600J:Example 600K:Instances 600L:Example 600M:Instance 611a: First functional grain 612a: Second functional grain 614: Column/Interconnect Structure 616b: connecting die 617: Connection die interconnection structure/interconnection structure 621a: Block carrier 646a: Redistribution (RD) structure 646b:RD structure 647: Dielectric layer 648: Conductive layer 651: Encapsulation material 651’: Encapsulation material 652: Auxiliary interconnection structure 652’: Encapsulation material 652a: Encapsulation material part 661: Bottom filling material 700:Instance method/method 705:block 710:block 715:block 720:block 725:block 730:block 735:block 740:block 742:block 745:block 750:block 755:block 760:block 765:block 770:block 775:block 780:block 790:block 800A: Example 800B:Example 800C: Example 800D:Example 800E:Example 800F:Example 800G:Instance 800H: Example 800I:Instance 800J:Example 800K:Instance 800L:Example 800M:Instance 800N:Example 811a: Functional grain 812a: Functional grain 814:Vertical interconnect structure 816b: connecting die 817: Connecting die interconnect structure 821a: Block carrier 846a: Redistribution (RD) Structure/Part 1 846b: Redistribution (RD) Structure/Part 2 847:Dielectric layer 848: Conductive layer 851: Encapsulation material 851’: Encapsulation material 852: Encapsulation material 852’: Encapsulation material 852a: Encapsulation material part 861: Bottom filling material 896: Second redistribution (RD) structure 897:Dielectric layer 898: Conductive layer 900:Example electronic device 911: Functional grain 912: Functional grain 916: Connect the die 930:RD structure 1000:Example electronic device 1030:Substrate

[FIG. 1] A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIGS. 2A-2Q] illustrate cross-sectional views illustrating example electronic devices and example methods of manufacturing the example electronic devices in accordance with various aspects of the present disclosure.

[FIG. 3] A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIGS. 4A-4N] illustrate cross-sectional views illustrating example electronic devices and example methods of manufacturing the example electronic devices in accordance with various aspects of the present disclosure.

[Fig. 5] A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIGS. 6A-6M] illustrate cross-sectional views illustrating example electronic devices and example methods of fabricating the example electronic devices in accordance with various aspects of the present disclosure.

[Fig. 7] A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure.

[FIG. 8A-FIG. 8N] illustrate cross-sectional views illustrating example electronic devices and example methods of manufacturing the example electronic devices in accordance with various aspects of the present disclosure.

[Fig. 9] A top view showing an example electronic device according to various aspects of the present disclosure.

[Fig. 10] A top view showing an example electronic device according to various aspects of the present disclosure.

200Q: Example/Example Implementation Plan

201: Functional grain

202: Functional grain

213: Die interconnection structure/first die interconnection structure

214: Die interconnection structure/second die interconnection structure

216b: Thin connecting die/connecting die

225: Encapsulation material

288:Substrate

299: The second group of connected die interconnect structures/second connected die interconnect structures

Claims (20)

An electronic device comprising: a first signal redistribution structure; a plurality of first vertical interconnect structures on a first side of the first signal redistribution structure; a connection die including a backside and a frontside, wherein The backside faces and is coupled to the first side of the first signal redistribution structure; a plurality of first connection die interconnect structures coupled to the front side of the connection die; a second signal redistribution structure A distribution structure including a first side and a second side opposite the first side, wherein the second side of the second signal redistribution structure is on the first vertical interconnect structure and on the on a first connection die interconnect structure; and a plurality of first conductive pads and a plurality of second conductive pads on the first side of the second signal redistribution structure, wherein the second The conductive pads are arranged at a finer pitch than the first conductive pads. The electronic device according to claim 1, comprising a first encapsulation material covering the first side of the first signal redistribution structure and laterally surrounding the plurality of first Vertical interconnect structures and the plurality of first connection die interconnect structures. The electronic device of claim 2, wherein the first encapsulation material laterally surrounds the connection die. The electronic device according to claim 2, wherein the first side of the first encapsulation material and the plurality of end surfaces of the plurality of first vertical interconnect structures and the plurality of first connection die interconnect structures The multiple end faces are coplanar. The electronic device according to claim 4, wherein the first side of the first signal redistribution structure, the first side of the second signal redistribution structure and the first side of the first encapsulation material are coplanar. . The electronic device according to claim 4, comprising a second encapsulation material covering the second signal redistribution structure. The electronic device according to claim 6, wherein the first side of the first signal redistribution structure, the first side of the second signal redistribution structure, the first side of the first encapsulation material and the The first sides of the second encapsulating material are coplanar. The electronic device of claim 1, wherein the backside of the connection die contains no electrical connections and is coupled to the conductive layer of the first signal redistribution structure. The electronic device of claim 1, wherein at least a portion of the connection die is above a topmost surface of the first signal redistribution structure. The electronic device of claim 1, wherein the volume directly vertically between the first signal redistribution structure and the second signal redistribution structure does not contain active electronic components. The electronic device of claim 1, wherein the first signal redistribution structure and the second signal redistribution structure are coreless. The electronic device according to claim 1, wherein the connection die is a part of a wafer or a connection die panel. The electronic device of claim 1, further comprising a second connection die coupled to the first side of the first signal redistribution structure. The electronic device of claim 1, wherein the connection die includes an electrical routing circuit without active electronic components and without passive electronic components. The electronic device of claim 1, wherein the connection die includes passive electronic components. The electronic device of claim 15, wherein the passive electronic component is a resistor. The electronic device of claim 15, wherein the passive electronic component is a capacitor device or inductor. The electronic device of claim 15, wherein the passive electronic component is an integrated passive device. The electronic device of claim 1, wherein the connection die does not contain active electronic components. The electronic device according to claim 1, wherein the first signal redistribution structure includes: a first structure including one or more first dielectric layers and one or more first conductive layers; and a second structure , which includes one or more second dielectric layers and one or more second conductive layers, the one or more second conductive layers having a higher density than the one or more first conductive layers of the first structure. Thicker spacing.