KR20200064874A - Semiconductor device including Trench MOSFET having high breakdown voltage - Google Patents

Abstract

Provided is a semiconductor device including a trench MOSFET having a high breakdown voltage. The semiconductor device includes: a semiconductor substrate including an active region and an edge termination region; a drift region formed across the active region and the edge termination region; a trench MOSFET formed in the active region; an edge trench formed in the edge termination region and forming an electric field relaxation structure therein; an embedded well formed adjacent to the lower edge trench; a first well formed adjacent to the side surface of the edge trench and having the same conductivity type as the embedded well, and an interlayer insulating film formed on the edge trench, the trench MOSFET, and the first well.

Description

Semiconductor device including trench MOSFET having high breakdown voltage

The present invention relates to a semiconductor device comprising a trench MOSFET having a high breakdown voltage.

The performance index of the power semiconductor may be determined by, for example, an ON resistance and a breakdown voltage. For example, a trench mosfet (TMOSFET) structure that forms a vertical channel to minimize on-resistance and increase current density may be used.

Recently, silicon carbide (SiC), a type of wide band gap semiconductor, is used as a semiconductor material, and the importance of the vertical structure is very high.

In SiC TMSOFET, the breakdown voltage can be divided into, for example, an active region and an edge termination region. In the active region, the electric field strength of the trench corner region and the shape of the implant region located at the bottom of the trench (thickness) And concentration), the thickness of the drift layer, and the like. In addition, research on its structure in the direction of increasing the breakdown voltage in the edge termination region is ongoing.

Korean Patent Publication No. 10-2018-0125404 (released on November 23, 2018)

The technical problem to be solved by the present invention is to provide a semiconductor device capable of improving reliability by improving the performance index of an element by relaxing the electric field concentration structure in the edge termination region.

The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing the semiconductor device at a small cost.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments for achieving the above technical problem includes: a semiconductor substrate including an active region and an edge termination region, a drift region formed across the active region and the edge termination region, a trench MOSFET formed in the active region, and an edge termination region An edge trench formed in and having an electric field relaxation structure formed therein, a buried well formed adjacent to the lower edge trench, a first well formed adjacent to the side of the edge trench and having the same conductivity type as the buried well, and the edge trench, And an interlayer insulating film formed on the trench MOSFET and the first well.

In some embodiments, the trench MOSFET includes an active trench formed in the active region, a gate electrode disposed inside the active trench, and the electric field relaxation structure includes the same material as the gate electrode and the edge trench And an edge trench electrode disposed therein.

In some embodiments, the gate electrode and the edge trench electrode include polysilicon.

In some embodiments, the field relaxation structure includes an insulating film filling the edge trench.

In some embodiments, the insulating film may include an oxide film extending from the interlayer insulating film.

In some embodiments, the first wells are spaced apart from each other and include second and third wells formed on the surface of the drift region, the second wells being formed adjacent to sides of the edge trench, and the second wells The edge trench is not formed between the well and the third well.

In some embodiments, the buried well is vertically aligned with the edge trench to form within the drift region.

In some embodiments, the semiconductor substrate includes SiC, and the conductivity type of the buried well and the first well may include a P type.

A method of manufacturing a semiconductor device according to some embodiments to achieve the above technical problem is prepared by preparing a semiconductor substrate including a drift region, wherein the drift region includes an active region and an edge termination region, and the surface and edge termination of the active region A first well is formed on the surface of the region, an active trench is formed between the first wells of the active region, an edge trench is formed between the first wells of the edge termination region, and a first is formed below the active trench and below the edge trench. And forming a buried well having the same conductivity type as the well, forming a gate electrode inside the active trench, and forming an electric field relaxation structure inside the edge trench.

In some embodiments, forming the electric field relaxation structure includes forming an edge trench electrode including the same material as the gate electrode inside the edge trench.

In some embodiments, forming the electric field relaxation structure includes filling the inside of the edge trench with an insulating film.

In some embodiments, the method of manufacturing the semiconductor device further includes forming an interlayer insulating layer including an oxide film on the drift region, and filling the inside of the edge trench includes filling the inside of the edge trench with an oxide film. do.

In some embodiments, the active trench and the edge trench can be formed simultaneously.

Details of other embodiments are included in the detailed description and drawings.

1 is a schematic layout of a semiconductor device in accordance with some embodiments.
2 is a cross-sectional view taken along the line PP′ of FIG. 1.
3 and 4 are diagrams for describing an effect of a semiconductor device according to some embodiments.
5 is a cross-sectional view of a semiconductor device in accordance with some embodiments.
6 is a view for explaining the effect of a semiconductor device according to some embodiments.
7 is a view for explaining the effect of a semiconductor device according to some embodiments.
8 is a cross-sectional view of a semiconductor device in accordance with some embodiments.
9 is a cross-sectional view of a semiconductor device in accordance with some embodiments.
10 to 14 are intermediate step views illustrating a method of manufacturing a semiconductor device in accordance with some embodiments.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and the ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims. Sizes and relative sizes of components indicated in the drawings may be exaggerated for clarity of explanation. Throughout the specification, the same reference numerals refer to the same components, and “and/or” includes each and every combination of one or more of the mentioned items.

Elements or layers referred to as "on" or "on" of another device or layer are not only directly above the other device or layer, but also when intervening another layer or other device in the middle. All inclusive. On the other hand, when a device is referred to as “directly on” or “directly above”, it indicates that no other device or layer is interposed therebetween.

The spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, etc., are as shown in the figure. It can be used to easily describe the correlation of a device or components with other devices or components. The spatially relative terms should be understood as terms including different directions of the device in use or operation in addition to the directions shown in the drawings. For example, if the element shown in the figure is flipped over, the element described as "below" or "beneath" the other element may be placed "above" the other element. Accordingly, the exemplary term “below” can include both the directions below and above. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to the orientation.

The terminology used herein is for describing the embodiments and is not intended to limit the present invention. In the present specification, the singular form also includes the plural form unless otherwise specified in the phrase. As used herein, “comprises” and/or “comprising” does not exclude the presence or addition of one or more other components other than the components mentioned.

Although the first, second, etc. are used to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, it goes without saying that the first element or component mentioned below may be the second element or component within the technical spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings commonly understood by those skilled in the art to which the present invention pertains. In addition, terms defined in the commonly used dictionary are not ideally or excessively interpreted unless specifically defined.

1 is a schematic layout of a semiconductor device in accordance with some embodiments. 2 is a cross-sectional view taken along the line P-P′ of FIG. 1.

1 and 2, the semiconductor device 1 may include an active region ACTIVE and an edge termination region EDGE defined in the semiconductor substrate 100.

The semiconductor substrate 100 may include, for example, silicon (Si). Specifically, the semiconductor substrate 100 may include, for example, silicon carbon (SiC). However, the embodiments are not limited thereto, and the material constituting the semiconductor substrate 100 may be modified and modified as needed. For example, in some embodiments, the semiconductor substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimony, lead tellurium compound, indium arsenic, indium phosphide, gallium arsenide, or gallium antimonide. have. Hereinafter, it will be described that the semiconductor substrate 100 includes silicon carbon.

A drift region 105 may be formed on the semiconductor substrate 100. In some embodiments, this drift region 105 may be part of the semiconductor substrate 100. Accordingly, the drift region 105 may include an active region ACTIVE and an edge termination region EDGE. In other words, the drift region 105 may be formed over the active region ACTIVE and the edge termination region EDGE.

In some embodiments, the conductivity type of drift region 105 may be N-type. However, the embodiments are not limited thereto, and the conductivity type of the drift region 105 may be modified and implemented as needed.

The base region 110 may be formed in the active region ACTIVE of the drift region 105. In some embodiments, the conductive type of the base region 110 may be, for example, a P type, but the embodiments are not limited thereto.

The active trench 142 may be formed in the active region ACTIVE to configure the gate electrode 162 of the trench MOSFET (TMOSFET). The active trench 142 may be formed to penetrate the base region 110 as shown.

A gate electrode 162 of a trench MOSFET (TMOSFET) may be formed inside the active trench 142. A portion of the interlayer insulating layer 170 formed in a form surrounding the gate electrode 162 along the outer wall of the active trench 142 may function as a gate insulating layer of the trench MOSFET (TMOSFET).

A buried well 152 may be formed under the active trench 142. The conductivity type of the buried well 152 may be different from, for example, the drift region 105. Specifically, the conductivity type of the buried well 152 may be, for example, a P type, but embodiments are not limited thereto.

In some embodiments, the buried well 152 is formed in the lower portion of the active trench 142, as shown, vertically aligned with the active trench 142 (e.g., aligned in the Y direction) Shape).

A gate wiring trench 144 may be formed in the active area ACTIVE to be spaced apart from the active trench 142. A wiring gate 164 electrically connected to the gate bus 300 may be formed inside the gate wiring trench 144. In some embodiments, the shape of the wiring gate 164 may be similar to the gate electrode 162 described above.

As illustrated in FIG. 1, the gate bus 300 may extend in a shape surrounding the outer periphery of the semiconductor device 1 and be electrically connected to the gate pad 310. However, such a wiring layout is only an example, and may be implemented with any modification.

In some embodiments, the buried well 154 is formed under the gate wiring trench 144, and may be formed in a vertical alignment with the gate wiring trench 144 as shown.

Edge trenches 140a to 140d may be formed in the edge termination area EDGE to relieve the electric field concentration in the edge termination area EDGE and increase the breakdown voltage. Although the drawing shows that four edge trenches 140a to 140d are formed in the edge termination area EDGE, this is only an example, and embodiments are not limited thereto. The number of edge trenches 140a to 140d may be differently modified as needed to be implemented.

In some embodiments, the size of the edge trenches 140a-140d and the size of the active trenches 142 may be different. For example, the width of the edge trenches 140a to 140d may be formed to be narrower than the width of the active trench 142. However, embodiments are not limited thereto, and if necessary, the edge trenches 140a to 140d may be formed to have the same size as the active trench 142.

The buried wells 150a to 150d may be formed under each of the edge trenches 140a to 140d. For example, the conductivity type of the buried wells 150a to 150d may be different from the drift region 105. Specifically, the conductivity type of the buried wells 150a to 150d may be, for example, a P type, but embodiments are not limited thereto.

In some embodiments, each of the buried wells 150a-150d is formed below the edge trenches 140a-140d, and may be formed in a vertically aligned shape with the edge trenches 140a-140d as shown.

An electric field relaxation structure may be formed inside the edge trenches 140a to 140d to alleviate electric field concentration and increase a breakdown voltage. The electric field relaxation structure may include, for example, edge trench electrodes 160a to 160d formed inside each of the edge trenches 140a to 140d as illustrated.

In some embodiments, the edge trench electrodes 160a-160d may include the same material as the gate electrode 162 of the trench MOSFET (TMOSFET) described above. In some embodiments, the edge trench electrodes 160a to 160d and the gate electrode 162 may include polysilicon, but embodiments are not limited thereto.

As illustrated, a portion of the interlayer insulating layer 170 may extend along the sidewalls of the edge trenches 140a to 140d, and may be formed in an enveloping shape of the edge trench electrodes 160a to 160d.

The first well 130 may be formed on the surface of the drift region 105. The first well 130 may be formed adjacent to the side surfaces of the edge trenches 140a to 140d and the side surface of the gate wiring trench 144 and may be formed in the base region 110. The depth of the first well 130 may be shallower than the depth of the edge trenches 140a to 140d, shallower than the depth of the gate wiring trench 144, and shallower than the depth of the active trench 142.

In some embodiments, the conductivity type of the first well 130 may be the same as the conductivity type of the buried wells 150a to 150d, 152 and 154 described above. Specifically, the conductivity type of the first well 130 may be P-type, but embodiments are not limited thereto.

The conductivity types of the first well 130 and the buried wells 150a to 150d, 152 and 154 are the same, but their impurity concentrations may be different. In some embodiments, the concentration of P-type impurities contained in the first well 130 may be higher than the concentration of P-type impurities contained in the buried wells 150a to 150d, 152 and 154. However, embodiments are not limited thereto.

The second well 120 may be formed in the active area ACTIVE. Specifically, the second well 120 may be formed in the base region 110 of the active region ACTIVE.

The second well 120 may have a different conductivity type from the first well 130. For example, the conductivity type of the second well 120 may be N-type, but embodiments are not limited thereto.

An interlayer insulating layer 170 may be formed on the active region ACTIVE and the edge termination region EDGE. In some embodiments, the interlayer insulating film 170 may include, for example, an oxide film. However, the embodiments are not limited thereto, and the interlayer insulating layer 170 may include a nitride film or an oxynitride film, if necessary. Hereinafter, it will be described that the interlayer insulating film 170 includes an oxide film.

As described above, a portion of the interlayer insulating layer 170 may be formed to extend to the sidewalls of the active trench 142, the edge trenches 140a to 140d, and the gate wiring trench 144. Here, the expression extended means that the first oxide film is formed through the first process on the sidewalls of the active trench 142, the edge trenches 140a to 140d, and the gate wiring trench 144, and the first through the second process. Also included is a form in which a second oxide film is formed on the oxide film.

As illustrated in FIG. 1, the source bus 200 may extend in a shape surrounding the outer periphery of the semiconductor device 1 and be electrically connected to the source pad 210. However, such a wiring layout is only an example, and may be implemented with any modification.

The source electrode 400 providing a source voltage to the trench MOSFET (TMOSFET) may be formed between the interlayer insulating layers 170 in a form that is electrically connected to the first well 130.

Hereinafter, the effect of the semiconductor device 1 described above will be described with reference to FIGS. 3 and 4.

3 and 4 are diagrams for describing an effect of a semiconductor device according to some embodiments.

First, FIG. 3 shows the edge trench (140a to 140d in FIG. 2) and the edge trench electrode (160a to 160d in FIG. 2) in the edge termination region (EDGE in FIG. 2), unlike the semiconductor device (1 in FIG. 2) described above. In addition, the electric field of the semiconductor device in which the buried well (150a-150d in FIG. 2) below the edge trench (140a-140d in FIG. 2) is not formed is vertical from the surface of the drift region (for example, the Y-direction in FIG. 2). ). Specifically, it is a graph in which the electric field is measured in the vertical direction (for example, the Y direction in FIG. 2) from the surface of the drift region at the P+ and N- junctions of the edge termination region under a predetermined reverse voltage.

Next, FIG. 4 is a graph of measuring the electric field of the above-described semiconductor device (1 in FIG. 2) in the vertical direction (for example, the Y direction in FIG. 2) from the surface of the drift region (105 in FIG. 2). Similarly, under the same predetermined reverse voltage as in FIG. 3, the electric field is measured in the vertical direction (for example, the Y direction in FIG. 2) from the surface of the drift region at the P+ and N- junctions of the edge termination region.

3 and 4, it can be seen that the electric field concentration phenomenon is significantly improved in the semiconductor device (1 in FIG. 2) according to the present embodiment. Specifically, the edge trench (140a-140d in FIG. 2), the edge trench electrode (160a-160d in FIG. 2), and the buried well (150a-150d in FIG. 2) under the edge trench (140a-140d in FIG. 2), etc. By alleviating the electric field concentration of the P+ and N- junctions, it can be seen that a lower electric field value is obtained and the maximum electric field value is also lowered.

Next, referring to FIG. 5, a semiconductor device according to some embodiments will be described. Hereinafter, a description overlapping with the above description will be omitted and the difference will be mainly described.

5 is a cross-sectional view of a semiconductor device in accordance with some embodiments.

Referring to FIG. 5, in the semiconductor device 2 according to the present embodiment, an electric field relaxation structure different from the above-described embodiment may be formed in the edge trenches 140a to 140d.

Specifically, insulating layers 161a to 161d filling the edge trenches 140a to 140d may be formed inside the edge trenches 140a to 140d of the semiconductor device 2 according to the present embodiment.

In some embodiments, the insulating films 161a to 161d may include the same material as the interlayer insulating film 170. Accordingly, the insulating films 161a to 161d may be formed in an extended form from the interlayer insulating film 170 as illustrated. However, the embodiments are not limited thereto, and the insulating layers 161a to 161d and the interlayer insulating layer 170 may be formed in separate forms. In some embodiments, the insulating films 161a to 161d may include oxide films.

6 is a view for explaining the effect of a semiconductor device according to some embodiments.

FIG. 6 is a graph of measuring the electric field of the above-described semiconductor device (2 in FIG. 5) in the vertical direction (for example, the Y direction in FIG. 5) from the surface of the drift region (105 in FIG. 5).

Referring to FIGS. 3 and 5, it can be seen that the electric field concentration phenomenon is also significantly improved in the semiconductor device (2 of FIG. 5) according to the present embodiment.

7 is a view for explaining the effect of a semiconductor device according to some embodiments.

In FIG. 7, A is a current-voltage graph of the semiconductor device in which an electric field relaxation structure is not formed in the edge termination region, B is a current-voltage graph of the semiconductor device 2 shown in FIG. 5, and A is in FIG. 2. It is a current-voltage graph of the semiconductor device 1 shown.

Referring to FIG. 7, the breakdown voltage of the semiconductor device 2 shown in FIG. 5 and the semiconductor device 1 shown in FIG. 2 is 50 to 60 percent compared to a semiconductor device in which an electric field relaxation structure is not formed in the edge termination region. You can see that it has increased.

Next, a semiconductor device according to some embodiments will be described with reference to FIG. 8. Differences from the above-described embodiments will also be mainly described below.

8 is a cross-sectional view of a semiconductor device in accordance with some embodiments.

Referring to FIG. 8, some of the first well 130 of the edge termination region EDGE of the semiconductor device 3 is formed adjacent to the edge trenches 140a and 140b, while the other portion is formed of the edge trench 140a. , 140b). In other words, edge trenches 140a and 140b are formed between some of the first wells 130 among the first wells 130, but edge trenches 140a and 140b are not formed between the remaining first wells 130. Can be.

Edge trench electrodes 160a and 160b may be formed inside the edge trenches 140a and 140b. As described above, duplicate description is omitted.

Next, a semiconductor device according to some embodiments will be described with reference to FIG. 9. Differences from the above-described embodiments will also be mainly described below.

9 is a cross-sectional view of a semiconductor device in accordance with some embodiments.

Referring to FIG. 9, insulating layers 161a and 161b may be formed in the edge trenches 140a and 140b of the semiconductor device 4, unlike the semiconductor device (3 in FIG. 8) described above. As described above, the insulating films 161a and 161b may be formed to extend into the interlayer insulating film 170.

Next, a method of manufacturing a semiconductor device according to some embodiments will be described with reference to FIGS. 10 to 14.

10 to 14 are intermediate step views for describing a method of manufacturing a semiconductor device in accordance with some embodiments.

Referring first to FIG. 10, a semiconductor substrate 100 is prepared, and a drift region 105 is formed on the semiconductor substrate 100.

Subsequently, the base region 110 is formed in the drift region 105 using, for example, a mask not shown. Then, the mask M1 is formed on the drift region 105, and the second well 120 is formed in the base region 110 using the formed mask M1.

Referring to FIG. 11, a first well 130 is formed in the drift region 105 using a mask M2. At this time, for example, an ion implant or the like may be used to form the first well 130, but embodiments are not limited thereto.

Referring to FIG. 12, an active trench 142, a gate wiring trench 144, and edge trenches 140a to 140d are formed in the drift region 105 using the mask M3. At this time, a protective film may be formed on sidewalls of the active trench 142, the gate wiring trench 144, and the edge trenches 140a to 140d.

Referring to FIG. 13, buried wells 152, 154 and 150a to 150d are formed under active trench 142, gate wiring trench 144, and edge trenches 140a to 140d.

Next, referring to FIG. 14, the previously formed mask and protective film may be removed, for example, a thermal oxidation process may be performed. Accordingly, an oxide film may be formed in the active trench 142, the gate wiring trench 144, and the edge trenches 140a to 140d.

Subsequently, for example, polysilicon is deposited in the active trench 142, the gate wiring trench 144, and the edge trenches 140a to 140d, such that the gate electrode 162, the wiring gate 164, and the edge trench electrode 160a ~160d). Then, after forming the interlayer insulating layer 170 covering the gate electrode 162, the wiring gate 164, and the edge trench electrodes 160a to 160d, the source electrode 400 and the gate bus 300 shown in FIG. And source bus 200.

As described above, in the manufacturing method of the semiconductor device according to the present embodiment, the process cost is additionally formed because the electric field relaxation structure of the edge termination region EDGE is not formed through a separate process, but is simultaneously formed when the active region is formed. Does not occur. Accordingly, it is possible to manufacture a semiconductor device including a trench MOSFET capable of securing reliability at a small cost.

The method of manufacturing the semiconductor device shown in FIG. 2 has been described above with reference to FIGS. 10 to 14, but other semiconductor devices described above may be manufactured in a similar manner. For example, in the process of FIG. 14, when the edge trench electrodes 160a to 160d are not formed in the edge trenches 140a to 140d, and the inside of the edge trenches 140a to 140d is filled with insulating films 161a to 161d, It is possible to manufacture the semiconductor device 2 shown in FIG. 5.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and may be manufactured in various different forms, and having ordinary knowledge in the technical field to which the present invention pertains. It will be understood that a person can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: semiconductor substrate
105: drift area
140a-140d: edge trench
160a~160d: edge trench electrode

Claims (13)

A semiconductor substrate including an active region and an edge termination region;
A drift region formed over the active region and the edge termination region;
A trench MOSFET (TMOSFET) formed in the active region;
An edge trench formed in the edge termination region and having an electric field relaxation structure formed therein;
A buried well formed adjacent to the lower edge of the edge trench;
A first well formed adjacent to the side surface of the edge trench and having the same conductivity type as the buried well; And
A semiconductor device including the edge trench, the trench MOSFET, and an interlayer insulating layer formed on the first well. According to claim 1,
The trench MOSFET includes an active trench formed in the active region and a gate electrode disposed inside the active trench,
The electric field relaxation structure includes a same material as the gate electrode and includes an edge trench electrode disposed inside the edge trench. According to claim 2,
The gate electrode and the edge trench electrode include polysilicon. According to claim 1,
The electric field relaxation structure includes a semiconductor device filling the edge trench. The method of claim 4,
The insulating film comprises an oxide film extending from the interlayer insulating film. According to claim 1,
The first well includes second and third wells spaced from each other and formed on the surface of the drift region,
The second well is formed adjacent to the side of the edge trench,
A semiconductor device in which the edge trench is not formed between the second well and the third well. According to claim 1,
The buried well is vertically aligned with the edge trench and is formed in the drift region. According to claim 1,
The semiconductor substrate includes SiC,
A semiconductor device having a conductivity type of the buried well and the first well includes a P type. A semiconductor substrate including a drift region is prepared, wherein the drift region includes an active region and an edge termination region,
A first well is formed on the surface of the active region and the edge termination region,
Forming an active trench between the first wells in the active region, and forming an edge trench between the first wells in the edge termination region,
A buried well having the same conductivity type as the first well is formed under the active trench and under the edge trench,
A method of manufacturing a semiconductor device, comprising forming a gate electrode in the active trench and forming an electric field relaxation structure in the edge trench. The method of claim 9,
Forming the electric field relaxation structure,
A method of manufacturing a semiconductor device including forming an edge trench electrode including the same material as the gate electrode inside the edge trench. The method of claim 9,
Forming the electric field relaxation structure,
A method of manufacturing a semiconductor device including filling the inside of the edge trench with an insulating film. The method of claim 11,
Further comprising forming an interlayer insulating film including an oxide film on the drift region,
The filling of the inside of the edge trench includes filling the inside of the edge trench with an oxide film. The method of claim 9,
The method of manufacturing a semiconductor device wherein the active trench and the edge trench are formed simultaneously.

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