KR20110015788A - Trench gate semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device including a trench gate structure is provided to improve the breakdown voltage property of the semiconductor device by alleviating electric field concentration generated at the lower side of a trench gate under a breakdown voltage state. CONSTITUTION: A gate pad electrode forming region(110) is formed on a semiconductor substrate(100). An active region(120) includes a plurality of cells for conducting currents. An edge termination region(130) surrounds the active region. A peripheral region is located between the active region and the edge termination region. A gate bus-line(140) transmitting gate signals is formed along the peripheral of the active region.

Description

Semiconductor device having a trench gate structure

The present invention relates to a power semiconductor device having a trench gate structure.

Recently, as devices using power semiconductors have increased in volume, power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) Not only is demand soaring, but power semiconductor devices are becoming more efficient.

Widely used in high voltage and high current applications, IGBTs have high breakdown voltages, and research on increasing breakdown voltages is ongoing. IGBT is a kind of switching device that applies voltage to gate to form channel and controls the flow of current through electrons and holes. It is defined as the maximum voltage that can be applied to collector-emitter in off state. The breakdown voltage is mainly determined by the maximum electric field concentrated at the P base.

The gate of a power semiconductor device such as an IGBT or a MOSFET may have various forms such as a planar structure or a trench structure.

Since the trench gate structure of the semiconductor device has a larger number of cells per unit area than the planar gate structure of the semiconductor device, that is, the integration density of the cell can be increased. Correspondingly, the conductivity is excellent due to the high current density. In addition, the IGBT of the trench gate structure has an on-state characteristic that is superior to that of the planar gate structure because the channel of higher density is formed vertically without the parasitic junction field effect transistor region component of the planar gate structure. Has

However, when the semiconductor device of the trench gate structure is in the off state, an electric field is concentrated under the trench gate, so that a breakdown voltage is lower than that of the semiconductor device of the planar gate structure.

That is, in an inner (eg, active region) trench region disposed far from an edge termination region of the semiconductor substrate among the plurality of trenches, a depletion layer is extended along the side and bottom surfaces thereof to evenly distribute the electric field. However, in the vicinity of the outermost trench disposed closest to the edge termination region, there is no trench on the outer side thereof, thereby limiting the expansion of the depletion layer, so that the field strength is stronger than that of other portions, so that the occurrence of a breakdown phenomenon is facilitated in the outermost trench region.

When the breakdown occurs, a large current flows intensively into the outermost trench region, which may deteriorate and destroy the IGBT. Therefore, by reducing electric field concentration occurring at the lower end of the outermost trench gate, the breakdown voltage characteristics of the semiconductor device are improved and the trench is reduced. A method of alleviating deterioration of the gate oxide film is required.

The background art described above is technical information possessed by the inventors for the derivation of the present invention or acquired during the derivation process of the present invention, and is not necessarily a publicly known technique disclosed to the general public before the application of the present invention.

The present invention is to provide a semiconductor device having a trench gate structure to ensure a safe operation when using a semiconductor device of the same rating by having a robust characteristic with a high breakdown voltage.

In addition, the present invention is to provide a semiconductor device having a trench gate structure capable of reducing the electric field concentration occurring at the lower end of the trench gate in the breakdown voltage state to improve the breakdown voltage characteristics of the semiconductor device and to mitigate deterioration of the trench gate oxide layer. will be.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a semiconductor device having a trench gate structure formed using a first conductivity type semiconductor substrate, the semiconductor device comprising: an active area; An edge termination area surrounding the active area; And a peripheral area positioned between the active area and the edge termination area, wherein a second conductivity type well formed in the peripheral area has a junction depth for accommodating at least the outermost trench therein. There is provided a semiconductor device having a trench gate structure, which is formed to have.

The second conductivity type well formed in the peripheral region may be formed to the same or greater junction depth than the second conductivity type well formed in the edge termination region.

The second conductivity type well formed in the peripheral region may be formed at the same concentration or higher than the second conductivity type well formed in the edge termination region.

Two or more second conductive wells may be horizontally formed in the peripheral region, and the second conductive wells accommodating the outermost trench may have a relatively deep junction depth.

Two or more second conductivity type wells having different concentrations may be horizontally formed in the peripheral region, and a second conductivity type well containing the outermost trench may be formed at a relatively high concentration.

The trenches formed in the peripheral area and the active area may not match at least one of a width and a mesa.

The second conductivity type wells formed in the peripheral area may be formed in a closed loop to surround the active area.

One or more of the second conductivity type wells formed in the active region, the edge termination region, and the peripheral region may be diffused to contact the second conductivity type well that is horizontally adjacent.

One or more of each of the trenches formed in the active region may be connected to neighboring trenches by distal ends thereof extending in a direction not parallel to the trench walls.

The trench gate structured semiconductor device may be at least one of an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor based effect transistor (MOSFET).

According to the embodiment of the present invention, it has an effect of ensuring a safe operation when using a semiconductor device of the same rating by having a robust characteristic with a high breakdown voltage.

In addition, by reducing electric field concentration occurring at the lower end of the trench gate, the breakdown voltage characteristics of the semiconductor device may be improved and the deterioration of the trench gate oxide layer may be alleviated.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

If an element such as a layer, region or substrate is described as being on or "onto" another element, the element may be directly above or directly above another element and There may also be intervening elements. On the other hand, if one element is mentioned as being "directly on" or extending "directly onto" another element, no other intermediate elements are present. In addition, when one element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present. have. On the other hand, when one element is described as being "directly connected" or "directly coupled" to another element, no other intermediate element exists.

"Below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" Relative terms such as "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region, as shown in the figures. It is to be understood that these terms are intended to encompass other directions of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a general semiconductor device, and FIG. 2 is a cross-sectional view of the ab portion of FIG. 1, and FIGS. 3 and 4 are diagrams illustrating breakdown voltage characteristics of an IGBT of a planar gate structure and an IGBT of a trench gate structure, respectively. .

1 and 2, the semiconductor substrate 100 made of silicon has an upper side and a lower side facing each other, and the upper side includes a gate pad electrode formation region 110 and a plurality of cells for current conduction. The active region 120 and the edge termination region 130 for supporting the high breakdown voltage are formed, and the collector electrode 210 is formed on the lower side. In the active region 120, a gate electrode and an emitter electrode having a trench gate structure are disposed, and the edge termination region 130 is formed such that an electric field is more uniformly developed over its width.

A gate bus line 140, which is electrically connected to the gate pad and transmits the gate signal, extends from the gate pad forming region 110 and is formed along the periphery of the active region 120. For example, the gate bus line 140 may be formed in a closed loop, but the form of the gate bus line 140 is not limited to the annular shape. Hereinafter, for convenience of description, an area in which the gate bus line 140 is formed as a periphery of the active area 120 will be referred to as a peripheral area.

Referring to FIG. 2, which is a cross-sectional view of an ab portion of FIG. 1, the semiconductor substrate 100 includes an N-type emitter region 215 and a P-type body region 220 formed under the N-type emitter region 215. N-type base region 225 and P-type collector region 230, which may be referred to as a drift region.

A gate conductor 245 made of poly-silicon is disposed in the trench 235 formed surrounded by the P-type body region 220, and a gate is formed between the gate conductor 245 and the inner wall of the trench. A gate oxide 240 is formed.

Since the gate conductor 245 faces the P-type body region 220 through the gate insulating layer 240, the gate conductor 245 functions as a gate electrode for forming a channel in the P-type body region 220. That is, by controlling the channel formation at the interface between the gate insulating film 240 and the P-type body region 220 by using the voltage applied to the gate electrode, the voltage between the collector and the emitter and the on / off operation of the semiconductor device are controlled. .

When a voltage is applied between the collector and the emitter in the off state of the semiconductor device, voltage is distributed in the reverse direction between the P-type body region 220 and the N-type base region 225, and the voltage applied between the collector and the emitter gradually increases. As it increases, the semiconductor device eventually enters a breakdown state. The electric field is then concentrated in the PN junction region and the bottom region of the trench gate, in particular the bottom of the trench 250 located at the outermost of the arranged trenches (ie, the position closest to the edge termination region 130). Focus on the part. This field concentration phenomenon is a cause of influencing the ruggedness and the breakdown voltage characteristics of the semiconductor device.

Simulation results of the semiconductor device using the structure of the 1200V class IGBT to illustrate the above-described electric field concentration phenomenon are illustrated in FIGS. 3 and 4. For reference, FIG. 3 is a simulation result of the semiconductor device for the edge termination of the IGBT of the planar gate structure, and FIG. 4 is an edge of the IGBT of the trench gate structure in which only the peripheral region is enlarged for comparison with the simulation result of FIG. 3. Simulation results of the semiconductor device for termination.

Referring to FIG. 3, which shows the breakdown voltage characteristics of a planar gate structure semiconductor device including a peripheral region and an edge termination region 130, a collision occurs in the first P-type well 260 of the edge termination region 130 when a breakdown occurs. An ionization phenomenon occurs, and the breakdown voltage is 1368V.

On the contrary, referring to FIGS. 4A to 4D, the breakdown voltage characteristics of the semiconductor device having the same structure as that of the semiconductor device illustrated in FIG. 3 and having the trench gate in the outer region are shown. In the case where the trench gate is present in the peripheral region, when the breakdown occurs, an electric field is concentrated at the lower end of the outermost trench, so that impact ionization occurs. This field concentration phenomenon occurs regardless of the position of the P-type well 270 surrounding the surrounding area, and thus, the breakdown voltage is reduced to 1200V or less (for example, 1170V in FIG. 4A). have.

As described above, in the semiconductor device of the trench gate structure, a strong electric field in the vertical and horizontal directions applied by the voltage across the collector-emitter in the breakdown voltage generation mode is concentrated in the outermost trench cell.

This electric field concentration weakens the breakdown voltage characteristic of the semiconductor device, promotes deterioration of the gate oxide film, and decreases the reliability of the semiconductor device, and causes the breakdown voltage to be lower than that of the planar gate structure semiconductor device employing the same technology. Becomes

5 is a cross-sectional view of the trench gate structure IGBT shown in part ab of FIG. 1 according to an embodiment of the present invention, FIG. 6 is a plan view of a semiconductor substrate according to an embodiment of the present invention, and FIG. 1 is a diagram illustrating a breakdown voltage characteristic of an IGBT of a trench gate structure according to an exemplary embodiment. In describing the IGBT of the trench gate structure according to the exemplary embodiment of the present invention with reference to the related drawings, the description of the same parts as those described above will be omitted.

Referring to FIG. 5, an area of the P-type well 570 formed in the peripheral area is formed so as to completely surround the bottom of one or more trenches formed in the area. In contrast, in the IGBT of the general trench gate structure described above with reference to FIG. 2, a trench formed in the peripheral region penetrates through the P-type well 270 and the bottom thereof is positioned in the N-type base region 225.

That is, the P-type well 570 formed in the peripheral region and surrounding the outermost trench 250 may be formed of the P-type well 260 of the edge termination region 130 or the P-type body region 220 of the active region 120. May be implemented in other forms.

For example, the P-type well 570 formed in the peripheral region may have a deeper junction depth than the trench gate, and may be formed to have the same or deeper junction depth with the plurality of P-type wells 260 formed in the edge termination region. . For example, the junction depth of the P-type well 570 may be implemented to be several μm deeper than the vertical depth of the trench gate formed in the peripheral region. Assuming that the P-type well regions respectively present in the active region, the peripheral region, and the edge termination region are A 220, B 570, and C 260, the relationship between the junction depths is " junction depth A < Bond depth (C)? Bond depth (B) ".

In this case, the diffusion depth of the P-type ions implanted into each region satisfies the relationship of "concentration (C) ≤ concentration (B)" so that the above-described relationship between the junction depths can be satisfied. May be different.

Alternatively, when the concentration of the P-type ions implanted into the peripheral region and the edge termination region 130 is constant, the P-type well 570 formed in the peripheral region may have the bottom of the trench gate so that the above-described relationship between the junction depths is satisfied. You can also spread it to the extent that it completely wraps. In this case, since the concentration of P-type ions implanted into the edge termination region 130 may not be high enough, a diffusion process with a higher temperature and / or longer time may be required than when the concentrations do not match. .

The P-type wells formed by the above-described diffusion process may not be separated by being connected in a horizontal direction inside the chip due to a narrow gap between them.

In addition, the width and mesa of the trench gate formed in the peripheral area may be formed to be the same as or not equal to the width and the mesa of the trench cell formed in the active area 120 according to a mask design scheme.

As described above, the P-type well 570 having the deepest junction depth may be formed, for example, in a closed loop along the bottom of the gate bus line as shown in area 620 of FIG. 6 in the plane of the semiconductor device. .

As illustrated in FIG. 6, the unit cells 610 may be disposed in the active region 120 in a stripe arrangement, and the trench gate end of each unit cell is not parallel to the trench wall (eg, Extend in a vertical direction) to be connected to neighboring trench gates. Here, one or more of the trench gates may not be connected to the neighboring trench gates, and the shape or arrangement of the unit cells in the active region 120 may vary.

FIG. 7 illustrates the breakdown voltage characteristics of the IGBT of the trench gate structure in which the P-type well 570 is formed to sufficiently surround the trench gate in the peripheral region. Referring to FIG. 7, in the case of the IGBT having a deep junction depth so as to fully enclose the trench gate, the value close to the IGBT of the planar gate structure without the trench gate appears.

That is, the P-type well 570 having a deep junction depth is introduced to mitigate a phenomenon in which the strongest electric field is concentrated at the bottom of the outermost trench, resulting in a breakdown voltage increase of about 100 to 200 V as compared with the case of FIG. 4. do.

8 is a cross-sectional view of the trench gate structure IGBT shown in part a-b of FIG. 1 according to another embodiment of the present invention. In describing the IGBT of the trench gate structure according to the exemplary embodiment of the present invention with reference to the related drawings, the description of the same parts as those described above will be omitted.

As illustrated in FIG. 8, the outermost trench of the plurality of trenches formed in the peripheral area is formed such that its bottom is completely covered by the P-type well 570, and other trenches are formed in the conventional IGBT. Like the structure, it may be formed to penetrate the P-type well 810.

That is, since the electric field is concentrated near the bottom of the trench disposed on the outermost side of the semiconductor substrate, the outermost trench is wrapped in the P-type well 570 to relax the electric field concentration, and the remaining trenches formed in the peripheral region are formed in the same manner as before. can do. At this time, considering the diffusion characteristics of the P-type ions, at least one of the trenches formed inside the outermost trench may be wrapped to the bottom of the P-type well 570.

In this case, assuming that the P-type well regions respectively present in the active region, the outer region, and the edge termination region are A 220, D 810, B 570, and C 260, the relationship between the junction depths is as follows. Can be expressed as "bonding depth (A) <joining depth (C) <joining depth (D) <joining depth (B)".

In addition, the concentration of the P-type ions implanted in each region so that the above-described relationship between the junction depths is satisfied may satisfy the relationship of "concentration (C) ≤ concentration (D) ≤ concentration (B)", or each P-type. Different temperature conditions and / or time conditions for the diffusion process may be applied to allow the wells to diffuse to the appropriate depth.

In the above embodiment, the case of IGBT has been described as an example. However, the present invention is not limited to this, and can be applied to power semiconductor devices such as MOSFETs, for example. In this case, it will be apparent to those skilled in the art that the above-described collector and emitter of the IGBT correspond to the drain and source of the MOSFET, respectively.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

1 is a plan view of a general semiconductor device.

FIG. 2 is a sectional view taken along a-b of FIG. 1; FIG.

3 and 4 show breakdown voltage characteristics of the edge termination of the IGBT of the planar gate structure and the IGBT of the trench gate structure, respectively.

5 is a cross-sectional view of the trench gate structure IGBT shown in part a-b of FIG. 1 in accordance with an embodiment of the present invention.

6 is a plan view of a semiconductor device according to an embodiment of the present invention.

7 is a view showing breakdown voltage characteristics of an IGBT of a trench gate structure according to an embodiment of the present invention.

8 is a cross-sectional view of the trench gate structure IGBT shown in part a-b of FIG. 1 in accordance with another embodiment of the present invention.

Claims (10)

A semiconductor device having a trench gate structure formed using a first conductivity type semiconductor substrate, Active area; An edge termination area surrounding the active area; And A peripheral area located between the active area and the edge termination area, And a second conductivity type well formed in the peripheral region to have a junction depth for accommodating at least the outermost trench therein. The method of claim 1, And the second conductivity type well formed in the peripheral region has a junction depth greater than or equal to the second conductivity type well formed in the edge termination region. The method of claim 1, And the second conductivity type well formed in the peripheral region is formed to have the same or higher concentration than the second conductivity type well formed in the edge termination region. The method of claim 1, Two or more second conductive wells are formed horizontally in the peripheral region, and the second conductive wells accommodating the outermost trenches are formed to have a relatively deep junction depth. A semiconductor device. The method of claim 1, Two or more second conductivity type wells having different concentrations are formed horizontally in the peripheral region, and a second conductivity type well containing the outermost trench is formed at a relatively high concentration. Semiconductor device having a. The method of claim 1, And trenches formed in the peripheral region and the active region, respectively, in which at least one of a width and a mesa does not coincide. The method of claim 1, And a second conductive well formed in the peripheral region is formed in a closed loop to surround the active region. The method of claim 1, At least one of the second conductivity type wells formed in the active region, the edge termination region, and the peripheral region is diffused to be in contact with the second conductivity type well which is horizontally adjacent to each other. . The method of claim 1, At least one of each of the trenches formed in the active region extends in a direction not parallel to the trench wall to be connected to neighboring trenches. The method of claim 1, The semiconductor device having the trench gate structure is a semiconductor device having a trench gate structure, characterized in that at least one of an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor effect transistor (MOSFET).

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