KR20200058882A - Electroluminescence display device - Google Patents

Abstract

A display device, according to an embodiment of the present specification, includes: a substrate having a display area with a plurality of pixels and a non-display area around the display area; a gate driving circuit arranged along at least one side of the display area in the non-display area; a plurality of gate signal lines connected to pads in the non-display area and the gate driving circuit and transferring a gate control signal to the gate driving circuit; and an anti-erosion structure provided on the gate signal line. The electrostatic prevention structure may prevent electrochemical action generated through moisture, thereby preventing the electrolysis of the gate signal line.

Description

Electroluminescent display device {ELECTROLUMINESCENCE DISPLAY DEVICE}

This specification relates to an electroluminescent display device.

The image display device is a key technology in the era of information and communication, and is developing in a direction of high performance while being thinner, lighter and more portable. Accordingly, an electroluminescent display device or the like that displays an image by electrically controlling the amount of light emitted by the self-luminous element is in the spotlight.

The electroluminescent display device is a display device employing a self-luminous element using a thin light-emitting layer between electrodes, and has the advantage of being capable of thinning because it can operate without a separate light source. A general electroluminescent display device has a structure in which a pixel driving circuit and a light emitting element are formed on an array substrate, and light emitted from the light emitting element is sent to the top or bottom to display an image.

The electroluminescent display device may be classified into an organic light emitting display device and an inorganic light emitting display device according to the material of the light emitting element used. Various display devices, including the organic light emitting display device, are designed to block moisture penetration and / or propagation in various ways since performance such as reliability may deteriorate when moisture permeation occurs. In particular, various structures have been recently researched and applied to prevent moisture and / or defects from penetrating the outer portion of the display device.

This specification aims to propose a moisture-permeable and corrosion-resistant structure of the electroluminescent display device. Particularly, the embodiments of the present specification propose a structure capable of suppressing moisture intrusion occurring at the outer periphery of the display device and the occurrence of defects.

The tasks of the present specification are not limited to the above-mentioned tasks, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

To achieve the object as described above, a display device according to an exemplary embodiment of the present invention includes a substrate having a display area with a plurality of pixels and a non-display area around the display area. The non-display area includes a gate driving circuit arranged along at least one side of the display area. It includes a plurality of gate signal lines that are connected to a pad and a gate driving circuit in a non-display area and transmit a gate control signal to the gate driving circuit. It includes an anti-erosion structure provided in the gate signal line.

A display device according to another exemplary embodiment of the present specification includes a substrate having a display area and a non-display area surrounding the display area. There is an insulating layer on the top of the substrate. At least one planarization layer may be disposed in the display area and the non-display area. A gate driving circuit and a pad are included in the non-display area. It is on the insulating layer and includes a plurality of gate signal lines connecting the pad and the gate driving circuit. Here, the planarization layer may cover side surfaces of at least one gate signal line among the plurality of gate signal lines, and expose an insulating layer between the plurality of gate signal lines.

Specific details of other embodiments are included in the detailed description and drawings.

Embodiments of the present specification may provide a display device in which defect problems due to damage to signal wiring are improved. In addition, embodiments of the present specification may provide a structure for blocking the moisture permeation path through the circuit portion outside the display device.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 illustrates an exemplary display device that may be included in an electronic device.
2A and 2B are schematic diagrams schematically illustrating a display area and a non-display area of a display device according to an exemplary embodiment of the present specification.
3A to 3B are exemplary views illustrating wiring arrangements of the display device.
4A to 4B are photographs showing conductive wires.
5A to 5B are views illustrating a display device according to an exemplary embodiment of the present specification.
6A to 6B are cross-sectional views schematically illustrating a display device according to another exemplary embodiment of the present specification.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and the ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When 'include', 'have', 'consist of', etc. mentioned in this specification are used, other parts may be added unless '~ man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, if the positional relationship of two parts is described as '~ top', '~ upper', '~ bottom', '~ side', etc., 'right' Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

An element or layer being referred to as being "on" another element or layer includes all instances of another layer or other element immediately above or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The same reference numerals refer to the same components throughout the specification.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each of the features of the various embodiments of the present invention may be partially or totally combined or combined with each other, and technically various interlocking and driving may be possible as those skilled in the art can fully understand, and each of the embodiments may be implemented independently of each other. It can also be implemented together in an associative relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates an exemplary display device that may be included in an electronic device.

The display device may be a flexible display device to which flexibility is given, that is, a foldable display device, a bendable display device, a rollable display device, or the like. The organic light emitting display device 100 includes at least one active area, and an array of pixels is formed in the display area. One or more inactive areas may be disposed around the display area. That is, the non-display area may be adjacent to one or more side surfaces of the display area. In FIG. 1, the non-display area surrounds a rectangular display area. However, the shape of the display area and the shape / arrangement of the non-display area adjacent to the display area are not limited to the example shown in FIG. 1. The display area and the non-display area may be in a form suitable for the design of an electronic device on which the organic light emitting display device 100 is mounted. Exemplary forms of the display area are pentagonal, hexagonal, circular, and elliptical.

Referring to FIG. 1, the display device 100 includes a display panel, a timing controller (not shown), a data driver (not shown), and a gate driving circuit (GIP).

The display panel is divided by a plurality of data lines DL and a plurality of gate lines GL (or scan lines) intersecting each other, and a plurality of data lines DL and a plurality of gate lines GL connected to each other. It includes a pixel PX. The display panel 110 includes a display area defined by a plurality of pixels PX and a non-display area in which various signal lines, pads, and the like are formed.

One pixel PX includes a transistor connected to the gate line GL and / or data line DL, and a pixel circuit operating in response to the gate signal and the data signal supplied by the transistor. The pixel PX may be implemented as an organic light emitting display panel including an organic light emitting device according to the configuration of the pixel circuit.

When the display panel 110 is composed of an organic light emitting display panel, the display panel 110 may be implemented by a top-emission method, a bottom-emission method, or a double-emission method. Can be.

A timing controller, a data driver, and a portion of the gate driver not shown in FIG. 1 may be formed on separate PCB substrates and connected to the display panel through pads PAD.

The timing controller receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through a reception circuit such as an LVDS or TMDS interface connected to an image board. The timing controller generates timing control signals for controlling the operation timing of the data driver and the scan driver based on the input timing signal.

The data driver includes a plurality of source drive ICs (Integrated Circuit). The plurality of source drive ICs receive digital video data (RGB) and a source timing control signal (DDC) from a timing controller. The plurality of source drive ICs convert digital video data RGB into a gamma voltage in response to the source timing control signal DDC to generate a data voltage, and supply the data voltage through the data line DL of the display panel. .

The gate driver outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal supplied from the timing controller. The embodiment of FIG. 1 exemplifies a case in which the gate driver is a GIP (Gate In Panel) type, a level shifter LS mounted on a flexible printed circuit board and a shift formed on a substrate in a non-display area of the display panel It includes a register (SR).

The level shifter LS receives signals such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from a timing controller, and also gate high voltage VGH and gate low voltage VGL. The driving voltage of the lamp is supplied.

The level shifter LS is shift clock signals CLK level-shifted by a start pulse ST input from a timing controller and each of the gate shift clocks GLCK to a gate high voltage VGH and a gate low voltage VGL. ).

Accordingly, each of the start pulse VST and the shift clock signals CLK output from the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL.

The start pulse VST and the shift clock signals CLK output from the level shifter LS are input to the shift register SR of the GIP unit through a gate signal line on the substrate.

The start register VST, clock signals CLK1 to CLKn, gate low voltage VGL and gate high voltage VGH output from the level shifter LS are in the shift register SR in the GIP portion of the non-display area. ) Is entered. These signals are input to the shift register SR through the gate signal line on the substrate. The shift register SR includes a plurality of stages (not shown) that are connected to each other. The clock signals CLK1 to n are n (n is a natural number of 2 or more) phase clock signals whose phases are sequentially delayed. The clock signals CLK1 to CLKn are supplied to each stage through clock signal supply lines (not shown).

The organic light emitting display device 100 may include various additional elements for generating various signals or driving pixels in the display area. Additional elements for driving the pixel may include an inverter circuit, a multiplexer, and an electrostatic discharge (ESD) circuit. The organic light emitting display device 100 may also include additional elements related to functions other than pixel driving. For example, the organic light emitting display device 100 may include additional elements that provide a touch sensing function, a user authentication function (eg, fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, and the like. have. The above-mentioned additional elements may be located in the non-display area and / or external circuit connected to the connection interface.

A portion of the non-display area visible from the front surface of the display device may be covered with a bezel. The bezel can be formed of a unique structure, or a housing or other suitable element. Some of the non-display area visible from the front of the display device may be hidden under an opaque mask layer such as black ink (eg, a polymer filled with carbon black). The opaque mask layer may be provided on various layers (touch sensor layer, polarization layer, cover layer, etc.) included in the organic light emitting display device 100.

2A and 2B are diagrams schematically illustrating a display area of a display device and a gate signal line (GSL) area connecting a GIP and a connection interface according to an embodiment of the present disclosure.

The illustrated display area and GSL area may be applied to at least a portion of the display area A / A and the non-display area I / A described in FIG. 1. Hereinafter, the display device will be described using an organic light emitting display as an example.

In the case of an organic light emitting display device, the display area (A / A) includes a thin film transistor (112, 114, 116, 118), an organic light emitting device (122, 124, 126) and various functional layers on the base layer (111). layer) is located. Meanwhile, various driving circuits, electrodes, wiring, and functional structures may be located on the base layer 111 in the non-display area I / A.

The base layer 111 supports various components of the organic light emitting diode display 100. The base layer 111 may be formed of a transparent insulating material, for example, an insulating material such as glass or plastic.

A buffer layer may be located on the base layer 111. The buffer layer is a functional layer for protecting a thin film transistor (TFT) from impurities such as alkali ions flowing out of the base layer 111 or lower layers. The buffer layer may be made of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

A thin film transistor is placed on the base layer 111 or the buffer layer. In the thin film transistor, the semiconductor layer 112, the gate insulating layer 113, the gate electrode 114, the interlayer insulating layer 115, and the source and drain electrodes 116 and 118 may be sequentially disposed. The semiconductor layer 112 is located on the base layer 111 or the buffer layer. The semiconductor layer 112 may be made of polysilicon (p-Si), in which case a predetermined region may be doped with impurities. Further, the semiconductor layer 112 may be made of amorphous silicon (a-Si), or may be made of various organic semiconductor materials such as pentacene. Furthermore, the semiconductor layer 112 may be made of oxide. The gate insulating layer 113 may be formed of an insulating inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be formed of an insulating organic material. The gate electrode 114 may be formed of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof. And the like.

The interlayer insulating layer 115 may be formed of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be formed of an insulating organic material. A contact hole through which the source and drain regions are exposed may be formed by selectively removing the interlayer insulating layer 115 and the gate insulating layer 113.

The source and drain electrodes 116 and 118 are formed of a single layer or a multi-layered shape as an electrode material on the interlayer insulating layer 115.

The planarization layer 117 may be located on the thin film transistor. The planarization layer 117 protects the thin film transistor and planarizes the top. The planarization layer 117 may be formed in various forms, such as an organic insulating film such as Benzocyclobutene (BCB) or acrylic (Acryl), or an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx). Various modifications are possible, such as being formed in a single layer or composed of double or multiple layers.

The organic light emitting device may have a shape in which the first electrode 122, the organic light emitting layer 124, and the second electrode 126 are sequentially arranged. That is, the organic light emitting device includes a first electrode 122 formed on the planarization layer 117, an organic light emitting layer 124 positioned on the first electrode 122, and a second electrode located on the organic light emitting layer 124 ( 126).

The first electrode 122 is electrically connected to the drain electrode 118 of the driving thin film transistor through the contact hole. When the organic light emitting diode display 100 is a top emission method, the first electrode 122 may be made of an opaque conductive material having high reflectance. For example, the first electrode 122 may be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof. .

The bank 120 is formed in regions other than the emission region. Accordingly, the bank 120 has a bank hole exposing the first electrode 122 corresponding to the emission region. The bank 120 may be made of an inorganic insulating material such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx) or an organic insulating material such as BCB, acrylic resin or imide resin.

The organic light emitting layer 124 is positioned on the first electrode 122 exposed by the bank 120. The organic light emitting layer 124 may include a light emitting layer, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, and the like. The organic light emitting layer may be configured with a single light emitting layer structure that emits one light, or may be configured with a plurality of light emitting layers to emit white light.

The second electrode 126 is positioned on the organic emission layer 124. When the organic light emitting diode display 100 is a top emission type, the second electrode 126 is transparently conductive, such as indium tin oxide (ITO) or indium zinc oxide (IZO). By being formed of a material, light generated in the organic light emitting layer 124 is emitted to the second electrode 126.

The protective layer 128 and the encapsulation layer 130 are positioned on the second electrode 126. The protective layer 128 and the encapsulation layer 130 prevent oxygen and moisture penetration from outside in order to prevent oxidation of the light emitting material and the electrode material. When the organic light emitting device is exposed to moisture or oxygen, a pixel shrinkage phenomenon in which the light emitting region is reduced may occur, or a dark spot in the light emitting region may occur. The passivation layer and / or the encapsulation layer is made of an inorganic film made of a glass, metal, aluminum oxide (AlOx) or silicon (Si) -based material, or the organic film and the inorganic film alternately It may be a stacked structure. The inorganic film serves to block the penetration of moisture or oxygen, and the organic film serves to flatten the surface of the inorganic film. The reason for forming the encapsulation layer as a multi-layered thin film layer is to make the movement path of moisture or oxygen longer and more complicated than a single layer, making it difficult to penetrate moisture / oxygen to the organic light emitting device.

The organic light emitting display device 100 may further include a touch layer, a polarization layer 160, and a cover layer 170 on the encapsulation layer 130. A touch panel / touch sensing electrode may be provided to sense a user's touch input on the top surface of the organic light emitting device (eg, the top surface of the encapsulation layer). If necessary, an independent layer provided with a touch sensing electrode and / or other components related to touch input sensing may be provided inside the organic light emitting display device 100. The touch sensing electrode (eg, a touch driving / sensing electrode) is a carbon-based material such as indium tin oxide or graphene, a carbon nanotube, a conductive polymer, a hybrid material made of a mixture of various conductive / non-conductive materials, etc. It may be formed of a transparent conductive material. In addition, a metal mesh (eg, aluminum mesh, silver mesh, etc.) may be used as the touch sensing electrode.

The organic light emitting display device 100 may include a polarization layer 160 to control display characteristics (eg, external light reflection, color accuracy, luminance, etc.). The cover layer 170 may be used to protect the organic light emitting display device 100 and may be, for example, cover glass.

In order to increase the strength and / or robustness in a specific portion of the organic light emitting display device 100,

One or more support layers 180 may be provided below the base layer 111. The support layer 180 is attached to the opposite side (second side) of the side (first side) with the organic light emitting element among both sides of the base layer 111. The support layer 180 is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyethylene ether phthalate (polyethylene ether phthalate), polycarbonate (polycarbonate), polyarylate (polyarylate), poly It can be made of a thin plastic film composed of a combination of polyether imide, polyether sulfonate, polyimide polyacrylate, and other suitable polymers. Other suitable materials that may be used to form the support layer 180 may be thin glass, a metal foil shielded with a dielectric, a multi-layer polymer, a polymer film containing a polymer material in combination with nanoparticles or microparticles, and the like. have.

The pixel circuit is not disposed in the non-display area I / A, but the base layer 111 and the organic / inorganic functional layers 113, 115, 117 128, 130, etc. may be present. In addition, materials used in the configuration of the display area A / A may be disposed in the non-display area I / A for other purposes.

For example, as shown in FIG. 2B, a metal 114 'used as a gate electrode of a TFT of a display area TFT, or a metal 118' used as a source / drain electrode is used for wiring and electrodes. / A). Furthermore, the metal 122 ′ used as one electrode (eg, anode) of the organic light emitting diode may be disposed in the non-display area I / A for wiring and electrodes.

3A to 3B are exemplary views illustrating wiring arrangements of the display device.

3A is an enlarged view of a portion of the GSL region of FIG. 1. 3B is a cross-sectional view taken along line I-I 'of FIG. 3A. Although there are a plurality of gate signal lines in the GSL area, for convenience of description, only three wires 118a, 118b, and 118c of the plurality of gate signal lines are simply shown in FIG. 3A.

In the non-display area of the display device, pads for applying an external signal to the panel, such as pads for lighting inspection and pads for COF bonding, are positioned. Therefore, depending on the design of the non-display area, the protective layer 128 and the encapsulation layer 130 formed to protect the organic light emitting device of the display area may not be formed. For the above reasons, the protective layer 128 and the encapsulation layer 130 are not formed on the GSL region. The gate signal line of the GSL region is formed of the same material and structure as the source and / or drain electrodes of the display region. For example, it may be a metal layer (so-called Ti / Al / Ti) having the same multi-layer structure stacked in the order of titanium (Ti), aluminum (Al), and titanium (Ti). The gate signal line of such a material and structure has strong characteristics against corrosion due to exposure to the external environment. However, the side surface of the gate signal line may be etched due to the etchant used when forming the first electrode 122 of the organic light emitting device. When the side surface of the gate signal line is damaged due to etching, a problem of increasing resistance occurs. In order to prevent this, a planarization layer formed of an organic insulating layer that protects the thin film transistor in the display area and planarizes the upper portion of the gate signal line is formed.

Several vulnerabilities have been found in the above-described protective structure (organic insulating layer) of the gate signal line in the GSL region. One of them was a phenomenon that prevented moisture from penetrating into the organic film due to a long-time use environment. Moreover, it has been found that electrolysis due to the potential difference between the gate signal lines may appear through the penetration of moisture. In the gate signal line of the GSL region illustrated in FIGS. 3A to 3B, the gate high line 118a has a gate high voltage V _GH of about + 8V to + 14.5V, and the gate low line 118b has a − A gate low voltage V _{GL of} 8V and a reset voltage QRST of + 8V to -8V may be applied to the Q reset line 118c. In this situation, when moisture (electrolytes and / or ions) in the organic insulating film penetrates, each gate signal line is caused by a large potential difference between the gate high voltage (V _GH ), the gate low voltage (V _GL ), and the reset voltage (QRST). An oxidation / reduction reaction occurs in the liver, and the reaction can develop into electrochemical corrosion. In addition, damage to the gate signal line may occur due to the above-described electroforming.

3B is a diagram illustrating the interaction between the gate high line 118a, the gate low line 118b, and the Q reset line 118c. Eating caused by this cause may increase the resistance of the conductors, causing heat damage, disconnection, and / or poor display (eg, bright lines).

4A to 4B are actual photographs of the conductive wire. 4A is a plan view showing the damage of the gate signal line due to the occurrence of electric shock. And Figure 4b can be seen that the conductor is damaged in the cross-sectional view of Figure 4a. Accordingly, the present inventors have recognized the above-described problem and devised a structure capable of preventing the electroplating of the conducting wire caused by the moisture of the organic insulating film.

5A to 5B are views illustrating a display device according to an exemplary embodiment of the present specification.

In the display device, a structure for preventing electric shock described in FIG. 4 is applied. That is, the display device includes an anti-corrosion structure provided in the gate signal line. The display device includes a substrate having a display area with a plurality of pixels and a non-display area around the display area; An insulating layer on top of the substrate; A gate driving circuit arranged along at least one side of the display area in the non-display area; The gate layer may include a plurality of gate signal lines 118a, 118b, and 118c that are disposed on the insulating layer, are connected to the pad and the gate driving circuit, and transmit gate control signals to the gate driving circuit. The pad may transfer a gate control signal from a timing control unit to a gate driving circuit.

The substrate may be the same as the base layer 111 described in FIGS. 2A and 2B. In addition, the insulating layer may include at least one of the gate insulating layer 113 and the interlayer insulating layer 115 in the display area.

5A to 5B are views schematically illustrating a display device according to an exemplary embodiment of the present specification. 6A to 6B are cross-sectional views schematically illustrating a display device according to another exemplary embodiment of the present specification.

5A is an enlarged view of a portion of the gate signal line region. 5B, 6A and 6B are cross-sectional views taken along line I-I 'of FIG. 5A. For convenience of description, only the gate high line 118a, the gate low line 118b, and the Q reset line 118c are simply shown in FIG. 5A. The stacked structure of the portion of FIG. 5A is illustrated separately in FIGS. 5B, 6A, and 6B corresponding to different embodiments. However, FIGS. 5B, 6A, and 6B are only examples, and the spirit of the present invention is not limited thereto.

5A, 5B, 6A, and 6B, the electrostatic prevention structure is provided to block the electrochemical action generated by moisture through a plurality of gate signal lines 118a, 118b, and 118c.

The plurality of gate signal lines 118a, 118b, and 118c may be covered with separate organic insulating layers 117, respectively. For example, the separated organic insulating layer 117 may cover both side and top surfaces of each gate signal line 118a, 118b, 118c (FIG. 5B). As another example, the separated organic insulating layer 117 may cover only the side surfaces of each of the gate signal lines 118a, 118b, and 118c (FIG. 6A). As another example, the separated organic insulating layer 117 may cover both side surfaces and a portion of the top surface of each gate signal line 118a, 118b, 118c (FIG. 6B).

The organic insulating layer 117 independently covers the gate signal lines 118a, 118b, and 118c to which different voltages are applied. That is, unlike the embodiments of FIGS. 3A to 3B, the organic insulating layer 117 covers the gate signal lines 118a, 118b, and 118c individually so as to be separated (isolated) to prevent moisture transfer, and furthermore, the gate signal line (118a, 118b, 118c) is provided to prevent the chemical action mediated by moisture. Referring to FIG. 5B, between the wires where the potential difference is large, for example, the gate high line 118a to which the gate high voltage V _GH is applied, and the gate low line 118b to which the gate low voltage V _GL is applied. ), The organic insulating layer 117 is not shared between the Q reset lines 118c to which the reset voltage QRST is applied, thereby exposing the lower insulating layers 113 and / or 115 between the gate signal lines. That is, no organic insulating layer is shared between the gate signal lines having different potentials, so that even if moisture penetrates the organic insulating layer 117, no chemical reaction (electricity) occurs between the gate signal lines due to the moisture. . The organic insulating layer 117 may be made of the same material as the planarization layer of the display area.

The method of forming the organic insulating layer may be simultaneously formed when forming the planarization layer of the display area. First, an organic material (eg, photoacrylic (PAC)) is coated on a substrate on which a gate signal line is formed, and then a mask is positioned on the substrate. The mask may have a blocking region in which light is not transmitted, a transmitting region in which light is transmitted, and a slit region in which the blocking region and the transmitting region are alternately formed according to the shape of the organic insulating layer. Light (UV) is irradiated with a light irradiator on the top of the mask. The light passing through the mask exposes the organic material and removes the exposed organic material using a developer. The desired pattern can be formed by adjusting the thickness of the organic insulating layer according to the mask design.

A display device according to an embodiment of the present invention may be described as follows.

A display device according to an exemplary embodiment of the present invention includes a substrate having a display area having a plurality of pixels and a non-display area around the display area; A gate driving circuit arranged along at least one side of the display area in the non-display area; A plurality of gate signal lines connected to the pad in the non-display area and the gate driving circuit and transferring a gate control signal to the gate driving circuit; It may include an anti-erosion structure provided in the gate signal line.

The electrostatic prevention structure may block the electrochemical action generated through moisture between the plurality of gate signal lines. That is, the anti-corrosion structure may include an organic insulating layer covering each of the plurality of gate signal lines.

The organic insulating layer may cover side surfaces of the plurality of gate signal lines, and the organic insulating layer may completely cover each of the plurality of gate signal lines.

Alternatively, the organic insulating layer may cover a part of upper surfaces of the plurality of gate signal lines.

The organic insulating layer may be formed of the same material as the planarization layer of the display area.

An insulating layer may be further included on the substrate. For example, the insulating layer may include at least one of a gate insulating layer and an interlayer insulating layer in the display area.

The pad may transmit a gate control signal from a timing control unit to the gate driving circuit.

A display device according to another embodiment of the present invention can be described as follows.

A substrate including a display area and a non-display area surrounding the display area; An insulating layer on top of the substrate; At least one planarization layer disposed on the display area and the non-display area; A gate driving circuit in the non-display area; A pad in the non-display area; A plurality of gate signal lines on the insulating layer and connecting the pad and the gate driving circuit; The planarization layer may cover side surfaces of at least one wiring among the plurality of gate signal lines, and expose the insulating layer between the plurality of gate signal lines.

The planarization layer may completely cover each of the plurality of gate signal lines. Further, the planarization layer may cover a portion of the upper surfaces of the plurality of gate signal lines. Here, the planarization layer may include an organic insulating material.

The plurality of gate signal lines may be made of the same material as the source and drain electrodes of the display area. The insulating layer may include at least one of a gate insulating layer and an interlayer insulating layer in the display area.

Although the embodiments of the present specification have been described in detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit. Therefore, the embodiments disclosed in the present specification are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Each of the features of the various embodiments of the present invention may be partially or wholly combined with or combined with each other, and may be technically interlocked and driven by a person skilled in the art, and each of the embodiments may be implemented independently of each other or together in an associative relationship. It may be practiced. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present invention.

100: display device
111: base layer
112: semiconductor layer
113: gate insulating film
114: gate electrode
115: interlayer insulating film
116: source electrode
117: planarization layer
118: drain electrode
118a: Gate High Line
118b: Gate low line
118c: Q reset line
120: bank
122: first electrode
124: organic light emitting layer
126: second electrode
128: protective layer
130: bag layer
160: polarizing layer
170: cover layer
180: support layer

Claims (16)

A substrate having a display area with a plurality of pixels and a non-display area around the display area;
A gate driving circuit arranged along at least one side of the display area in the non-display area;
A plurality of gate signal lines connected to the pad of the non-display area and the gate driving circuit and transferring a gate control signal to the gate driving circuit;
A display device comprising an anti-corrosion structure provided in the gate signal line.
According to claim 1,
The electrostatic prevention structure, a display device for blocking the electrochemical action generated through the moisture between the plurality of gate signal lines.
According to claim 1,
The anti-corrosion structure, the display device including a separate organic insulating layer covering each of the plurality of gate signal lines.
According to claim 3,
The organic insulating layer covers the side surfaces of the plurality of gate signal lines.
According to claim 3,
The organic insulating layer completely covers each of the plurality of gate signal lines.
According to claim 4,
The organic insulating layer covers a portion of the upper surfaces of the plurality of gate signal lines.
The method according to claim 3 to 6,
The organic insulating layer is a display device made of the same material as the planarization layer of the display area.
According to claim 1,
A display device further comprising an insulating layer on the substrate.
The method of claim 8,
The insulating layer includes at least one of a gate insulating layer and an interlayer insulating layer in the display area.
According to claim 1,
The pad is a display device provided to transmit a gate control signal from a timing controller to the gate driving circuit.
A substrate including a display area and a non-display area surrounding the display area;
An insulating layer on top of the substrate;
A planarization layer disposed on the display area and the non-display area;
A gate driving circuit in the non-display area;
A pad in the non-display area; And
A gate signal line on the insulating layer and connecting the pad and the gate driving circuit,
The flattening layer covers a side surface of at least one gate signal line among the plurality of gate signal lines and exposes the insulating layer between the plurality of gate signal lines.
The method of claim 11,
The flattening layer is separated to completely cover each of the plurality of gate signal lines.
The method of claim 11,
The flattening layer is separated to cover a portion of the upper surface of the plurality of gate signal lines.
The method of claim 11,
The flattening layer is a display device including an organic insulating material.
The method of claim 11,
The plurality of gate signal lines are the same material as the source and drain electrodes of the display area.
The method of claim 11,
The insulating layer includes at least one of a gate insulating layer and an interlayer insulating layer in the display area.

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