KR20200054003A - Clock converting method for semiconductor device test and clock converter and test system thereof - Google Patents

Abstract

According to one aspect of a technical idea of the present disclosure provides a clock converter outputting a clock signal for testing a semiconductor device, which comprises: a clock input terminal receiving an input clock; a first frequency conversion circuit receiving the input clock and outputting a first conversion clock in which a frequency of the input clock is increased by a fixed multiplication order; a second frequency conversion circuit receiving the input clock and outputting a second conversion clock in which the frequency of the input clock is raised higher than the frequency of the first conversion clock by a variable multiplication order; and a selection circuit outputting the first conversion clock or the second conversion clock in accordance with a received mode selection signal.

Description

Clock conversion method for testing semiconductor device and clock converter and test system including same {CLOCK CONVERTING METHOD FOR SEMICONDUCTOR DEVICE TEST AND CLOCK CONVERTER AND TEST SYSTEM THEREOF}

The technical idea of the present disclosure relates to a method for generating a clock output to a semiconductor device for testing a semiconductor device, and a clock converter and test system including the same.

In accordance with the rapid development of the electronics industry and the needs of users, electronic devices are becoming more and more miniaturized, highly functional, and large in capacity. Accordingly, a test process for a semiconductor device included in an electronic device is also complicated. As an example, when a high-performance memory semiconductor device is tested as a device under test (DUT), if the device under test performs various functions such as read and write operation with high bandwidth, the test equipment also performs such high bandwidth. It needs to be designed to be tested.

The problem to be solved by the technical spirit of the present disclosure is to provide a clock conversion method and a clock converter and test system including the same, and a clock conversion method for testing a device under test using various mode bandwidths without replacing test equipment. have.

In order to achieve the above object, in a clock converter for outputting a clock signal for testing a semiconductor device according to an aspect of the technical idea of the present disclosure, a clock input terminal for receiving an input clock, receiving the input clock , A first frequency conversion circuit for outputting a first conversion clock that has increased the frequency of the input clock by a fixed multiplication order, receiving the input clock, and changing the frequency of the input clock to the first conversion clock by a variable multiplication order It may include a second frequency conversion circuit for outputting a second conversion clock increased higher than the frequency of, and a selection circuit for outputting the first conversion clock or the second conversion clock according to the received mode selection signal.

In a semiconductor test system for testing a semiconductor device according to an aspect of the technical spirit of the present disclosure, data is transmitted and received for testing the semiconductor device, and according to a band of an input clock and an output frequency for testing the semiconductor device An automatic test equipment including test logic for outputting a mode selection signal having different values, and a socket board electrically connected to the automatic test equipment, wherein the socket board receives the input clock. A clock input terminal, a first frequency conversion circuit that receives the input clock and outputs a first converted clock with an increased frequency of the input clock, receives the input clock, and sets the frequency of the input clock to the first converted clock. A second frequency side that outputs a second converted clock that is raised above the frequency of Depending on the circuit, and the received mode selection signal may include a clock converter comprising a selection circuit which on the basis of the first conversion frequency or the second frequency converting and outputting the output clock in the semiconductor device.

A method of converting a clock signal for testing a semiconductor device according to an aspect of the technical spirit of the present disclosure, the method comprising: receiving an input clock, and by a first frequency conversion circuit, the frequency of the input clock is a first multiplication order. Outputting the first converted clock raised to, and generated by one of a plurality of voltage-controlled oscillators that generate oscillation frequencies of different bands by a second frequency conversion circuit, and input the signal above the first multiplication order. And outputting the second converted clock multiplied by the clock and outputting the first converted clock or the second converted clock according to the received mode selection signal.

According to an exemplary embodiment of the present disclosure, the mode can be changed in the socket board to output a clock having a bandwidth required by the device under test, so that clocks of various bands can be generated without having a separate device. have. Accordingly, the cost of replacing the test equipment can be reduced, and various types of equipment under test can be tested.

1 is a block diagram illustrating a test system according to an embodiment of the present disclosure.
2 is a block diagram illustrating a socket board according to an embodiment of the present disclosure.
3 is a view for explaining a clock converter according to an embodiment of the present disclosure.
4 is a view for explaining an XOR gate according to an embodiment of the present disclosure.
5 is a view for explaining a second frequency conversion circuit according to an embodiment of the present disclosure.
6 is a view for explaining in detail a second frequency conversion circuit according to an embodiment of the present disclosure.
7 is a view for explaining in detail a second frequency conversion circuit according to an embodiment of the present disclosure.
8A and 8B are data flow diagrams for describing an input clock, an output clock, and data in a first frequency conversion circuit according to an embodiment of the present disclosure.
9 is a data flow diagram for describing an input clock, an output clock, and data in a second frequency conversion circuit according to an embodiment of the present disclosure.
10 is a flowchart illustrating a method of generating an output clock for testing a semiconductor device according to an embodiment of the present disclosure.
11 is a flowchart illustrating in detail a method of generating an output clock for testing a semiconductor device according to an embodiment of the present disclosure.
12 is a diagram for describing a test system according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a test system according to an embodiment of the present disclosure.

Referring to FIG. 1, a test system 10 for testing a semiconductor device includes a socket board 100 and a test logic 200, and one or more devices under test (DUT) 300 to be tested. ). The socket board 100 may include a first frequency conversion circuit 110, a second frequency conversion circuit 120 and a selection circuit 130.

According to an embodiment of the present disclosure, the first frequency conversion circuit 110 may increase the input clock CKI to a fixed multiplication order, and the second frequency conversion circuit 110 may vary the input clock CKI. It can be increased by multiplication order. For example, the first frequency conversion circuit 110 may multiply the input clock (CKI) by 2, and the second frequency conversion circuit may multiply the input clock (CKI) by 4 or 8 or multiples. As another example, the second frequency conversion circuit 120 may raise the input clock CKI higher than the first frequency conversion circuit 110. As another example, the first frequency conversion circuit 110 may be implemented as an XOR circuit including an exclusive OR (XOR) gate, and the second frequency conversion circuit 120 may include a PLL circuit including a phase locked loop (PLL). Can be implemented as Hereinafter, the multiplication order may mean an integer multiplied by the frequency of the input signal.

The socket board 100 may be implemented in various forms and locations to process the signal CKI output from the test logic 200 and output it to the device under test 300. In this case, the test logic 200 may be included in an automated test equipment (ATE), and the socket board 100 may be located on one side of the test equipment.

The test logic 200 may output an input clock CKI and data DQ to test the device under test 300. For example, the test logic 200 may test the device under test 300 based on whether data DQ suitable for the outputted input clock CKI is received. The device under test 300 may receive the output clock CKO and the data DQ based on the input clock CKI. The data DQ is transmitted and received between the test logic 200 and the device under test 300, and may be transmitted and received via the socket board 100.

Referring to FIG. 1, the device under test 300 is illustrated as one semiconductor device, but this is for convenience of description, and the device under test 300 may include a plurality of semiconductor devices. As an example, the semiconductor device may be a memory device including an array of memory cells. For example, the memory device includes dynamic random access such as DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, and Rambus Dynamic Random Access Memory (RDRAM). It may be a memory (Dynamic Random Access Memory, DRAM). Alternatively, the memory device may correspond to a nonvolatile memory such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and resistive RAM (ReRAM).

According to an embodiment of the present disclosure, the socket board 100 may process the input clock CKI received from the test logic 200 to be compatible with the device under test 300 to output the output clock CKO. . For example, when the bandwidth of the input clock CKI that the test logic 200 can output is limited to x Gbps (eg, x is an integer), the socket board 100 multiplies the input clock CKI by 2x. It may be provided to output an output clock (CKO) having a bandwidth higher than the bandwidth of the input clock (CKI), such as Gbps or 4x Gbps. The socket board 100 may output an inverted output clock CKO 'together with the output clock CKO. In this case, the socket board 100 may have the same number of channels through which the input clock CKI is received and the number of channels through which the output clock CKO is output.

According to an embodiment of the present disclosure, the socket board 100 receives a mode selection signal MSEL from the test logic 200, and either the first frequency conversion circuit 110 or the second frequency conversion circuit 120 is received. A signal output from one may be selected and an output clock CKO may be transmitted to the device under test 300. As an example, when the selection circuit 130 receives the mode selection signal MSEL having the first value, the signal received from the first frequency conversion circuit 110 may be amplified and provided as an output clock CKO. . As another example, when the mode selection signal MSEL having the second value is received, the selection circuit 130 may amplify the signal received from the second frequency conversion circuit 120 and provide it as an output clock CKO. .

The first frequency conversion circuit 110 may receive the first input clock CKIA and the second input clock CKIB. The input clock CKI may include a first input clock CKIA and a second input clock CKIB. As an example, the test logic 200 is 90 degrees from the phase of the first input clock CKIA. The second input clock CKIB having the shifted phase and having the same frequency as the first input clock CKIA may be output.

The first frequency conversion circuit 110 may XOR the first input clock CKIA and the second input clock CKIB to output a frequency signal of a frequency multiplied by 2 to the selection circuit 130. The second frequency conversion circuit 120 may perform a phase lock operation using the first input clock CKIA as a reference frequency signal. In this case, a signal of a frequency band allocated to each of the plurality of voltage-controlled oscillators included in the second frequency conversion circuit 120 may be output, which will be described later in FIG. 6.

According to the exemplary embodiment of the present disclosure, since the first frequency conversion circuit 110 performs an XOR operation on the first input clock CKIA and the second input clock CKIB in real time, a low delay occurs and a wide frequency There is a feature that can cover the band. The second frequency conversion circuit 120 may reduce noise of the output clock CKO by comparing the phases by feeding back signals output from the first input clock CKIA and the second frequency change circuit 120. Also, the second frequency conversion circuit 120 may perform frequency multiplication by an arbitrary multiple, and the number of input channels may be less than the first frequency conversion circuit 110.

Accordingly, according to an exemplary embodiment of the present disclosure, the second frequency conversion circuit 120 may operate to generate an output clock CKO having a high frequency even with a low input clock CKI because frequency multiplication is free. have. In addition, the second frequency conversion circuit 120 performs an operation for detecting a phase difference, so that even when noise is generated in the input clock CKI, an output clock CKO having low noise may be generated. Meanwhile, the first frequency conversion circuit 110 may operate to generate an output clock CKO of a lower frequency band compared to the second frequency conversion circuit 120. In addition, since the first frequency conversion circuit 110 including the XOR gate can generate the output clock CKO without delay even when the frequency of the input clock CKI changes in real time, the output clock having a variable frequency ( CKO) may be operated to test the device under test 300.

2 is a block diagram illustrating a socket board according to an embodiment of the present disclosure.

Referring to FIG. 2, the socket board 100 may include a plurality of socket chips 105_1 to 105_N, and each socket chip 105 includes a first frequency conversion circuit 110 and a second frequency conversion circuit ( 120) and a selection circuit 130, and may further include an input termination (RI), a clock input terminal (IT), and a clock output terminal (OT).

As an example, the plurality of socket chips 105_1 to 105_N may be stacked with each other and packaged as one. As another example, the plurality of socket chips 105_1 to 105_N may be spaced apart from each other on the socket board 100 and disposed in two dimensions. That is, the plurality of socket chips 105_1 to 105_N are output devices CKO [0] to CKO [N] and / or inverted output clocks of the socket chips 105_1 to 105_N to the device under test 300. CKO '[0] to CKO' [N]) may be included in the socket board 100 in various forms capable of outputting. For example, when testing a plurality of devices under test 300, the first output device CKO [0] and the inverted first output clock CKO '[0] are output to the first device under test. 2 A second output clock (CKO [1]) and an inverted second output clock (CKO '[1]) may be provided to the device under test. Further, the test logic 200 may output the input clocks CKIA [0] and CKIB [0] to test the first device under test, and the input clock CKIA [to test the second device under test. 1], CKIB [1]) can be output.

The socket board 100 may include a plurality of terminals for inputting various signals and voltages. The socket board 100 may include a supply voltage (VCC) terminal, a ground voltage (VEE) terminal, and a ground (GND) terminal for supplying power to the socket board 100 and / or the device under test 300. .

The socket board 100 may include a plurality of input clock (CKI) terminals. For example, a terminal for outputting a first input clock CKIA [0] input to the first socket chip 105_1 and a second input clock CKIB [0] input to the first socket chip 105_1 is included. The first input clocks CKIA [0]-[N] and the second input clocks CKIB [0]-[, which are input through the clock input terminal IT of each socket chip 105. N]) may be included. The socket board 100 is used for logically determining (eg, determining logic high or logic low) AC signals input or output in each of the components included in the input chip (CKI) and the socket chip 105, which are AC signals. It may include a reference voltage (VREF) terminal. The socket board 100 may include terminals for determining a maximum driving voltage VOH and a driving voltage swing level VR supplied to various configurations included in the socket chip 105 including the selection circuit 130. . The socket board 100 may include a terminal for receiving a mode selection signal MSEL applied to the selection circuit 130 and an oscillator selection signal OSEL applied to the second frequency conversion circuit 120.

The socket board 100 may include a plurality of terminals for outputting various signals and voltages. The socket board 100 includes output clocks (CKO [0] to CKO [N]) and inverted output clocks (CKO '[0] to CKO' [N]) output from the plurality of socket chips 105_1 to 105_N. It may include terminals for transmitting the device to be inspected (300). The configuration and function of each socket chip 105 will be described later in FIG. 3.

3 is a view for explaining a clock converter according to an embodiment of the present disclosure.

According to FIG. 3, each socket chip 105 includes a clock converter 107, and the clock converter 107 includes a first frequency conversion circuit 110, a second frequency conversion circuit 120, and a selection circuit 130. ), A clock input terminal IT and a clock output terminal OT. Also, the clock converter 107 may further include an input termination RI for matching the input impedance viewed from the clock input terminal IT.

According to an embodiment of the present disclosure, the first frequency conversion circuit 110 receives the first input clock CKIA and the second input clock CKIB, and the first conversion clock CKX and / or the inverted first conversion clock (CKX ') can be output. For example, the frequency of the first conversion clock CKX may be twice as high as the frequency of the first input clock CKIA. To this end, the first frequency conversion circuit 110 may be implemented as an integrated circuit including an XOR gate. For example, an XOR gate may be generated by XORing the first input clock CKIA and the second input clock CKIB to generate the first conversion clock CKX, which is an inverted signal of the first conversion clock CKX. And an inverter that generates the inverted first conversion clock CKX '.

4 is a view for explaining an XOR gate according to an embodiment of the present disclosure.

3 and 4, the first frequency conversion circuit 110 may include an XOR gate 111, and the XOR gate 111 may be implemented in various forms such as hardware or software. The XOR gate 111 outputs 0 when the first input and the second input are 0, 0 or 1, 1 according to a known truth table, and the first input and the second input are 0, 1 or 1, If it is 0, an exclusive OR operation that outputs 1 can be performed. The first input clock CKIA and the second input clock CKIB input to the XOR gate 111 according to the present disclosure may have a phase shifted by 1/4 cycle or 90 degrees. As the first input clock CKIA and the second input clock CKIB having phase shifted by 90 degrees are input, the XOR gate 111 outputs the first converted clock CKX whose frequency is doubled. Can be.

According to the first frequency conversion circuit 110 and the XOR gate 111 according to an embodiment of the present disclosure, an input clock CKI shifted by 90 degrees may be received to generate the first conversion clock CKX in real time. Since the delay can be reduced and the frequency of the input clock (CKI) is not limited, a wide band frequency can be covered. However, the first frequency conversion circuit 110 has a limit of multiplying the input frequency by twice.

Referring to FIG. 3 again, the second frequency conversion circuit 120 may receive the first input clock CKIA and output the second conversion clock CKY and / or the inverted second conversion clock CKY '. . For example, the frequency of the second conversion clock CKY may be N times higher than the frequency of the first input clock CKIA, and N may be an integer greater than 1.

To this end, the second frequency conversion circuit 120 may be implemented as a phase locked loop (PLL). For example, the second frequency conversion circuit 120 compares the phases of the first input clock CKIA and the second converted clock CKY fed back to generate a signal according to the phase difference, and converts the generated signal into a voltage. By converting, an oscillation signal according to the converted voltage can be output. The second frequency conversion circuit 120 may include at least one voltage controlled oscillator, and may select an oscillator outputting a desired frequency band among a plurality of voltage controlled oscillators according to the oscillator selection signal OSEL. In this regard, it will be described later in FIGS. 5 and 6.

According to an embodiment of the present disclosure, the maximum value of the frequency that the second conversion clock CKY may have may have a frequency higher than the maximum value of the frequency that the first conversion clock CKX may have. For example, the first frequency conversion circuit 110 may multiply the frequency by two through XOR operation, and the second frequency conversion circuit 120 arbitrarily controls the frequency division ratio of the divider 125, thereby multiplying by multiples ( For example, the second converted clock CKY multiplied by 4 may be output.

If the high frequency output clock CKO is generated using the second frequency conversion circuit 120, the frequency of the input clock CKI can be lowered. For example, when an output clock (CKO) of 20 Gbps is to be generated, the first frequency conversion circuit 110 needs an input clock (CKI) having a frequency of 10 Gbps, but the second frequency conversion circuit 120 sets the frequency to 4 Since multiplication is also possible, only an input clock (CKI) with a frequency of 5 Gbps is required. Therefore, it is possible to reduce the cost and time for the test logic 200 to output a high input clock (CKI).

The clock converter 107 according to the embodiment of the present disclosure inputs the first input clock CKIA and / or the second input clock CKIB to the first frequency conversion circuit 110 and the second frequency conversion circuit 120. It may be provided with a transmission line for. The first transmission line is connected to the first frequency conversion circuit 110 from the clock input terminal IT to which the first input clock CKIA is input, and the transmission line connected to the first frequency conversion circuit 110 is branched. The first transmission line may be connected to the two frequency conversion circuit 120. Meanwhile, a second transmission line may be connected to the first frequency conversion circuit 110 from the clock input terminal IT to which the second input clock CKIB is input. Further, an input termination RI may be provided along a transmission line branched from the first transmission line and the second transmission line, and a switch connected in series with the input termination RI may be provided.

The input termination (RI) according to an embodiment of the present disclosure is connected in parallel to the clock input terminal and the first frequency conversion circuit 110, and the impedance value of the input termination (RI) is the first input clock (CKIA) and the second input At the clock input terminal (IT) of the clock (CKIB), the impedance viewed in the direction of the first frequency conversion circuit 110 and the second frequency conversion circuit 120 and the impedance viewed in the opposite direction are impedance matching values. Can be.

Meanwhile, the input termination RI may be activated according to a termination enable signal. For example, the input termination RI is connected in series with the switch, and the termination enable signal TE can be controlled to turn the switch on or off. The termination enable signal TE may be input from the test logic 200 to the clock converter 107 through the socket board 100.

The selection circuit 130 according to an embodiment of the present disclosure receives the first converted clock CKX, the inverted first converted clock CKX ', the second converted clock CKY, and the inverted second converted clock CKY' Then, at least one of the received clocks may be selected to output the amplified output clock CKO and the inverted output clock CKO '.

The selection circuit 130 may include a multiplexer 131 and an operational amplifier circuit 132. The multiplexer 131 selects a signal output from one of the first frequency conversion circuit 110 and the second frequency conversion circuit 120 according to the mode selection signal MSEL, and selects the selected signal (CKS) ). For example, when the multiplexer 131 receives the mode selection signal MSEL having the first value, it outputs the first conversion clock CKX input from the first frequency conversion circuit 110 as the selection clock CKS. Then, the inverted first converted clock CKX 'can be output as the inverted select clock CKS'.

The operational amplifier circuit 132 may output the output clock CKO and the inverted output clock CKO 'amplified by the received select clock CKS and the inverted select clock CKS', respectively. According to an embodiment of the present disclosure, the operational amplifier circuit 132 may amplify the selection clock CKS and the inversion selection clock CKS 'based on the maximum driving voltage level VOH and the minimum driving voltage level VOL. have. In this case, the minimum driving voltage level VOL may be a value obtained by subtracting the driving voltage swing level VR from the maximum driving voltage level VOH received from the outside from the socket board 100 of FIG. 2 described above. For example, the operational amplifier circuit 132 may generate an output clock CKO that amplifies the selected clock CKS to a maximum driving voltage level VOH or less and a minimum driving voltage level VOL or more.

5 is a view for explaining a second frequency conversion circuit according to an embodiment of the present disclosure.

Referring to FIG. 5, the second frequency conversion circuit 120 includes a phase detection unit 121, a charge pump unit 122, a loop filter unit 123, a voltage controlled oscillation unit 124, and a divider 125. Can be. The phase detection unit 121 compares the phase of the clock fed from the first input clock CKIA and the divider 125, and the charge pump unit 122 generates a signal according to the phase difference, and the loop filter unit ( 123) converts the generated signal into a voltage, the voltage-controlled oscillation unit 124 outputs an oscillation signal according to the converted voltage, and the divider 125 divides the frequency of the oscillation signal and provides it to the phase detection unit 121 can do. That is, the second frequency conversion circuit 120 may be implemented as a phase locked loop (PLL).

The second frequency conversion circuit 120 receives the oscillator selection signal OSEL, selects one of a plurality of voltage controlled oscillators included in the voltage controlled oscillator 124, and removes it based on the output of the selected voltage controlled oscillator. 2 Convert clock (CKY) can be output. In relation, it will be described later in FIG. 6.

6 is a view for explaining in detail a second frequency conversion circuit according to an embodiment of the present disclosure.

The phase detector 121 according to the exemplary embodiment of the present disclosure compares the phase difference between the divided clock CKD output from the divider 125 and the first input clock CKIA, and generates a phase difference signal DSIG can do. The phase difference signal DSIG may include an up detection signal D_UP and a down detection signal D_DOWN.

Referring to FIG. 6, the phase detection unit 121 may include a first flip-flop 121a, a second flip-flop 121b, an AND gate 121c, and a delay unit 121d. The first input clock CKIA is input to the clock input terminal CK of the first flip-flop 121a, and the divided clock CKD output from the divider 125 is the clock input terminal of the second flip-flop 121b ( CK). The data input terminal D of the flip-flops 121a and 121b may be connected to a power supply voltage VCC. The up detection signal D_UP may be output from the data output terminal Q of the first flip-flop 121a, and the down detection signal D_DOWN may be output from the data output terminal Q of the second flip-flop 121b. have. For example, the up detection signal D_UP is a signal indicating that the first input clock CKIA having a phase higher than the frequency division signal CKD is input, and the down detection signal D_DOWN is a signal indicating the opposite. The AND gate 121c receives the up detection signal D_UP and the down detection signal D_DOWN to perform an AND operation. The delay unit 121d may delay the output of the AND gate 121c by a predetermined time and provide a reset signal to the reset (Re) terminal of the flip-flops 121a and 121b. Since the charge pump current sources 122a and 122b included in the charge pump unit 122 require a certain time while performing a turn-on or turn-off operation, the delay unit 121d delays the output by a predetermined time. Can be.

The phase detection unit 121 transmits an up detection signal D_UP to the charge pump unit 122 when the phase of the first input clock CKIA is faster than the phase of the division clock CKD, and vice versa. The detection signal D_DOWN can be transmitted.

According to an embodiment of the present disclosure, the charge pump unit 122 may supply electric charges to the loop filter unit 123 or discharge electric charges of the loop filter unit 123 based on the received phase difference signal DSIG. . That is, the charge pump unit 122 may convert the phase difference signal DSIG into the movement of electric charges. For example, when the charge pump unit 122 receives the up detection signal, the charge pump unit 122 may perform a positive charge pumping operation to supply charge to the loop filter unit 123. In another example, the charge pump unit 122 is down. Upon receiving the detection signal, a negative charge pumping operation may be performed to discharge the charge of the loop filter unit 123.

Referring to FIG. 6, the charge pump unit 122 includes a switch 122c turned on by a logic high of the up detection signal D_UP, and a switch 122d turned on by a logic high of the down detection signal D_DOWN. ). When receiving the up detection signal D_UP, the charge pump current source 122a may supply current to the loop filter unit 123. When receiving the down detection signal D_DOWN, the charge pump current source 122b may drain the current of the loop filter unit 123.

According to an embodiment of the present disclosure, the loop filter unit 123 may provide an oscillation control voltage (VCTR) corresponding to charges or discharged charges charged by the charge pump unit 122 to the voltage control oscillation unit 124. have. The loop filter unit 123 may be implemented with various filters such as a low pass filter, a band pass filter, and a high pass filter, and is illustrated as being composed of passive elements, but may also be implemented as a filter composed of active elements.

Referring to FIG. 6, the loop filter unit 123 may include capacitors C1 and C2 and a resistor R1. The first capacitor C1 charges or discharges the electric charge output from the charge pump unit 122 to generate an oscillation control voltage VCTR, and the resistor R1 is designed to have a constant time constant, loop The rapid change of the current or voltage of the filter unit 123 can be prevented. The second capacitor C2 can absorb the impulse current flowing when the phase locked loop is locked.

7 is a view for explaining in detail a second frequency conversion circuit according to an embodiment of the present disclosure.

Referring to FIG. 7, the voltage-controlled oscillator 124 may include a plurality of voltage-controlled oscillators 126 and an oscillation voltage selection circuit 127. The voltage controlled oscillator 124 converts the oscillation signal output from one of the plurality of voltage controlled oscillators 126 based on the received oscillator selection signal OSEL into a second conversion clock CKY and / or an inverted second conversion clock. (CKY ').

As an example, the oscillator selection signal OSEL may be provided to the plurality of voltage controlled oscillators 126. In this case, the at least one voltage controlled oscillator 126 is activated based on the oscillator selection signal OSEL, and the remaining voltage controlled oscillators 126 can be deactivated. The oscillation signal (eg, OS_1) output from the activated voltage-controlled oscillator 126 may be output as the second conversion clock CKY via the oscillation voltage selection circuit 127. Also, the oscillation voltage selection circuit 127 may invert the oscillation signal (eg, OS_1) output from the activated voltage-controlled oscillator 126 to output the inverted second conversion clock CKY '.

As another example, the oscillator selection signal OSEL may be provided to the oscillation voltage selection circuit 127. The oscillation voltage selection circuit 127 may select and output an oscillation signal (eg, OS_2) to be output as the second conversion clock CKY based on the oscillator selection signal OSEL. Also, the oscillation signal (eg, OS_2) may be inverted to output the inverted second conversion clock CKY '. For example, the oscillation voltage selection circuit 127 receives the oscillator selection signal OSEL as a control input and selects one of a plurality of oscillation signals OS_1 to OS_N, and a second conversion clock CKY that is a selected voltage. ) Inverter may be included.

As another example, the oscillator selection signal OSEL may be provided to the plurality of voltage controlled oscillators 126 and the oscillation voltage selection circuit 127 as a combination of the above-described examples. In this case, the voltage-controlled oscillator 126 activated by the oscillator selection signal OSEL among the plurality of voltage-controlled oscillators 126 outputs an oscillation signal (eg, OS_1), and the selection circuit 127 outputs the The oscillation signals (eg, OS_2 to OS_N) other than the oscillation signal (eg, OS_1) may not be output. That is, the oscillation voltage selection circuit 127 may output only the voltage of the voltage-controlled oscillator 126 selected by the oscillator selection signal OSEL as the second conversion clock CKY and the inverted second conversion clock CKY '. .

According to an embodiment of the present disclosure, each voltage-controlled oscillator 126 may output voltages having frequency signals of different bands. For example, the first oscillator 126_1 may output an oscillation signal OS_1 having a frequency of 1 Gbps to 3 Gbps, and the second oscillator 126_2 may oscillate signal OS_2 having a frequency of 3 Gbps to 5 Gbps. Can output In this case, when it is desired to output the output clock CKO having a frequency of 4 Gbps to the device under test 300, the test logic 200 oscillator select signal OSEL instructing the selection of the second oscillator 126_2. To the voltage controlled oscillator 126 and / or the oscillation voltage selection circuit 127. However, these frequency values are merely exemplary for convenience of description, and may have various frequency bands.

The frequency divider 125 according to an embodiment of the present disclosure may receive a second conversion clock CKY and output a frequency division frequency clock CKD. For example, in order to output the second conversion clock CKY multiplied by n times compared to the first input clock CKIA, the divider 125 divides the frequency of the second conversion clock CKY by n times. The clock CKD may be transmitted to the phase detection unit 121. The phase detector 121 may generate a phase difference signal DSIG for correcting a phase difference by comparing the first input clock CKIA and the divided clock CCK, which is divided by n times. have.

Meanwhile, the divider 125 may be designed with various types of circuits capable of frequency division, the divider 125 may include a parallel or serial counter, and the counter may include at least one flip-flop. Can be. For example, the counter may be implemented in various ways, such as a Modulo-n counter, a ring counter, a cyclic shift register counter, and a BCD counter.

8A and 8B are data flow diagrams for describing an input clock, an output clock, and data in a first frequency conversion circuit according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the first frequency conversion circuit 110 may receive the first input clock CKIA and the second input clock CKIB, and perform an XOR operation to output the first conversion clock CKX. have. The selection circuit 130 may receive the first conversion clock CKX and increase the amplitude to output the output clock CKO.

That is, the output clock CKO illustrated in FIGS. 8A and 8B may be the same as or similar to the first converted clock CXK. Meanwhile, since the phase of the second input clock CKIB is only 90 degrees shifted compared to the first input clock CKIA, illustration is omitted for convenience of description.

Referring to FIG. 8A, the first frequency conversion circuit 110 XOR-operates and outputs the first input clock CKIA and the second input clock CKIB shifted by 90 degrees from the phases of the first input clock CKIA. A clock CKO can be generated. The output clock CKO may include a clock obtained by doubling the frequency n of the first input clock CKIA in the first time period CLK 2n. In this case, the clock multiplied by 2 times may be a frequency for the device under test 300 to perform a write operation or a read operation.

Meanwhile, the first frequency conversion circuit 110 may generate an output of the output clock CKO including the clock of the low frequency required by the device under test 300 in the second time period FIXH / L. For example, the first frequency conversion circuit 110 may output a signal having a low frequency or a first signal including a DC signal in the second time period FIXH / L, and in the first time period CLK 2n A second signal having a high frequency can be output.

According to an embodiment of the present disclosure, in a second time period (FIXH / L), the first frequency conversion circuit 110 is used as the first input clock CKIA and the second input clock CKIB from the test logic 200. A fixed signal can be received as either logic high or logic low. That is, a signal maintained in direct current during the second time period (FIXH / L) may be received. As another example, the first frequency conversion circuit 110 may receive an AC signal in which the first input clock CKIA and the second input clock CKIB are the same in phase from the test logic 200. In this case, as the first frequency conversion circuit 110 receives the DC signal or two signals having the same phase, the first frequency conversion circuit 110 may output the DC signal in the first time period FIXH / L. For example, the first time interval (FIXH / L) of the device under test 300 that determines the speed or operation mode of the device under test 300 after power is supplied to the device under test 300 It may include an initializing step. Also, the output clock CKO of the first time period FIXH / L may include a preparation step for increasing the frequency of the output clock CKO in the second time period CLK 2n.

Referring to FIG. 8B, the first frequency conversion circuit 110 may generate an output clock CKO having a relatively low first frequency and a relatively high second frequency. The first frequency signal may be a signal before the time point 42, and the second frequency signal may be a signal after the time point 42. In addition, the first frequency signal and the second frequency signal may be the low-frequency clock FIXH / L and the double-multiplied clock CLK 2n described in FIG. 8A, respectively.

Referring to FIG. 8B, the test logic 200 provides a command to instruct the synchronization of the frequency of the data signal DQ and the frequency of the output clock CKO at the time point 41 to the first frequency conversion circuit 110. Can be. When the first frequency conversion circuit 110 receives a command from the test logic 200, the first input clock CKIA and the second input clock CKIB are received after the time point 42 after the delay time tDLY. A second frequency signal calculated by XOR can be output.

Meanwhile, the test logic 200 may output the data signal DQ having the same or similar frequency to the second frequency signal to the device under test 300.

The device under test 300 may receive the output clock CKO as a signal for capturing the data signal DQ. For example, when the device under test 300 is GDDR, the output clock CKO can be received as a write clock (WCK according to the JEDEC standard), and when the device under test 300 is LPDDR, the output clock ( CKO) can be received as a data strobe signal (DQS according to the JEDEC standard). That is, the first frequency conversion circuit 110 may generate a first conversion clock CKX as a signal for capturing the data signal DQ by the device under test 300, and the first conversion clock CKX It may be output to the device under test 300 as an output clock CKO via the selection circuit 130.

9 is a data flow diagram for describing an input clock, an output clock, and data in a second frequency conversion circuit according to an embodiment of the present disclosure.

Referring to FIG. 9, the second frequency conversion circuit 120 may receive the first input clock CKIA and perform a phase lock operation to output a second conversion clock CKY multiplied by n times the frequency. The selection circuit 130 may receive the second conversion clock CKY and increase the amplitude to output the output clock CKO. That is, the phase of the output clock CKO illustrated in FIG. 9 may be the same as or similar to the phase of the second converted clock CKY.

Referring to FIG. 9, the second frequency conversion circuit 120 may take a certain locking time (tLOCK) while performing a phase lock operation, after which the second conversion clock multiplied by the first input clock CKIA An output clock CKO may be generated based on (CKY). Meanwhile, FIG. 9 illustrates an output clock CKO that multiplies the frequency of the first input clock CKIA by 4 times, but this is for convenience of description, and the second frequency conversion circuit 120 is multiplied by various multiples. It goes without saying that the output clock CKO can be output.

The device under test 300 may receive the output clock CKO as a signal for capturing the data signal DQ. For example, when the device under test 300 is GDDR, the output clock CKO can be received as a write clock (WCK according to the JEDEC standard), and when the device under test 300 is LPDDR, the output clock ( CKO) can be received as a data strobe signal (DQS according to the JEDEC standard). That is, the second frequency conversion circuit 120 may generate a second conversion clock (CKY) as a signal for capturing the data signal (DQ) by the device under test 300, and the second conversion clock (CKY) is It may be output to the device under test 300 as an output clock CKO via the selection circuit 130.

10 is a flowchart illustrating a method of generating an output clock for testing a semiconductor device according to an embodiment of the present disclosure.

In step S510, the socket board 100 may receive an input clock CKI from the test logic 200. In this case, the input clock CKI may include a first input clock CKIA and a second input clock CKIB, and may have phases shifted by 90 degrees from each other.

In step S530, the socket board 100 may output the first conversion clock CKX having the frequency of the input clock CKI increased. The first frequency conversion circuit 110 may output the first conversion clock CKX by performing an XOR operation on the first input clock CKIA and the second input clock CKIB, and output the first conversion clock CKX. The inverted first converted clock CKX 'can be output. That is, the first frequency conversion circuit 110 may multiply the input clock CKI by the first multiplication order to output the first conversion clock CKX. For example, the first multiplication order may include 2.

In step S550, the socket board 100 may output the second converted clock CKY in which the frequency of the input clock CKI is raised higher than the frequency of the first converted clock CKX. For example, since the first frequency conversion circuit 110 including the XOR gate can multiply the input frequency signal by 2 times, the second frequency conversion circuit 120 may be provided to multiply the frequency signal by a higher multiple. have. The second frequency conversion circuit 120 may receive the first input clock CKIA and multiply the frequency through a phase locked operation. In addition, the second frequency conversion circuit 120 multiplies the input clock (CKI) by a first multiplication order or more based on the oscillation signal generated by one of a plurality of voltage-controlled oscillators generating oscillation frequencies of different bands. can do.

 In step S570, the socket board 100 amplifies the first conversion clock CKX or the second conversion clock CKY according to the mode selection signal MSEL received from the test logic 200, and outputs the amplified signal. It can be output as a clock (CKO).

Meanwhile, since steps S530 and S550 are performed in the first frequency conversion circuit 110 and the second frequency conversion circuit 120, respectively, steps S530 and S550 can be performed independently. For example, step S530 may be performed after step S550, it may be performed in the reverse order, and step S530 and step S550 may be simultaneously performed.

11 is a flowchart illustrating in detail a method of generating an output clock for testing a semiconductor device according to an embodiment of the present disclosure. For convenience of description, overlapping with the contents described in FIG. 10 described above is omitted.

In step S520, the frequency conversion circuit may be divided into a first frequency conversion circuit 110 and a second frequency conversion circuit 120.

In step S530, the first frequency conversion circuit 110 receives the first input clock CKIA and the second input clock CKIB to perform an XOR operation, thereby performing the first input clock CKIA and the second input clock CKIB. The first conversion clock CKX having the frequency of R can be output.

In step S551, the second frequency conversion circuit 120 receives the oscillator selection signal OSEL, and may select one of the plurality of voltage controlled oscillators 126 according to the oscillator selection signal OSEL received in step S552. have. This is because the plurality of voltage controlled oscillators 126 can output different bands, respectively. Based on the frequency band that can be output by the voltage-controlled oscillator 126 selected in step S553, the second converted clock CKY higher than the frequency of the first converted clock CKX may be output.

In step S571, the socket board 100 may select the first conversion clock CKX or the second conversion clock CKY according to the received mode selection signal MSEL, and increase the amplitude of the conversion clock selected in step S572. And output as an output clock (CKO). For example, when the mode selection signal MSEL has a first value, the first conversion clock CKX output from the first frequency conversion circuit 110 may be output as the output clock CKO. As another example, when the mode selection signal MSEL has a second value, the second conversion clock CKY output from the second frequency conversion circuit 120 may be output as the output clock CKO.

12 is a diagram for describing a test system according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the socket board 100 may include a first frequency conversion circuit 110, a second frequency conversion circuit 120 and a selection circuit 130. That is, the socket board 100 may include a clock converter 107. The clock converter 107 may be included in each of the plurality of socket chips 105_1 to 105_N. The automatic test equipment (ATE) 210 may include a test logic 200.

The socket board 100 may be electrically connected to the test logic 200, and the socket board 100 may inspect the output clock CKO based on various signals received from the test logic 200, the device under test 300. Can be output as Although not shown, the socket board 100 may include pins for receiving various signals and voltages from the test logic 200 or transmitting them to the test logic 200, and the test logic 200 also includes a socket board ( It may include pins for receiving various signals and voltages from 100) or transmitting them to the socket board 100. This is omitted because it was previously described in FIG. 2. Similarly, the socket board 100 and the device under test 300 may each include pins for transmitting and receiving various signals and voltages.

Each of the at least one device under test 300 is electrically connected to the socket board 100 to receive the output clock CKO and the data DQ, respectively, and the data DQ is returned to the socket board 100. After that, it may be transmitted to the test logic 200.

 In accordance with embodiments of the present disclosure, when the test logic 200 tests the device under test 300, the socket board 100 uses the output clocks CKO of various frequency bands based on the input clocks CKI. It can be transmitted to the device under test 300. The socket board 100 selects any one of the conversion clocks CKX and CKY output from the first frequency conversion circuit 110 and the second frequency conversion circuit 120 based on the mode selection signal MSEL. ) To be transmitted to the device under test 300. If it is to test whether data DQ is normally transmitted / received in a high frequency band, an output clock CKO can be output by the second frequency conversion circuit 120, and whether data DQ is normally transmitted / received in a low frequency band. If it is to test whether or not, the output clock CKO may be output by the first frequency conversion circuit 110.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although embodiments have been described using specific terminology in this specification, they are only used for the purpose of describing the technical spirit of the present disclosure and are not used to limit the scope of the present disclosure as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

10: inspection system 100: socket board
110: first frequency conversion circuit 120: second frequency conversion circuit
200: inspection logic 300: device under test

Claims (20)

In the clock converter for outputting a clock signal for testing a semiconductor device,
A clock input terminal for receiving an input clock;
A first frequency conversion circuit that receives the input clock and outputs a first conversion clock in which the frequency of the input clock is increased by a fixed multiplication order;
A second frequency conversion circuit that receives the input clock and outputs a second conversion clock in which the frequency of the input clock is raised higher than the frequency of the first conversion clock by a variable multiplication order; And
And a selection circuit for outputting the first converted clock or the second converted clock according to the received mode selection signal. According to claim 1,
The input clock includes a first input clock and a second input clock,
The first frequency conversion circuit, the first input clock and the second input clock, and the second frequency conversion circuit, the clock converter, characterized in that for receiving the first input clock. According to claim 2,
Further comprising; a transmission line branching from said clock input terminal to said first frequency conversion circuit and said second frequency conversion circuit;
Each of the first frequency conversion circuit and the second frequency conversion circuit is a clock converter, characterized in that for receiving the first input clock via the branched transmission line. According to claim 2,
The first frequency conversion circuit outputs the first conversion clock by performing an XOR (Exclusive OR) operation on the first input clock and the second input clock,
The second frequency conversion circuit, on the basis of sensing the phase difference between the divided clock and the first input clock divided by feeding back the second converted clock, the clock converter, characterized in that for outputting the second converted clock . The method of claim 4,
The second frequency conversion circuit includes a voltage controlled oscillating unit, and the voltage controlled oscillating unit includes a plurality of voltage controlled oscillators,
The voltage controlled oscillator, a clock converter, characterized in that based on the received oscillator selection signal, provides an oscillation signal output from one of the plurality of voltage controlled oscillators. The method of claim 5,
The oscillator selection signal, the clock converter, characterized in that to activate at least one of the plurality of voltage-controlled oscillators, and to deactivate the rest. The method of claim 5,
The voltage-controlled oscillation unit further includes an oscillation voltage selection circuit,
The oscillation voltage selection circuit selects one of the oscillation signals received from the plurality of voltage-controlled oscillators based on the oscillator selection signal, and outputs a selected oscillation signal and an inverted signal of the selected oscillation signal. converter. According to claim 3,
The first converted clock includes a first converted clock and an inverted first converted clock,
The first converted clock is a frequency signal obtained by XORing the first input clock and the second input clock with each other. In the inverted first converted clock, the first frequency converter circuit determines the phase of the first converted clock. A clock converter characterized in that it is an inverted frequency signal. According to claim 1,
The first conversion clock includes a first time period and a second time period,
In the first time period, the first converted clock is a clock obtained by XORing a first input clock and a second input clock having a difference of 90 degrees from the phase of the first input clock,
In the second time period, the first conversion clock is a clock converter, characterized in that consisting of a DC signal. According to claim 1,
The clock converter further includes an input termination,
The input termination is connected to the clock input terminal and the first frequency conversion circuit in parallel, and the value of the input termination is a clock converter characterized in that the input impedance of the clock converter is a value designed to be impedance matched. According to claim 1,
The selection circuit includes a multiplexer circuit and an amplifier,
The multiplexer circuit receives the first conversion clock and the second conversion clock through the input terminal of the multiplexer circuit, receives the mode selection signal through the control terminal of the multiplexer circuit, and the first conversion clock or the And outputting a second converted clock to the amplifier, wherein the amplifier amplifies and outputs the inputted first converted clock or the second converted clock based on the driving voltage of the amplifier. A semiconductor test system for testing a semiconductor device,
Automatic test equipment including test logic that transmits and receives data for testing the semiconductor device, and outputs a mode selection signal having a different value according to a frequency band of an input clock and an output clock for testing the semiconductor device ( Automatic Test Equipment); And
And a socket board electrically connected to the automatic test equipment,
The socket board,
A clock input terminal receiving the input clock;
A first frequency conversion circuit that receives the input clock and outputs a first converted clock with an increased frequency of the input clock;
A second frequency conversion circuit that receives the input clock and outputs a second converted clock in which the frequency of the input clock is raised higher than the frequency of the first converted clock; And
And a clock converter including a selection circuit that outputs the output clock to the semiconductor device based on the first converted clock or the second converted clock according to the received mode selection signal. . The method of claim 12,
The socket board includes a plurality of socket chips,
A semiconductor test system, wherein at least one of the plurality of socket chips includes the clock converter. The method of claim 13,
The socket board further includes a clock input terminal of the socket board connected to the clock input terminal of the clock converter,
The first clock input terminal of the socket board is electrically connected to the first clock input terminal of the clock converter included in the first socket chip, and the second clock input terminal of the socket board is included in the second socket chip. A semiconductor test system, which is electrically connected to a second clock input terminal of a clock converter. The method of claim 13,
A semiconductor test system characterized in that the voltage level and signals input to the socket board are branched to the plurality of socket chips, and the voltage level and the signals control the clock converter included in at least one socket chip. . The method of claim 12,
The input clock includes a first input clock and a second input clock,
And wherein the first frequency conversion circuit receives the first input clock and the second input clock, and the second frequency conversion circuit receives the first input clock. A method for converting a clock signal for testing a semiconductor device,
Receiving an input clock;
Outputting a first conversion clock by multiplying the frequency of the input clock by a first multiplication order by a first frequency conversion circuit;
A second conversion by multiplying the input clock by more than the first multiplication order based on an oscillation signal output from one of a plurality of voltage-controlled oscillators generating oscillation frequencies of different bands by a second frequency conversion circuit Outputting a clock; And
And outputting the first converted clock or the second converted clock according to the received mode selection signal. The method of claim 17,
When the mode selection signal is a first value, the first conversion clock is selected to increase and output an amplitude. When the mode selection signal is a second value, the second conversion clock having a higher frequency than the first conversion clock is output. The method further comprising the step of selecting and increasing the amplitude. The method of claim 18,
The outputting of the second converted clock may include:
Receiving an oscillator selection signal; And
And selecting one of the plurality of voltage controlled oscillators included in the second frequency conversion circuit based on the oscillator selection signal. The method of claim 19,
The step of selecting one of the plurality of voltage controlled oscillators included in the second frequency conversion circuit is
Activating one of the plurality of voltage controlled oscillators based on the oscillator selection signal; And
And outputting an oscillation signal output from the activated voltage-controlled oscillator and an inverted signal of the oscillation signal.

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