KR20200045180A - Non-volatile memory device and method for fabricating the same - Google Patents

Abstract

Disclosed is a non-volatile memory element which can implement a transparent memory element having excellent performance. The non-volatile memory element comprises: a substrate; source/drain electrodes formed on the substrate to be spaced apart from each other; an oxide semiconductor thin film formed on the substrate between the source/drain electrodes to cover a part of each of the source/drain electrodes; a tunneling insulating film formed on the oxide semiconductor thin film; a charge accumulation film formed on the tunneling insulating film and accumulating a charge tunneled through the tunneling insulating film; a gate insulating film formed to cover the charge accumulation film; and a gate electrode formed on the gate insulating film. The charge accumulation film has a structure in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked.

Description

Non-volatile memory device and its manufacturing method {NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device using a charge accumulation film having a structure in which an oxide semiconductor layer and an insulator layer are stacked, and a method of manufacturing the same.

The charge injection type memory basically controls the turn-on voltage of the memory based on the process of restraining or releasing the charge through the tunneling phenomenon of charge by including an additional charge accumulation layer for charge injection in the gate stack. At this time, in general, the case where the current value is large is defined as 'ON, and the state where the current value is small is defined as' OFF. A lot of research has been conducted on charge-injection memory based on Si electronic device technology, but there is a difficulty in realizing high performance and high integration, so a new type of memory is needed.

As one alternative to this, a charge injection type memory having a charge accumulation layer composed of an oxide semiconductor and an insulator having a high dielectric constant in a stacked structure may be proposed. Oxide semiconductors have the advantage of being able to implement transparency, high mobility, and low temperature processes in the visible light region due to a wide band gap, and these advantages enable fast program characteristics and low voltage driving, and are easy to apply to transparent and flexible devices. Insulators having a high dielectric constant have high charge accumulation density and can increase the efficiency of accumulation due to inherent defects, and increase the electric field applied to the tunneling insulating film, thereby enabling fast program characteristics and low voltage driving. Therefore, when manufacturing a charge injection type nonvolatile memory having a charge accumulation layer based on a stacked structure of an oxide semiconductor and an insulator having a high dielectric constant, it can have many potentials as a next-generation memory.

Republic of Korea Patent No. 1498492 Japanese Patent Application Publication No. 2011-135107

An object of the present invention is to implement a transparent memory device having excellent performance by using a charge accumulation layer having a structure in which a semiconductor layer and an insulator thin film in which a conductivity is properly adjusted in a thin film transistor structure using an oxide are stacked in a predetermined order. It is to provide a non-volatile memory device and a method of manufacturing the same.

A nonvolatile memory device according to an embodiment of the present invention is formed on a substrate, a source / drain electrode formed spaced apart from each other on the substrate, and a substrate between the source / drain electrodes, and a part of each of the source / drain electrodes An oxide semiconductor thin film formed to cover, a tunneling insulating film formed on the oxide semiconductor thin film, a charge accumulation film formed on the tunneling insulating film and accumulating tunneled charge through the tunneling insulating film, formed to cover the charge accumulation film And a gate electrode formed on the gate insulating layer, and the charge accumulation layer may have a structure in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked.

Here, the substrate may be formed of a transparent material.

Here, the oxide semiconductor thin film may be formed of a transparent oxide semiconductor in the visible region.

Here, the oxide semiconductor thin film includes a channel region having a predetermined length, and the tunneling insulating layer may be formed on the channel region.

Here, the amount, speed and retention time of the information stored in the charge accumulation film are the conductive range of the at least one oxide semiconductor layer, the type and thickness of the at least one insulator layer, the at least one oxide semiconductor layer and the At least one insulator layer may be adjusted according to the number of inserts and the lamination structure.

Here, the at least one oxide semiconductor layer may have a carrier concentration of 1e14cm ^-3 to 1e18cm ^-3 .

Here, the at least one insulator layer may be formed of an insulator having an energy band gap of 4eV to 10eV.

Here, the at least one insulator layer is stacked twice on the charge accumulation film, and may have a thickness of 1.5 nm to 2.5 nm.

Here, the at least one insulator layer is stacked twice on the charge accumulation film, and may have a thickness of 3.5 nm to 4.5 nm.

Here, the at least one insulator layer is stacked four times on the charge accumulation layer, and may have a thickness of 1.5 nm to 2.5 nm.

Here, a pair of contact via holes formed through the gate insulating film so that the source / drain electrodes are exposed, and a source / drain electrode formed to fill the pair of contact via holes and connected to the source / drain electrodes It may further include a pad.

A nonvolatile memory device according to another embodiment of the present invention is formed in a substrate, a gate electrode formed on the substrate, a gate insulating film formed to cover the gate electrode, and formed in a groove formed in an upper surface of the gate insulating film and tunneled. A charge accumulation film accumulating charge, a tunneling insulation film formed on the gate insulating film and the charge accumulation film, a source / drain electrode formed spaced apart from each other on the tunneling insulating film, and a tunneling insulating film between the source / drain electrodes The oxide semiconductor thin film is formed to cover a portion of each of the source / drain electrodes, and a protective insulating film formed on the oxide semiconductor thin film. The oxide semiconductor thin film includes a channel region having a predetermined length. The width of the charge accumulation film is equal to the length of the channel region, and at least one or more Luggage at least one insulator layer and the semiconductor layer may have a structure of alternately laminated.

Here, the substrate is formed of a transparent material, and the oxide semiconductor thin film may be formed of a transparent oxide semiconductor in the visible light region.

Here, the amount, speed and retention time of the information stored in the charge accumulation film are the conductive range of the at least one oxide semiconductor layer, the type and thickness of the at least one insulator layer, the at least one oxide semiconductor layer and the At least one insulator layer may be adjusted according to the number of inserts and the lamination structure.

Here, the at least one insulator layer is stacked twice on the charge accumulation film, and may have a thickness of 1.5 nm to 2.5 nm.

Here, the at least one insulator layer is stacked twice on the charge accumulation film, and may have a thickness of 3.5 nm to 4.5 nm.

Here, the at least one insulator layer is stacked four times on the charge accumulation layer, and may have a thickness of 1.5 nm to 2.5 nm.

A method of manufacturing a nonvolatile memory device according to an embodiment of the present invention includes forming a source / drain electrode spaced apart from each other on a substrate, and a substrate between the source / drain electrodes to cover a portion of each of the source / drain electrodes Forming an oxide semiconductor thin film on the oxide film, forming a tunneling insulating film on the oxide semiconductor thin film, forming a charge accumulation film accumulating tunneled charges on the tunneling insulating film, and forming the oxide semiconductor thin film. , Etching the tunneling insulating layer and the charge accumulation layer in the same pattern, forming a gate insulating layer to cover the source / drain electrode and the charge accumulation layer, and forming a gate electrode on the gate insulating layer, The forming of the accumulation film may include at least one oxide semiconductor layer and Even may be alternately laminated in at least one insulating layer to form the charge storage film.

Here, the step of forming the charge accumulation layer may control the number of cycles of the atomic layer deposition (ALD) to control the thickness and the number of stacks of the at least one oxide semiconductor layer and the at least one insulator layer. .

Here, forming a pair of contact via holes exposing the source / drain electrodes by etching the gate insulating layer, and filling the pair of contact via holes, and a source / drain electrode connected to the source / drain electrodes The method may further include forming a pad.

A method of manufacturing a nonvolatile memory device according to another embodiment of the present invention includes forming a gate electrode on a substrate, forming a gate insulating film to cover the gate electrode, and etching the upper surface of the gate insulating film to form a groove. Forming, forming a charge accumulation film accumulating tunneled charges in the groove, forming a tunneling insulation film on the gate insulating film and the charge accumulation film, and separating source / drain electrodes on the tunneling insulation film from each other Forming, forming an oxide semiconductor thin film on the tunneling insulating film between the source / drain electrodes to cover a portion of each of the source / drain electrodes, and forming a protective insulating film on the oxide semiconductor thin film, , The step of forming the charge accumulation film may be performed with at least one oxide semiconductor layer. Also it is possible to form the charge storage film are stacked alternately with at least one insulation layer.

Here, the oxide semiconductor thin film includes a channel region having a predetermined length, and the width of the charge accumulation layer may be the same as the length of the channel region.

Here, the step of forming the charge accumulation layer may control the number of cycles of the atomic layer deposition (ALD) to control the thickness and the number of stacks of the at least one oxide semiconductor layer and the at least one insulator layer. .

According to an embodiment of the present invention, a transparent memory device having excellent performance is obtained by using a charge accumulation film having a stacked structure composed of an oxide semiconductor layer having appropriately controlled conductivity and an insulator layer having a high dielectric constant in a thin film transistor structure using all oxides. Can be implemented.

1 is a cross-sectional view of a nonvolatile memory device according to a first embodiment of the present invention.
2A is a cross-sectional view showing the structure of a charge accumulation film layer according to a first derivative embodiment derived from the first embodiment of the present invention.
2B is a cross-sectional view showing the structure of a charge accumulation film layer according to a second derivative embodiment derived from the first embodiment of the present invention.
2C is a cross-sectional view showing the configuration of a charge accumulation film layer according to a third derivative embodiment derived from the first embodiment of the present invention.
3 is a cross-sectional view of a nonvolatile memory device according to a second embodiment of the present invention.
4 is a conceptual diagram illustrating a band structure when a positive program voltage is applied to a gate electrode of a nonvolatile memory device according to an embodiment of the present invention.
5 is a conceptual diagram illustrating a band structure when a negative program voltage is applied to a gate electrode of a nonvolatile memory device according to an embodiment of the present invention.
6A to 6C are graphs illustrating gate voltage-drain current characteristics of nonvolatile memory devices according to the first embodiment of the present invention and embodiments derived therefrom.
7 is a graph illustrating on / off programming characteristics of nonvolatile memory devices according to a first embodiment of the present invention and embodiments derived therefrom through various program voltages.
8 is a TEM image showing a structure of a charge accumulation layer of nonvolatile memory devices according to the second and third derivatives derived from the first embodiment of the present invention.
9A to 9E are intermediate step views illustrating a method of manufacturing the nonvolatile memory device shown in FIG. 1.
10A and 10B are intermediate step views illustrating a method of manufacturing the nonvolatile memory device shown in FIG. 3.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are exemplified only for the purpose of illustrating the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention These can be implemented in various forms and are not limited to the embodiments described herein.

Embodiments according to the concept of the present invention can be applied to various changes and can have various forms, so that the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosure forms, and includes changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be referred to as the second component, Similarly, the second component may also be referred to as the first component.

When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle. Expressions describing the relationship between the elements, for example, "between" and "immediately between" or "directly neighboring to" should also be interpreted.

The terminology used herein is only used to describe specific embodiments and is not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "include" or "have" are intended to designate the presence of a feature, number, step, action, component, part, or combination thereof as described, one or more other features or numbers, It should be understood that the existence or addition possibilities of steps, actions, components, parts or combinations thereof are not excluded in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms such as those defined in a commonly used dictionary should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined herein. Does not. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a nonvolatile memory device according to a first embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device 1 according to an embodiment of the present invention includes a substrate 100, a source / drain electrode 102, an oxide semiconductor thin film 104, a tunneling insulating film 106, and charge accumulation It includes a film 108, a gate insulating film 110, a gate electrode layer 114 and a source / drain electrode pad 112. Meanwhile, in FIG. 1, an upper gate structure in which the gate electrode is positioned above the channel region will be described as an example, but the present invention is not limited thereto, and a lower gate structure may also be manufactured. A detailed description of the lower gate structure will be described later through other embodiments.

The substrate 100 may include a transparent substrate. More specifically, the substrate 100 is a flexible substrate or a flexible substrate that can be bent, and may include a glass substrate or a flexible substrate.

The source / drain electrodes 102 are formed to be spaced apart from each other in the first direction X on the substrate 100. More specifically, the source / drain electrodes 102 are formed to be spaced apart from each other in the first direction X on the substrate 100, so that the source electrode and the drain electrode may be respectively formed in electrically separated regions. In addition, the length of the first direction X of the channel region (not shown) may be determined by the distance between the source / drain electrodes 102.

The source / drain electrode 102 may be formed of a conductive oxide thin film or a conductive organic thin film. For example, the conductive oxide thin film may include, but is not limited to, a material having high conductivity and sufficient transparency characteristics similar to that of the conductive oxide material, indium-tin oxide (ITO) or ITO.

Further, according to the characteristics required by the application system of the nonvolatile memory device 1 according to an embodiment of the present invention, it may be formed of a metal thin film used in the manufacture of a conventional thin film transistor. In the metal thin film, for example, to reduce the resistance of the electrode itself, aluminum (Al), titanium (Ti), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), Yttrium (Y), Zirconium (Zr), Niobium (Nb), Ruthenium (Ru), Palladium (Pd), Silver (Ag), Lanthanum (La), Hafnium (Hf), Tantalum (Ta) , Tungsten (W), platinum (Pt), gold (Au), erbium (Er), yttrium (Y), ytterbium (Yb), or a combination thereof, may be a metal having a low specific resistance, but in this embodiment It is not limited.

Further, the metal layer may be a metal nitride. The metal nitride may be a material in which metal / metalloid elements and nitrogen are combined at a constant composition ratio, such as tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), and tungsten nitride (WN).

The oxide semiconductor thin film 104 is formed on the substrate 100 between the source / drain electrodes 102 and includes a channel region having a predetermined length. More specifically, a portion of the oxide semiconductor thin film 104 may contact the substrate 100 and the other portion may contact a portion of the source / drain electrode 102. That is, both ends of the oxide semiconductor thin film 104 may be formed to cover a portion of the source / drain electrodes 102. This is because the oxide semiconductor thin film 104 is formed to cover the source / drain electrodes 102 and then patterned through an etching process. Detailed description thereof will be described later.

Since the oxide semiconductor thin film 104 has a wide energy band gap, it is preferable to be formed of a transparent oxide semiconductor thin film which is transparent in the visible light region and has semiconductor properties. For example, the oxide semiconductor thin film 104 is formed of zinc oxide (ZnO), indium-gallium-zinc oxide (In-Ga-Zn-O), zinc-tin oxide (Zn-Sn-O), or zinc ( Zn), indium (In), gallium (Ga), tin (Sn), or aluminum (Al). Alternatively, the oxide semiconductor thin film 104 may be formed by doping various elements on the aforementioned oxide. The oxide semiconductor thin film 104 is preferably formed at a temperature of 200 ° C or lower.

In addition, the upper portion of the oxide semiconductor thin film 104 may include a channel region, but is not limited thereto, and the entire oxide semiconductor thin film 104 may be a channel region in actual driving.

The tunneling insulating film 106 is formed on the oxide semiconductor thin film 104. More specifically, the tunneling insulating film 106 may be formed on the channel region between the source / drain electrodes 102 on the oxide semiconductor thin film 104. The tunneling insulating film 106 basically serves as a tunneling operation in which electrons of the oxide semiconductor thin film 104 are injected into the charge accumulation film 108 or vice versa in the operation of the charge injection type memory device. In addition, in a subsequent process after the formation of the tunneling insulating film 106, it may prevent physical or chemical damage of the oxide semiconductor thin film 104 and may serve as a protective insulating film that improves properties.

The tunneling insulating film 106 may be formed of an oxide insulating film having excellent insulating properties, and the thickness of the tunneling insulating film 106 in the second direction Y may include data retention or program / erase characteristics of the memory device. It can be formed in various thicknesses in consideration. Preferably, it can be formed within 10 nm in view of tunneling efficiency. Further, the tunneling insulating film 106 is formed of a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (HfO) ₂ ), zirconium oxide (ZrO ₂ ), magnesium oxide (MgO), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lanthanum oxide (La ₂ O ₃ ), strontium-titanium oxide (SrTiO ₃ ) Can be formed. Alternatively, the tunneling insulating film 106 may be formed of a silicate insulating film in which silicon and metal elements constituting the aforementioned oxide are mixed. Of course, in the manufacture of a typical thin film transistor, the tunneling insulating film 106 may be formed of insulating film materials that can be used as a gate insulating film material.

The charge accumulation film 108 is formed on the tunneling insulating film 106 and is characterized by having a stacked structure of an oxide semiconductor layer and an insulator layer. More specifically, the charge accumulation film 108 is formed on the tunneling insulating film 106 and may have a width corresponding to the channel region of the oxide semiconductor thin film 104. That is, the width of the first direction X of the charge accumulation film 108 may coincide with the width of the first direction X of the channel region. This is because the oxide semiconductor thin film 104, the tunneling insulating film 106, and the charge accumulation film 108 are continuously deposited and then etched into a pattern having a size corresponding to the same region at a time. Detailed description thereof will be described later.

The charge accumulation film 108 may be formed to contact the tunneling insulating film 106. That is, the charge accumulation film 108 is formed on the tunneling insulating film 106 and may be formed to be in direct contact.

In addition, the charge accumulation film 108 may be formed of a stacked structure of the same composition as the oxide semiconductor thin film 104 and the tunneling insulating film 106 described above, in which case, in the case of the oxide semiconductor layer, excellent performance of a nonvolatile memory device is realized. In order to have a suitable conductivity. That is, the charge accumulation film 108 has a structure in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked.

With respect to proper conductivity, in the case of the oxide semiconductor layer constituting the stacked structure of the charge accumulation film 108, the range of suitable carrier concentration may be 1e14 cm-3 or more to 1e18 cm-3 or less, but is not limited thereto. In addition, the charge accumulation film 108 may be composed of the same composition as the oxide semiconductor thin film 104, and may have an energy band gap of 3 to 4 eV, and electrons are injected into a deep level inside the energy band gap. Information can be stored.

In addition, in the case of an insulator layer constituting the stacked structure of the charge accumulation film 108, the dielectric layer having a high dielectric constant (Al ₂ O ₃ ), a hafnium oxide film (HfO ₂ ), and the like may be composed of the same composition as the tunneling insulating film 106 However, it is not limited to a metal oxide of a specific element. The insulator layer can also store information by injecting electrons at a deep level of the energy bandgap, where the energy bandgap of the insulator layer can be 4eV to 10eV. The amount, speed, and retention time of the stored information are variously adjusted according to the conductive range of the oxide semiconductor layer constituting the charge accumulation film 108, the type and thickness of the insulator layer, the number of inserts, and the stacked structure of the oxide semiconductor layer and the insulator layer. Can be.

The gate insulating layer 110 is formed to cover the charge accumulation layer 108. More specifically, the gate insulating layer 110 may be formed to surround the charge accumulation layer 108 on the charge accumulation layer 108. Further, the gate insulating layer 110 may be made of the same material as the tunneling insulating layer 106 described above.

The gate insulating layer 110 may also serve as a blocking oxide layer and also a passivation role. That is, it is possible to prevent the carrier from being tunneled or moved from the charge accumulation film 108 to the gate electrode 114, and to protect the charge accumulation film 108 from external impact. Therefore, the gate insulating layer 110 plays a large role in improving the performance of the nonvolatile memory device in an environmental aspect.

The source / drain electrode pad 112 is formed to pass through the gate insulating layer 110 and is formed to fill the contact via hole H exposing the source / drain electrode 102. That is, the source / drain electrode pad 112 is formed to fill the contact via hole H, so that it can be electrically connected to the source / drain electrode.

In addition, the source / drain electrode pad 112 may be formed of the same material as the source / drain electrode 102 described above, but is not limited thereto.

The gate electrode 114 is formed on the gate insulating layer 110. More specifically, the gate electrode 114 is formed on the gate insulating layer 110 and may be formed in a form aligned with the charge accumulation layer 108.

In addition, the gate electrode 114 may be formed of a conductive oxide thin film or a conductive organic thin film, or may be formed of a metal thin film used in the manufacture of conventional thin film transistors. That is, the gate electrode 114 may be made of the same material as the source / drain electrode 102 described above, but is not limited thereto.

The nonvolatile memory device 1 according to an embodiment of the present invention can be manufactured through a structurally simplified process, and by appropriately designing a stacked structure constituting the charge accumulation film 108 proposed in the present invention, It can have improved performance. That is, since the oxide semiconductor thin film 104, the tunneling insulating film 106, and the charge accumulation film 108 are successively deposited, they can be simultaneously formed in a size corresponding to the same region through one patterning process, resulting in charge accumulation. Except for the additional deposition process of the film 108, it is possible to manufacture in almost the same number of processes as the conventional thin film transistor of the upper gate structure, and by appropriately controlling the stacked structure of the charge accumulation film 108, the energy band gap of the charge accumulation film And the amount, speed, and retention time of information stored at the interface of the layered structure.

Hereinafter, with reference to FIGS. 2A to 2C, a description will be given of a method of configuring a charge accumulation film layer according to some embodiments of the present invention. A detailed description of the content overlapping with the above-described embodiment will be omitted.

2A to 2C, it can be seen that the stacked structure of the oxide semiconductor thin film and the insulator thin film constituting the charge accumulation film layer of the present invention can be variously configured.

2A is a cross-sectional view showing the structure of a charge accumulation film layer according to a first derivative embodiment derived from the first embodiment of the present invention.

Referring to FIG. 2A, the first derivative embodiment includes an oxide semiconductor layer 108a and an insulator layer 108b as the charge accumulation film 108.

Here, the oxide semiconductor layer may include zinc oxide (ZnO), indium gallium zinc oxide (IGZO), etc., and the insulator layer may include hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon oxide ( SiO ₂ ), silicon oxynitride (SiON), silicon nitride (SiNx), and the like may be included, but the materials used are not limited to those specified above.

In the first derivative embodiment, an insulator layer having a thickness of 1.5 nm to 2.5 nm inside the charge accumulation film of 20 nm to 30 nm may enter the oxide semiconductor layer twice or less. Accordingly, since the proportion of the oxide semiconductor layer is larger than that of the insulator layer in the charge accumulation film, the influence of the oxide semiconductor layer in the process of storing and removing information by charge injection is greater.

2B is a cross-sectional view showing the structure of a charge accumulation film layer according to a second derivative embodiment derived from the first embodiment of the present invention.

Referring to FIG. 2B, an insulator layer having a thickness of 1.5 nm to 2.5 nm inside the charge accumulation film of 20 nm to 30 nm may enter the oxide semiconductor layer four or more times.

2C is a cross-sectional view showing the configuration of a charge accumulation film layer according to a third derivative embodiment derived from the first embodiment of the present invention.

Referring to Figure 2c, a thick insulator layer of 3.5nm to 4.5nm inside the charge accumulation film of 20nm to 30nm may enter the oxide semiconductor layer more than once. At this time, the distance between the insulator layer and the oxide semiconductor layer is kept constant.

Hereinafter, a nonvolatile memory device according to a second embodiment of the present invention will be described with reference to FIG. 3. Details overlapping with the above-described embodiments will be omitted.

3 is a cross-sectional view of a nonvolatile memory device according to a second embodiment of the present invention.

Referring to FIG. 3, it can be seen that the nonvolatile memory device 3 according to the second embodiment of the present invention is a non-volatile memory device having a lower gate structure, unlike the nonvolatile memory device 1 of FIG. 1.

The non-volatile memory device 3 having a lower gate structure includes a substrate 100, a gate electrode 214, a gate insulating film 210, a charge accumulation film 208, a tunneling insulating film 216, a source / drain electrode 202, It includes an oxide semiconductor thin film 204, a protective insulating film 206, a gate electrode pad and a contact via hole not shown in FIG.

The gate electrode 214 is formed on the substrate 100. More specifically, the gate electrode 214 is formed on the substrate 100 and may be formed of a conductive oxide electrode or a conductive organic electrode having transparent properties in visible light. In addition, the region where the gate electrode 214 is formed may be patterned based on the channel region, and may include the same material as the gate electrode of the nonvolatile memory device 1.

The gate insulating layer 210 is formed to cover the gate electrode 214. More specifically, the gate insulating layer 210 is formed on the gate electrode 214 to serve as a blocking oxide layer. Also, the gate insulating layer 210 may be formed of an oxide insulating layer or an organic insulating layer having transparent properties in visible light. That is, the same material as the gate insulating film of the nonvolatile memory device 1 may be included.

The charge accumulation layer 208 is formed on the gate insulating layer 210. More specifically, the charge accumulation layer 208 may be formed to be surrounded by the gate insulating layer 210, and the first direction (the same as the first direction X width) of the channel region included in the oxide semiconductor thin film 204 ( X) can have a width. Further, the charge accumulation film 208 may include the same material as the charge accumulation film of the nonvolatile memory device 1, and may be formed to have the appropriate conductivity described above.

The tunneling insulating film 216 is formed on the charge accumulation film 208. More specifically, the tunneling insulating film 216 is formed on the charge accumulation film 208 and the gate insulating film 210, and in the second direction (Y) to induce an appropriate tunneling phenomenon of charges when driving the nonvolatile memory device. The thickness can be comprised between 4 nm and 10 nm. In addition, the same material as the tunneling insulating film of the nonvolatile memory device 1 may be included.

Although the gate electrode pad is not illustrated in FIG. 3, a contact via hole (not shown) penetrating through the tunneling insulating layer 216 and the gate insulating layer 210 may be formed. In addition, the gate electrode pad may be connected to the gate electrode 214 by being formed to fill in a contact via hole (not shown).

The source / drain electrodes 202 are formed to be spaced apart in the first direction X on the tunneling insulating layer 216. More specifically, the source / drain electrode 202 is formed to be spaced apart in the first direction X on the tunneling insulating layer 216, and may include the same material as the source / drain electrode of the nonvolatile memory device 1. have.

The oxide semiconductor thin film 204 is formed on the tunneling insulating layer 216 between the source / drain electrodes 202 and includes a channel region. More specifically, a portion of the oxide semiconductor thin film 204 may contact the tunneling insulating layer 216 and the other portion may contact a portion of the source / drain electrode 202. That is, both ends of the oxide semiconductor thin film 204 may be formed to cover a portion of the source / drain electrodes 202. In addition, the oxide semiconductor thin film 204 may include the same material as the oxide semiconductor thin film of the nonvolatile memory device 1.

The protective insulating film 206 is formed on the oxide semiconductor thin film 204. More specifically, the protective insulating layer 206 may be formed on the channel region between the source / drain electrodes 202 on the oxide semiconductor thin film 204. In addition, the protective insulating layer 206 may include the same material as the tunneling insulating layer of the nonvolatile memory device 1.

Hereinafter, with reference to FIGS. 4 and 5, the movement of a carrier when a positive or negative program voltage is applied to a gate electrode of a nonvolatile memory device according to some embodiments of the present invention will be described.

4 is a conceptual diagram illustrating a band structure when a positive program voltage is applied to a gate electrode of a nonvolatile memory device according to some embodiments of the present invention, and FIG. 5 is a nonvolatile memory according to some embodiments of the present invention This is a conceptual diagram illustrating a band structure when a negative program voltage is applied to the gate electrode of the device.

The amount of charge injected into the charge accumulation film by the program voltage applied to the gate electrode is the size of the barrier height formed between the tunneling insulation film and the charge accumulation film and the tunneling insulation film (or nonvolatile memory device 1 or nonvolatile memory device) The protective insulating film of (3); hereinafter referred to as a tunneling insulating film) will vary depending on the thickness of itself. Assuming that the tunneling insulating film has a sufficient barrier height and an appropriate thickness of 10 nm or less, the possibility of tunneling movement of electric charges may depend on the structure of a charge accumulation film composed of a stacked structure of an oxide semiconductor layer and an insulator layer. Basically, an oxide semiconductor and an insulator, which are N-type semiconductor materials, have a unique band structure. The majority of electrons inherent in the oxide semiconductor mostly exist in a shallow level state, and there are many defects in a deep level state. Insulators have inherent defects in the shallow and deep level states within the bandgap.

Therefore, referring to FIG. 4, when a positive program voltage is applied to the gate electrode due to this unique band structure, electrons tunneled through the tunneling insulating film 302 from the oxide semiconductor thin film 300 are charged accumulation film 304. Is injected into the deep level state 308 of the oxide semiconductor layer constituting or the shallow level state 306 of the insulator constituting the charge accumulation film 304. This state is defined as a memory off (off) state.

On the other hand, referring to FIG. 5, when a negative program voltage is applied to the gate electrode, intrinsic electrons existing in the shallow level state 326 and deep level state 328 inside the charge accumulation film are easily charged. Tunneled through the tunneling insulating film 322 from 324) is a memory on (on) state. Here, the charge storage capacity may be changed by changing the composition and type of the oxide semiconductor layer and the insulator layer constituting the charge accumulation film 324, and the memory characteristics may be changed according to the stacked structure constituting the charge accumulation film 324. It can lead to change. That is, the performance of the nonvolatile memory device according to some embodiments of the present invention may be determined by adjusting the stacked structure of the charge accumulation layer 324.

In this regard, the effect of the stacked structure of the charge accumulation film on the memory performance can be explained by dividing it into the following three cases. Each case corresponds to the first derived embodiment, the second derived embodiment, and the third derived embodiment derived from the first embodiment.

The first case referring to the first derived embodiment is a case in which an insulator, which is one of elements constituting the charge accumulation film, has a relatively thin thickness of about 1.5 nm to 2.5 nm and enters twice or less. When the program voltage is applied to the gate electrode in a state where the thin insulator is less than twice, the insulator is very thin and difficult to act as a charge accumulation film, but rather, it can act as a disturbance factor, thereby deteriorating the charge accumulation capability. However, since the ratio of the insulator to the total charge accumulation film is very small, the effect on the overall memory performance is not large. Since the thin insulating film is less in the entire charge accumulation film, the oxide semiconductor occupies a relatively large proportion, and thus the influence of the oxide semiconductor layer constituting the charge accumulation film in the information storage process by charge injection is large.

When a positive program voltage is applied to the gate electrode in a state where the conductivity of the oxide semiconductor is appropriate, electrons flowing inside the oxide semiconductor thin film are injected into a deep level state inside the charge accumulation film without a large resistance element. In addition, since the injected charge is effectively injected into a deep state, stored information can be maintained for a long time.

In addition, when a negative program voltage is applied to the gate electrode in a state where the conductivity of the charge accumulation film is appropriate, intrinsic electrons in an appropriate amount of shallow level state can be tunneled into the oxide semiconductor thin film to obtain sufficient memory characteristics. As a result, excellent memory performance can be obtained due to the proper conductivity of the oxide semiconductor.

The second case, referring to the second derivative, is a case in which an insulator, one of elements constituting the charge accumulation film, has a relatively thin thickness of about 1.5 nm to 2.5 nm and has been entered more than four times. When the program voltage is applied to the gate electrode in a state in which a thin insulator has been entered more than four times, the insulator is very thin, which makes it difficult to act as a charge accumulation film, and may act as a disturbance factor. This has the effect of not only storing the charge, but also preventing the movement of the charge, causing a decrease in program speed. Therefore, the more the thin-walled insulator enters, the higher the proportion of the insulator that prevents the accumulation of charges with respect to the entire charge accumulation film increases, so the performance of the memory device deteriorates.

 The third case, referring to the third derivative, is a case in which an insulator, which is one of elements constituting the charge accumulation film, has a relatively thick thickness of 3.5 nm to 4.5 nm and is entered more than once. When the program voltage is applied to the gate electrode in a state where the thick insulator is twice, the insulator has a sufficient trap density to improve the charge accumulation ability. Although the rate of charge transfer in the insulator is slower than that of the oxide semiconductor, the program speed is relatively slow, but the impact on overall memory performance is not large. Therefore, a memory property having excellent charge storage capability can be obtained by inserting an insulator of sufficient thickness into an oxide semiconductor and a stacked structure.

That is, as described above, in the case of a nonvolatile memory device according to some embodiments of the present invention, by applying a stacked structure of an oxide semiconductor having an appropriate conductivity and an insulator having a high dielectric constant, a charge accumulation film is formed, so that it is nonvolatile In the process of driving the memory device, not only can the efficiency of charge injection be improved, but also the ability to maintain the injected charge for a long time can be improved.

Hereinafter, gate voltage-drain current characteristics of nonvolatile memory devices according to some embodiments of the present invention will be described with reference to FIGS. 6A to 6C.

< Experimental example >

6A to 6C are graphs illustrating gate voltage-drain current characteristics of nonvolatile memory devices according to the first embodiment of the present invention and embodiments derived therefrom.

First, test conditions for the gate voltage (VGS) -drain current (IDS) characteristics shown in FIGS. 6A to 6C are as follows.

A fixed voltage of 0.5 V (VDS) is applied to the drain terminal, and sweep voltages of -10 V to +10 V, -15 V to +15 V, -20 V to +20 V, and -25 V to +25 V to the gate terminal ( VGS) to evaluate the gate voltage-drain current characteristics.

First, the substrate uses a glass substrate, and the source / drain electrode uses an ITO thin film having a thickness of 150 nm. As the oxide semiconductor thin film, a 16 nm thick indium-gallium-zinc oxide (In-Ga-Zn-O) thin film formed by a sputtering method is used, and the tunneling insulating film serving as a tunneling insulating film has a temperature of 180 ° C by atomic layer deposition. The aluminum oxide film (Al ₂ O ₃ ) having a thickness of 5 nm was used. As the charge accumulation film, a layered structure is used such that zinc oxide (ZnO) and hafnium oxide (HfO ₂ ) are 22 nm in total by atomic layer deposition. At this time, ₂ nm or 4 nm of hafnium oxide (HfO ₂ ) between zinc oxide is configured to enter once, twice, or four times, and the distance between zinc oxide (ZnO) and hafnium oxide (HfO ₂ ) is controlled to be constant. In addition, a 50 nm thick aluminum oxide film (Al ₂ O ₃ ) formed at a temperature of 150 ° C. by an atomic layer deposition method is used as the gate insulating film, and the photoresist is etched by etching the gate insulating film to form a contact via hole. A wet etching process used as a mask can be applied. A 150 nm thick indium tin oxide thin film is used as the gate electrode and the source / drain electrode pad, and the gate electrode and the source / drain electrode pad can be formed by sputtering.

Here, as the elements used for measuring the gate voltage-drain current characteristic, any one of the nonvolatile memory elements according to some embodiments of the present invention described above may be applied.

Hereinafter, three nonvolatile memory elements having charge accumulation films of different structures will be described as an example in order to check characteristics according to the stacked structure of the charge accumulation film.

First, since the three nonvolatile memory devices (first derived embodiment, second derived embodiment, and third derived embodiment) each have a charge accumulation film having a different structure, each charge accumulation film is respectively shown in FIGS. 2A to 2C. As specified in, a 2 nm hafnium oxide (HfO ₂ ) film is included twice, four times, or a 4 nm hafnium oxide film twice. That is, each of the non-volatile memory devices manufactured under these three conditions is the first derived embodiment (device 1: contains hafnium oxide film twice 2 nm), and the second derived embodiment (device 2: includes hafnium oxide film 2 nm four times) , 3rd derivative example (device 3: hafnium oxide film 4nm twice included).

Referring to FIGS. 6A to 6C for the experimental example, the first, second, and third derivatives are clockwise hysteresis curves when sweeping the gate voltage VGS. ①-> ②), and it can be seen that the operating voltage width (width in the horizontal direction) increases as the gate voltage increases. Through this, the successful operation of the nonvolatile memory device through the Fowler-Nordheim tunneling process was confirmed. In addition, the operating voltage width was greater as the hafnium oxide film was thicker (third derivative) and less when the hafnium oxide film was thin (first derivative). This means that the hafnium oxide film acts as a sufficient charge accumulation film when it is thickly introduced at 4 nm or more.

Hereinafter, on / off programming characteristics of nonvolatile memory devices according to some embodiments of the present invention will be described with reference to FIG. 7 through various program voltages.

7 is a graph illustrating on / off programming characteristics of nonvolatile memory devices according to a first embodiment of the present invention and embodiments derived therefrom through various program voltages.

The test conditions for the gate voltage (VGS) -drain current (IDS) characteristic shown in FIG. 7 are as follows.

A program voltage characteristic according to the pulse length is evaluated under the condition that a fixed voltage of 0.1 V (VDS) is applied to the drain terminal and a pulse of -20 V or +20 V is applied to the gate terminal.

In addition, to test the on / off programming characteristics, the on / off program voltage was applied to + 20V and -20V for 1us, 10us, 100us, 500us, 1ms, 10ms, 100ms, 200ms, 500ms, and 1s, respectively, and then the read voltage Drain current IDS was obtained by applying 0 V to the gate electrode and 0.1 V to the drain electrode, respectively.

When the same size and width of the on / off program voltage were applied to the gate electrode, it can be seen that there is a large difference in program characteristics according to the three types of devices manufactured according to each derivative. The program speed was found to be fast in the order of the first derived embodiment (Device1), the third derived embodiment (Device3), and the second derived embodiment (Device2). In addition, it can be seen that a memory on / off current ratio of up to 1e8 or more can be obtained. As a result, in terms of memory program characteristics, the speed is fastest when a thin hafnium oxide (HfO ₂ ) film is put in, but it can be seen that all three devices perform successfully.

Hereinafter, with reference to FIG. 8, a TEM image of a charge accumulation film of nonvolatile memory devices according to some derivative embodiments of the present invention will be described.

8 is a TEM image showing a structure of a charge accumulation layer of nonvolatile memory devices according to the second and third derivatives derived from the first embodiment of the present invention.

Referring to FIG. 8, it can be seen that both devices have a charge accumulation film having a stacked structure of a hafnium oxide (HfO ₂ ) film and a zinc oxide (ZnO) film having uniform and clean interfaces. The hafnium oxide (HfO ₂ ) film included in the charge accumulation film of Device 2 has a thickness of about 2 nm and is contained 4 times inside the charge accumulation film with a total thickness of 22 nm. The hafnium oxide (HfO ₂ ) film included in the charge accumulation film of Device 3 has a thickness of about 4 nm, and is twice inside the charge accumulation film of a total thickness of 22 nm. Therefore, it can be confirmed that the layered structure of the charge accumulation film is well controlled. In addition, it can be seen that the difference in electrical characteristics of the devices arises from the difference in the structure of the charge accumulation film.

As described above, looking at the characteristics of the nonvolatile memory devices according to some embodiments of the present invention, it can be seen that the program characteristics can be controlled as well as the basic gate voltage-drain current characteristics of the memory transistor according to the structure of the charge accumulation layer. Able to know. More specifically, the characteristics of the memory transistor may be controlled according to the thickness and number of times the hafnium oxide (HfO2) film is contained in the zinc oxide (ZnO). If the hafnium oxide (HfO ₂ ) film of too thin 1.5nm to 2.5nm enters more than 4 times, the hafnium oxide (HfO ₂ ) film acts as an insulator and can act as an element that interferes with the basic operation of the memory transistor. And program characteristics. On the other hand, it can be seen that a hafnium oxide (HfO ₂ ) film of an appropriate thickness has a sufficient charge accumulation density and thus has a key effect on a wide operating voltage width and sufficient memory on / off program characteristics. As described above, these results can be secured by providing a nonvolatile memory device comprising a stacked structure using an oxide semiconductor having a controlled conductivity and an insulator having a high dielectric constant and a method of manufacturing the same.

Hereinafter, a method of manufacturing the nonvolatile memory device of FIG. 1 will be described with reference to FIGS. 9A to 9E. Hereinafter, contents overlapping with those described in FIG. 1 will be omitted.

9A to 9E are intermediate step views illustrating a method of manufacturing the nonvolatile memory device of FIG. 1.

9A, source / drain electrodes 102 spaced apart from each other in the first direction X are formed on the substrate 100.

Here, the substrate 100 may include a glass substrate or a flexible substrate. If it is a flexible substrate, an appropriate pre-treatment process may be necessary to improve smoothness.

In addition, in the case of the source / drain electrode 102, after forming a conductive film (not shown) for the source / drain electrode on the substrate 100, it may be formed by patterning it through a wet etching or dry etching process. Here, the conductive film for the source / drain electrodes (not shown) may be formed by sputtering.

Referring to FIG. 9B, an oxide semiconductor thin film 103, a tunneling insulating film 105, and a charge accumulation film 107 are sequentially stacked on a substrate 100 between source / drain electrodes 102.

Here, since the thickness and composition of the oxide semiconductor thin film 103 serve as important variables for determining the operating conditions of the memory device, the deposition thickness (second direction (Y) thickness) of the oxide semiconductor thin film 103 is considered in consideration of the following. It is desirable to decide.

First, the thickness of the oxide semiconductor thin film 103 is determined within a range in which operating characteristics of the memory device can be secured. Second, it is desirable to determine the thickness of the oxide semiconductor thin film 103 so that a low voltage driving of the memory transistor is possible. In addition, the oxide semiconductor thin film 103 is preferably formed at a temperature of 200 ° C or lower.

In addition, the thickness of the tunneling insulating layer 105 can serve as an important device parameter that determines memory operating characteristics. Therefore, it is preferable to determine the deposition thickness (second direction (Y) thickness) of the tunneling insulating layer 105 in consideration of the following matters.

First, it must be determined in a range that does not excessively increase the operating voltage of the memory transistor. That is, when the thickness of the tunneling insulating film 105 is too thick, not only the charge injection efficiency is lowered, but also the cause of raising the driving voltage of the memory transistor due to the series capacitor generated by the insulating film constituting a part of the gate stack of the transistor. Because it can. Therefore, when considering such matters, it is preferable that the thickness of the tunneling insulating film 105 is determined in a range of 10 nm or less. Second, it must be determined in a range capable of sufficiently suppressing process degradation during the etching process of the oxide semiconductor thin film 103 and a range capable of preventing excessive tunneling. As a result, when considering two points at the same time, the thickness of the tunneling insulating film 105 is preferably determined in the range of 4nm to 10nm.

Meanwhile, the oxide semiconductor thin film 103, the tunneling insulating film 105, and the charge accumulation film 107 may be formed by a thin film forming method commonly used in a semiconductor device manufacturing process. For example, atomic layer deposition (Atomic) Layer Deposition, ALD), Chemical Vapor Deposition (CVD), Reactive Sputtering (Reactive Sputtering). At this time, it is preferable to determine the process temperature, whether plasma is used, thin film forming raw materials, etc., so that the specific process conditions do not deteriorate the properties of the oxide semiconductor thin film 103 and the tunneling insulating film 105 formed at the bottom. In addition, the process of forming the oxide semiconductor thin film 103, the tunneling insulating film 105 and the charge accumulation film 107 is preferably performed continuously (ie, in situ process) in the same equipment.

Here, in the case of the charge accumulation film 107, electrical characteristics can be adjusted through a change in the stacked structure. More specifically, it is exemplified when a thin film is formed by using an atomic layer deposition method. When a thin film is formed by using an atomic layer deposition method, a stacked film having a desired structure may be formed by controlling a cycle configuration. For example, when forming a stacked structure of a zinc oxide film (ZnO) and a hafnium oxide film (HfO2), controlling the number of cycles of the atomic layer deposition method accumulates charges depending on how many times the hafnium oxide film (HfO2) enters with a certain thickness. Changes abilities. In consideration of this, if the stack structure of the charge accumulation film 107 is appropriately controlled by using the atomic layer deposition method, a nonvolatile memory device composed of the charge accumulation film 107 of the stack structure having excellent performance proposed in the present invention can be implemented. You can.

9C, the oxide semiconductor thin film 103, the tunneling insulating film 105, and the charge accumulation film 107 are etched in the same pattern. More specifically, the oxide semiconductor thin film 103, the tunneling insulating film 105 and the charge accumulation film 107 are etched to etch the oxide semiconductor thin film 104, the tunneling insulating film 106, and the charge accumulation film on the channel region of the memory transistor. (108) can be formed. Here, the etching process may be performed by a photolithography process. For example, a wet etching process may be performed using a predetermined wet etching solution, or a dry etching process using plasma may be performed. When performing such an etching process, the tunneling insulating layer 106 can effectively prevent the oxide semiconductor thin film 108 from deteriorating.

On the other hand, as described above, the step of forming the charge accumulation film 108 is performed by alternately laminating at least one oxide semiconductor layer and at least one insulator layer to form the charge accumulation film 108, thereby forming the charge accumulation film 108. It has a stacked structure of an oxide semiconductor layer and an insulator layer.

Referring to FIG. 9D, a gate insulating layer 110 is formed to cover the source / drain electrodes 102 and the etched charge accumulation layer 108. More specifically, the gate insulating film 110 may be formed to cover the source / drain electrode 102, the oxide semiconductor thin film 104, the tunneling insulating film 106, and the charge accumulation film 108.

Referring to FIG. 9E, a contact via hole H that penetrates the gate insulating layer 110 and exposes the source / drain electrodes 102 is formed. More specifically, the contact via hole H exposing the source / drain electrode 102 may be formed by etching the gate insulating layer 110. Here, the formation of the contact via hole H is preferably performed by an etching process using photolithography or a wet etching process using a predetermined wet etching solution.

In addition, after forming the contact via hole H, the contact via hole H is filled, and the non-volatile shown in FIG. 1 is formed by forming a source / drain electrode pad (112 of FIG. 1) connected to the source / drain electrode. The memory element 1 can be manufactured.

Hereinafter, a method of manufacturing the nonvolatile memory device 2 of FIG. 3 will be described with reference to FIG. 10. 3 and 9A to 9E, descriptions that overlap with the description will be omitted.

10A and 10B are intermediate step views illustrating a method of manufacturing the nonvolatile memory device of FIG. 3.

Referring to FIG. 10A, first, a gate electrode 214 is formed on the substrate 100. Thereafter, the gate insulating layer 210 may be formed to cover the gate electrode 214.

Referring to FIG. 10B, after the gate insulating layer 210 is formed, a groove is formed by etching the upper surface of the gate insulating layer 210 instead of the substrate 100. Etching may be performed, for example, by applying a wet vision process using a photoresist as an etching mask, and applying a mask to a region other than the region where the groove is formed in the upper surface of the gate insulating layer 210.

An etched charge accumulation film 208 is formed in the formed groove. After the charge accumulation layer is formed on the upper surface of the gate insulating layer 210, the charge accumulation layer 208 may be formed by etching the charge accumulation layer by applying a mask to the rest of the region except for the groove.

If the tunneling insulating film, the oxide semiconductor thin film, and the protective insulating film are sequentially formed by applying the process described in FIGS. 9A to 9E after the charge accumulation film 208 is formed, the nonvolatile memory device 2 shown in FIG. 3 is manufactured Can be.

Although the embodiments have been described by the limited drawings as described above, a person skilled in the art can make various modifications and variations from the above description. For example, the described techniques are performed in a different order than the described method, and / or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or other components Alternatively, even if replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

1, 3: Non-volatile memory device
100: substrate 102, 202: source / drain electrode
104, 204: oxide semiconductor thin film 106, 216: tunneling insulating film
108, 208: charge accumulation film 110, 210: gate insulating film
112: source / drain electrode pad 114, 214: gate electrode
206: protective insulating film H: contact via hole

Claims (22)

Board;
A source / drain electrode spaced apart from each other on the substrate;
An oxide semiconductor thin film formed on a substrate between the source / drain electrodes and formed to cover a portion of each of the source / drain electrodes;
A tunneling insulating film formed on the oxide semiconductor thin film;
A charge accumulation film formed on the tunneling insulating film and accumulating electric charges tunneled through the tunneling insulating film;
A gate insulating film formed to cover the charge accumulation film; And
It includes a gate electrode formed on the gate insulating film,
The charge accumulation layer has a structure in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked.
According to claim 1,
The substrate is a non-volatile memory device formed of a transparent material.
According to claim 1,
The oxide semiconductor thin film is a non-volatile memory device formed of a transparent oxide semiconductor in the visible region.
According to claim 1,
The oxide semiconductor thin film includes a channel region having a predetermined length,
The tunneling insulating layer is a non-volatile memory device formed on the channel region.
According to claim 1,
The amount, speed, and retention time of the information stored in the charge accumulation layer are the conductive range of the at least one oxide semiconductor layer, the type and thickness of the at least one insulator layer, the at least one oxide semiconductor layer and the at least one or more A non-volatile memory device that is controlled according to the number of insulating layers inserted and the stacked structure.
The method of claim 5,
The at least one oxide semiconductor layer is a non-volatile memory device having a carrier concentration of 1e14cm ^-3 to 1e18cm ^-3 .
The method of claim 5,
The at least one insulator layer is formed of an insulator having an energy band gap of 4eV to 10eV.
The method of claim 5,
The at least one insulator layer is stacked twice on the charge accumulation layer and has a thickness of 1.5 nm to 2.5 nm.
The method of claim 5,
The at least one insulator layer is stacked twice on the charge accumulation layer and has a thickness of 3.5 nm to 4.5 nm.
The method of claim 5,
The at least one insulator layer is stacked four times on the charge accumulation layer and has a thickness of 1.5 nm to 2.5 nm.
According to claim 1,
A pair of contact via holes formed through the gate insulating layer to expose the source / drain electrodes; And
A non-volatile memory device further comprising source / drain electrode pads formed to fill the pair of contact via holes and connected to the source / drain electrodes.
Board;
A gate electrode formed on the substrate;
A gate insulating film formed to cover the gate electrode;
A charge accumulation film formed in a groove formed in an upper surface of the gate insulating film and accumulating tunneled charges;
A tunneling insulating film formed on the gate insulating film and the charge accumulation film;
A source / drain electrode formed spaced apart from each other on the tunneling insulating film;
An oxide semiconductor thin film formed on a tunneling insulating layer between the source / drain electrodes and formed to cover a portion of each of the source / drain electrodes; And
It includes a protective insulating film formed on the oxide semiconductor thin film,
The oxide semiconductor thin film includes a channel region having a predetermined length,
The width of the charge accumulation film is the same as the length of the channel region, and has a structure in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked.
The method of claim 12,
The substrate is formed of a transparent material,
The oxide semiconductor thin film is a non-volatile memory device formed of a transparent oxide semiconductor in the visible region.
The method of claim 12,
The amount, speed, and retention time of the information stored in the charge accumulation layer are the conductive range of the at least one oxide semiconductor layer, the type and thickness of the at least one insulator layer, the at least one oxide semiconductor layer and the at least one or more A non-volatile memory device that is controlled according to the number of insulating layers inserted and the stacked structure.
The method of claim 14,
The at least one insulator layer is stacked twice on the charge accumulation layer and has a thickness of 1.5 nm to 2.5 nm.
The method of claim 14,
The at least one insulator layer is stacked twice on the charge accumulation layer and has a thickness of 3.5 nm to 4.5 nm.
The method of claim 14,
The at least one insulator layer is stacked four times on the charge accumulation layer and has a thickness of 1.5 nm to 2.5 nm.
Forming source / drain electrodes spaced apart from each other on a substrate;
Forming an oxide semiconductor thin film on the substrate between the source / drain electrodes so as to cover a portion of each of the source / drain electrodes;
Forming a tunneling insulating film on the oxide semiconductor thin film;
Forming a charge accumulation film on the tunneling insulating film to accumulate charges tunneled through the tunneling insulating film;
Etching the oxide semiconductor thin film, the tunneling insulating film, and the charge accumulation film in the same pattern;
Forming a gate insulating film to cover the source / drain electrodes and the charge accumulation film; And
And forming a gate electrode on the gate insulating layer,
The forming of the charge accumulation film is a method of manufacturing a nonvolatile memory device in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked to form the charge accumulation film.
The method of claim 18,
The step of forming the charge accumulation layer is a nonvolatile memory device that controls the number of cycles of atomic layer deposition (ALD) to control the thickness and the number of stacks of the at least one oxide semiconductor layer and the at least one insulator layer. Method of manufacturing.
The method of claim 18,
Etching the gate insulating layer to form a pair of contact via holes exposing the source / drain electrodes; And
And forming a source / drain electrode pad connected to the source / drain electrode and filling the pair of contact via holes.
Forming a gate electrode on the substrate;
Forming a gate insulating film to cover the gate electrode;
Forming a groove by etching an upper surface of the gate insulating film;
Forming a charge accumulation film in the groove to accumulate tunneled charges;
Forming a tunneling insulating film on the gate insulating film and the charge accumulation film;
Forming source / drain electrodes spaced apart from each other on the tunneling insulating film;
Forming an oxide semiconductor thin film on the tunneling insulating layer between the source / drain electrodes so as to cover a portion of each of the source / drain electrodes; And
And forming a protective insulating film on the oxide semiconductor thin film,
The forming of the charge accumulation film is a method of manufacturing a nonvolatile memory device in which at least one oxide semiconductor layer and at least one insulator layer are alternately stacked to form the charge accumulation film.
The method of claim 21,
The step of forming the charge accumulation layer is a nonvolatile memory device that controls the number of cycles of atomic layer deposition (ALD) to control the thickness and the number of stacks of the at least one oxide semiconductor layer and the at least one insulator layer. Method of manufacturing.

Images