WO2008079684B1 - Electron blocking layers for electronic devices - Google Patents
Electron blocking layers for electronic devicesInfo
- Publication number
- WO2008079684B1 WO2008079684B1 PCT/US2007/087167 US2007087167W WO2008079684B1 WO 2008079684 B1 WO2008079684 B1 WO 2008079684B1 US 2007087167 W US2007087167 W US 2007087167W WO 2008079684 B1 WO2008079684 B1 WO 2008079684B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dielectric layer
- gate stack
- dielectric
- component
- forming
- Prior art date
Links
- 230000000903 blocking effect Effects 0.000 title 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract 12
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims abstract 8
- 229910052735 hafnium Inorganic materials 0.000 claims abstract 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract 5
- 238000000034 method Methods 0.000 claims abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 10
- 239000003989 dielectric material Substances 0.000 claims 9
- 230000005641 tunneling Effects 0.000 claims 9
- 229910052681 coesite Inorganic materials 0.000 claims 5
- 229910052906 cristobalite Inorganic materials 0.000 claims 5
- 239000000377 silicon dioxide Substances 0.000 claims 5
- 229910052682 stishovite Inorganic materials 0.000 claims 5
- 229910052905 tridymite Inorganic materials 0.000 claims 5
- 230000005684 electric field Effects 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 4
- 239000002159 nanocrystal Substances 0.000 claims 4
- 229910016909 AlxOy Inorganic materials 0.000 claims 3
- 229910020781 SixOy Inorganic materials 0.000 claims 3
- 150000001875 compounds Chemical class 0.000 claims 3
- 229910052593 corundum Inorganic materials 0.000 claims 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Methods and apparatus for electronic devices such as non-volatile memory devices are described. The momory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control electric includes a combination of high-k dielectric meterials such as aluminium oxide (A12O3), Hafnium oxide (HfO2), and/or hybrid films of Hafnium aluminium oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g, two, three or four bit) operation.
Claims
1. A gate stack of a memory device, the gate stack comprising: a charge storage layer comprising localized charge traps on a tunneling dielectric layer; a first dielectric layer having a first dielectric constant on the charge storage layer; a second dielectric layer having a second dielectric constant on the first dielectric layer and disposed adjacent to a gate contact of the memory device, the second dielectric constant being higher than the first dielectric constant.
2. The gate stack of claim 1 , wherein the charge storage layer comprises a nitride layer.
3. The gate stack of claim 1, wherein the first dielectric layer has a thickness of about 15 nm or less and the second dielectric layer has a thickness of about 10 nm or less.
4. The gate stack of claim 1 , wherein a thickness of the first dielectric layer is no more than about 200% of a thickness of the second dielectric layer.
5. The gate stack of claim 1 , wherein the second dielectric layer comprises hafnium.
6. The gate stack of claim 5, wherein the second dielectric layer comprises a hafnium-containing compound selected from the group consisting of: HfO2, HfAlO3, HfSiO2, Hf1-xAlxOy, Hf1-xSixOy, Hf1-xSixO2-yNy, where x is a positive number between 0 and 1 , and y is a positive number.
7. The gate stack of claim 1, wherein the first dielectric layer comprises Al2O3 and the second dielectric layer comprises HfO2.
8. The gate stack of claim 1, wherein the first dielectric layer comprises SiO2 and the second dielectric layer comprises HfO2. - 33 -
9. The gate stack of claim 1 , wherein an amount of at least a first component of the second dielectric material of the second dielectric layer varies in a predetermined manner across a thickness thereof.
10. The gate stack of claim 9, wherein the second dielectric material includes the first component and a second component, and a ratio of the first component to the second component varies in a predetermined manner across the thickness of the second dielectric layer.
11. The gate stack of claim 1 , wherein the second dielectric layer comprises a plurality of layers.
12. The gate stack of claim 1 , wherein the gate contact comprises a metal.
13. The gate stack of claim 12, wherein the gate contact comprises TaN.
14. The gate stack of claim 1 , wherein the memory device has a program/erase window of greater than about 8 volts.
15. The gate stack of claim 14, wherein the memory device has a program/erase window of greater than about 9 volts.
16. The gate stack of claim 15 , wherein the memory device has a program/erase window of greater than about 10 volts.
17. The gate stack of claim 1 , wherein a tunneling current through the first dielectric layer is less than about 10"4 A/cm2 at an electric field strength that is equivalent to an electric field strength of 2.5 x 107 V/cm in SiO2.
18. A gate stack of a memory device comprising: a tunneling dielectric layer; a charge storage layer comprising a plurality of nanocrystals on the tunneling dielectric layer; a first dielectric layer comprising a first dielectric material having a first dielectric constant on the charge storage layer; a second dielectric layer comprising a second dielectric material having a second dielectric constant on the first dielectric layer; and a third dielectric layer comprising a third dielectric material having a third dielectric constant on the second dielectric layer, wherein the first and third dielectric constants are greater than the second dielectric constant.
19. The gate stack of claim 18, wherein the first dielectric layer comprises hafnium.
20. The gate stack of claim 19, wherein the first dielectric layer comprises a hafnium- containing compound selected from the group consisting of: HfO2, HfAlO3, HfSiO2, Hf1- xAlxOy, Hf1-xSixOy, Hf1-xSixO2-yNy, where x is a positive number between O and 1, and y is a positive number.
21. The gate stack of claim 18, wherein the second dielectric layer comprises one of Al2O3 and SiO2.
22. The gate stack of claim 18, wherein the third dielectric layer comprises hafnium.
23. The gate stack of claim 22, wherein the third dielectric layer comprises a hafnium- containing compound selected from the group consisting of: HfO2, HfAlO3, HfSiO2, Hf1- x AlxOy, Hf1-xSixOy, Hf1-xSixO2-yNy, where x is a positive number between O and 1, and y is a positive number.
24. The gate stack of claim 18, wherein the second dielectric layer comprises Al2O3 and the first and third dielectric layers comprise HfO2. - 35 -
25. The gate stack of claim 18, wherein the second dielectric layer comprises SiO2 and the first and third dielectric layers comprise HfO2.
26. The gate stack of claim 18, wherein an amount of at least a first component of the first dielectric material of the first dielectric layer varies in a predetermined manner across a thickness thereof.
27. The gate stack of claim 26, wherein the first dielectric material includes the first component and a second component, and a ratio of the first component to the second component varies in a predetermined manner across the thickness of the second dielectric layer.
28. The gate stack of claim 18, wherein an amount of at least a first component of the third dielectric material of the third dielectric layer varies in a predetermined manner across a thickness thereof.
29. The gate stack of claim 28, wherein the third dielectric material includes the first component and a second component, and a ratio of the first component to the second component varies in a predetermined manner across the thickness of the third dielectric layer.
30. The gate stack of claim 18, wherein a thickness of the second dielectric layer is no more than about 200% of a thickness of each of the first and third dielectric layers.
31. The gate stack of claim 18, further comprising a gate contact on the third dielectric layer, wherein the gate contact comprises a metal.
32. The gate stack of claim 31 , wherein the gate contact comprises TaN.
33. The gate stack of claim 18, wherein the memory device has a program/erase window of greater than about 8 volts. - 36 -
34. The gate stack of claim 18, wherein the memory device has a program/erase window of greater than about 9 volts.
35. The gate stack of claim 34, wherein the memory device has a program/erase window of greater than about 10 volts.
36. The gate stack of claim 18, wherein a tunneling current through the first dielectric layer is less than about 10"4 A/cm2 at an electric field strength that is equivalent to an electric field strength of 2.5 x 107 V/cm in SiO2.
37. The gate stack of claim 18, wherein the nanocrystals comprise a metal.
38. The gate stack of claim 37, wherein the nanocrystals comprise a metal selected from the group consisting of: ruthenium, nickel, platinum and palladium.
39. A method for forming a memory device, comprising: forming a tunneling dielectric layer over a substrate; forming a charge storage layer comprising localized charge traps over the tunneling dielectric layer; forming a first dielectric layer comprising a first dielectric constant over the charge storage layer; forming a second dielectric layer comprising a second dielectric constant over the first dielectric layer, the second dielectric constant being higher than the first dielectric constant; and forming a gate contact over the second dielectric layer.
40. A method for forming a memory device, comprising: forming a tunneling dielectric layer over a substrate; forming a charge storage layer comprising a plurality of nanocrystals over the tunneling dielectric layer; - 37 -
forming a first dielectric layer comprising a first dielectric constant over the charge storage layer; forming a second dielectric layer comprising a second dielectric constant over the first dielectric layer; forming a third dielectric layer comprising a third dielectric constant over the second dielectric layer, the first and third dielectric constants being greater than the second dielectric constant; and forming a gate contact over the third dielectric layer.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020097012821A KR101443731B1 (en) | 2006-12-20 | 2007-12-12 | Electron blocking layers for electronic devices |
| CN200780046789.2A CN101589461B (en) | 2006-12-20 | 2007-12-12 | Electron blocking layers for electronic devices |
| JP2009543077A JP2010531048A (en) | 2006-12-20 | 2007-12-12 | Electronic block layer for electronic devices |
| US12/247,917 US7847341B2 (en) | 2006-12-20 | 2008-10-08 | Electron blocking layers for electronic devices |
| US12/390,275 US8686490B2 (en) | 2006-12-20 | 2009-02-20 | Electron blocking layers for electronic devices |
| US14/164,065 US9214525B2 (en) | 2006-12-20 | 2014-01-24 | Gate stack having electron blocking layers on charge storage layers for electronic devices |
Applications Claiming Priority (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/641,956 | 2006-12-20 | ||
| US11/641,956 US20080150003A1 (en) | 2006-12-20 | 2006-12-20 | Electron blocking layers for electronic devices |
| US11/688,087 US20080150004A1 (en) | 2006-12-20 | 2007-03-19 | Electron Blocking Layers for Electronic Devices |
| US11/688,087 | 2007-03-19 | ||
| US11/743,085 | 2007-05-01 | ||
| US11/743,085 US20080150009A1 (en) | 2006-12-20 | 2007-05-01 | Electron Blocking Layers for Electronic Devices |
| US93148807P | 2007-05-23 | 2007-05-23 | |
| US60/931,488 | 2007-05-23 | ||
| EP07252410A EP1936672A1 (en) | 2006-12-20 | 2007-06-14 | Electron blocking layers for gate stacks of nonvolatile memory devices |
| EP07252410.1 | 2007-06-14 |
Related Parent Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/688,087 Continuation-In-Part US20080150004A1 (en) | 2006-12-20 | 2007-03-19 | Electron Blocking Layers for Electronic Devices |
| US11/743,085 Continuation-In-Part US20080150009A1 (en) | 2006-12-20 | 2007-05-01 | Electron Blocking Layers for Electronic Devices |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/247,917 Continuation-In-Part US7847341B2 (en) | 2006-12-20 | 2008-10-08 | Electron blocking layers for electronic devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2008079684A2 WO2008079684A2 (en) | 2008-07-03 |
| WO2008079684A3 WO2008079684A3 (en) | 2008-09-04 |
| WO2008079684B1 true WO2008079684B1 (en) | 2008-10-23 |
Family
ID=39563160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2007/087167 WO2008079684A2 (en) | 2006-12-20 | 2007-12-12 | Electron blocking layers for electronic devices |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR101443731B1 (en) |
| WO (1) | WO2008079684A2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8686490B2 (en) | 2006-12-20 | 2014-04-01 | Sandisk Corporation | Electron blocking layers for electronic devices |
| US7847341B2 (en) | 2006-12-20 | 2010-12-07 | Nanosys, Inc. | Electron blocking layers for electronic devices |
| US8383479B2 (en) | 2009-07-21 | 2013-02-26 | Sandisk Technologies Inc. | Integrated nanostructure-based non-volatile memory fabrication |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586785B2 (en) * | 2000-06-29 | 2003-07-01 | California Institute Of Technology | Aerosol silicon nanoparticles for use in semiconductor device fabrication |
| US6844604B2 (en) * | 2001-02-02 | 2005-01-18 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
| JP2004281662A (en) | 2003-03-14 | 2004-10-07 | Toshiba Corp | Semiconductor memory device and its manufacturing method |
| JP4040534B2 (en) | 2003-06-04 | 2008-01-30 | 株式会社東芝 | Semiconductor memory device |
| US7138680B2 (en) * | 2004-09-14 | 2006-11-21 | Infineon Technologies Ag | Memory device with floating gate stack |
| US7352631B2 (en) * | 2005-02-18 | 2008-04-01 | Freescale Semiconductor, Inc. | Methods for programming a floating body nonvolatile memory |
| KR100652402B1 (en) * | 2005-02-21 | 2006-12-01 | 삼성전자주식회사 | Non-volatile memory device, and method of fabricating the same |
-
2007
- 2007-12-12 WO PCT/US2007/087167 patent/WO2008079684A2/en active Application Filing
- 2007-12-12 KR KR1020097012821A patent/KR101443731B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008079684A3 (en) | 2008-09-04 |
| KR101443731B1 (en) | 2014-09-23 |
| WO2008079684A2 (en) | 2008-07-03 |
| KR20090113253A (en) | 2009-10-29 |
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