KR20200042450A - Semiconductor device with shield for electromagnetic interference - Google Patents

Abstract

A semiconductor device comprises a first die embedded in a molding material, wherein contact pads of the first die are adjacent to a first side surface of the molding material. The semiconductor device further comprises: a redistribution structure positioned on the first side surface of the molding material; a first metal coating positioned along the sidewalls of the first die and between the first die and the molding material; and a second metal coating positioned along the sidewalls of the molding material and on a second side surface of the molding material which is at the opposite side of the first side surface.

Description

A semiconductor device having a shield against electromagnetic interference {SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE}

This application claims the priority of U.S. Provisional Patent Application 62 / 527,879, filed on June 30, 2017, under the name of the invention " Semiconductor Device with Shield for Electromagnetic Interference, " Are merged within.

The present invention relates to a semiconductor device having a shield against electromagnetic interference.

The semiconductor industry has experienced rapid growth due to constant improvements in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has resulted from repeated reductions in minimum feature size, which allows more components to be integrated within a given area. As the demand for much smaller electronic devices has recently increased, the need for smaller and more creative packaging technologies for semiconductor dies has grown.

Examples of such packaging technologies are POP (Package-on-Package) technology. In the POP package, the top semiconductor packages are stacked on the top of the bottom semiconductor package to enable high density and component density. Another example is MCM (Multi-Chip-Module) technology, in which several semiconductor dies are packaged in one semiconductor package to provide integrated functions to semiconductor devices.

The high degree of integration of advanced packaging technologies enables the production of semiconductor devices with improved functionality and small footprint, which is advantageous for small form factor devices such as cell phones, tablets, and digital music players. Another advantage is that the length of the conductive path connecting the interconnects in the semiconductor package is shortened. This improves the electrical performance of the semiconductor device because shorter routing of interconnects between circuits speeds signal propagation and reduces noise and crosstalk.

In an embodiment, the semiconductor device comprises: a first die embedded in the molding material, wherein the contact pads of the first die are near the first side of the molding material; A redistribution structure over the first side of the molding material; A first metal coating along sidewalls of the first die and between the first die and the molding material; And a second metal coating on the second side of the molding material, along the sidewalls of the molding material, opposite the first side. In an embodiment, the first metal coating and the second metal coating are electrically connected to the ground contact. In an embodiment, the redistribution structure includes vias electrically coupled to the first metal coating. In an embodiment, the via has a first dimension along the first direction and a second dimension along the second direction perpendicular to the first direction, the second dimension being less than the first dimension. In an embodiment, the first die has a plurality of conductive pillars coupled to each of the contact pads, and at least one of the plurality of conductive pillars is electrically coupled to the first metal coating. In an embodiment, the top surface of the plurality of conductive pillars distal to the contact pads is flush with the first side of the molding material. In an embodiment, the second metal coating is electrically coupled to the conductive line of the redistribution structure, and the conductive line is exposed at the sidewall of the redistribution structure. In an embodiment, the semiconductor device further includes a second die embedded within the molding material and laterally spaced from the first die, the contact pads of the second die being electrically coupled to the redistribution structure. In an embodiment, the side walls of the second die are free of metal coating. In an embodiment, the first die and the second die have different functions. In an embodiment, the first metal coating extends continuously from sidewalls of the first die to sidewalls of the second die.

In an embodiment, a semiconductor device includes: a first die in a molding layer; A first redistribution structure comprising conductive lines electrically coupled to the contact pads of the first die, the first redistribution structure on the first side of the molding layer; A second redistribution structure on the second side of the molding layer, opposite the first side; A first conductive structure within the molding layer and laterally spaced from the first die, the first conductive structure comprising a first dielectric region around the first die and conductive coatings on both sides of the first dielectric region. Ham-; And a via in the molding layer, the via being coupled to the first conductive line of the first redistribution structure and the second conductive line of the second redistribution structure. In an embodiment, the via comprises a second dielectric region; And a second conductive coating on sidewalls of the second dielectric region. In an embodiment, the via is between the first die and the first conductive structure. In an embodiment, the first conductive structure is electrically coupled to at least one conductive line of the first redistribution structure and at least one conductive line of the second redistribution structure. In an embodiment, the second redistribution structure includes a ground plane, and the first conductive structure is electrically coupled to the ground plane.

In an embodiment, the method includes attaching the first die to the carrier, wherein the contact pads on the front side of the first die are back to the carrier; Forming a molding material over the carrier and around the first die; Forming a redistribution structure distal to the carrier, over the first side of the molding material, wherein the redistribution structure includes conductive lines electrically coupled to the first die, and the first conductive feature of the redistribution structure is a sidewall of the redistribution structure Exposed at-; Separating the carrier; And forming a first conductive coating along the second side of the molding material, opposite sidewalls and the first side of the molding material, the first conductive coating being electrically applied to the first conductive feature of the redistribution structure. Connected. In an embodiment, the method further includes forming a second conductive coating on the sidewalls and backside of the first die prior to attaching the first die to the carrier. In an embodiment, the first die has conductive pillars that are over the contact pads of the first die and are electrically coupled to the contact pads, and the first conductive pillar of the conductive pillars extends to the edge of the first die, and is conductive The first conductive pillars of the pillars are electrically coupled to the second conductive coating through vias of the redistribution structure. In an embodiment, the vias of the redistribution structure are electrically coupled to the second conductive coating. In an embodiment, the via is formed to have an elliptical shape when viewed in plan view.

In an embodiment, a method includes forming a first dielectric structure on a carrier; Forming a conductive layer over the first dielectric structure; Attaching the first die to the carrier, the first die being laterally separated from the first dielectric structure; Encapsulating the first die and the first dielectric structure in a molding layer; Forming a first redistribution structure on the first side of the molding layer, the first redistribution structure electrically conducting lines electrically coupled to contact pads of the first die and electrically conductive layer over the first dielectric structure Contains-; Separating the carrier; And forming a second redistribution structure on the second side of the molding layer, opposite the first side, the second redistribution structure comprising conductive lines electrically coupled to the conductive layer over the first dielectric structure. Includes. In an embodiment, the method further comprises recessing the molding layer from the first side of the molding layer after encapsulating the first die and the first dielectric structure and before forming the first redistribution structure, the recessing Exposes the conductive pillars of the first die and the first surface of the first dielectric structure. In an embodiment, the method further comprises recessing the molding layer from the second side of the molding layer after separating the carrier, wherein the recessing is on the opposite side of the first surface of the first dielectric structure. The second surface of the dielectric structure is exposed. In an embodiment, the method further includes forming a second dielectric structure on the carrier, the second dielectric structure is made of the same dielectric material as the first dielectric structure, and the conductive layer is formed over the second dielectric structure , The conductive layer over the second dielectric structure is electrically coupled between the conductive lines of the first redistribution structure and the conductive lines of the second redistribution structure.

In an embodiment, a semiconductor device comprises: a first die; A second die laterally spaced from the first die; Molding material-the first die and the second die are surrounded by a molding material-; A redistribution structure over the first side of the molding material, the conductive line of the redistribution structure being exposed at the sidewall of the redistribution structure; And a first conductive layer on the second side of the molding material and on the sidewalls of the molding material, opposite the first side, the first conductive layer being electrically connected to the conductive line of the redistribution structure. In an embodiment, the semiconductor device further includes a second conductive layer along sidewalls of the first die. In an embodiment, the sidewalls of the second die are free of a second conductive layer.

In an embodiment, a package comprises: a substrate; A connector electrically coupled to the first conductive pads of the substrate, the connector comprising a signal terminal and a ground terminal; A semiconductor device electrically coupled to the second conductive pads of the substrate, the semiconductor device including a first die embedded in a molding material, the first die having a first conductive coating on sidewalls of the first die; A redistribution structure over the first side of the molding material, the redistribution structure having conductive lines electrically coupled to the first die; A second conductive coating on the second side of the molding material, opposite the first side, along sidewalls of the molding material; And external connectors attached to the redistribution structure, the external connectors including a signal connector, a first ground connector, and a second ground connector, the signal connector being coupled to the signal terminal by a conductive line of the substrate, and the first ground The connector and the second ground connector are respectively coupled to the ground terminal by the first ground plane and the second ground plane of the board, and the conductive line is between the first ground plane and the second ground plane. In an embodiment, the connector is a radio frequency (RF) connector.

The disclosed embodiments have many advantages. The metal coating 109 on the semiconductor dies 30/40 and / or the metal coating 119 on the outer surface of the molding material 123 provides EMI protection, so that the formed semiconductor device is more resistant to EM interference. It has excellent performance. The disclosed EMI shielding structures can be easily integrated with existing manufacturing flows with little or no extra space required to accommodate the EMI shielding structures, thereby enabling a low cost package with small size and improved EMI protection. Features such as elongated via 133A (see FIG. 7B) for connection to a metal coating (e.g., reference number 109) enable greater error margins for the photolithography process, and more reliable grounding of the metal coating. Provide anger. The disclosed EMI protection / isolation structure also simplifies the analysis of the EM performance of the formed semiconductor devices, and consequently, the simulation time for analyzing the EM performance of the semiconductor devices is greatly reduced, reducing the design cycle, and time to market. Reduces it. Analysis shows that a nearly perfect Faraday cage can be achieved by connecting a metal coating (eg, reference numeral 109) to the electrical ground in the first via layer of the redistribution structure (eg, via 133A). The dual metal coating structure (e.g., 109 and 119) provides improved EM performance by using an outer metal coating (e.g., 119) to further reduce EM interference reaching the semiconductor device. Achieve.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to standard practice in this industry, various features have not been drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of explanation.
1 and 2 show cross-sectional views of a semiconductor die at various stages of manufacture, in accordance with some embodiments.
3 and 4 show enlarged views of the semiconductor die shown in FIG. 2, in accordance with some embodiments.
5, 6, 7A, 7B, 7C, and 8 illustrate various aspects of a semiconductor device at various fabrication steps, in accordance with some embodiments.
9-12 show cross-sectional views of a semiconductor device at various fabrication steps, in accordance with some embodiments.
13, 14, 15, 16, 17A, and 17B show various aspects of a semiconductor device at various manufacturing stages, in accordance with some embodiments.
18 shows a cross-sectional view of an electrical system with electromagnetic shielding, in some embodiments.
19 shows a flow chart of a method of forming a semiconductor device, in some embodiments.

The following disclosure provides many different embodiments or examples that implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples, and are not intended to be limiting. For example, in the following detailed description, formation of the first feature on or above the second feature may include embodiments in which the first and second features are formed by direct contact, and also the first and second features. Additional features may include an embodiment in which additional features may be formed between the first and second features so that they are not in direct contact.

Also, "below", "below", "below", "above", "above" to describe the relationship of one element or feature (s) to another element (s) or feature (s) shown in the figures. Spatial relative terms such as "can be used here for ease of explanation. Spatial relative terms are intended to cover different orientations of the device in use or in operation in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 ° or rotated in another orientation), and thus the spatial relative descriptors used herein can be interpreted the same.

1 and 2 show cross-sectional views of a semiconductor die at various stages of manufacture, in accordance with some embodiments. In FIG. 1, a plurality of semiconductor dies 30 (see FIG. 2), which may also be referred to as integrated circuit dies or dies, are formed in the semiconductor wafer 30 ′. Dozens, hundreds, or even more semiconductor dies 30 may be formed in the semiconductor wafer 30 'and will be singulated to form a plurality of individual semiconductor dies 30 (see FIG. 2). ).

The wafer 30 ′ may be or include a semiconductor substrate such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate includes other semiconductor materials such as germanium; Compound semiconductors including silicon carbide, gallium arsenide, gallium phosphorus, gallium nitride, indium phosphorus, indium arsenide, and / or indium antimony; Alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, and the like can be formed in and / or on a semiconductor substrate, such as one or more dielectric layers on the semiconductor substrate to form integrated circuits within the semiconductor dies 30. Can be interconnected by interconnecting structures formed by the metallization patterns within.

The semiconductor dies 30 further include a contact pad 101 such as an aluminum pad to which an external connection is made. The contact pad 101 is where it can be referred to as each active side or front side of the semiconductor dies 30. The passivation film 103 can be on the semiconductor dies 30 and on portions of the contact pad 101. The opening passes through the passivation film 103 to reach the contact pad 101. Die connectors 105, such as conductive pillars (eg, including a metal such as copper), can pass through the passivation film 103 and extend into the opening, and each contact pad 101 ) Mechanically and electrically. The die connectors 105 may be formed, for example, by plating or the like. The die connectors 105 electrically couple respective integrated circuits of the semiconductor dies 30. In the following description, the die connectors 105 may also be referred to as conductive pillars 105.

The dielectric material 107 is on the active side of the semiconductor dies 30, such as on the passivation film 103 and die connectors 105. Dielectric material 107 encapsulates die connectors 105 laterally. The dielectric material 107 may include polymers such as polybenzoxazole (PBO), polyimide, and benzocyclobutene (BCB); Nitrides such as silicon nitride; Oxides such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), and Boron-doped PhosphoSilicate Glass (BSG); Or a combination thereof, which may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In the example of FIG. 1, the top surface of dielectric material 107 extends farther from contact pad 101 than the top surfaces of conductive pillars 105.

Next, in FIG. 2, the front side of the wafer 30 'is attached to a tape 108, such as a dicing tape, and singulated along the lines 31 to form a plurality of dies 30. A conductive coating 109 comprising a copper layer or other suitable material that can provide an electromagnetic shield to reduce electromagnetic interference (EMI) or reduce electromagnetic susceptibility (EMS) dies ( It is formed on the rear side (eg, opposite side of the front side) of 30) and on the side walls of the dies 30. The conductive coating 109 can include one or more sub-layers (see FIGS. 3 and 4), and at least one of the sub-layers can include a suitable metal, such as copper. In some embodiments, the conductive coating 109 is conformally formed over the backsides and sidewalls of the dies 30. Although not shown in FIG. 2, a conductive coating 109 can also be formed over the top surface of the tape 108. The conductive coating 109 may also be referred to as a metal coating 109 in the following description.

In some embodiments, FIGS. 3 and 4 show enlarged views of region 150 and region 140 of semiconductor die 30 of FIG. 2, respectively. The structures of the conductive coating 109 of FIGS. 3 and 4 are merely non-limiting examples, and other numbers of sub-layers and / or other structures are also possible, which are fully intended to be included within the scope of the present disclosure. .

As shown in FIG. 3, the conductive coating 109 includes three sub-layers, such as the interfacial layer 159, the barrier layer 157, and the conductive layer 154. The interfacial layer 159 is formed on the back side and side walls of the die 30, for example, between the die 30 and the barrier layer 157. The interfacial layer 159 may include a suitable material such as silicon oxide, and may be formed by thermal oxidation, CVD, physical vapor deposition (PVD), combinations thereof, or other suitable forming method. have. The interfacial layer 159 may act as an adhesive layer between the semiconductor die 30 and a layer to be formed later (eg, reference numeral 157), and layers to be formed later (eg, reference numerals 157 and 109) It can help attach to the semiconductor die 30.

3, the barrier layer 157 is formed over the interface layer 159. The barrier layer 157 may be formed, for example, to prevent or reduce diffusion of the material (eg, copper) of the metal coating 109 into the substrate of the semiconductor dies 30. In some embodiments, the barrier layer 157 includes titanium nitride, but other materials such as tantalum nitride, titanium oxide, tantalum oxide, titanium, tantalum, etc. may alternatively be used. The barrier layer 157 may be formed using a CVD process such as plasma-enhanced CVD (PECVD). However, other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) can alternatively be used.

Next, a conductive layer 154 is formed on the barrier layer 157. The conductive layer 154 can include a suitable metal, such as copper, and can have a thickness between about 3 μm and about 5 μm, such as about 3 μm, but other dimensions are also possible. To form the conductive layer 154, a suitable deposition method such as sputtering, spraying, or plating can be used. In some embodiments, a seed layer (not shown) is formed over the barrier layer 157, and then a conductive layer 154 is formed over the seed layer using a plating process.

In embodiments in which the interfacial layer 159 (eg, silicon oxide) is formed by thermal oxidation of the substrate (eg, silicon) of the semiconductor die 30, the region 140 of the semiconductor die 30 The inner conductive coating 109 may have a different structure from the conductive coating 109 in the region 150, as shown in FIG. 4. The conductive coating 109 in the region 140 corresponds to portions of the conductive coating 109 disposed along the sidewalls of the dielectric material 107 of the die 30. Since the thermal oxidation process does not produce, for example, silicon oxide over the dielectric material 107, the interfacial layer 159 shown in FIG. 3 is not formed within the region 140. Thus, the conductive coating 109 in the region 140 includes a barrier layer 157 and a conductive layer 154, both of which are electrically conductive layers.

5, 6, 7A, 7B, 7C, and 8 illustrate various aspects of the semiconductor device 200 in various manufacturing steps, in accordance with some embodiments. In FIG. 5, the die 30 having the metal coating 109 as shown in FIG. 2 is supported by the adhesive layer 121, while the front side of the die 30 faces the carrier 120. 120). A second die 40, which may be a die having different functionalities than die 30, is also attached to carrier 120, with the front side of die 40 facing back carrier 120.

The carrier 120 may be made of a material such as silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, beryllium oxide, tape, or other suitable material for structural support. In some embodiments, the adhesive layer 121 is deposited or laminated over the carrier 120. The adhesive layer 121 may be photosensitive, and may be easily separated from the carrier 120 by shining ultraviolet (UV) light on the carrier 120 in a subsequent carrier debonding process. For example, the adhesive layer 121 may be a light-to-heat-conversion (LTHC) coating manufactured by a 3M company located in St. Paul, Minnesota.

The second die 40 can be formed with processing steps similar to the die 30 described above, without the metal coating 109. The die 40 has a contact pad 111 in the passivation film 113, a conductive pillar 115 coupled to the contact pad 111, and a dielectric material 117 over the conductive pillar 115. The contact pad 111, the passivation film 113, the conductive pillar 115, and the dielectric material 117 of the die 40 are the contact pad 101, the passivation film 103, and the conductive pillar of the die 30, respectively. (105), and the same or similar material to the dielectric material 107, and may be formed using a similar or the same method. Therefore, details are not repeated.

In some embodiments, die 30 is a radio frequency (RF) die, and die 40 is a digital logic die. Since the RF die (e.g., die 30) is more susceptible to electromagnetic interference than a logic die (e.g., die 40), die 30 is coated with metal to shield die 30 from EMI (109) Have The metal coating 109 is also generated by the die 30 so that the EM interference generated by the die 30 causes little or no interference with other dies (eg, die 40). EM interference can be suppressed (eg, restricted). Die 40 has no metal coating 109 in the illustrated embodiment. In other embodiments, both die 30 and die 40 have a metal coating 109, and die 40 is formed following processing steps similar to those shown in FIGS. 1-4.

Next, a molding material 123 is formed over the carrier 120 and around the dies 30, 40. The deposited molding material 123 can extend over the top surface of the dies 30, 40. The molding material 123 may include, for example, an epoxy, organic polymer, a silica-based or a polymer with or without a glass filler, polyamide, or other materials. In some embodiments, molding material 123 includes a liquid molding compound (LMC) that is a gel-type liquid when applied. The molding material 123 can also include a liquid or solid when applied. The molding material 123 can be molded using, for example, compression molding, transfer molding, or other methods.

Once deposited, the molding material 123 can be cured by a curing process. The curing process may include heating the molding material 123 to a predetermined temperature during a predetermined time period using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination with a heating process. Alternatively, the molding material 123 can be cured using other methods. In some embodiments, a curing process is not performed.

Next, to remove the upper portions of the molding material 123, to expose the conductive pillars 105 of the die 30, to expose the conductive pillars 115 of the die 40, chemical mechanical polishing (chemical A planarization process such as mechanical polish (CMP) may be performed. The planarization process is a substantially coplanar top surface between conductive pillars (eg, reference number 105, reference number 115), dielectric materials (eg, reference number 107, reference number 117), and molding material 123 To achieve. The planarization process can remove the top portions of the dielectric materials 107/117 and further remove the tops of the conductive pillars 105/115.

Next, in FIG. 6, redistribution structure 130 is formed over die 30, die 40, and molding material 123. Redistribution structure 130 includes conductive features, such as conductive lines 131 formed in one or more dielectric layers 132 and one or more layers of vias 133. In some embodiments, one or more dielectric layers 132 are formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In other embodiments, the one or more dielectric layers 132 may include nitride, such as silicon nitride; Oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), and boron-doped phosphosilicate glass (BSG); And the like. The one or more dielectric layers 132 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, or a combination thereof.

In some embodiments, conductive features of redistribution structure 130 include conductive lines 131 and / or conductive vias 133 formed of a suitable conductive material, such as copper, titanium, tungsten, aluminum, and the like. The conductive features are, for example, forming an opening in the dielectric layer 132 to expose the underlying conductive features, forming a seed layer over and in the dielectric layer 132, patterning with a pattern designed over the seed layer Forming the photoresist, plating the conductive material over the seed layer and in the designed pattern (eg electroplating or electroless plating), and photoresist and portions of the seed layer where the conductive material is not formed. It can be formed by removing.

Redistribution structure 130 is electrically coupled to dies 30 and 40. A conductive pad 137, which may be UBM (under bump metallurgy) structures, may be formed on the redistribution structure 130 and electrically coupled to the redistribution structure 130. As illustrated in FIG. 6, at least one conductive line 131A of the redistribution structure 130 extends to the sidewalls of the redistribution structure 130 and is exposed at the sidewalls of the redistribution structure 130. The conductive line 131A is connected to the conductive layer 119 (see FIG. 8) to be formed later and can be used to ground the conductive layer 119.

As shown in FIG. 6, the metal coating 109 of the die 30 is electrically coupled to the conductive line 131A, for example, via via 133A. Conductive line 131A, in some embodiments, is a contact configured to be connected to ground contact pad 101A (eg, electrical ground), such as the leftmost or rightmost contact pad of die 30 of FIG. 6. Pad). The ground contact pad 101A, in some embodiments, is connected to an electrical ground (not shown) through an external connector 143 attached to the conductive pad 137A (see, for example, reference numeral 143A in FIG. 8). Combined. Therefore, the metal coating 109 of the die 30 is grounded to provide shielding from electromagnetic interference to the die 30. In addition, the metal coating 109 can prevent or reduce electromagnetic interference generated by the die 30 from interfering with other dies in the system (eg, die 40).

7A is a cross-sectional view of a portion of a semiconductor device 200 showing details of grounding of the metal coating 109 shown in FIG. 6 in an embodiment. As shown in FIG. 7A, the ground contact pad 101A is coupled to the conductive pillar 105A, which is connected to a ground contact pad (to facilitate electrical connection with the metal coating 109). It may be formed to have an extension extending from 101A) to a location close to the edge of the die 30 (eg, sidewalls), thus to a location close to the metal coating 109. The via 133A, which may be formed in the first via layer of the redistribution structure 130 (eg, the via layer of the redistribution structure 130 closest to the die 30), is coated with a conductive pillar 105A with a metal coating ( 109).

7B is a cross-sectional view of the semiconductor device 200 of FIG. 7A along the cross-section A-A. The A-A cross section crosses the via 133A, so the conductive pillar 105A and the ground contact pad 101A are not visible in the plane of the A-A cross section, so it is shown with a dotted line in FIG. 7B. For simplicity, not all layers and all components of the semiconductor device 200 are shown in the top view of FIG. 7B. 7A is a cross-sectional view of portions of the semiconductor device 200 of FIG. 7B along a B-B cross-section.

As shown in FIG. 7B, the conductive coating 109 is around the side walls of the die 30. The contact pad 101 and ground contact pad 101A shown in FIG. 7A are shown on the same line as the B-B cross section in FIG. 7B. Also shown in FIG. 7B is a via 133 over the contact pad 101 of FIG. 7A and a conductive pillar 105A coupled to the ground contact pad 101A of FIG. 7A. In addition, in FIG. 7B, additional ground contacts formed in the dielectric material 107 and electrically connected to the ground contact pad 101A by conductive features 105 ′ (eg, conductive lines formed in the dielectric material 107). Pad 101B is shown. Since the contact pad 101B and the conductive feature 105 'are not on the line of the B-B cross section, they are not visible in the cross section of Fig. 7A.

In the illustrated embodiment of FIG. 7B, via 133A is used to facilitate electrical connection between metal coating 109 and via 133A, other vias of redistribution structure 130 (eg, via 133 )). In particular, the via 133A may have an elongated shape instead of a circular shape, for example, when viewed in plan view. In some embodiments, the elongated shape of via 133A has a larger dimension along the B-B direction than a dimension along the direction perpendicular to the B-B direction. The elongated shape of via 133A provides a large tolerance for inaccuracies in the photolithography process used to form the pattern for via 133A. For example, even if the actual location of the via 133A moves slightly to the left or to the right (e.g., several nanometers) compared to the intended location (e.g., designed location), the elongated shape retains the via 133A and the metal coating ( 109) makes it easy to achieve reliable electrical connection between them.

In FIG. 7B, via 133A is shown as having an elliptical shape, but has a rectangular shape, a race track shape (eg, a rectangle having a semicircular shape on both sides of the rectangle, see reference numeral 133B), and other suitable shapes. Other elongate shapes such as can also be used. The second via 133B, which is not visible in the cross-sectional view of FIG. 7A, connects the conductive feature 105 'with the metal coating 109. The second via 133B is shown as having a race track shape as an example. In other embodiments, the second via 133B may have the same shape (eg, elliptical) as the first via 133A, or may have other suitable shapes. Thus, in the example of FIG. 7B, the metal coating 109 is grounded by the vias 133A and vias 133B, thus further increasing the reliability of grounding of the metal coating 109.

7C illustrates a cross-sectional view of the semiconductor device 200 shown in FIGS. 7A and 7B along the cross section B1-B1 of FIG. 7B. As shown in FIG. 7C, via 133B electrically connects conductive feature 105 ′ with metal coating 109. Since the conductive feature 105 'is coupled to the ground contact pads 101A, 101B (see FIG. 7B), the metal coating 109 is grounded.

Next, in FIG. 8, an external connector 143 is formed over the conductive pad 137, the carrier 120 is separated, and a conductive layer 119 is formed over the sidewalls and top surface of the molding material 123. In some embodiments, the external connector 143 is conductive bumps, such as controlled collapse chip connection (C4) bumps or ball grid array (BGA) bumps, a material such as tin, or other suitable material such as silver or copper It may include. In embodiments where the outer connector 143 is tin solder bumps, the outer connector 143 may be formed by initially forming a tin layer through any suitable method such as electroplating, deposition, printing, solder transfer, ball placement. have. When the tin layer is formed on the conductive pad 137, reflow is performed to shape the material into a desired bump shape.

However, although the external connector 143 has been described above as a C4 bump or BGA bump, those skilled in the art will recognize that this is intended to be illustrative only and not intended to limit the embodiments. Rather, microbump, copper pillar, copper layer, nickel layer, lead free (LF) layer, electroless nickel electroless palladium immersion gold (ENEPIG) layer, Cu / LF layer, Sn / Any suitable type of external contacts, such as Ag layer, Sn / Pb, or combinations thereof, may alternatively be used. Any suitable external connector, and any suitable process for forming the external connector can be used for the external connector 143, and all such external connectors are intended to be completely included within the scope of the present embodiments.

In some embodiments, the carrier 120 is separated after the external connector 143 is formed on the conductive pad 137. For example, the structure shown in FIG. 6 in which the external connector 143 is formed is flipped upside down, and the external connector 143 is attached to a tape (eg, a dicing tape, not shown). In some embodiments, the tape is soft and has a thickness greater than the height of the external connector 143. Accordingly, the semiconductor device 200 may be compressed on the tape such that the external connector 143 is embedded (eg, compressed) on the tape. This may prevent electrical short circuit of the semiconductor device 200 in a subsequent process step for forming the conductive layer 119.

Next, the carrier 120 is separated by an appropriate method, such as chemical wet etching, plasma dry etching, mechanical peeling, CMP, mechanical grinding, heat baking, laser scanning, or wet stripping, as examples. In some embodiments, the carrier 120 is a glass carrier, and is separated by shining light on the carrier 120. For example, ultraviolet (UV) light emitted by an excimer laser can pass through a glass carrier and be absorbed near the glass / adhesive interface. Ultraviolet light initiates a photochemical process that destroys chemical bonds in the adhesive layer 121. As a result, the glass carrier 120 is easily removed.

In other embodiments, carrier separation may be performed before the external connector 143 is formed, for example, by attaching the redistribution structure 130 to the tape and then removing the carrier 120. After the carrier 120 is separated, the semiconductor device 200 is removed from the tape, upside down, and an external connector 143 is formed on the conductive pad 137. It is intended that these processing steps and other modifications be included entirely within the scope of the present disclosure. In embodiments in which a plurality of semiconductor devices 200 are simultaneously formed, a singulation process (not shown) is performed to form a plurality of individual semiconductor devices 200.

Next, a conductive layer 119 may be formed over the semiconductor device 200 that may include copper or other suitable material for electromagnetic interference protection, for example, using plating, sputtering, spraying, or other suitable forming method. do. The thickness of the conductive layer 119 may range from about 3 μm to about 5 μm, such as 3 μm, but other dimensions are also possible.

As shown in FIG. 8, conductive layer 119 is formed on the back side of dies 30/40 (eg, over adhesive layer 121) and along sidewalls of molding material 123. . Since the conductive layer 119 (also referred to as the metal coating 119) does not contact the substrates of the dies 30 and 40, diffusion of the material of the conductive layer 119 (eg, copper diffusion) is problematic. Therefore, a barrier layer similar to the barrier layer 157 (see FIG. 3) may be omitted when forming the conductive layer 119. Thus, in some embodiments, unlike the conductive coating 109 (see FIG. 3) having the underlying barrier layer 157 and the underlying interfacial layer 159 (see FIG. 3), the conductive layer 119 is a conductive layer. Without having a barrier layer between 119 and dies 30/40, it can be formed over sidewalls of molding material 123 and over adhesive layer 121. In some embodiments, the conductive layer 119 has a single layer structure and is formed of a suitable material, such as copper, in which case the conductive layer 119 (eg, copper) is, for example, a molding material 123 ), The adhesive layer 121, and one or more dielectric layers 132 in direct contact. In some embodiments, for example, depending on the material of the conductive layer 119, the conductive layer 119 and, for example, the molding material 123, the adhesive layer 121, and one or more dielectric layers 132 ) There may be an interfacial layer.

As shown in FIG. 8, the conductive layer 119 is grounded by being coupled to conductive lines 131A exposed at the sidewalls of the redistribution structure 130, in some embodiments. 8 also shows a via 133A of the redistribution structure 130, which via 133A is bonded to a conductive coating 109 over the die 30 (similar to FIGS. 7A and 7B). Thus, the conductive layer 119 and the conductive coating 109 are electrically grounded, for example, by being coupled to one or more ground contact pads 101A grounded by one or more external connectors 143A connected to electrical ground.

9-12 show cross-sectional views of a semiconductor device 300 in various fabrication steps, in accordance with some embodiments. Since similar numbers in FIGS. 9 to 12 indicate similar parts as in FIGS. 3 to 8, detailed description is not repeated. As shown in FIG. 9, the semiconductor dies 30 and 40 are attached to the carrier 120 through the adhesive layer 121, respectively. Note that in the example of FIG. 9, dies 30 and 40 are not coated with conductive coating 109 before being attached to carrier 120. The dies 30, 40 may be of the same type (eg, having the same function) or different types (eg, having a different function). After the dies 30 and 40 are attached to the carrier 120, a conductive coating 109 is conformally formed over the die 30, die 40, and carrier 120.

In FIG. 9, portions of the conductive coating 109 in the regions 150 ′, such as portions of the conductive coating 109 in contact with the semiconductor substrate of the dies 30 and 40, have the same structure as shown in FIG. 3. Can have Also, other portions of the conductive coating 109, such as portions of the conductive coating 109 over the dielectric material 107, over the adhesive layer 121, and over the carrier 120, are shown in FIG. 4. It can have the same structure as that.

Next, as shown in FIG. 10, a molding material 123 is formed over the carrier 120 and around the dies 30/40. A curing process may be performed to cure the molding material 123. Next, to expose the conductive pillars 105 of the die 30 and the conductive pillars 115 of the die 40, the (cured) molding material 123 is planarized, for example by a CMP process. The planarization process removes portions of the conductive coating 109 on the front side of the dies 30, 40. Thus, in the cross-sectional view of FIG. 10, after planarization, the remaining portions of the conductive coating 109 have a U-shape between the dies 30, 40, and the outer sidewalls of the dies 30, 40 (eg , Near the edges of the semiconductor device 300).

Next, in FIG. 11, a redistribution structure 130 is formed over the front side of the dies 30, 40 and is electrically coupled to the dies 30, 40. Redistribution structure 130 includes conductive lines 131 and vias 133. Conductive pads 137, which may be UBM structures, are formed on the top surface of the redistribution structure 130. At least one conductive line 131A of the redistribution structure 130 is exposed at the sidewall of the redistribution structure 130.

In the illustrated example of FIG. 11, the conductive coating 109 is connected to the redistribution structure 130 (eg, via via 133A), and grounded, as in the embodiments illustrated in FIGS. 7A and 7B. It is grounded through connection to the contact pad 101A. The conductive coating 109 can also be electrically coupled to the ground contact pad 111A of the die 40 through the redistribution structure 130, as shown in FIG. 11.

Next, as shown in FIG. 12, an external connector 143 is formed on the conductive pad 137, the carrier 120 is separated, and the conductive layer 119 is the back side of the dies 30/40. Over the fields (eg, over the adhesive layer 121) and over the sidewalls of the molding material 123. The conductive layer 119 is grounded by being coupled to a conductive line 131A exposed by a sidewall of the redistribution structure 130 in some embodiments.

In some embodiments, the conductive layer 119 is conformally formed, and may also have a thickness equal to that of the conductive coating 109 that is conformally formed. In the regions 119D, the conductive layer 119 and the conductive coating 109 are merged so that they are thicker than the conductive layer 119 or the conductive coating 109 in regions other than the regions 119D (eg Note that, forming a conductive layer (eg, copper) of about twice the thickness). For example, the thickness of the (merged) conductive layer between the dies 30, 40 may be twice the thickness of the conductive coating 109 along the sidewalls of the dies 30, 40. As another example, the thickness of the (merged) conductive layer between the dies 30 and 40 may be twice the thickness of the conductive coating 119 over the adhesive layer 121 or along the sidewalls of the molding material 123. . In the cross-sectional view of FIG. 12, the conductive layer 119 and the conductive coating 109 form a U-shape between the dies 30 and 40 and near the outer sidewalls of the dies 30 and 40. In other embodiments, the conductive layer 119 and the conductive coating 109 have different thicknesses.

13, 14, 15, 16, 17A, and 17B show various aspects of the semiconductor device 400 in various manufacturing steps, in accordance with some embodiments. In FIG. 13, a dielectric film, such as a photosensitive dielectric layer, is formed over the carrier 120. The dielectric film is patterned using a photolithography and / or etching process to form structures 151 and 153. In some embodiments, due to the photolithography process used, the width of structures 151 (or 153) in the cross-sectional view of FIG. 13 as structures 151 (or 153) are moved away from carrier 120 Decreases. For example, structures 151 and 153 have trapezoidal cross sections, as shown in FIG. 13. A more detailed description of structures 151/153 will be described later.

In FIG. 14, a conductive layer 155, such as copper or other suitable material capable of providing EMI shielding and / or protection, is formed over the structure shown in FIG. The conductive layer 155 may include a metal (eg, copper), and may be formed by sputtering, spraying, plating, or other suitable method. In some embodiments, the thickness of the conductive layer 155 is from about 3 μm to about 5 μm, although other dimensions are possible.

In some embodiments, structures 151 are dielectric structures. Referring briefly to FIG. 17B, which is a cross-sectional view of the semiconductor device 400 along the E-E cross-section in FIG. 17A, structures 151 may include die 30 and / or dielectric structures surrounding die 40. Structures 151 may be a continuous dielectric structure surrounding die 30 and / or die 40, as shown in FIG. 17B, in some embodiments. In other embodiments, structures 151 are die 30 and / or a plurality of individual segments of dielectric structures surrounding die 40 (eg, segments with a gap between them, not shown) ). The structures 151 are made of a dielectric material, but after being coated by the conductive layer 155, the coated structures 151 are electromagnetic around the semiconductor dies 30/40 to prevent or reduce EMI. A shielding structure is formed (see FIGS. 17A and 17B).

Referring again to FIG. 14, in some embodiments, structures 153 are dielectric structures and have a substantially cylindrical or truncated cone shape. In some embodiments, each coated structure 153 is coated with a conductive layer 155 and then forms conductive vias. Referring briefly to FIG. 17B, the coated structure 153 is a solid dielectric core (eg, structure 153) having a conductive layer 155 coated on outer sidewalls of the dielectric core, in accordance with some embodiments. )).

Referring now to FIG. 15, semiconductor dies 30 and 40 are attached to carrier 120 by adhesive layer 121. Next, the molding material 123 is deposited, if necessary, cured, and then planarized to expose the conductive pillars 105/115 of the dies 30/40. The planarization process may also, as shown in FIG. 15, over the tops of the conductive layers 155 (eg, distal to the carrier 120, the top surfaces of the structures 151/153). Portion of the conductive layer 155), and expose the dielectric material of the structures 151 and 153.

Next, in FIG. 16, a redistribution structure 130 is formed over the front sides of the dies 30, 40. Redistribution structure 130 may include conductive lines 131 and vias 133. A conductive pad 137 is formed over the redistribution structure 130 and is electrically coupled to the redistribution structure 130. As shown in FIG. 16, the conductive layer 155 is grounded by, for example, an electrical connection to the redistribution structure 130 through vias 133A, where the redistribution structure 130 includes ground contact pads ( 101A / 111A) and conductive lines and / or vias coupled to the conductive lines and / or vias that are electrically coupled to one or more external connectors 143 (see FIG. 17A). In some embodiments, conductive line 131A of redistribution structure 130 is exposed at the sidewall of redistribution structure 130.

Next, in FIG. 17A, an external connector 143 is formed, the carrier 120 is separated, and after the carrier separation, the exposed surface of the semiconductor device 400 (eg, after the dies 30/40) The surface near the side) is recessed by an appropriate grinding process and / or etching process, such as CMP. In some embodiments, the recessing process removes portions of the conductive layer 155 over the back sides of the dies 30, 40. The recessing process can also remove the adhesive layer 121. Thus, after the recessing process, in some embodiments, the dielectric material of structures 151/153 near the back sides of dies 30, 40 is exposed.

Next, another redistribution structure 160 is formed on the rear side of the dies 30 and 40 and may be formed using the same or similar formation method to the redistribution structure 130. Redistribution structure 160 is electrically coupled to the remaining portions of conductive layer 155, such as portions of conductive layers 155 over sidewalls of structure 151 and over sidewalls of structure 153. It includes conductive lines 161 and vias 163. In some embodiments, conductive lines 161 ′ of redistribution structure 160 include ground planes. Structures 151 with ground planes (eg, reference numeral 161 ') and conductive coating 155 form an EMI shield around and over dies 30 and 40. The EMI shield reduces EM interference to the dies 30, 40. The EMI shield can also suppress EM interference generated by the dies 30 and 40, thereby reducing EM interference.

17A, openings 164 are formed in the redistribution structure 160. The openings 164 can be formed by laser drilling, etching, or other suitable process. In some embodiments, the openings 164 are conductive lines that are electrically coupled to the conductive layer 155 over the structures 153 to electrically couple the redistribution structure 130 with the redistribution structure 160. Portions of the fields 161 are exposed. The exposed portion of conductive lines 161 also provides access for electrical connections at the back sides of dies 30 and 40. For example, another semiconductor device (not shown) can be disposed over the semiconductor device 400 and electrically and mechanically coupled to exposed portions of the conductive lines 161 to form a PoP package. .

17B is a cross-sectional view of the semiconductor device 400 of FIG. 17A along the E-E cross-section, and FIG. 17A is a cross-sectional view of the semiconductor device 400 of FIG. 17B along the F-F cross-section. For clarity, the molding material 123 is not shown in FIG. 17B. 17B, structures 151 include a continuous structure around dies 30 and 40, and conductive layer 155 is formed on both sidewalls of structures 151. 17B also shows structures 153 that may have a circular cross section, and a conductive layer 155 formed over the sidewalls of the structures 153.

17B is only a non-limiting example of structures 151 and 153, and other shapes and / or cross sections for structure 151 and structure 153 are also possible, and are within the scope of the present disclosure. It is intended to be fully included. For example, structure 151 may include a plurality of individual (eg, separate) segments of dielectric regions that collectively surround dies 30 and 40. As another example, the cross section of the structure 153 can have other suitable shapes, such as oval, square, or rectangular.

18 shows an electrical system 500 with EMI protection. The electrical system 500 includes a semiconductor device 510 similar to the semiconductor device 200 of FIG. 8 but with a metal coating 509 for both the die 30 and the die 40. The metal coating 509 can be similar to the metal coating 109 of FIG. 8. The semiconductor device 510 further has a conductive layer 519 that can be similar to the conductive layer 119 of FIG. 8. The electrical system 500 can be a printed circuit board (PCB) having conductive traces (eg, 521/523/525) and conductive pads (eg, 527) formed on and / or on top. The substrate 520 is further included. 18 also shows a connector 530 (eg, RF connector) mechanically and electrically coupled to the substrate 520. 18, the connector 530 has a signal terminal 533 and a ground terminal 531. The signal terminal 533 may be a terminal for carrying an RF signal (eg, an RF input signal to be processed by the electrical system 500), and the ground terminal 531 may be electrically grounded. In some embodiments, ground terminal 531 is a metal shell or metal mesh around signal terminal 533 to provide good EMI protection.

18, the two external connectors 541 and 545 of the semiconductor device 510 are electrically grounded, respectively connected to the conductive lines 521 and 525 of the substrate 520, and the conductive line Fields 521 and 525 are coupled to ground terminal 531 of connector 530. The signal terminal 533 of the connector 530 is connected to the external connector 543 of the semiconductor device 510, and the external connector 543 is connected to a signal (for example, an RF input signal from the connector 530). Is for In some embodiments, the conductive lines 521 and 525 are ground planes, and the conductive line 523 that carries the RF signal is disposed between the ground planes 521 and 525. System 500 has good EMI protection. For example, there are dual EMI shields for the semiconductor device 510 (eg, conductive coatings 509, 519). In addition, ground planes 521 and 525 disposed above and below conductive line 523 provide enhanced EMI isolation for conductive line 523 carrying RF signals. These features, combined with EMI shielding for the signal terminal 533 provided by the ground terminal 531, provide good EMI protection across the signal chain of the electrical system 500, thus providing excellent robustness against EM interference do.

Variations to the disclosed embodiments are possible, and are fully intended to be included within the scope of the present disclosure. For example, two semiconductor dies (eg, reference number 30 and reference number 40) are used as an example in a semiconductor device. However, more or less than two dies can be used in the formed semiconductor device. As another example, the shape of structure 151 (see FIG. 17B) can include two separate rings, each of which surrounds one of dies 30/40. Further, each of the two individual rings may be a continuous ring or a ring formed by a plurality of individual segments. As another example, the number and location of structures 153 can be changed from that shown in FIG. 17B without departing from the spirit of the present disclosure.

19 shows a flow diagram of a method of forming a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment methods illustrated in FIG. 19 are examples of many possible embodiment methods. Those skilled in the art will recognize numerous variations, alternatives, and modifications. For example, the various steps shown in FIG. 19 can be added, removed, replaced, rearranged, and repeated.

Referring to FIG. 19, in step 1010, a first die is attached to a carrier, wherein contact pads on the front side of the first die are backing the carrier. In step 1020, a molding material is formed over the carrier and around the first die. In step 1030, a redistribution structure is formed on the first side of the molding material, distal to the carrier, the redistribution structure comprising conductive lines electrically coupled to the first die, the first conductive feature of the redistribution structure Is exposed at the sidewall of the redistribution structure. In step 1040, the carriers are separated. In step 1050, a first conductive coating is formed along sidewalls of the molding material and a second side of the molding material opposite the first side, the first conductive coating being electrically applied to the first conductive feature of the redistribution structure. Connected.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or achieve the same advantages of the embodiments presented herein. You should know Those skilled in the art also appreciate that such equivalent arrangements do not depart from the spirit and scope of the disclosure, and those skilled in the art will appreciate various changes, substitutions, and modifications without departing from the spirit and scope of the disclosure. It should be appreciated that it can be done in the invention.

Examples

Example 1 In a semiconductor device,

A first die embedded in a molding material, wherein the contact pads of the first die are near a first side of the molding material;

A redistribution structure over the first side of the molding material;

A first metal coating along sidewalls of the first die and between the first die and the molding material; And

And a second metal coating on the second side of the molding material, along sidewalls of the molding material, opposite the first side.

Embodiment 2. The semiconductor device of embodiment 1, wherein the first metal coating and the second metal coating are electrically connected to a ground contact.

Example 3 The semiconductor device of example 1, wherein the redistribution structure comprises vias electrically coupled to the first metal coating.

Embodiment 4 In Embodiment 3, the via has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, wherein the second dimension is greater than the first dimension. A small semiconductor device.

Example 5 In Example 1, the first die has a plurality of conductive pillars coupled to each of the contact pads, and at least one of the plurality of conductive pillars is electrically connected to the first metal coating. Semiconductor device that is coupled to.

Embodiment 6. The semiconductor device of embodiment 5, wherein a distal, top surface of the plurality of conductive pillars relative to the contact pads is flush with the first side of the molding material.

Embodiment 7. The semiconductor device of embodiment 1, wherein the second metal coating is electrically coupled to a conductive line of the redistribution structure, and the conductive line is exposed at a sidewall of the redistribution structure.

Example 8. The method of Example 1, further comprising a second die embedded within the molding material and spaced laterally from the first die, wherein the contact pads of the second die are electrically coupled to the redistribution structure. Semiconductor device.

Example 9. The semiconductor device of example 8, wherein sidewalls of the second die are free of metal coating.

Embodiment 10. The semiconductor device of embodiment 9, wherein the first die and the second die have different functions.

Embodiment 11. The semiconductor device of embodiment 8, wherein the first metal coating extends continuously from sidewalls of the first die to sidewalls of the second die.

Example 12. In a semiconductor device,

A first die in the molding layer;

A first redistribution structure comprising conductive lines electrically coupled to contact pads of the first die and on a first side of the molding layer;

A second redistribution structure on the second side of the molding layer, opposite the first side;

A first conductive structure in the molding layer and spaced laterally from the first die-the first conductive structure,

 A first dielectric region around the first die; And

 And conductive coatings on both sides of the first dielectric region; And

And a via in the molding layer, wherein the via is coupled to a first conductive line of the first redistribution structure and a second conductive line of the second redistribution structure.

Example 13. In Example 12, the via is

A second dielectric region; And

And a second conductive coating on sidewalls of the second dielectric region.

Embodiment 14. The semiconductor device of embodiment 12, wherein the via is between the first die and the first conductive structure.

Embodiment 15. The semiconductor device of embodiment 12, wherein the first conductive structure is electrically coupled to at least one conductive line of the first redistribution structure and at least one conductive line of the second redistribution structure.

Embodiment 16 The semiconductor device of embodiment 15, wherein said second redistribution structure comprises a ground plane, and said first conductive structure is electrically coupled to said ground plane.

Example 17. In a method,

Attaching a first die to the carrier-contact pads on the front side of the first die facing the carrier-;

Forming a molding material over the carrier and around the first die;

Forming a redistribution structure on a first side of the molding material, distal to the carrier, the redistribution structure comprising conductive lines electrically coupled to the first die, the first conductive feature of the redistribution structure Is exposed on the sidewall of the redistribution structure-;

Separating the carrier; And

Forming a first conductive coating along sidewalls of the molding material and a second side of the molding material, opposite the first side, wherein the first conductive coating is the first of the redistribution structure. A method that is electrically connected to a conductive feature.

Embodiment 18. The method of embodiment 17, further comprising forming a second conductive coating on the sidewalls and rear side of the first die prior to attaching the first die to the carrier.

Embodiment 19. The Embodiment 18, wherein the first die has conductive pillars on the contact pads of the first die and electrically coupled to the contact pads, the first conductive pillar of the conductive pillars. Is extended to the edge of the first die, the first conductive pillar of the conductive pillars being electrically coupled to the second conductive coating through vias of the redistribution structure.

Example 20. The method of example 18, wherein the vias of the redistribution structure are electrically coupled to the second conductive coating.

Claims (10)

In a semiconductor device,
A first die in the molding layer;
A first redistribution structure electrically coupled to the first die and on a first side of the molding layer;
A second redistribution structure on the second side of the molding layer, opposite the first side; And
A first conductive structure in the molding layer and spaced laterally from the first die,
A first dielectric region around the first die; And
A first conductive coating on both sidewalls of the first dielectric region
Containing, the first conductive structure
Semiconductor device comprising a. According to claim 1,
The first conductive structure is a semiconductor device that is electrically coupled to the first redistribution structure and the second redistribution structure. According to claim 1,
Wherein the first conductive coating of the first conductive structure is electrically coupled to the ground contact pad of the first die through the first redistribution structure. According to claim 3,
The second redistribution structure includes a ground plane, and the first conductive coating of the first conductive structure is electrically coupled to the ground plane. According to claim 1,
And the first dielectric region of the first conductive structure extends continuously around the first die. According to claim 1,
And wherein the first dielectric region of the first conductive structure includes a plurality of individual segments enclosing the first die collectively. According to claim 1,
And a via in the molding layer and electrically coupled to the first redistribution structure and the second redistribution structure. According to claim 1,
The conductive line of the first redistribution structure is exposed at a sidewall of the first redistribution structure. In a semiconductor device,
A die embedded in the molding material;
A first redistribution structure on the first side of the molding material;
A second redistribution structure on the second side of the molding material, opposite the first side of the molding material; And
Electromagnetic interference (EMI) shield for the die
Including,
The EMI shield,
A first dielectric structure within the molding material and surrounding the die-a first surface of the first dielectric structure is at the same level as the first side of the molding material, and a second surface of the first dielectric structure is the At the same level as the second side of the molding material-;
A first conductive material on sidewalls of the first dielectric structure; And
Ground plane of the second redistribution structure
That includes,
Semiconductor device. In a semiconductor device,
A first die;
A dielectric structure spaced apart from the first die and surrounding the first die;
A molding material around the first die and the dielectric structure;
A conductive coating disposed between the dielectric structure and the molding material on sidewalls of the dielectric structure;
A first redistribution structure on the first side of the molding material; And
A second redistribution structure on the second side of the molding material, opposite the first side of the molding material
Including,
And the conductive coating is electrically coupled to the first redistribution structure and the second redistribution structure.

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