CN110534484B - Packaging structure - Google Patents
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- CN110534484B CN110534484B CN201910676042.XA CN201910676042A CN110534484B CN 110534484 B CN110534484 B CN 110534484B CN 201910676042 A CN201910676042 A CN 201910676042A CN 110534484 B CN110534484 B CN 110534484B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
A package structure, comprising: the semiconductor chip packaging structure comprises a carrier plate, a plurality of semiconductor chips, a plurality of plastic packaging layers and a plurality of bonding pads, wherein the plurality of bonding pads are arranged on a plurality of functional surfaces of the semiconductor chips which are bonded on the carrier plate, metal bumps are formed on the surfaces of the bonding pads, the functional surfaces are also provided with the first plastic packaging layers, the surfaces of the first plastic packaging layers are flush with the top surfaces of the metal bumps, and the first plastic packaging layers and the bonding pads on the functional surfaces of the semiconductor chips are bonded on the carrier plate; and the second plastic packaging layer is positioned on the carrier plate and wraps the non-functional surface and the side wall surface of the semiconductor chip. The first plastic packaging layer is arranged, so that the surface of each semiconductor chip is provided with a flat surface, when the first plastic packaging layers on a plurality of discrete semiconductor chips are bonded with the carrier plate, the first plastic packaging layers are provided with the flat surfaces, so that high adhesive force is provided between each semiconductor chip and the carrier plate, and when the second plastic packaging layers covering the plurality of semiconductor chips are formed on the carrier plate, all the semiconductor chips cannot generate offset on the carrier plate when the second plastic packaging layers are impacted by injection molding or plastic transfer pressure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a fan-out type packaging structure.
Background
The fan-in chip package is a manufacturing method that rewiring and solder ball bump preparation are performed on the whole wafer, and finally the wafer is cut into single chips. The final package size of the package is equivalent to the chip size, and the package can be miniaturized and lightened, and is widely applied to portable equipment. Although the chip size after packaging can be greatly reduced by the chip fan-in type packaging, the number of the implanted balls on a single chip is limited, and the wafer packaging form is difficult to be applied to the chip with high density I/O port number. Therefore, for a chip with a higher I/O density, if wafer level packaging is performed, in order to ensure that the chip to be packaged and the printed circuit board can be interconnected, the high density I/O must be fanned out to a low density package pin, i.e., chip fan-out type packaging is performed, and compared with the conventional chip fan-in type packaging, the chip fan-out type packaging can achieve a smaller packaging size, better electrical and thermal properties and higher packaging density.
Currently, the main processes of chip fan-out packaging include: firstly, the front surfaces (the front surfaces are the surfaces with the bonding pads) of a plurality of divided semiconductor chips are bonded on a carrier plate through adhesive tapes or adhesive layers; forming a plastic packaging layer covering the semiconductor chips on the carrier plate, and carrying out plastic packaging on the plurality of semiconductor chips on the carrier plate; stripping the carrier plate, and then re-wiring the front surface of the semiconductor chip to form a re-wiring layer connected with the bonding pad; forming a solder ball connected with the rewiring layer on the rewiring layer; and finally, cutting to form a plurality of discrete packaging structures.
However, in the packaging structure formed by the existing chip fan-out type packaging process, the electrical connection between the rewiring layer and the semiconductor chip is easy to be unstable, and the performance of the packaging structure is influenced.
Disclosure of Invention
The invention aims to solve the technical problems of improving the electrical connection stability of a rewiring layer and a semiconductor chip in a packaging structure formed by a chip fan-out type packaging process and improving the performance of the packaging structure.
The present invention provides a package structure, comprising:
a carrier plate;
the semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, wherein the functional surface is provided with a plurality of bonding pads, metal bumps are formed on the surfaces of the bonding pads, the functional surface is also provided with a first plastic packaging layer, the surface of the first plastic packaging layer is flush with the top surfaces of the metal bumps, and the first plastic packaging layer and the bonding pads on the functional surface of the semiconductor chip are bonded on the carrier plate;
and the second plastic packaging layer is positioned on the carrier plate and wraps the non-functional surface and the side wall surface of the semiconductor chip.
Optionally, the semiconductor chip is formed by an integrated manufacturing process, including the steps of: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming a first plastic packaging material layer covering the metal lug and the functional surface; flattening the first plastic package material layer, exposing the surface of the isolation sacrificial layer, taking the rest first plastic package material layer as a first plastic package layer, and enabling the surface of the first plastic package layer to be flush with the surface of the isolation sacrificial layer; and after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips.
Optionally, the first plastic package material layer and the second plastic package layer are made of resin, and the first plastic package material layer and the second plastic package layer are formed by an injection molding or rotational molding process.
Optionally, the size of the material particles in the first plastic package layer is smaller than the size of the material particles in the second plastic package layer.
Optionally, the metal bump further includes an isolation sacrificial layer formed on a top surface or a top and sidewall surface of the metal bump, and a surface of the first molding compound layer is flush with a surface of the isolation sacrificial layer.
Optionally, the semiconductor chip is formed by an integrated manufacturing process, including the steps of: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming an isolation sacrificial layer on the metal bump; forming a first plastic packaging material layer covering the isolation sacrificial layer and the functional surface; flattening the first plastic packaging material layer, exposing the surface of the isolation sacrificial layer, and taking the rest first plastic packaging material layer as a first plastic packaging layer; and after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips.
Optionally, the isolation sacrificial layer is made of silicon oxide, silicon nitride, or silicon oxynitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the packaging structure of the invention comprises: the semiconductor chip packaging structure comprises a carrier plate, a plurality of semiconductor chips, a plurality of plastic packaging layers and a plurality of bonding pads, wherein the functional surfaces of the semiconductor chips are bonded on the carrier plate, metal bumps are formed on the surfaces of the bonding pads, the functional surfaces of the semiconductor chips are also provided with the first plastic packaging layers, the surfaces of the first plastic packaging layers are flush with the top surfaces of the metal bumps, and the first plastic packaging layers and the bonding pads on the functional surfaces of the semiconductor chips are bonded on the carrier plate; and the second plastic packaging layer is positioned on the carrier plate and wraps the non-functional surface and the side wall surface of the semiconductor chip. The existence of the first plastic packaging layer ensures that the surface of each semiconductor chip has a flat surface, when the first plastic packaging layers on a plurality of discrete semiconductor chips are bonded with the carrier plate, because the first plastic packaging layer has a flat surface, each semiconductor chip and the carrier plate have higher adhesive force, when the second plastic packaging layer for coating a plurality of semiconductor chips is formed on the carrier plate, when the semiconductor chip is impacted by the pressure of injection molding or transfer molding, the positions of all the semiconductor chips on the carrier plate can not be deviated, so that a pre-packaged panel is formed after the carrier plate is removed, when a rewiring layer connected with the bonding pads is formed on the back surface of the pre-packaged panel, the connection position of the rewiring layer and the corresponding bonding pads can not generate deviation, therefore, the electrical connection performance between the rewiring layer and the bonding pad is improved, and the stability and the reliability of the packaging structure are improved.
Further, the metal lug still including the isolation sacrificial layer that is located the top surface or the top and the lateral wall surface of metal lug formed, first plastic packaging material layer covers the first plastic packaging layer of isolation sacrificial layer gets rid of partial first plastic packaging material layer and isolation sacrificial layer in order to expose the metal lug through the technology that chemical mechanical polishing technology and subsequent sculpture technology both combined together, specifically, adopt chemical mechanical polishing technology to get rid of part earlier first plastic packaging material layer exposes the surface of isolation sacrificial layer, remaining first plastic packaging material layer is as first plastic packaging layer, then adopts the sculpture technology to get rid of on the metal lug top surface isolation sacrificial layer exposes the top surface of metal lug, therefore can not only expose the top surface of metal lug to because adopt chemical mechanical polishing technology to get rid of part when first plastic packaging material layer, exposed is the isolation sacrificial layer surface, and the grinding pad in the grinding equipment can not contact with the metal lug, so that grinding force can not be brought to the metal lug, the metal lug is better prevented from loosening or falling off from the bonding pad, the precision of the connecting position between the subsequently formed rewiring layer and the corresponding metal lug is further improved, and the electrical connection performance of the rewiring layer and the metal lug is further improved.
Further, the forming process of the semiconductor chip is as follows: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming a first plastic packaging material layer covering the metal lug and the functional surface by an injection molding or plastic transfer process; flattening the first plastic packaging material layer, exposing the top surface of the metal bump, and taking the rest first plastic packaging material layer as a first plastic packaging layer; and after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips. When the injection molding or plastic conversion process is carried out, the bottom of the wafer is fixed in a mold, the wafer cannot move in the mold of the injection molding or plastic conversion equipment due to the large area of the bottom of the wafer, so that the formed first plastic package material layer has a flat surface, the first plastic package material layer is subsequently flattened to expose the top surface of the metal bump, the rest first plastic package material layer also has a flat surface as the first plastic package layer, after the wafer is cut, the formed plurality of discrete semiconductor chips all have flat surfaces, the thicknesses of the plurality of semiconductor chips can be kept consistent, and when the first plastic package layers and the bonding pads on the plurality of discrete semiconductor chips are bonded with the support plate, the first plastic package layers have flat surfaces, so that high adhesive force exists between each semiconductor chip and the support plate.
Furthermore, the size of the material particles in the first plastic package layer is smaller than that of the material particles in the second plastic package layer formed subsequently, so that the first plastic package layer can better fill gaps between and on two sides of the metal bumps, the first plastic package layer is more tightly contacted with the side faces of the metal bumps, and the first plastic package layer has a better fixing effect on the metal bumps.
Drawings
Fig. 1-19 are schematic structural diagrams illustrating a process of forming a package structure according to an embodiment of the invention.
Detailed Description
As mentioned in the background art, in the package structure formed by the conventional fan-out package process of the chip, the electrical connection between the rewiring layer and the semiconductor chip is easily unstable, which affects the performance of the package structure.
Research shows that the reason why the electrical connection between the rewiring layer and the semiconductor chip in the conventional fan-out package structure is easily unstable is: the connection position of the rewiring layer and the pad of the semiconductor chip is shifted.
Further research has found that the reason why the connection position of the rewiring layer and the pad of the semiconductor chip is shifted is: when fan-out packaging is carried out, one side of a plurality of semiconductor chips with bonding pads is bonded on a carrier plate through an adhesive tape or an adhesive layer, because the surface flatness of different semiconductor chips is different, particularly when metal bumps are also formed on the bonding pads, the surface flatness difference of different chips is larger, so that when different semiconductor chips are bonded with the carrier plate through the adhesive tape or the adhesive layer, the adhesive force between different semiconductor chips and the carrier plate is different, when a plastic package layer is formed, part of the semiconductor chips generate offset at the position on the carrier plate under the action of injection molding pressure or impact force due to insufficient adhesive force, and after the carrier plate is removed, when a re-wiring layer is formed on the plastic package layer and the front surface of the semiconductor chip, the connecting position between the re-wiring layer and the bonding pads on the semiconductor chips with offset is generated, thereby affecting the electrical connection performance of the rewiring layer and the bonding pad in the formed fan-out packaging structure.
The invention provides a packaging structure and a forming method thereof, wherein the forming method comprises the steps of providing a plurality of semiconductor chips, wherein a functional surface of each semiconductor chip is provided with a bonding pad, a metal bump is formed on the surface of the bonding pad, the functional surface is also provided with a first plastic packaging layer, and the surface of the first plastic packaging layer is flush with the top surface of the metal bump; bonding the first plastic packaging layers and the bonding pads on the functional surfaces of the plurality of semiconductor chips on the carrier plate; and forming a second plastic packaging layer which coats the non-functional surface and the side wall surface of the semiconductor chip on the carrier plate. The existence of the first plastic packaging layer ensures that the surface of each semiconductor chip has a flat surface, when the first plastic packaging layers on a plurality of discrete semiconductor chips are bonded with the carrier plate, because the first plastic packaging layer has a flat surface, each semiconductor chip and the carrier plate have higher adhesive force, when the second plastic packaging layer for coating a plurality of semiconductor chips is formed on the carrier plate, when the semiconductor chip is impacted by the pressure of injection molding or transfer molding, the positions of all the semiconductor chips on the carrier plate can not be deviated, so that a pre-packaged panel is formed after the carrier plate is removed, when a rewiring layer connected with the bonding pads is formed on the back surface of the pre-packaged panel, the connection position of the rewiring layer and the corresponding bonding pads can not generate deviation, therefore, the electrical connection performance between the rewiring layer and the bonding pad is improved, and the stability and the reliability of the packaging structure are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-19 are schematic structural diagrams illustrating a process of forming a package structure according to an embodiment of the invention.
Referring to fig. 1 to 7, a plurality of semiconductor chips 160 (refer to fig. 7) are provided, each semiconductor chip 160 includes a functional surface 11 and a non-functional surface 12 opposite to the functional surface 11, the functional surface 11 has a plurality of pads 101 thereon, metal bumps 102 are formed on the surfaces of the pads 101, the functional surface 11 also has a first molding compound layer 103 thereon, and the surface of the first molding compound layer 103 is flush with the top surfaces of the metal bumps 102.
The semiconductor chip 160 has a functional surface 11 and a non-functional surface 12 opposite to the functional surface 11, the functional surface is a surface on which an integrated circuit and a bonding pad are formed, the integrated circuit is formed in the semiconductor chip 160, a plurality of bonding pads 101 are formed on the functional surface of the semiconductor chip 160, the bonding pads 101 are electrically connected to the integrated circuit in the semiconductor chip 160, and the bonding pads 101 serve as ports for electrically connecting the integrated circuit in the semiconductor chip 160 to the outside. In one embodiment, the integrated circuit in the semiconductor chip 160 may include several semiconductor devices (such as transistors, memories, sensors, diodes and/or transistors, etc.) and interconnection structures (including metal wires and metal plugs) for connecting the semiconductor devices. The peripheral surface between the functional surface 11 and the non-functional surface 12 of the semiconductor chip 160 is a sidewall of the semiconductor chip 160.
The semiconductor chip 160 is formed by a semiconductor integrated manufacturing process, and a specific process of forming the semiconductor chip 160 is described in detail below with reference to fig. 1 to 7.
Firstly, referring to fig. 1 and fig. 2, fig. 2 is a schematic cross-sectional structure view along a cutting line AB in fig. 1, providing a wafer 100, where the wafer 100 includes a plurality of chip regions arranged in rows and columns and a dicing street region located between the chip regions; correspondingly forming a plurality of semiconductor chips 160 in a plurality of chip areas of the wafer 100; a plurality of pads 101 are formed on the functional surface of the semiconductor chip 160.
In one embodiment, the material of the wafer 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. The material of the bonding pad 101 may be one of aluminum, nickel, tin, tungsten, platinum, copper, and titanium.
Referring to fig. 3 and 4, fig. 4 is an enlarged schematic view of a metal bump formed on one pad in fig. 3, and a metal bump 102 is formed on a surface of the pad 101.
The metal bump 102 protrudes from the surface of the pad 101 and the functional surface, in an embodiment, the metal bump 102 is formed by one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver, which are used as materials of the metal bump 102 to raise the pad 101 for subsequent wiring, and the metal bump 102 also has the functions of protecting the pad and conducting heat.
In one embodiment, the process of forming the metal bump 102 includes: forming an insulating layer 150 on the functional surface 11 of the semiconductor chip 160, wherein the insulating layer 150 has a first opening exposing a part of the surface of the pad 101, the insulating layer 150 may be a single-layer or multi-layer stacked structure, and the material of the insulating layer 150 may be one or more of silicon nitride, silicon oxide, and resin material; forming an Under Bump Metal (UBM) on the surface of the insulating layer 150 and the sidewall and bottom surfaces of the first opening, the under bump metal being a single-layer or multi-layer stacked structure; forming a mask layer with a second opening on the convex lower metal layer, wherein the second opening at least exposes the surface of the convex lower metal layer in the first opening; forming a metal bump 102 in the second opening of the fox through an electroplating process; removing the mask layer; and etching to remove the under-bump metal layer on the surface of the insulating layer on both sides of the metal bump 102.
Referring to fig. 5, a first molding compound layer 123 is formed on the surface of the wafer 100 (the functional surface of the semiconductor chip 160), and the first molding compound layer 123 covers the metal bumps 102.
The first plastic package material layer 123 covers the top and the side wall surface of the metal bump 102, the first plastic package material layer 123 has a flat surface, the forming process of the first plastic package material layer 123 is an injection molding or transfer molding process, the first plastic package layer 103 is made of resin, and the resin can be one or more of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.
Specifically, when the injection molding or transfer molding process is performed, the bottom of the wafer 100 is fixed in a mold, because the area of the bottom of the wafer is large, the wafer does not move in the mold of the injection molding or transfer molding device, so that the formed first plastic package material layer 123 has a flat surface, the first plastic package material layer 123 is subsequently planarized, the top surfaces of the metal bumps 102 are exposed, the remaining first plastic package material layer serving as the first plastic package layer 103 also has a flat surface, after the wafer is cut, the formed plurality of discrete semiconductor chips 160 all have flat surfaces, the thicknesses of the plurality of semiconductor chips 160 can be kept consistent, and when the first plastic package layer 103 and the bonding pads on the plurality of discrete semiconductor chips 160 are subsequently bonded with the carrier plate, because the first plastic package layer 103 has a flat surface, the adhesive force between each semiconductor chip 160 and the carrier plate is high, therefore, when a second plastic package layer covering a plurality of semiconductor chips 160 is formed on the carrier plate subsequently and is impacted by pressure of injection molding or rotational molding, all the semiconductor chips 160 cannot generate offset on the carrier plate, the carrier plate is removed subsequently, a pre-packaged panel is formed, and when a rewiring layer connected with the bonding pad is formed on the back surface of the pre-packaged panel, the connection position of the rewiring layer and the corresponding bonding pad cannot generate offset, so that the electrical connection performance between the rewiring layer and the bonding pad is improved, and the stability and the reliability of the packaging structure are improved.
In addition, the formed first plastic package layer 103 is also used for fixing the metal bump 102, and flattening the first plastic package material layer, so as to prevent the metal bump 102 from loosening or falling off from the pad 101.
The formed first molding compound layer 103 may also be used to protect the metal bump 102, and prevent the metal bump 102 from being contaminated or damaged in a subsequent process.
In an embodiment, the size of the material particles in the first plastic package layer 103 is smaller than the size of the material particles in the second plastic package layer to be formed later, so that the first plastic package layer 103 can better fill the gaps between the metal bumps 102 and the gaps on both sides, and the first plastic package layer 103 is more tightly contacted with the side surfaces of the metal bumps 102, thereby the first plastic package layer 103 has a better fixing effect on the metal bumps 102.
Referring to fig. 6, the first plastic package material layer is planarized to expose the top surfaces of the metal bumps 102, the remaining first plastic package material layer serves as a first plastic package layer 103, and the surface of the first plastic package layer 103 is flush with the top surfaces of the metal bumps 102.
And planarizing the first plastic packaging material layer 103 by adopting a chemical mechanical polishing process.
Referring to fig. 7, after the first molding compound layer 103 is planarized, the wafer 100 is diced along the dicing street regions (refer to fig. 6), and a plurality of discrete semiconductor chips 160 having the first molding compound layer 103 are formed.
In other embodiments, referring to fig. 8, the formed metal bump further includes an isolation sacrificial layer 120 formed on the top surface or the top and sidewall surfaces of the metal bump 102; after the isolation sacrificial layer 120 is formed, a first molding compound layer 123 is formed to cover the isolation sacrificial layer 120 and the functional surface of the semiconductor chip 160. Referring to fig. 9, the first plastic package material layer 123 is planarized to expose the surface of the isolation sacrificial layer 120, the remaining first plastic package material layer is used as the first plastic package layer 103, and the surface of the first plastic package layer 103 is flush with the surface of the isolation sacrificial layer 120 on the metal bump. Referring to fig. 10, after the first molding compound layer is planarized, the wafer is diced to form a plurality of discrete semiconductor chips.
It has been found that if the first molding compound layer 123 is formed to directly cover the top surfaces of the metal bumps 102, when a portion of the first molding compound layer 123 is removed by planarization (chemical mechanical polishing process) to expose the top surfaces of the metal bumps 102, the polishing force may cause a portion of the metal bumps 102 to loosen or fall off the pads 101 during planarization (chemical mechanical polishing process) of the first molding compound layer 123. Therefore, in this embodiment, before the first plastic package material layer 103 is formed, an isolation sacrificial layer 120 is formed on the top surface or the top and sidewall surfaces of the metal bump 102 (the isolation sacrificial layer 120 is a part of the metal bump 102), and a part of the first plastic package material layer and the isolation sacrificial layer 120 may be removed by a process combining a chemical mechanical polishing process and a subsequent etching process to expose the metal bump, specifically, a chemical mechanical polishing process is first used to remove a part of the first plastic package material layer to expose the surface of the isolation sacrificial layer, the remaining first plastic package material layer is used as a first plastic package layer, and then an etching process is used to remove the isolation sacrificial layer on the top surface of the metal bump 102 to expose the top surface of the metal bump, so that not only the top surface of the metal bump is exposed, but also when a part of the first plastic package material layer is removed by a chemical mechanical polishing process, the exposed surface is the surface of the isolation sacrificial layer, and a grinding pad in grinding equipment cannot be in contact with the metal bump, so that grinding force cannot be brought to the metal bump, the metal bump 102 is better prevented from loosening or falling off from the bonding pad 101, the precision of the connecting position between a subsequently formed rewiring layer and the corresponding metal bump is further improved, and the electrical connection performance of the rewiring layer and the metal bump 102 is further improved.
In addition, the formation of the isolation sacrificial layer 120 can also improve the adhesion between the first molding layer 103 and the metal bump 102.
In an embodiment, the isolation sacrificial layer 120 is made of silicon oxide, silicon nitride, or silicon oxynitride.
Referring to fig. 10, the wafer 100 is diced along the scribe line region (refer to fig. 9), and a plurality of discrete semiconductor chips 160 having the isolation sacrificial layer 120 and the first molding compound 103 are formed.
Referring to fig. 11 or 13, a carrier plate 107 is provided; the first molding layer 103 and the pads 102 on the functional side of the semiconductor chips 160 are bonded to the carrier board 107.
The carrier plate 107 serves as a support platform for a subsequent process, the carrier plate 107 may be a glass carrier plate, a silicon carrier plate or a metal carrier plate, and the carrier plate 107 may also be a carrier plate made of other suitable materials.
The first molding compound 103 and the pads 102 on the semiconductor chip 160 are bonded to the surface of the carrier board 107 through an adhesive layer, and the functional surface (or the pads 101) of the semiconductor chip 160 faces the adhesive surface of the carrier board 107.
The adhesive layer may be made of various materials, and in one embodiment, the adhesive layer is made of a UV glue. UV glue is a glue material that reacts to ultraviolet radiation of a particular wavelength. The UV adhesive can be divided into two types according to the change of viscosity after ultraviolet irradiation, wherein one type is a UV curing adhesive, namely, a photoinitiator or a photosensitizer in the material generates active free radicals or cations after absorbing ultraviolet light under the irradiation of ultraviolet light, and initiates the chemical reaction of monomer polymerization, crosslinking and grafting, so that the UV curing adhesive is converted from a liquid state to a solid state within several seconds, and the surface of an object contacted with the UV curing adhesive is bonded; another type of UV glue is highly viscous in the absence of UV radiation, and the cross-linking chemical bonds within the material are broken after UV radiation, resulting in a substantial decrease or loss of viscosity. The latter is the UV glue used for the adhesive layer. The adhesive layer may be formed by a film attaching process, a glue printing process, or a glue rolling process.
In other embodiments, the material of the bonding layer may also be epoxy glue, polyimide glue, polyethylene glue, benzocyclobutene glue or polybenzoxazole glue.
The semiconductor chips 160 are uniformly bonded to the carrier plate 107 in rows and columns.
Referring to fig. 12 or 13, a second molding layer 109 is formed on the carrier 107 to cover the non-functional surface and the sidewall surface of the semiconductor chip 160.
The second molding compound 109 is used to seal and fix the semiconductor chip 160 for forming a pre-packaged panel in the following. The second plastic package layer 109 also covers the surface of the carrier board 107 and the surface of the sidewall of the first plastic package layer 103.
The material of the second molding compound layer 109 may be one or more of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.
The second molding layer 109 may be formed by injection molding (injection molding) or transfer molding (transfer molding) or other suitable processes.
When the second plastic package layer 109 is formed, the first plastic package layer 103 enables the surface of each semiconductor chip 160 to have a flat surface, when the first plastic package layers 103 on a plurality of discrete semiconductor chips 160 are bonded with the carrier board, because the first plastic package layers 103 have flat surfaces, the adhesion force between each semiconductor chip 160 and the carrier board is high, when the second plastic package layers 109 covering a plurality of semiconductor chips 160 are formed on the carrier board 107, when the second plastic package layers 109 covering the plurality of semiconductor chips 160 are impacted by the pressure of injection molding or transfer molding, the positions of all the semiconductor chips 160 on the carrier board cannot be shifted, so that a pre-packaged panel is formed after the carrier board 107 is removed, when a re-wiring layer connected with a pad is formed on the back of the pre-packaged panel, the connection position of the re-wiring layer and the corresponding pad cannot be shifted, and the electrical connection performance between the re-wiring layer and the pad is improved, thereby improving the stability and reliability of the package structure.
Referring to fig. 14 or fig. 15 and 16 in combination, fig. 14 is performed on the basis of fig. 12, fig. 15 is performed on the basis of fig. 13, and fig. 16 is performed on the basis of fig. 15, the carrier board 107 (see fig. 12 or fig. 13) is peeled off to form a pre-cover board 21, and the pads 103 are exposed from the back surface of the pre-cover board 21.
The adhesive layer is removed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal baking, or the like, so that the carrier plate 107 is peeled off.
In an embodiment, when the isolation sacrificial layer is not formed, the metal bump 102 is directly exposed after the carrier is stripped.
In another embodiment, when forming the isolation sacrificial layer 120, referring to fig. 15, the carrier is first stripped to expose the surface of the isolation sacrificial layer 120; referring to fig. 16, the isolation sacrificial layer 120 (refer to fig. 15) on the top surface of the metal bump 102 is removed by an etching process to expose the top surface of the metal bump 102, specifically, an opening 121 in the first molding compound layer 103 is formed at a position where the isolation sacrificial layer 120 is removed, and the opening 121 exposes the top surface of the metal bump 102. In this embodiment, by forming the isolation sacrificial layer 120, a chemical mechanical polishing process may be first used to remove a portion of the first plastic package material layer to expose the surface of the isolation sacrificial layer, and then an etching process is used to remove the isolation sacrificial layer on the top surface of the metal bump 102 to expose the top surface of the metal bump 102, so that the top surface of the metal bump can be exposed through the combination of the specific structure and the specific process, and since the surface of the isolation sacrificial layer is exposed when the chemical mechanical polishing process is used to remove a portion of the first plastic package material layer, a polishing pad in a polishing device does not contact with the metal bump, and thus does not bring a polishing force to the metal bump, thereby better preventing the metal bump 102 from loosening or falling off the pad 101, and further improving the precision of a connection position between a subsequently formed rewiring layer and the corresponding metal bump, the electrical connection performance of the re-wiring layer and the metal bump 102 is further improved.
The etching process for removing the isolation sacrificial layer 120 is wet etching or dry etching. In an embodiment, when the isolation sacrificial layer 120 is made of silicon nitride, the isolation sacrificial layer 120 is removed by wet etching, and an etching solution used in the wet etching is a phosphoric acid solution.
Referring to fig. 17 and 18, an external contact structure connected to the metal bump 102 is formed on the back surface of the pre-cover plate 21.
The external contact structure includes a redistribution layer 110 on the back surface of the pre-packaged panel 21 and connected to the metal bumps 102, and an external contact 112 on the redistribution layer 110 and connected to the redistribution layer 110, and the metal bumps 102 on each semiconductor chip 160 are connected to the corresponding external contact structure. The external contact 112 is a solder ball, or the external contact 112 may also include a metal pillar and a solder ball on the surface of the metal pillar.
In a specific embodiment, the formation of the redistribution layer 110 and the external contacts 112 includes: after the carrier board is stripped, a rewiring layer 110 is formed on the back surface of the pre-sealing panel 21; forming an insulating layer 111 on the back surfaces of the rewiring layer 110 and the pre-sealing plate 21, wherein an opening for exposing part of the surface of the rewiring layer 110 is formed in the insulating layer 111, and the insulating layer 121 can be made of silicon nitride, borosilicate glass, phosphorosilicate glass or borophosphosilicate glass; external contacts 112 are formed in the openings.
Referring to fig. 19, after forming the external contact structure, further comprising: the pre-cover board is cut to form a plurality of discrete package structures 22.
It should be noted that the process of forming the external contact structure on the basis of fig. 16 is substantially the same as the process of forming the external contact structure in fig. 17-18, and is not described again here.
An embodiment of the present invention further provides a package structure, please refer to fig. 12 or fig. 13, including:
a carrier plate 107;
a plurality of semiconductor chips 160 adhered on the carrier board 107, each semiconductor chip 160 comprising a functional surface 11 and a non-functional surface 12 opposite to the functional surface 11, the functional surface 11 having a plurality of pads 101, the surface of each pad 101 having a metal bump 102 formed thereon, the functional surface 11 further having a first molding compound layer 103 thereon, the surface of the first molding compound layer 103 being flush with the top surface of the metal bump, the first molding compound layer 103 and the pads 101 on the functional surface of the semiconductor chip 160 being adhered on the carrier board 107;
and a second molding compound layer 109 positioned on the carrier plate 107 and covering the non-functional surface and the sidewall surface of the semiconductor chip 160.
In one embodiment, the semiconductor chip 160 is formed by an integrated manufacturing process, including the steps of: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming a first plastic packaging material layer covering the metal lug and the functional surface; flattening the first plastic package material layer, exposing the surface of the isolation sacrificial layer, taking the rest first plastic package material layer as a first plastic package layer, and enabling the surface of the first plastic package layer to be flush with the surface of the isolation sacrificial layer; and after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips.
In an embodiment, the material of the first plastic package material layer and the second plastic package layer 109 is resin, and the forming process of the first plastic package material layer and the second plastic package layer 109 is an injection molding or rotational molding process.
In one embodiment, the size of the material particles in the first molding layer 103 is smaller than the size of the material particles in the second molding layer 109.
In an embodiment, referring to fig. 13, the metal bump 102 further includes an isolation sacrificial layer 120 formed on a top surface or a top and sidewall surface of the metal bump 102, and a surface of the first molding compound layer 103 is flush with a surface of the isolation sacrificial layer 120.
In one embodiment, the semiconductor chip 160 is formed by an integrated manufacturing process, including the steps of: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming an isolation sacrificial layer on the metal bump; forming a first plastic packaging material layer covering the isolation sacrificial layer and the functional surface; flattening the first plastic packaging material layer, exposing the surface of the isolation sacrificial layer, and taking the rest first plastic packaging material layer as a first plastic packaging layer; and after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips.
The isolation sacrificial layer 120 is made of silicon oxide, silicon nitride or silicon oxynitride.
It should be noted that, in the present embodiment, for other limitations or descriptions of the package structure, please refer to corresponding limitations or descriptions of the formation process of the package structure, which are not repeated in the present embodiment.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A package structure, comprising:
the semiconductor chip comprises a plurality of semiconductor chips, each semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, the functional surface is provided with a plurality of bonding pads, metal bumps are formed on the surfaces of the bonding pads, the functional surface is also provided with a first plastic packaging layer, and the first plastic packaging layer is provided with an opening for exposing the surfaces of the metal bumps;
the second plastic package layer wraps the non-functional surface and the side wall surface of the semiconductor chip, and the size of the material particles in the first plastic package layer is smaller than that of the material particles in the second plastic package layer;
an external contact structure connected to the metal bump through the opening;
wherein the external contact structure and the opening exposing the surface of the metal bump are formed by the following processes: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, each semiconductor chip comprises a functional surface, and a bonding pad is arranged on each functional surface; forming a metal bump on the pad; forming an isolation sacrificial layer on the metal bump; forming a first plastic packaging material layer covering the isolation sacrificial layer and the functional surface; flattening the first plastic package material layer by a chemical mechanical polishing process to expose the surface of the isolation sacrificial layer, wherein the rest first plastic package material layer is used as a first plastic package layer, and the surface of the first plastic package layer is flush with the surface of the isolation sacrificial layer; after the first plastic packaging material layer is flattened, cutting the wafer to form a plurality of discrete semiconductor chips; providing a carrier plate; bonding the first plastic packaging layers and the bonding pads on the functional surfaces of the plurality of semiconductor chips on the carrier plate; forming a second plastic packaging layer wrapping the non-functional surface and the side wall surface of the semiconductor chip on the carrier plate; stripping the carrier plate to form a pre-sealing panel; etching to remove the isolation sacrificial layer, and forming an opening exposing the metal bump in the first plastic package layer, so that when the opening exposing the metal bump is formed in the first plastic package layer by removing part of the first plastic package material layer and removing the isolation sacrificial layer through the combined process of the chemical mechanical polishing process and the etching process, the metal bump can be better prevented from loosening or falling off from the pad; and forming an external contact structure connected with the metal bump on the back surface of the pre-cover plate.
2. The package structure of claim 1, wherein the first molding compound layer and the second molding compound layer are made of resin, and a forming process of the first molding compound layer and the second molding compound layer is an injection molding or rotational molding process.
3. The package structure of claim 1, wherein the isolation sacrificial layer is made of silicon oxide, silicon nitride or silicon oxynitride.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910676042.XA CN110534484B (en) | 2019-07-25 | 2019-07-25 | Packaging structure |
| US17/629,040 US20220278075A1 (en) | 2019-07-24 | 2020-07-17 | Packaging structure and formation method thereof |
| PCT/CN2020/102767 WO2021013097A1 (en) | 2019-07-25 | 2020-07-17 | Packaging structure and formation method thereof |
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| CN201910676042.XA CN110534484B (en) | 2019-07-25 | 2019-07-25 | Packaging structure |
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| CN110534484B true CN110534484B (en) | 2022-04-12 |
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