KR20200011830A - Light emitting display device - Google Patents

Abstract

The present application is to provide a light emitting display device preventing black lifting. According to the present application, the light emitting display device comprises: a display panel connected to a plurality of data lines, a plurality of scan lines, and a plurality of reference voltage lines, and provided with a plurality of pixels each including a driving transistor and an organic light emitting diode; a panel driving unit sensing a predetermined voltage of the plurality of pixels through the plurality of reference voltage lines and outputting the sensed voltage as digital sensed data; and a control unit supplying a reference voltage to the reference voltage line in a display mode in which the plurality of pixels emit light. The control unit transmits a variable signal to the panel driving unit in a sensing mode for compensating the electron mobility or threshold voltage of the driving transistor. The panel driving unit receives the variable signal and increases a reference voltage value to output the same.

Description

Light emitting display device {LIGHT EMITTING DISPLAY DEVICE}

The present application relates to a light emitting display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been utilized. Among them, the organic light emitting display device is capable of driving a low voltage, is thin, has an excellent viewing angle, and has a fast response speed.

The organic light emitting diode display includes a display panel including a plurality of sub-pixels formed at intersections of data lines, scan lines, data lines, and scan lines, a scan driver supplying scan signals to the scan lines, and data lines. And a data driver supplying data voltages to the data drivers. Each of the sub-pixels includes an organic light emitting diode, a driving transistor for controlling an amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and a scan signal of the scan line. And a scan transistor for supplying a data voltage to the gate electrode of the driving transistor.

The threshold voltage of the driving transistor may vary from pixel to pixel due to a process variation in manufacturing an organic light emitting display device or a deterioration of the driving transistor due to long term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode should be the same, but due to the difference in the threshold voltage of the driving transistor between the pixels, even if the same data voltage is applied to the pixels, the organic light emitting diode is applied. The current supplied can vary from pixel to pixel. In addition, the organic light emitting diode may also be deteriorated due to long-term driving, in which case the luminance of the organic light emitting diode may vary from pixel to pixel. Accordingly, even when the same data voltage is applied to the pixels, the luminance of the organic light emitting diode may vary from pixel to pixel. In particular, in the process of turning on or turning off the organic light emitting diode display, the black light-up phenomenon in which white light appears on the black screen may occur due to the deteriorated organic light emitting diode, and may cause inconvenience to the viewer.

The present application is to provide a light emitting display device that prevents the black floating phenomenon occurs.

The light emitting display device according to the present application is connected to a plurality of data lines, a plurality of scan lines, and a plurality of reference voltage lines, and is provided with a plurality of pixels including a driving transistor and a plurality of pixels including organic light emitting diodes. A panel driver which senses a predetermined voltage of the plurality of pixels through a voltage line and outputs the sensing data as digital data; and a controller which supplies a reference voltage to the reference voltage line in a display mode in which each of the plurality of pixels emits light. The controller may transmit a variable signal to the panel driver in a sensing mode for compensating the electronic mobility or the threshold voltage of the driving transistor, and the panel driver receives the variable signal and outputs the reference voltage upward.

The light emitting display device according to the present application may prevent the black floating phenomenon from occurring by adjusting a voltage value so that the organic light emitting diode is not turned on in each sensing mode when the light emitting display device is turned on or turned off. .

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a perspective view illustrating a light emitting display device according to an exemplary embodiment of the present specification.
2 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present specification.
3 is a circuit diagram illustrating in detail a pixel of FIG. 2.
4A and 4B are exemplary views illustrating an operation of a pixel during first to second periods in a first sensing mode.
5A through 5C are exemplary views illustrating an operation of a pixel during first to third periods in a second sensing mode.
6 is a block diagram illustrating a signal transmission system between a panel controller and a panel driver according to an exemplary embodiment of the present specification.
7 is a waveform diagram of signals supplied to a pixel in a sensing mode and a display mode.

Advantages and features of the present application, and a method of achieving them will be apparent with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below, but may be implemented in various different forms, only examples of the present application are intended to complete the disclosure of the present application, and the general knowledge in the art to which the present application belongs. It is provided to fully inform the person having the scope of the invention, and this application is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the example of the present application are exemplary, and thus the present application is not limited to the illustrated items. Like reference numerals refer to like elements throughout. In addition, in describing the present application, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted.

In the case where 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upper', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

In the case of a description of a temporal relationship, for example, if the temporal after-term relationship is described as 'after', 'following', 'after', 'before', or the like, 'directly' or 'direct' This may include cases that are not continuous unless used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present application.

The "first horizontal axis direction", the "second horizontal axis direction" and the "vertical axis direction" are not to be interpreted only as geometrical relationships in which the relationship between each other is vertical, and the range in which the configuration of the present application can function. It can mean having a wider direction than within.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means two items of the first item, the second item, or the third item, as well as two of the first item, the second item, and the third item, respectively. It can mean a combination of all items that can be presented from more than one.

Each of the features of the various examples of the present application may be combined or combined with each other, partly or wholly, and technically various interlocking and driving are possible, and each of the examples may be independently implemented with respect to each other or may be implemented in association with each other. .

Hereinafter, a preferred example of a light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings.

1 is a perspective view illustrating a light emitting display device according to an exemplary embodiment of the present specification, and FIG. 2 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present specification.

1 and 2, a light emitting display device according to an exemplary embodiment of the present specification may be an organic light emitting display device using an organic light emitting device as a light emitting device.

In the light emitting display device according to the exemplary embodiment of the present specification, the display panel 110, the data driver 120, the flexible films 122, the scan driver 130, the source circuit board 140, and the first flexible cable 150 are provided. ), The control circuit board 160, the timing controller 170, the memory 180, the voltage supply unit 190, the system on chip 210, the system circuit board 220, and the second flexible cable 230. do.

The display panel 110 may include a first substrate 111 and a second substrate 112. The first substrate 111 may be formed of a glass substrate or a plastic film, and the second substrate 112 may be formed of a glass substrate, a plastic film, an encapsulation film, or a barrier film.

The display panel 110 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area in which pixels P are formed to display an image. The display panel 110 includes data lines D1 to Dm and m is a positive integer of 2 or more, reference voltage lines R1 to Rp and p is a positive integer of 2 or more, and scan lines S1 to Sn and n. Is a positive integer of 2 or more), and sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may cross the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the pixels P may be any one of the data lines D1 to Dm, one of the reference voltage lines R1 to Rp, one of the scan lines S1 to Sn, and sensing signal lines. SE1 to SEn). Each of the pixels P of the display panel 10 may include a light emitting element EL and a plurality of transistors for supplying current to the light emitting element EL, as shown in FIG. 3.

The data driver 120 and the scan driver 130 may be referred to as panel drivers.

The data driver 120 may include at least one source drive integrated circuit (IC) 121 as shown in FIG. 2. In FIG. 2, the data driver 120 includes eight source drive ICs 121, but the number of source drive ICs 121 is not limited thereto.

Each source drive IC 121 may be mounted on each flexible film 122. Each flexible film 122 may be a tape carrier package or a chip on film. Each flexible film 122 may be bent or bent. Each flexible film 122 may be attached to the lower substrate 111 and the source circuit board 140. Each flexible film 122 may be attached onto the first substrate 111 by a tape automated bonding (TAB) method using an anisotropic conductive film, so that each source drive IC 121 may receive data. May be connected to the lines.

Each source drive IC 121 may include a data voltage supply 121A, an analog digital converter (ADC) 121B, and a switching unit 121C as shown in FIG. 2.

The data voltage supply 121A is connected to data lines to supply data voltages. The data voltage supply unit 121A receives the digital data and the data timing control signal DCS from the timing controller 170. The digital data may be any one of compensation video data CVDATA and first and second sensing digital data PDATA1 and PDATA2.

The data voltage supply 121A receives the compensation video data CVDATA in the display mode, converts the compensation video data CVDATA into emission data voltages, and applies the compensation video data CVDATA to the data lines according to the data timing control signal DCS. The display mode is a mode in which the pixels P emit light to display an image. The light emission data voltage is a voltage for emitting light of the light emitting element EL of the pixel P with a predetermined luminance.

The data voltage supply unit 121A receives the first sensing digital data PDATA1 in the electronic mobility sensing mode and converts the first sensing digital data PDATA1 into a first sensing data voltage according to the data timing control signal DCS. To the data lines. The electron mobility sensing mode is a sensing mode in which the source voltage of the driving transistor DT is sensed according to the first sensing data voltage to compensate for the electron mobility of the driving transistors of the pixels P.

The data voltage supply unit 121A receives the second sensing digital data PDATA2 in the threshold voltage sensing mode, converts the second sensing digital data PDATA2 into a second sensing data voltage according to the data timing control signal DCS. Applied to the data lines. The threshold voltage sensing mode senses a source voltage of the driving transistor according to the second sensing data voltage to compensate for the threshold voltage of the driving transistor of each pixel P.

Hereinafter, for convenience of description, the electronic mobility sensing mode will be described as a first sensing mode and a threshold voltage sensing mode as a second sensing mode.

The ADC 121B converts the voltages sensed from the reference voltage lines in the first sensing mode and the second sensing mode into sensing data SD1 / SD2, which are digital data, and outputs them to the timing controller 170. The ADC 121B converts the voltages sensed from the reference voltage lines in the first sensing mode into first sensing data SD1 and outputs the first sensing data SD1 to the timing controller 170. The ADC 121B converts the voltages sensed from the reference voltage lines in the second sensing mode into second sensing data SD2 and outputs the second sensing data SD2 to the timing controller 170.

The switching unit 121C switches the connection between the reference voltage lines and the voltage supply unit 190, and switches the connection between the reference voltage lines R1 to Rz and the ADC 140. To this end, the switching unit 121C includes a first switch SW1 connected between each reference voltage line and the voltage supply unit 190 and a second switch connected between each reference voltage line and the ADC 121B as shown in FIG. 3. (SW2) may be included.

The scan driver 130 includes a scan signal output unit 131 and a sensing signal output unit 132. The scan signal output unit 131 is connected to the scan lines S1 to Sn to apply scan signals. The scan signal output unit 131 generates scan signals according to the scan timing control signal SCS input from the timing controller 170 and applies the scan signals to the scan lines S1 to Sn.

The sensing signal output unit 132 is connected to the sensing signal lines SE1 to SEn to apply sensing signals. The sensing signal output unit 132 generates sensing signals according to the sensing timing control signal SENCS input from the timing controller 170 and applies the sensing signals to the sensing signal lines SE1 to SEn.

The scan signal output unit 131 and the sensing signal output unit 132 may be directly formed in the non-display area NDA of the display panel 110 by using a gate driver in panel (GIP) method including a plurality of transistors. Alternatively, the scan signal output unit 131 and the sensing signal output unit 132 may be formed in the form of a driving chip and mounted on the gate flexible film attached to the first substrate 111 of the display panel 110. have. In this case, the scan signal output unit 131 and the sensing signal output unit 132 may be formed in a chip form like an integrated circuit.

The source circuit board 140 may include first connectors 151 for connecting to the first flexible cables 150. The source circuit board 140 may be connected to the first flexible cables 150 through the first connectors 151. The source circuit board 50 may be a flexible printed circuit board or a printed circuit board.

The control circuit board 160 may include second connectors 152 for connecting to the first flexible cables 150. The control circuit board 160 may be connected to the first flexible cables 150 through the second connectors 152.

In FIG. 1, the source circuit board 140 and the control circuit board 160 are connected to the plurality of first flexible cables 150 through the plurality of first connectors 151 and the plurality of second connectors 152. Although illustrated, the present invention is not limited thereto. That is, each of the source circuit board 140 and the control circuit board 160 may be connected to one first flexible cable 150 through one first connector 151 and one second connector 152.

The timing controller 170, the voltage supplier 190, and the power gamma reference voltage generator 200 may be referred to as a panel controller.

The timing controller 170 receives digital video data VDATA and timing signals from the system on chip 210. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 170 generates control signals for controlling the operation timing of the data voltage supply unit 121A, the scan signal output unit 131, and the sensing signal output unit 132. The control signals include a data timing control signal DCS for controlling the operation timing of the data voltage supply unit 121A, a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 131, and a sensing signal output. And a sensing timing control signal SENCS for controlling the operation timing of the unit 132.

The timing controller 170 may control the light emitting display device to any one of a display mode, a first sensing mode, and a second sensing mode.

The display mode is a mode that emits the pixels P by supplying the emission data voltages corresponding to the compensation video data CVDATA to the pixels P.

The first sensing mode supplies the first sensing data voltage according to the first sensing digital data PDATA1 to the pixels P, and sets predetermined voltages of the pixels P through the reference voltage lines R1 to Rp. Sensing mode. In detail, the first sensing mode is a mode in which the source voltage of the driving transistor according to the first sensing data voltage is sensed as the first sensing data SD1 to compensate for the electron mobility of the driving transistors of the pixels P. Referring to FIG. . The first sensing mode may be performed as soon as the light emitting display device is turned on before displaying an image on the display panel 110.

The second sensing mode supplies the second sensing data voltage according to the second sensing digital data PDATA2 to the pixels P, and sets predetermined voltages of the pixels P through the reference voltage lines R1 to Rp. Sensing mode. In detail, the second sensing mode is a mode in which the source voltage of the driving transistor according to the second sensing data voltage is sensed as the second sensing data SD2 in order to compensate for the threshold voltage of the driving transistor of each pixel P. The second sensing mode may be performed before the light emitting display is turned off.

The timing controller 170 converts the digital video data VDATA into the compensation video data CVDATA using the compensation data CDATA stored in the memory 180 in the display mode. The timing controller 170 outputs the compensation video data CVDATA and the data timing control signal DCS to the data voltage supply 121A in the display mode, and transmits the scan timing control signal SCS to the scan signal output unit 131. The sensing timing control signal SENCS is output to the sensing signal output unit 132.

The timing controller 170 outputs the first sensing digital data PDATA1 and the data timing control signal DCS stored in the memory 180 to the data voltage supply 121A in the first sensing mode, and scan scan control signals SCS. ) Is output to the scan signal output unit 131, and the sensing timing control signal SENCS is output to the sensing signal output unit 132. The timing controller 170 may receive the first sensing data SD1 from the ADC 121B in the first sensing mode, generate new compensation data CDATA according to the first sensing data SD1, and store the memory 180. Save it). That is, the timing controller 170 updates the compensation data CDATA stored in the memory 180 by reflecting the first sensing data SD1 sensed in the first sensing mode. In the first sensing mode, the first sensing data SD1 is data obtained by converting the source voltage of the driving transistor according to the first sensing data voltage in each pixel P into digital data by the ADC 121B.

The timing controller 170 outputs the second sensing digital data PDATA2 and the data timing control signal DCS stored in the memory 180 to the data voltage supply 121A in the second sensing mode, and scan scan control signals SCS. ) Is output to the scan signal output unit 131, and the sensing timing control signal SENCS is output to the sensing signal output unit 132. The second sensing digital data PDATA2 is different from the first sensing digital data PDATA1. The timing controller 170 receives the second sensing data SD2 from the ADC 121B in the second sensing mode, generates new compensation data CDATA according to the second sensing data SD2, and stores the new compensation data CDATA in the memory 180. Save it. That is, the timing controller 170 updates the compensation data CDATA stored in the memory 180 by reflecting the second sensing data SD2 sensed in the second second sensing mode. In the second sensing mode, the second sensing data SD2 is data obtained by converting the source voltage of the driving transistor according to the second sensing data voltage in each pixel P into digital data by the ADC 121B.

In addition, the timing controller 170 may receive a turn-on signal of the display device indicating whether the display device is turned on from the system on chip 210. When the turn-on signal of the display device is input, the timing controller 170 drives the display panel driver in the first sensing mode before displaying an image. In addition, when the second sensing mode ends, the timing controller 170 outputs a driving end signal to the system on chip 210.

In addition, the timing controller 170 may be configured to control the first switch control signal SCS1 and the second switch SW2 for controlling the first switch SW1 of the switch 121C of the data driver 120. The switch control signal SCS2 can be generated and output.

The memory 180 stores the first sensing digital data PDATA1, the second sensing digital data PDATA2, and the compensation data CDATA. The timing controller 170 may read the first sensing digital data PDATA1, the second sensing digital data PDATA2, and the compensation data CDATA from the memory 180, and may read the first sensing data SD1 and the first sensing data SD1. 2, the new compensation data CDATA calculated by using the sensing data SD2 may be written. The memory 180 may include volatile memories and nonvolatile memories. The volatile memory may be DDR memory, and the nonvolatile memory may be NAND flash memory.

The voltage supply unit 190 generates a reference voltage VREF from the main power source applied from the main power supply unit 240 of the system circuit board 220 and supplies the reference voltage VREF to the source drive ICs 121 of the data driver 120. In addition, the power supply unit 190 generates the first power supply voltage EVDD corresponding to the high potential voltage and the second power supply voltage EVSS corresponding to the low potential voltage from the main power supply MV to display panel 110. The driving voltages may be supplied to the source drive ICs 121A, the scan signal output unit 131, the sensing signal output unit 132, the timing controller 170, and the memory 180.

The power gamma reference voltage generator 200 may generate a gamma voltage and supply the gamma voltage to the data driver 120. The gamma voltage may be a set of a plurality of voltage signals corresponding to values of the plurality of grayscale data according to the gamma curve set in the display device.

The data driver 120 receives the data timing control signal DCS from the timing controller 170, receives the gamma voltage from the power gamma reference voltage generator 200, and transmits the generated data signal to the display panel 110. Can supply

The timing controller 170, the memory 180, the voltage supply 190, and the power gamma reference voltage generator 200 may be mounted on the control circuit board 160. In this case, the timing controller 170, the voltage supply unit 190, and the power gamma reference voltage generator 200 may be formed in a chip form like an integrated circuit. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

The system on chip 210 may convert the digital video data VDATA input from the outside according to the resolution of the light emitting display device and output the converted digital video data VDATA to the timing controller 170. The system on chip 210 may perform various image quality processing algorithms on the digital video data VDATA as well as convert the resolution of the input digital video data VDATA and output the same to the timing controller 170. In addition, the system on chip 210 may output a turn-on signal indicating whether the display device is turned on together with the digital video data VDATA to the timing controller 170.

The system on chip 210 receives a driving end signal from the timing controller 170. In this case, the system on chip 210 may block the main power supply 240 from outputting the main power MV.

The system on chip 210 and the main power supply unit 240 may be mounted on the system circuit board 220. In this case, the system on chip 210 and the main power supply 240 may be formed in a chip form like an integrated circuit. The system circuit board 220 may be a flexible printed circuit board or a printed circuit board.

The control circuit board 160 may include third connectors 231 to be connected to the second flexible cables 230. The control circuit board 160 may be connected to the second flexible cables 230 through the third connectors 231. The system circuit board 220 may include fourth connectors 232 to be connected to the second flexible cables 230. The system circuit board 220 may be connected to the second flexible cables 230 through fourth connectors 232.

In FIG. 1, the control circuit board 160 and the system circuit board 220 are connected to the plurality of flexible cables 220 through the plurality of third connectors 231 and the plurality of fourth connectors 232. It is not limited to this. That is, the control circuit board 160 and the system circuit board 220 may be connected to one second flexible cable 230 through one third connector 231 and one fourth connector 232.

3 is a circuit diagram illustrating in detail a pixel of FIG. 2.

In FIG. 3, for convenience of description, j j (j is a positive integer satisfying 1 ≦ j ≦ m) data line Dj, and u (u is a positive integer satisfying 1 ≦ u ≦ p) reference voltage. The sub-pixel connected to the line Ru, the kth (k is a positive integer satisfying 1 ≦ k ≦ n) scan line Sk, and the kth sensing signal line SEk, the voltage supply unit 190, and the data. Only the switch SW connected between the voltage supply unit 121A, the ADC 121B, the u-th reference voltage line Ru and the voltage supply unit 190 is shown.

Referring to FIG. 3, the pixel P of the display panel 110 includes an organic light emitting diode OLED, a driving transistor DT, first and second switching transistors ST1 and ST2, and a storage capacitor Cst. It may include.

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. The organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. When a voltage is applied to the anode electrode and the cathode electrode, the organic light emitting diode OLED moves to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combines and emits light in the organic light emitting layer. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to the second power line ESL supplied with a second power source lower than the first power source.

The driving transistor DT adjusts a current flowing from the first power line EVL to the organic light emitting diode OLED according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first switching transistor ST1, the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is connected to the first power line EVL. Can be connected to.

The first switching transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to connect the j-th data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the first driving transistor DT1, and the second electrode is the j-th data line Dj ) Can be connected.

The second switching transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SEk to connect the uth reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST3 is connected to the kth sensing signal line SEk, the first electrode is connected to the u reference voltage line Ru, and the second electrode is a source of the driving transistor DT. Can be connected to the electrode.

The storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores the difference voltage between the gate voltage and the source voltage of the driving transistor DT.

4A and 4B are exemplary diagrams illustrating an operation of a pixel during first to second periods in a first sensing mode.

First, as illustrated in FIG. 4A, the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk during the first period. The second switching transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SEk. The first switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage during the first period, and the second switch SW2 is the second switch control signal of the second logic level voltage. It is turned off by (SCS2).

The reference voltage VREF is supplied from the voltage supply unit 80 to the u th reference voltage line Ru due to the turn-on of the first switch SW1 during the first period. The reference voltage VREF of the u reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the first period. That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

Secondly, as shown in FIG. 4B, during the second period, the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. The second switching transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SEk. During the second period, the first switch SW1 is turned off by the first switch control signal SCS1 of the second logic level voltage, and the second switch SW2 is the second switch control signal of the first logic level voltage. It is turned on by (SCS2).

The reference voltage VREF is not supplied to the u th reference voltage line Ru because of the turn-off of the first switch SW1 during the second period. In addition, the reference voltage line Ru is connected to the ADC 140 due to the turn-on of the second switch SW2 during the second period. The first sensing data voltage SVdata1 is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1 during the second period. During the second period, the source electrode of the driving transistor DT is connected to the ADC 140 through the u reference voltage line Ru due to the turn-on of the second switching transistor ST2.

Since the voltage difference Vgs = SVdata1 -VREF between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage Vth of the driving transistor DT during the second period, the driving transistor DT is formed. Current will flow.

Since the current of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT as in Equation 1, the amount of increase in the source voltage Vs of the driving transistor DT during the second period is increased by the driving transistor ( It is proportional to the electron mobility K of DT). That is, as the electron mobility of the driving transistor DT increases, the amount of increase in the source voltage Vs of the driving transistor DT increases during the second period.

As a result, the rising amount of the source voltage Vs of the driving transistor DT varies according to the electron mobility K of the driving transistor DT during the second period, and the source voltage according to the electron mobility K of FIG. 9. The amount of rise of (Vs) was defined as α. The source voltage of the driving transistor DT rises to "VREF + α" as shown in FIG. 9 according to the electron mobility K. Therefore, a voltage in which the electron mobility K of the driving transistor DT is reflected is sensed on the source electrode of the driving transistor DT during the second period.

As described above, in the exemplary embodiment of the present invention, the source voltage “VREF + α” of the driving transistor reflecting the electron mobility K of the driving transistor DT may be sensed in the first sensing mode.

5A through 5C are exemplary views illustrating an operation of a pixel during first to third periods in a second sensing mode.

First, as illustrated in FIG. 5A, the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk during the first period. The second switching transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SEk. The first switch SW1 is turned on by the first switch control signal SCS1 of the first logic level voltage during the first period, and the second switch SW2 is the second switch control signal of the second logic level voltage. It is turned off by (SCS2).

The reference voltage VREF is supplied from the voltage supply unit 80 to the u th reference voltage line Ru due to the turn-on of the first switch SW1 during the first period. The reference voltage VREF of the u reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the first period. That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

Secondly, as shown in FIG. 5B, the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk during the second period. The second switching transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SEk. During the second period, the first switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage, and the second switch SW2 is the second switch control signal of the second logic level voltage. It is turned off by (SCS2).

The reference voltage VREF is not supplied to the u th reference voltage line Ru because of the turn-off of the first switch SW1 during the second period. In addition, since the first switching transistor ST1 is turned on during the second period, the second sensing data voltage SVdata2 is supplied to the gate electrode of the driving transistor DT.

Since the voltage difference Vgs = SVdata2-VREF between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage Vth of the driving transistor DT during the second period, the driving transistor DT The current flows until the voltage difference Vgs between the gate electrode and the source electrode reaches the threshold voltage Vth. For this reason, the source voltage of the driving transistor DT rises to "SVdata2-Vth" as shown in FIG. That is, the threshold voltage of the driving transistor DT is sensed by the source electrode of the driving transistor DT during the second period.

Third, as illustrated in FIG. 5C, the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk during the third period. The second switching transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SEk. The first switch SW1 is turned off by the second switch control signal SCS2 of the second logic level voltage during the third period, and the second switch SW2 is the second switch control signal of the first logic level voltage. It is turned on by (SCS2).

The u-th reference voltage line Ru is connected to the ADC 140 due to the turn-on of the second switch SW2 during the third period. The source electrode of the driving transistor DT is connected to the ADC 140 through the u reference voltage line Ru due to the turn-on of the second switching transistor ST2 during the third period. Therefore, the ADC 140 may sense the source voltage of the driving transistor DT, that is, "SVdata1-Vth".

As described above, in the second sensing mode, the source voltage “SVdata1-Vth” of the driving transistor DT reflecting the threshold voltage of the driving transistor DT may be sensed.

6 is a block diagram illustrating a signal transmission system between a panel controller and a panel driver according to an exemplary embodiment of the present specification. As described above, the panel controller includes a timing controller 170 and a power gamma reference voltage generator 200, each of which is formed on the control circuit board 160. The panel driver includes a data driver 120. Hereinafter, only some configurations of the panel controller and the panel driver will be described in FIG. 6.

Referring to FIG. 6, the panel controller transmits a variable signal VS to the panel driver. For example, the panel controller may transmit a variable signal VS to the panel driver in the first sensing mode and the second sensing mode for compensating electron mobility of the driving transistor or compensating a threshold voltage. As described above, the first sensing mode may correspond to when the display device is turned on, and the second sensing mode may correspond to when the display device is turned off.

In detail, the timing controller 170 generates the variable control signal VCS when the display device is turned on or turned off by the main power supply MV output by the main power supply 240 to generate the power gamma reference voltage generator. The power gamma reference voltage generator 200 may receive the variable control signal VCS, generate a variable signal VS, and transmit the variable signal VS to the data driver 120. In this case, the timing controller 170 may combine the EVDD_Reset signal and the ON RF_Done signal to use the variable control signal VCS. For example, the timing controller 170 may transmit a variable control signal VCS, which is a combination of a high signal of EVDD_Reset and a low signal of ON RF_Done in a first sensing mode, through an input terminal connected to the power gamma reference voltage generator. .

The power gamma reference voltage generator 200 may generate the variable signal VS from the variable control signal VCS through a logic circuit designed therein. For example, the power gamma reference voltage generator 200 generates the variable signal VS when the variable control signal VCS is combined with the EVDD_Reset high signal and the ON RF_Done low signal when the EVDD signal is high. can do. A detailed description of the EVDD_Reset and ON RF_Done signals will be described later with reference to FIG. 7.

The data driver 120 may receive the variable signal VS and upwardly output the reference voltage or the second power supply voltage above a preset value. As described above, the voltage supply unit 190 supplies the reference voltage REF to the reference voltage line through the first switch SW1. At this time, when the third and fourth switches connected to the voltage supply unit 190 are formed before the first switch SW1, and the variable signal VS is not input, the third switch is turned on and the existing reference is established. When the voltage REF is supplied to the reference voltage line and the variable signal VS is input, the fourth switch is turned on so that a reference voltage having a higher voltage value than the existing reference voltage REF is supplied to the reference voltage line. Supply.

Similarly, the voltage supply unit 190 may supply the second power supply voltage EVSS to the cathode electrode of the organic light emitting diode OLED of the display panel 110. At this time, when the fifth switch and the sixth switch are formed between the voltage supply unit 190 and the cathode electrode, and the variable signal VS is not input, the fifth switch is turned on and the existing second power supply voltage EVSS is turned on. ) Is supplied to the cathode electrode, and when the variable signal VS is input, the sixth switch is turned on to supply a power supply voltage having a voltage value higher than that of the existing second power supply voltage EVSS to the cathode electrode.

As described above, in the light emitting display device according to the exemplary embodiment of the present specification, the organic light emitting diode is turned on in the sensing mode by adjusting the reference voltage REF and the second power supply voltage EVSS through the variable signal VS. It can prevent.

For example, when the threshold voltage of the driving transistor is lowered due to deterioration of the light emitting display device, the Vgs of the driving transistor has a higher value than the threshold voltage, so that a large current flows in the driving transistor, and the organic light source connected to the source electrode of the driving transistor is organic. The voltage difference between the anode electrode of the light emitting diode and the cathode electrode of the organic light emitting diode becomes higher than the turn-on voltage of the organic light emitting diode, which may cause a problem that the organic light emitting diode is turned on. Therefore, when the LED is turned on or turned off, black is not displayed on the entire screen. Instead, the organic light emitting diode is turned on in the pixel at which the threshold voltage of the driving transistor is lowered. Lifting may occur.

However, when the light emitting display device is turned on or turned off, the light emitting display device according to the exemplary embodiment of the present disclosure generates a variable signal VS to adjust the reference voltage REF and the second power supply voltage EVSS. Therefore, the organic light emitting diode can be prevented from being turned on. For example, if the reference voltage REF is raised to have a higher value than the preset value, and the output voltage is increased, the Vgs of the driving transistor is lowered. The organic light emitting diode is not turned on because it is lower than the turn-on voltage of. In addition, when the second power supply voltage EVSS is raised to have a higher value than the preset value, the voltage applied to the cathode of the organic light emitting diode is increased, so that the voltage difference between the anode electrode and the cathode of the organic light emitting diode is increased. Is less than the turn-on voltage of the organic light emitting diode, the organic light emitting diode does not turn on.

As described above, the light emitting display device according to the exemplary embodiment of the present specification turns on or turns off the light emitting display device, that is, in the first sensing mode and the second sensing mode, through the variable signal VS. REF) and the second power supply voltage EVSS may be adjusted to prevent black lifting.

7 is a waveform diagram of signals supplied to a pixel in a sensing mode and a display mode.

Referring to FIG. 7, the light emitting display device includes a first period t1 corresponding to the first sensing mode, a second period t2 corresponding to the display mode, and a third period t3 corresponding to the second sensing mode. It may include.

Since the first power supply voltage EVDD is supplied to the display panel 110 in the first period t1, the EVDD signal is turned on and maintained at a high signal, and the EVDD_Reset signal corresponds to a power-up confirmation signal, so the EVDD_Reset signal is turned on. Logic operation begins while maintaining a high signal.

Since the ON RF_Done signal is turned on as a high signal when the ON RF corresponding to the first sensing mode ends, the ON RF_Done maintains a low signal in the first period t1.

At this time, since both the reference voltage REF supply signal VpreR and the second power supply voltage EVSS supply signal are turned on as high signals, the reference voltage REF and the second power supply voltage EVSS during the first period t1. ) Can be seen to be output upward beyond the preset value.

In the first period t1, the timing controller 170 may transmit the variable control signal VCS, which is a combination of the EVDD_Reset high signal and the ON RF_Done low signal, to the power gamma reference voltage generator 200, and generate the power gamma reference voltage. The unit 200 may generate the variable signal VS after receiving the variable control signal VCS.

Since both VpreR and EVSS are changed to the low signal in the second period t2, the reference voltage REF and the second power supply voltage EVSS are not outputted upward in the second period t2 and are outputted as preset values. Therefore, the display mode can be normally driven.

The light emitting display is turned off as the EVDD and EVDD_Reset are changed to the low signal in the third period t3. At this time, the ON RF_Done signal is maintained as a high signal and then changed to a low signal. When the ON RF_Done signal is changed from a high signal to a low signal, the OFF-RS corresponding to the second sensing mode is started.

At this time, since the reference voltage REF supply signal VpreR and the second power supply voltage EVSS supply signal are both turned on as high signals, the reference voltage REF and the second power supply voltage EVSS in the third period t3. ) Can be seen to be output upward beyond the preset value.

As described above, in the light emitting display device according to the exemplary embodiment of the present specification, the reference voltage REF and the third voltage may be applied in the first period t1 corresponding to the first sensing mode and the third period t3 corresponding to the second sensing mode. 2 Since the power supply voltage (EVSS) is raised above a predetermined value and output, the organic light emitting diode is turned on to prevent black lifting.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical matters of the present application. It will be apparent to those who have the knowledge of. Therefore, the scope of the present application is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope of the present application.

110: display panel 111: lower substrate
112: upper substrate 120: data driver
121: source drive IC 121A: data voltage supply
121B: analog-to-digital converter 121C: switching unit
122: flexible film 130: scan driver
131: scan signal output unit 132: sensing signal output unit
140: source circuit board 150: first flexible cable
160: control circuit board 170: timing control unit
180: memory 190: voltage supply
200: power gamma reference voltage generator 210: system on chip
220: system circuit board 230: second flexible cable
240: main power supply

Claims (7)

A display panel connected to data lines, reference voltage lines, and scan lines, the display panel including pixels including a driving transistor and an organic light emitting diode;
A panel driver configured to sense a predetermined voltage of the pixels through the reference voltage lines and output the sensing data as digital data;
A panel controller configured to supply a reference voltage to the reference voltage lines in a display mode in which each of the pixels emits light;
The panel controller transmits a variable signal to the panel driver in a sensing mode for compensating electron mobility or threshold voltage of the driving transistor,
And the panel driver receives the variable signal and outputs the reference voltage upwardly above a preset value. The method of claim 1,
The panel control unit,
A timing controller configured to receive the sensing data from the panel driver;
A voltage supply unit configured to generate a first power supply voltage corresponding to a high potential voltage and a second power supply voltage corresponding to a low potential voltage from a main power supply, and supply the second power supply voltage to a display panel;
And the panel driver receives the variable signal and outputs the second power voltage upwards above a preset value. The method of claim 1,
Further comprising a main power supply for outputting the main power,
And the panel controller generates the variable signal when the display device is turned on or turned off by the main power supply. The method of claim 2,
The panel control unit,
The apparatus further includes a power gamma reference voltage generator for generating the power gamma reference voltage.
The timing controller generates a variable control signal in the sensing mode and transmits the variable control signal to the power gamma reference voltage generator.
And the power gamma reference voltage generator receives the variable control signal, generates the variable signal, and transmits the variable signal to the panel driver. The method of claim 1,
The data line is connected to a gate electrode of the driving transistor,
The reference voltage line is connected to a source electrode of the driving transistor;
And a voltage difference Vgs between the gate electrode and the source electrode of the driving transistor is equal to a difference between the data voltage supplied to the data line and the reference voltage. The method of claim 5,
And the Vgs is smaller than a voltage for turning on the organic light emitting diode in the sensing mode. The method of claim 2,
A source electrode of the driving transistor is connected to an anode electrode of the organic light emitting diode,
A second power line for supplying the second power voltage to a cathode of the organic light emitting diode is connected,
The difference between the voltage applied to the anode electrode of the organic light emitting diode and the voltage applied to the cathode in the sensing mode is smaller than the voltage for turning on the organic light emitting diode.

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