KR20190140699A - Display Device - Google Patents

Abstract

The present invention relates to a display device for preventing the degradation in image quality. The display device comprises: a pixel connected to a data line and sensing line; a multiplexer TFT interconnecting a data channel and data line of a data driver according to a multiplexer clock signal inputted to a gate electrode; a switching TFT interconnecting the data line and sensing line according to a multiplexer sensing signal; and a sensing unit sensing a change of a threshold voltage of the multiplexer TFT through the sensing line. According to the change of the multiplexer TFT, a level of the multiplexer clock signal is varied.

Description

Display Device

The present invention relates to a display device.

Display devices are widely used in portable computers such as laptop computers, PDAs, mobile phones, and the like, as well as monitors of desktop computers due to advantages of miniaturization and light weight.

Among the display devices, an organic light emitting display device of an active matrix type includes an organic light emitting diode (hereinafter, referred to as an “OLED”) which emits light by itself, and has a fast response speed, high luminous efficiency, brightness and The viewing angle has a great advantage and is widely used.

The OLED display includes OLED pixels arranged in a matrix and adjusts luminance of pixels according to gray levels of image data. Each of the pixels includes a driving thin film transistor (TFT) for controlling a driving current flowing through the OLED according to the gate-source voltage, and one or more switch TFTs for programming the gate-sort voltage of the driving TFT. In addition, a plurality of TFTs are also incorporated in the multiplexer circuit provided for time-divisionally outputting image data to a larger number of data lines than the number of image data output channels of the data driving circuit 12.

It is preferable that the TFTs included in the display device operate according to design values in which electrical characteristics such as threshold voltage and mobility are set. However, as the driving time of the TFT device increases, the threshold voltage of each TFT may change due to a gate-bias stress or the like.

The change in the threshold voltage of the TFT included in the multiplexer circuit degrades the performance of the multiplexer circuit, and as a result, the charging rate of the data voltage is reduced, resulting in poor image quality such as vertical dimming on the screen.

The present invention provides a display device which prevents image quality from being degraded due to performance degradation of a multiplexer circuit.

According to an exemplary embodiment, a display device includes: a pixel connected to a data line and a sensing line; A multiplexer TFT interconnecting a data channel of the data driver and a data line according to a multiplexer clock signal input to the gate electrode; A switching TFT which interconnects the data line and the sensing line according to a multiplexer sensing signal; And a sensing unit configured to detect a change in the threshold voltage of the multiplexer TFT through the sensing line, wherein the level of the multiplexer clock signal is changed according to the change in the threshold voltage of the multiplexer TFT.

A display device according to an embodiment of the present invention, the data drive circuit 12 having a data channel for outputting image data; A pixel array including pixels connected to the data line and the sensing line; A multiplexer circuit including a multiplexer TFT operating according to a multiplexer clock signal to transfer the image data output from the data channel to the data line; A switching unit interconnecting a data line of the multiplexer TFT and a sensing line of a pixel according to a multiplexer sensing signal; And a sensing unit configured to detect a change in the threshold voltage of the multiplexer TFT through the sensing line.

The display device of the present invention has an effect of preventing image quality deterioration such as vertical dimming on the screen due to a change in the threshold voltage of the TFT included in the multiplexer circuit.

The display device of the present invention can compensate for deterioration of the multiplexer TFT by sensing the threshold voltage of the TFT included in the multiplexer circuit and varying the clock voltage input to the gate electrode of the multiplexer TFT. As a result, the charging rate of the image data is prevented from decreasing due to deterioration of the multiplexer TFT, thereby reducing the luminance of a specific data line, thereby improving image quality defects such as vertical dimming on the screen.

1 illustrates a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a display panel of FIG. 1.
3 is a circuit diagram illustrating an embodiment of the multiplexer circuit of FIG. 2.
4 is a circuit diagram illustrating an embodiment of the sensing block of FIG. 2.
5 is a view illustrating a pixel voltage sensing principle of the display device of the present invention.
6 is a view illustrating a multiplexer sensing principle in the display device of the present invention.
7 is a diagram illustrating a configuration of a sensing unit according to an embodiment of the present invention.
8 is a view showing a driving waveform during multiplexer sensing of the present invention.
9 to 13 are diagrams showing simulation results of the present invention.

Advantages and features of the present specification, and a method of accomplishing the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be implemented in various forms, and the present embodiments are merely provided to make the disclosure of the present disclosure complete, and those of ordinary skill in the art to which the present disclosure belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present specification are exemplary, and thus, the present specification is not limited thereto. Like reference numerals refer to like elements throughout. When 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on top', 'on bottom', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component referred to below may be a second component within the spirit of the present specification.

Like reference numerals refer to like elements throughout.

In the present specification, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as TFTs having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited thereto and may be implemented with TFTs having a p-type MOSFET structure. have. The TFT is a three-electrode element that includes a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start to flow from the source. The drain is an electrode from which the carrier goes out of the TFT. That is, the carrier flow in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In contrast, in the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. Note that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the description of the embodiments of the present specification, one of the source and the drain is described as the first electrode, and the other of the source and the drain as the second electrode.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described based on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical spirit of the present disclosure is not limited to an organic light emitting display device, but may be applied to an inorganic light emitting display device including an inorganic light emitting material.

In the following description, when it is determined that a detailed description of known functions or configurations related to the present disclosure may unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof will be omitted.

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention may include a display panel 10 having pixels PXL, a data driving circuit 12 outputting image data through a channel 14, and gate lines. And a timing controller 11 for controlling the driving timing of the data driving circuit 12 and the gate driving circuit 13.

The pixels PXL are arranged in a matrix on the display panel 10. Pixels PXL arranged on the same horizontal line form one pixel array. The pixels PXL may be supplied with the high potential and low potential driving voltages EVDD and EVSS and the reference voltage Vref in common.

The pixels PXL may include an OLED. The OLED, which is a self-luminous element, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel for color implementation. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. Meanwhile, the white pixel may be omitted from the unit pixel. The pixels PXL of the present invention may have a circuit structure capable of sensing electrical characteristics of the driving TFT. The circuit configuration of the pixels PXL can be variously modified. For example, the pixels PXL may include at least two switch TFTs and at least one storage capacitor in addition to the OLED and the driving TFT DT. The TFTs constituting the pixel P may be implemented in p type, n type, or hybrid type in which p type and n type are mixed. In addition, the semiconductor layer of the TFTs constituting the pixel P may include amorphous silicon, polysilicon, or an oxide.

The timing controller 11 rearranges the digital video data RGB input from the outside to the data driving circuit 12 in accordance with the resolution of the display panel 10. In addition, the timing controller 11 may use the data driving circuit 12 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing of the gate signal and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC. The gate driving circuit 13 may include a scan driver generating a scan signal and an emission driver generating an emission signal. The scan driver and the emission driver can be modified in various ways according to the pixel (PXL) structure.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage VD based on the data control signal DDC and outputs the same through the output channel 14. In addition, the data driving circuit 12 according to the embodiment of the present invention detects deterioration of the multiplexer TFT, for example, a threshold voltage of the multiplexer TFT according to the data timing control signal DDC applied from the timing controller 11 during sensing driving. The sensing data voltage for generating may be generated and supplied. The data driving circuit 12 may receive the sensing voltage of the multiplexer TFT and sense the threshold voltage of the multiplexer TFT.

Here, the timing controller 11 may separate the sensing driving and the display driving in time according to a predetermined control sequence. When driving the display, the timing controller 11 may rearrange the video data RGB to match the resolution of the display panel 10 and supply the video data RGB to the data driving circuit 12. The sensing driving may include driving for sensing degradation of the multiplexer TFT in the display panel 10 and updating a compensation value accordingly. It is also possible to further include a drive for sensing and compensating for deterioration of the driving TFT, OLED, and the like. According to the control operation of the timing controller 11, the sensing driving for detecting the deterioration of the multiplexer TFT may be performed in the power off sequence period after the display driving is finished. In addition, while the system power is being applied, the screen of the display device may be turned off, for example, in a standby mode, a sleep mode, a low power mode, or the like. The timing controller 11 senses the threshold voltage of the multiplexer TFT through the sensing driving, and varies the level of the multiplexer clock signal input to the gate electrode of the multiplexer TFT according to the sensing result.

2 is a diagram illustrating a configuration of a display panel 10 of a display device according to an exemplary embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an embodiment of the multiplexer circuit 20 of FIG. 2, and FIG. A circuit diagram showing an embodiment of the sensing unit 30 of FIG.

Referring to FIG. 2, the display panel 10 includes a display area AA in which a pixel array is formed, a multiplexer circuit 20 for time-divisionally outputting image data output from the data driving circuit 12, and data. And a switching unit 30 connecting the line DL and the sensing line SL of the pixel PXL.

In the display area AA, k (k is a natural number) gate lines 15 arranged in the horizontal direction and j (j is a natural number) data lines DL1 to DLj arranged in the vertical direction and j sensing lines SL1 to SLj and j * k pixels PXL arranged at these intersections may be included. That is, the (N, M) th pixel PXL is connected to the M th gate line, the N th data line DLN, and the M th sensing line SLM. The sensing line SL may be used to apply a reference voltage Vref to each pixel PXL when driving the display of the display panel. The sensing line SL may output a sensing value of a device connected to the sensing line SL during sensing driving. Can be used. The sensing line SL may be configured such that two or more pixels PXL share one sensing line SL. The j * k pixels PXL may be divided into a plurality of R pixels for displaying a red image, a plurality of G pixels for displaying a green image, and a plurality of B pixels for displaying a blue image. Can be.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into RGB analog data voltages and supplies them to the multiplexer circuit 20 through the n output channels DC1 to DCn. The data driving circuit 12 converts digital video data RGB corresponding to pixels PXL (j pixels) of one horizontal line into an RGB analog data voltage signal, and converts j image data of one horizontal line. It outputs through the n output channels (DC1 to DCn) consisting of a smaller number than this.

Here, the data driving circuit 12 sequentially outputs j image data three times during one horizontal period through the multiplexer circuit 20. For example, the data driving circuit 12 simultaneously outputs R image data of the j image data through the n output channels DC1 to DCn during the first period of the horizontal period, and then the j image data. G image data are simultaneously output through the n output channels DC1 to DCn during the second period of the horizontal period, and then G image data of the j image data are output during the third period of the horizontal period. Simultaneously outputs through n output channels DC1 to DCn.

The multiplexer circuit 20 transfers the analog data voltages output through the n output channels DC1 through DCn to the j data lines DL1 through DLj.

Referring to FIG. 3, the multiplexer circuit 20 time-divisions and outputs j image data from the data driver circuit 12 according to the multiplexer clock signals Mux_CLK and CLK1 to CLK3 inputted from the outside, and then time-divided. Image data is sequentially supplied to the plurality of data lines DL1 to DLj. To this end, the multiplexer circuit 20 includes first to third multiplexer TFTs (Mux_TFT1, Mux_TFT2, Mux_TFT3) sequentially turned on according to the first to third multiplexer clock signals CLK1 to CLK3.

The first multiplexer TFT Mux_TFT1 supplies the R image data V _R1 from the data driver circuit 12 to the R pixel according to the first multiplexer clock signal CLK1, and the second multiplexer TFT Mux_TFT2 supplies the second multiplexer TFT Mux_TFT2. The G image data V _G1 from the data driver circuit 12 is supplied to the G pixel according to the multiplexer clock signal CLK2, and the third multiplexer TFT Mux_TFT3 supplies the data driving circuit according to the third multiplexer clock signal CLK3. The B image data V _B1 from the furnace 12 is supplied to the B pixel.

The gate electrode of the first multiplexer TFT Mux_TFT1 is connected to the signal line to which the first multiplexer clock signal CLK1 is applied, and the drain electrode is connected to the first data channel DC1 of the data driving circuit 12. The electrode is connected to the first data line DL1.

The gate electrode of the second multiplexer TFT Mux_TFT2 is connected to the signal line to which the second multiplexer clock signal CLK2 is applied, and the drain electrode is connected to the first data channel DC1 of the data driving circuit 12. The electrode is connected to the second data line DL2.

The gate electrode of the third multiplexer TFT Mux_TFT3 is connected to the signal line to which the third multiplexer clock signal CLK3 is applied, and the drain electrode is connected to the first data channel DC1 of the data driving circuit 12. The electrode is connected to the third data line DL3.

Although not shown in FIG. 3, the multiplexer circuit 20 includes, in addition to the above-described first to third multiplexer TFTs Mux_TFT1, Mux_TFT2, and Mux_TFT3, a plurality of other multiplexers connected to each of the remaining output channels DC2 to DCn. Further comprising first to third multiplexer TFTs Mux_TFT1, Mux_TFT2, Mux_TFT3, and other first to third multiplexer TFTs Mux_TFT1, Mux_TFT2, Mux_TFT3 are also connected to the first data channel DC1 described above. The first to third multiplexer TFTs (Mux_TFT1, Mux_TFT2, Mux_TFT3) are connected between the corresponding output channel and the corresponding data lines. Meanwhile, all of the first multiplexer TFTs Mux_TFT1 included in the multiplexer circuit 20 are commonly supplied with the first multiplexer clock signal CLK1 regardless of the output channel to which they are connected. In addition, all second multiplexer TFTs Mux_TFT2 are commonly supplied with the second multiplexer clock signal CLK2, and all third multiplexer TFTs Mux_TFT3 are commonly supplied with the third multiplexer clock signal CLK3.

The switching unit 30 interconnects the data line DL1 of the multiplexer TFT Mux_TFT and the sensing line SL1 of the pixel PXL according to the multiplexer sensing signal Mux_sen.

Referring to FIG. 4, the switching unit 30 may turn on when the sensing signal Mux_sen is input to connect the data line DL1 and the sensing line SL1 to each other.

To this end, the switching unit 30 includes switching TFTs SW1, SW2, and SW3 which are turned on according to the sensing signal Mux_sen to interconnect the data line DL1 and the sensing line SL1. The gate electrode of the switching TFTs SW1, SW2, SW3 is connected to the signal line to which the sensing signal Mux_sen is applied, the drain electrode (or source electrode) is connected to the data line DL1, and the source electrode (or data electrode) ) Is connected to the sensing line SL1. All the switching TFTs SW included in the switching unit 30 are commonly supplied with the sensing signal Mux_sen to which they are connected.

5 is a view illustrating a principle of sensing a pixel PXL of a display device of the present invention, and FIG. 6 is a view illustrating a multiplexer sensing principle of a display device of the present invention.

In the present embodiment, each pixel PXL includes an OLED, a thin film transistor (TFT), a storage capacitor (Cst), a first TFT, and a second TFT, and the first TFT includes a first scan signal ( SCAN1 is input and the second TFT receives the second scan signal SCAN2.

The OLED includes an anode electrode connected to the source node Ns and a cathode electrode connected to the input terminal of the low potential pixel power source EVSS. The driving TFT DR controls the driving current flowing through the OLED according to the voltage difference between the voltage Vg of the gate node and the voltage Vs of the source node. The driving TFT DR has a gate electrode connected to the gate node, a first electrode connected to the input terminal of the high potential pixel power supply EVDD, and a second electrode connected to the source node. The storage capacitor Cst is connected between the gate node and the source node to store the gate-source voltage of the driving TFT DR.

Referring to FIG. 5, when the characteristic of the pixel PXL is sensed, the multiplexer TFT Mux TFT is turned on and the switching TFT SW included in the switching unit 30 is turned off. The on / off operation of the multiplexer TFT (Mux TFT) and the switching TFT (SW) may be controlled by the multiplexer clock signal Mux_CLK and the multiplexer sensing signal Mux_sen supplied from the timing controller 11.

When the characteristic of the pixel PXL is sensed, the first TFT and the second TFT in the pixel PXL are turned on. The data driving circuit 12 supplies the pixel data VD_PXL to the pixel PXL through the data line DL1 and receives the pixel detection signal VS_PXL output to the sensing line SL1 to receive the pixel data VDL_PXL. The electrical characteristics can be detected.

Referring to FIG. 6, when sensing characteristics of the multiplexer, the first TFT and the second TFT in the pixel PXL are turned off so that the pixel PXL is electrically separated from the data line DL1 and the sensing line SL1. The multiplexer TFT (Mux TFT) and the switching TFT (SW) are turned on.

When the switching TFT SW is turned on, the data line DL1 and the sensing line SL1 are connected to each other. Accordingly, a path may be formed in which the multiplexer data VD_MUX output from the data driving circuit 12 is output from the sensing line SL1 via the multiplexer TFT (Mux TFT) and the data line DL1.

The multiplexer clock signal Mux_CLK is supplied to the gate electrode of the multiplexer TFT, and the multiplexer data VD_MUX is supplied to the drain electrode to source the threshold voltage of the multiplexer TFT. After operating the TFT by a source follower method, the source voltage of the multiplexer TFT (Mux TFT) is input to the sensing line VS1 as the sensing voltage VS_MUX, and thus the multiplexer TFT is based on the sensing voltage VS_MUX. A change in the threshold voltage Vth of the mux TFT may be sensed.

One or more switching TFTs SW may be provided as many as the maximum number of data lines. As the number of switching TFTs SW increases, it is possible to detect the threshold voltage Vth of a large number of multiplexer TFTs (Mux TFTs), thereby increasing sensing accuracy. However, as the number of sensing multiplexer TFTs (Mux TFTs) increases, processing time may increase and circuit complexity may increase. Accordingly, it is preferable to provide a switching TFT SW based on a certain number of data lines according to the total number of data lines. For example, four to eight switching TFTs SW may be provided.

7 is a diagram illustrating a configuration of a sensing unit SU according to an embodiment of the present invention.

The sensing unit SU supplies the multiplexer data VD_MUX to the data line DL1 while the pixel PXL is turned off and electrically separated from the data line DL1 and the sensing line SL1. The sensing voltage VS_MUX output to the sensing line SL1 is sensed via the TFT and the data line DL1.

The sensing unit SU may include an initialization switch SPRE1, a sensing switch SPRE2, and an ADC.

The initialization switch SPRE1 connects the input terminal of the initialization voltage Vpre and the sensing line SL1 in the initialization period, and the sensing switch SPRE2 switches so that the ADC and the sensing line SL1 are connected in the sensing period.

When the initialization switch SPRE1 connects the input terminal of the initialization voltage Vpre and the sensing line SL1 during the initialization period, the initialization power supply Vpre is connected to the multiplexer TFT (Mux TFT) through the sensing line SL1 and the data line DL1. Is connected to the source electrode. Thus, the voltage of the source electrode of the multiplexer TFT (Mux TFT) can be initialized.

When the sensing switch SPRE2 connects the ADC and the sensing line SL1, the ADC digitally outputs the sensing voltage VS_MUX output to the sensing line SL1 via the multiplexer TFT and the data line DL1. Can be converted to

Since the sensing voltage VS_MUX varies according to the threshold voltage Vth of the multiplexer TFT (Mux TFT), a change in the threshold voltage Vth of the multiplexer TFT (Mux TFT) may be sensed through the sensing voltage VS_MUX.

The configuration of the sensing unit SU is not limited to the above-described embodiment, and various types of sensing circuits capable of sensing the sensing voltage VS_MUX output from the sensing line SL may be applied.

On the other hand, as the use time elapses, deterioration of the multiplexer TFT (Mux TFT) is intensified, resulting in a decrease in the charging rate of the image data. Accordingly, the present invention changes the level of the multiplexer clock signal Mux_CLK input to the gate electrode of the multiplexer TFT according to the change of the threshold voltage Vth of the multiplexer TFT (Mux TFT). To compensate for deterioration. To this end, the timing controller 11 receives the multiplexer clock signal input to the gate electrode of the multiplexer TFT according to a change in the threshold voltage Vth of the multiplexer TFT detected through the sensing unit SU. Mux_CLK) can be provided with variable levels.

The level-adjusted multiplexer clock signal Mux_CLK is equally applied to the multiplexer TFT sharing the same clock line. For example, the first multiplexer clock signal CLK1 is input to all the first multiplexer TFTs Mux_TFT1 in the multiplexer circuit 20, and the second multiplexer clock signal CLK2 is input to all the second multiplexer TFTs 20 in the multiplexer circuit 20. The third multiplexer clock signal CLK3 is input to all the third multiplexer TFTs Mux_TFT3 in the multiplexer circuit 20. Accordingly, the level of the multiplexer clock signal Mux_CLK can compensate for the threshold voltage Vth of the most deteriorated multiplexer TFT among the multiplexer TFTs that receive the same multiplexer clock signal Mux_CLK. Is set.

8 is a view showing a driving waveform during multiplexer sensing of the present invention. 8 illustrates a case where the pixel array AA, the multiplexer circuit 20, and the switching unit 30 are all composed of N-type TFTs, and the high level is on level and the low level is off level.

The multiplexer sensing period may include an initialization period and a sensing period.

The first scan signal SCAN1 and the second scan signal SCAN2 are applied at a low level during the multiplexer sensing period. Accordingly, since the first TFT and the second TFT in the pixel PXL are kept in the OFF state during the multiplexer sensing period, the pixel PXL may be electrically separated from the data line DL1 and the sensing line SL1. have.

The multiplexer clock signal Mux_CLK and the multiplexer sensing signal Mux_sen are applied at a high level during the multiplexer sensing period. Thus, the multiplexer TFT (Mux TFT) and the switching TFT (SW) are kept in the turned on state. When the switching TFT SW is turned on, the data line DL1 and the sensing line SL1 are connected to each other. Accordingly, a path may be formed in which the multiplexer data VD_MUX output from the data driving circuit 12 is output from the sensing line SL1 via the multiplexer TFT (Mux TFT) and the data line DL1.

In the initialization period during the multiplexer sensing period, the initialization switch signal S_spre1 is applied to a high level which is an on level. Accordingly, the initialization switch SPRE1 operates so that the input terminal of the initialization voltage Vpre and the sensing line SL1 are connected to each other. When the input terminal of the initialization voltage Vpre and the sensing line SL1 are connected, the initialization power supply Vpre is connected to the source electrode of the multiplexer TFT Mux TFT through the sensing line SL1 and the data line DL1. Accordingly, the voltage of the source electrode of the multiplexer TFT (Mux TFT) is initialized so that the sensing voltage VS_MUX is detected as the initialization voltage Vpre.

The sensing switch signal S_spre2 is applied at a high level, which is an on level, in the sensing period during the multiplexer sensing period. Accordingly, the sensing switch SPRE2 switches to connect the ADC and the sensing line SL1. Accordingly, the multiplexer TFT (Mux TFT) operates in a source follower method, and thus the sensing voltage VS_MUX gradually increases. The sensing voltage VS_MUX is a voltage input to the gate electrode of the multiplexer TFT (Mux TFT), that is, the difference between the voltage of the multiplexer clock signal Mux_CLK and the threshold voltage Vth of the multiplexer TFT (Mux TFT) (Vs = Vg−). Up to Vth). Therefore, the threshold voltage Vth of the multiplexer TFT (Mux TFT) may be sensed based on the sensing voltage VS_MUX.

9 to 12 are diagrams showing the simulation results of the present invention.

Referring to FIG. 9, when the display panel is a 9.7 "QXGA 60Hz Portrait Panel, the simulation condition of detecting the threshold voltage of the multiplexer TFT according to an embodiment of the present invention is that the specification of the multiplexer TFT is not specified. 1000u / 6u, and the voltage of the multiplexer clock signal Mux_CLK may be set to 12V (minimum voltage) and the multiplexer data VD_MUX to 16V (maximum voltage).

FIG. 10 is a graph of results when simulated under the above conditions, and FIG. 11 is a table listing the results of FIG. 10.

FIG. 10 is a graph illustrating a sensing voltage VS_MUX sensed through the multiplexer data VS_MUX when the threshold voltage variation of the multiplexer TFT is -1V, 0V, 1V, or 2V. As shown in FIG. 10, since the multiplexer TFT (Mux TFT) operates in the source follower method during the sensing period, the sensing voltage VS_MUX gradually increases to the previous voltage. The graph of FIG. 10 is shown in FIG. 10 and 11, when the threshold voltage variation of the multiplexer TFT (Mux TFT) is -1V, 0V, 1V, or 2V, the threshold voltage calculated based on the Vth sensing value detected through the multiplexer data VD_MUX, respectively. It can be seen that the variations (-0.999, 0, 0.999, 1.998) are almost identical.

FIG. 12 illustrates the multiplexer TFT (Mux_TFT) when the level of the multiplexer clock signal Mux_CLK input to the gate electrode of the multiplexer TFT according to the threshold voltage change amount of the multiplexer TFT (Mux TFT) is varied. The graph shows the result of simulating Charging Ratio. The horizontal axis of the graph represents the positive bias temperature stress (PBTS) voltage of the multiplexer TFT (Mux TFT), that is, the Vth value according to bias or temperature stress. The vertical axis represents the voltage of the gate electrode MUX VGH of the multiplexer TFT. Areas marked with the same color in the graph mean that they have the same charging ratio, and the higher the charging rate, the darker the area. As can be seen from the graph, when the voltage of the gate electrode MUX VGH, that is, the level of the multiplexer clock signal Mux_CLK increases as the PBTS increases, the same charging rate as before may be obtained.

For example, when the threshold voltage variation sensing value of the multiplexer clock signal Mux_CLK is 20V, the level of the multiplexer clock signal Mux_CLK should be adjusted to 22V (20V + 2V). The same filling rate can be maintained.

FIG. 13 is a graph illustrating detection results of threshold voltages Vth of the multiplexer TFTs, in which the horizontal axis represents Mux Channel and the vertical axis represents threshold voltage Vth. As shown in the graph, the threshold voltage Vth of the multiplexer TFT (Mux TFT) has been sensed to have a range of 1.4V to 1.7V. On the other hand, the threshold voltage Vth of the multiplexer TFT (Mux TFT) was measured as 1.63V as a result of actual measurement in the TFT inline. That is, it is found that the value (1.63V) of measuring the threshold voltage Vth of the actual multiplexer TFT (Mux TFT) and the threshold voltage Vth (1.4V to 1.7V) sensed according to the sensing method of the present invention are similar. .

Through the above simulation, it is possible to sense the threshold voltage Vth of the multiplexer TFT according to the sensing method of the present invention, and based on the sensing result, the multiplexer clock signal Mux_CLK by the amount of change of the threshold voltage Vth. By adjusting the level of, you can get the same level of charge as before.

As described above, the present invention provides a sensing voltage VS_MUX that interconnects the data line DL and the sensing line SL and supplies the multiplexer data VS_MUX to the data line while the pixel PXL is turned off. The threshold voltage Vth of the multiplexer TFT (Mux TFT) is sensed. When it is determined that the threshold voltage Vth of the multiplexer TFT (Mux TFT) is changed, the level of the multiplexer clock signal Mux_CLK is increased by the amount of change in the threshold voltage Vth to compensate for the deterioration of the multiplexer TFT (Mux TFT). Can be.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present specification. Therefore, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 12 13: gate driver

Claims (10)

A pixel connected to the data line and the sensing line;
A multiplexer TFT interconnecting a data channel of the data driver and a data line according to a multiplexer clock signal input to the gate electrode;
A switching TFT which interconnects the data line and the sensing line according to a multiplexer sensing signal;
A sensing unit configured to detect a change in the threshold voltage of the multiplexer TFT through the sensing line,
And a level of the multiplexer clock signal varies according to a change in the threshold voltage of the multiplexer TFT. The method of claim 1,
The switching TFT is provided with a predetermined number of data lines as a unit. The method of claim 1,
And a timing controller configured to vary a level of the multiplexer clock signal according to a change in the threshold voltage of the multiplexer TFT. The method of claim 3,
The timing controller,
And varying a level of the multiplexer clock signal based on a sensing value of a threshold voltage of at least two or more multiplexer TFTs. The method of claim 4, wherein
The timing controller,
And varying the level of the multiplexer clock signal based on a threshold voltage having the largest change among sensing values of threshold voltages of at least two multiplexer TFTs. The method of claim 4, wherein
The timing controller,
And varying the level of the multiplexer clock signal based on an average value of sensing values of threshold voltages of at least two multiplexer TFTs. The method of claim 1,
The sensing unit,
And an initialization switch configured to switch an input terminal of an initialization power supply (Vpre) and the sensing line to be connected when the data line and the sensing line are connected to each other according to the multiplexer sensing signal. The method of claim 7, wherein
The sensing unit,
And a sensing switch configured to switch the sensing line to be connected to the ADC after disconnecting from the input terminal of the initialization power supply (Vpre) after a preset period. The method of claim 1,
The multiplexer TFT,
And a drain electrode connected to the data channel and a source electrode connected to the data line. The method of claim 9,
The multiplexer TFT,
And a multiplexer clock signal to the gate electrode and a multiplexer data voltage to the drain electrode to operate in a source follower method.

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