KR20190133535A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor element, which increases brightness, comprises: a first semiconductor layer; an active layer including a well layer and a barrier layer and arranged on the first semiconductor layer; a second semiconductor layer arranged on the active layer; an electron blocking layer arranged on the second semiconductor layer; and a third semiconductor layer arranged on the electron blocking layer. The electron blocking layer includes a first electron blocking layer, a second electron blocking layer, and a third electron blocking layer which are sequentially arranged on the second semiconductor layer. The concentration of a p-type dopant of the second electron blocking layer is higher than the concentration of the p-type dopant of the first electron blocking layer, and a peak of a concentration profile of the p-type dopant exists in the active layer.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device having improved brightness and improved operating voltage.

Since a semiconductor device including a compound such as GaN or AlGaN has many advantages, such as having a wide and easy-to-adjust band gap energy, the semiconductor device may be variously used as a light emitting device, a light receiving device, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using nitride semiconductor materials can realize various colors such as red, green, blue, and ultraviolet rays by developing thin film growth technology and device materials. Efficient white light can be realized by using fluorescent materials or combining colors, and has the advantages of low power consumption, semi-permanent life, fast response speed, safety and environmental friendliness compared to conventional light sources such as fluorescent and incandescent lamps.

In addition, when a light-receiving device such as a photodetector or a solar cell is manufactured using a nitride semiconductor material, the development of device materials absorbs light in various wavelength ranges and generates a photocurrent, thereby generating a photocurrent. Light is available. It also has the advantages of fast response speed, safety, environmental friendliness and easy control of device materials, making it easy to use in power control or microwave circuits or communication modules.

Therefore, the semiconductor device may replace a light emitting diode backlight, a fluorescent lamp, or an incandescent bulb, which replaces a cold cathode tube (CCFL) constituting a backlight module of an optical communication means, a backlight of a liquid crystal display (LCD) display device. Applications are expanding to include white light emitting diode lighting devices, automotive headlights and traffic lights, and sensors that detect gas or fire, and applications to high frequency application circuits, other power control devices, and communication modules.

On the other hand, in the semiconductor element used as the light source of the illuminating device, since the light emitted from the light emitting layer is isotropic, it is irradiated to the inside of the crystal growth substrate, and the light is emitted from the back and side surfaces of the substrate. In this case, light having an incident angle at the interface with the air layer of the light irradiated inside the substrate is greater than the critical angle is totally reflected at the interface, confined inside the substrate, and is not emitted to the outside of the substrate, thereby causing a decrease in luminance of the semiconductor device. In the case of a nitride semiconductor device, hole injection efficiency using a dopant is relatively low, which is difficult to improve luminance, and when the concentration of the dopant is increased by increasing the dopant amount of the dopant, the film quality of the doped layer is lowered, thereby improving the characteristics of the semiconductor device. There is a problem of deterioration. The present invention has been proposed to solve this problem.

The technical problem to be solved by the present invention is to provide a semiconductor device with improved brightness by improving the hole injection efficiency without degrading the characteristics of the semiconductor device.

Another technical problem to be solved by the present invention is to provide a semiconductor device with improved operating voltage.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention includes a first semiconductor layer, an active layer disposed on the first semiconductor layer including a well layer and a barrier layer, a second semiconductor layer disposed on the active layer, and the second semiconductor. An electron blocking layer disposed on the layer and a third semiconductor layer disposed on the electron blocking layer, wherein the electron blocking layer comprises: a first electron blocking layer and a second disposed sequentially on the second semiconductor layer; An electron blocking layer and a third electron blocking layer, wherein the concentration of the p-type dopant of the second electron blocking layer is higher than that of the p-type dopant of the first electron blocking layer, and the concentration of the p-type dopant in the active layer There is a peak in the profile.

The p-type dopant may be present in the third electron blocking layer at a concentration lower than the peak, but the concentration of the p-type dopant in the thickness direction may be constant.

The second electron blocking layer includes a 2-1 electron blocking layer and a 2-2 electron blocking layer sequentially disposed on the first electron blocking layer, and the concentration of the p-type dopant is 2-1. The electron blocking layer may be higher than the second-2 electron blocking layer.

The 2-1 electron blocking layer may be grown in a temperature range of more than 660 ℃ to 735 ℃.

The p-type dopant having a concentration range of 1.35E + 20 atoms / cm ³ or more and 1.65E + 20 atoms / cm ³ or less may be doped into the 2-1 electron blocking layer.

The first electron blocking layer and the second-2 electron blocking layer may be grown in a temperature range higher by 100 ° C. or more than the 2-1 electron blocking layer.

The second semiconductor layer and the first electron blocking layer may be doped with a p-type dopant having a lower concentration than the 2-1 electron blocking layer.

The active layer may have a multi quantum well (MQW) structure.

The p-type dopant doped in the second semiconductor layer may be doped to the last well layer region of the multi-quantum well.

According to one embodiment of the present invention, the 2-1 electron blocking layer is grown at a low temperature, and the layer adjacent to the 2-1 electron blocking layer is grown at a high temperature, so that a large amount of p is present in the 2-1 electron blocking layer. By lowering the concentration of the total dopant doped in the semiconductor device while doping the dopant, the operation voltage problem due to the separation of the dopant is improved, and the light absorption problem due to the doping is reduced, thereby improving the brightness of the semiconductor device. .

Effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a conceptual diagram of a semiconductor device according to an embodiment of the present invention.
2 is a conceptual diagram of an electron blocking layer of a semiconductor device according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a second electron blocking layer of the electron blocking layer of the semiconductor device according to the exemplary embodiment of the present invention.
4 is a conceptual diagram of a third electron blocking layer of a semiconductor device according to an embodiment of the present invention.
5 is a conceptual diagram of an active layer of a semiconductor device according to an embodiment of the present invention.
6 is a conceptual diagram of a third semiconductor layer of a semiconductor device according to an embodiment of the present disclosure.
7 is a graph showing an analysis result by a time-of-flight secondary ion mass spectrometry (TOF-SIMS) of a conventional semiconductor device.
8 is a graph illustrating an analysis result by time-of-flight secondary ion mass spectrometry (TOF-SIMS) of a semiconductor device according to an embodiment of the present invention.
9 is a graph illustrating an operating voltage of a semiconductor device according to an embodiment of the present disclosure.
10 is a graph illustrating the light output and the external quantum efficiency of a semiconductor device according to an exemplary embodiment of the present invention.

Hereinafter, the details of the above-described objects and technical configurations of the present invention and the effects thereof will be more clearly understood by the following detailed description.

In the description of the present invention, terms such as first and second which are used hereinafter are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are used as the first and second terms. It is not limited to.

Singular expressions include plural expressions unless the context clearly indicates otherwise. The terms “comprises” or “having” are intended to indicate that a feature, number, step, operation, component, part, or combination thereof is present on the specification and that one or more other features, numbers, or steps are present. It is to be understood that the acts, components, parts or combinations thereof may be added.

As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements, or Does not exclude additional

In the description of the present invention, each layer (film), region, pattern or structure is "on" or "under" the substrate, each layer (film), region, pad or pattern. "Formed in" includes both those formed directly or through another layer. Criteria for the top / bottom or bottom / bottom of each layer will be described with reference to the drawings.

Hereinafter, the semiconductor device 10 according to an exemplary embodiment will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram of a semiconductor device 10 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 10 according to an exemplary embodiment may include a first semiconductor layer 100, an active layer 200, a second semiconductor layer 300, an electron blocking layer 400, and a third The semiconductor layer 500 is included.

The first semiconductor layer 100 may be implemented with compound semiconductors such as group III-V and group II-VI, and the first semiconductor layer 100 may be doped with a first dopant. The first semiconductor layer 100 is a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), for example, GaN, AlGaN, InGaN, InAlGaN and the like can be selected. Meanwhile, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te, and when the first dopant is an n-type dopant, the first semiconductor layer 100 may be an n-type semiconductor layer.

The active layer 200 may be disposed on the first semiconductor layer 100. The active layer 200 is a layer where electrons (or holes) injected through the first semiconductor layer 100 and holes (or electrons) injected through the third semiconductor layer 500 meet each other. As the holes recombine, they transition to low energy levels, producing light with corresponding wavelengths.

The active layer 200 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, but is not limited thereto. . The active layer 200 may generate light in the ultraviolet wavelength band.

If the active layer 200 is formed in a well structure, the well layer / barrier layer of the active layer 200 may be InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP). / AlGaP may be formed of any one or more pair structure, but is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

A second semiconductor layer 300 is _{In x Al y Ga 1 -x- y} P (0≤x≤1, 0≤y≤1, 0≤x + y≤1) or _{In x Al y Ga 1-xy} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1)

A semiconductor material having a compositional formula may be selected from AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, and the like.

Meanwhile, a second dopant may be doped in the second semiconductor layer 300, and Mg, Zn, Ca, Sr, and Ba may be doped as the second dopant.

An electron blocking layer (EBL) 400 may be disposed on the second semiconductor layer 300. The electron blocking layer 400 blocks the flow of electrons supplied from the first semiconductor layer 100 to the third semiconductor layer 500, thereby increasing the probability of electrons and holes recombining in the active layer 200. have. The energy band gap of the electron blocking layer 400 may be larger than the energy band gap of the active layer 200 and / or the third semiconductor layer 500.

Semiconductor material having a composition formula of the electron blocking layer 400 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1), for example, AlGaN , InGaN, InAlGaN, etc. may be selected, but is not limited thereto. In addition, the second blocking dopant may be doped in the electron blocking layer 400.

The third semiconductor layer 500 may be disposed on the electron blocking layer 400. The third semiconductor layer 500 is Ⅲ-Ⅴ group, may be implemented as a compound semiconductor such as Ⅱ-Ⅵ prosthesis, In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1 , 0 ≦ x + y ≦ 1), or a material selected from AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP. The second semiconductor layer 500 may be doped with a second dopant, and when the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the third semiconductor layer 500 may be a p-type semiconductor layer. Can be. 2 is a conceptual diagram of an electron blocking layer 400 of a semiconductor device 10 according to an embodiment of the present invention. Referring to FIG. 2, an electron blocking layer of the semiconductor device 10 according to an embodiment of the present invention. 400 includes a first electron blocking layer 410, a second electron blocking layer 420, and a third electron blocking layer 430.

The first electron blocking layer 410 may be disposed on the second semiconductor layer 300. The first electron blocking layer 410 may include AlGaN, and the content of Al may be 29% or more and 33% or less. When the Al content is less than 29%, it may be difficult to form a high energy band gap between the active layer 200 and the third semiconductor layer 500. When the Al content exceeds 33%, it may be difficult to inject sufficient current due to an increase in resistance. Because it can.

The first electron blocking layer 410 has a p-type dopant of 4.18E + 19 atoms / cm ³ or more and 4.62E + 19 atoms / cm ³ It may be doped in the following concentration ranges. If the doping concentration of the p-type dopant is less than 4.18E + 19 atoms / cm ³ , there may be a loss of the p-type dopant doped in the 2-1 electron blocking layer 421 to be described later, and 4.62E + 19 atoms / cm This is because, if it exceeds ³ , device characteristics may be degraded due to overdoping.

Since the first electron blocking layer 410 has the above-described composition, a high energy band gap is formed between the active layer 200 and the third semiconductor layer 500 so that electrons supplied from the first semiconductor layer 100 are transferred to the third layer. The flow out of the semiconductor layer 500 can be effectively blocked.

Meanwhile, the first electron blocking layer 410 may be grown at a temperature range of 860 ° C. or more and 960 ° C. or less, and when grown at a temperature below the range, the second electron blocking layer 421 may be described later. When the doped p-type dopant moves toward the first electron blocking layer 410 and cannot dop the high concentration of the p-type dopant in the 2-1 electron blocking layer 421, and is grown at a temperature exceeding the above range. It can be difficult to achieve the target thickness you want to grow.

As described above, the electron blocking layer 400 includes a second electron blocking layer 420 and a third electron blocking layer (sequentially stacked on the first electron blocking layer 410 and the first electron blocking layer 410). 430).

The second electron blocking layer 420 will be described with reference to FIG. 3, and the third electron blocking layer 430 will be described later with reference to FIG. 4.

3 is a conceptual diagram illustrating a second electron blocking layer 420 included in the electron blocking layer 400 of the semiconductor device 10 according to an embodiment of the present disclosure. Referring to FIG. 3, a second electron blocking layer is illustrated. The 420 includes a 2-1 electron blocking layer 421 and a 2-2 electron blocking layer 423 sequentially disposed on the first electron blocking layer 410.

The 2-1 electron blocking layer 421 may include AlGaN, and the content of Al may be 3.8% or more and 4.2% or less. If Al is included below 3.8%, light absorption may occur, and if it exceeds 4.2%, current injection efficiency may be reduced due to an increase in resistance.

The p-type dopant may be doped in the 2-1 electron blocking layer 421 at a concentration of 1.35E + 20 atoms / cm ³ or more and 1.65 + 20 atoms / cm ³ or less. If the doping concentration is less than the above range, it is difficult to improve the brightness of the semiconductor device 10, and if it exceeds the above range, light absorption due to overdoping may occur.

The concentration of the p-type dopant doped in the 2-1 electron blocking layer 421 is higher than that of the first electron blocking layer 410. This is because the 2-1 electron blocking layer 421 is grown in a low temperature range of 660 ° C. or higher and 735 ° C. or lower unlike the two adjacent layers. Thus, the high concentration of p-type in the 2-1 electron blocking layer 421 is increased. As the dopant is doped, the luminance of the semiconductor device according to the exemplary embodiment may be improved.

On the other hand, when growing the 2-1 electron blocking layer 421, when the growth temperature is less than the temperature range, the time required to achieve the target doping concentration increases, and when the temperature exceeds the temperature range, p-type It may be difficult to dop the dopant at high concentrations.

While the high concentration of p-type dopant is doped in the 2-1 electron blocking layer 421, hole injection may be enhanced, but light absorption and operation voltage may increase due to a decrease in film quality. This can be solved by growing the 2-2 electron blocking layer 423 adjacent to the 2-1 electron blocking layer 421 at a high temperature range of 900 ° C or more and 990 ° C or less to improve film quality. In this case, when the growth is below the temperature range, the film quality improvement effect of the 2-1 electron blocking layer 421 is insignificant, and when the growth is over the temperature range, the film quality may drop rapidly.

The second-2 electron blocking layer 423 may include AlGaN, and the content of Al may be 3.8% or more and 4.2% or less. If the content of Al is less than the above range, there is a problem of absorbing light, and if it exceeds the above range, the current injection efficiency may be lowered.

Meanwhile, the thickness of the first electron blocking layer 410 may be 2.38 nm or more and 2.63 nm or less, and the thicknesses of the 2-1 electron blocking layer 421 and the 2-2 electron blocking layer 423 may be 10 nm, respectively. Or more to 13.1 nm or less. If the thickness of each layer is less than the minimum range, the electron blocking efficiency may decrease, and if the thickness exceeds the maximum range, a problem may arise in that the operating voltage rises.

Next, the third electron blocking layer 430 will be described with reference to FIG. 4.

4 is a conceptual diagram of a third electron blocking layer 430 of the semiconductor device 10 according to an embodiment of the present invention.

The third electron blocking layer 430 is composed of AlGaN layers 431-1, 431-2, ..., 431-n and GaN (432-1, 432-2, ..., 432-n) layers. It may include a pair (pair), may include a superlattice structure having a plurality of pairs, and may be configured as about 12 pairs, but is not limited thereto.

In this case, the AlGaN layer and the GaN layer constituting each pair may have a thickness of 0.8 nm or more and 1.05 nm or less, respectively. When the thickness of each layer is less than 0.8 nm, it may be difficult to prevent excessive flow of electrons, and when the thickness of each layer exceeds 1.05 nm, the thickness of the third electron blocking layer 430 may be thickened to increase resistance. This is because problems can occur.

The AlGaN layer and the GaN layer constituting each pair may be grown in a temperature range of 900 ° C or more and 990 ° C or less, respectively. If it is grown below 900 ℃ growth time may be long to obtain the desired thickness, because when grown at a temperature exceeding 990 ℃ film quality may be lowered.

When the pair is composed of 12 pairs, the pair is divided into four groups, and the AlGaN layer of the first group in the order adjacent to the second-second electron blocking layer 423 has a concentration range of 24.7% or more to 27.3% or less. The AlGaN layer of the second group may include Al having a concentration range of 27.6% or more and 30.5% or less, and the AlGaN layer of the third group may have a concentration range of 21.9% or more and 24.2% or less. It may include Al having, and the AlGaN layer of the fourth group may include Al having a concentration range of 15.2% or more to 16.8% or less.

By adjusting the Al concentration of the AlGaN layer constituting the pair as described above, it is possible to prevent the excessive flow of electrons to reduce the consumption of hole carriers due to non-radiative recombination to improve the light efficiency. In addition, since the effective potential of the hole is lowered to facilitate the diffusion of the hole, the hole injection efficiency may be improved. On the other hand, if the concentration of the AlGaN layer of each group is out of the above range, care should be taken because the difference in Al concentration with other adjacent groups is insignificant, so that the light efficiency and the hole injection efficiency may be improved.

5 is a conceptual diagram of an active layer 200 included in a semiconductor device 10 according to an embodiment of the present invention.

Referring to FIG. 5, in the active layer 200 included in the semiconductor device 10 according to an exemplary embodiment, a multi-quantum well (MQW) in which well layers 211 and 221 and barrier layers 213 are alternately disposed. It has a multi quantum well (SUL) structure, and includes an outermost barrier layer (LQB) 223 at a portion adjacent to the second semiconductor layer 300.

The outermost barrier layer 223 is made of GaN, and may be grown in a temperature range of 830 ° C. or more and 920 ° C. or less.

The outermost barrier layer 223 is located at the outermost portion of the multi-quantum well and serves as a barrier layer, and is formed thicker than the prior art with a thickness of 8.6 nm or more and 9.5 nm or less, and is distributed in a multi-quantum well. By effectively preventing re-diffusion of the dopant toward the third semiconductor layer 500, hole injection may be enhanced in the multi-quantum well. In addition, the outermost barrier layer 223 also serves to prevent the well layers 211 and 221 from being damaged by heat.

In this case, the p-type dopant distributed in the multi-quantum well may be supplied from the second semiconductor layer 300.

The second semiconductor layer 300 may include GaN and provide a p-type dopant for hole injection in the multi-quantum well. The p-type dopant may be doped in a concentration range of 1.20E + 20 atoms / cm ³ or more and 1.49E + 20 atoms / cm ³ or less. If the doping concentration is less than 1.20E + 20 atoms / cm ³ , sufficient hole injection is not performed in the multi-quantum well, so that the effect of improving the brightness is insignificant. If the doping concentration exceeds 1.49E + 20 atoms / cm ³ , the doping is excessive. This is because the film quality degradation problem may occur.

In this case, the concentration of the p-type dopant doped in the second semiconductor layer 300 is lower than that doped in the 2-1 electron blocking layer 421.

On the other hand, the second semiconductor layer 300 may be grown in a temperature range of more than 830 ℃ to 920 ℃.

In this case, the thickness of the second semiconductor layer 300 may be 4.75 nm or more and 5.25 nm or less, and when the thickness is less than 4.75 nm, there is no effect of improving the deterioration of the low power characteristic, and when the thickness exceeds 5.25 nm, the resistance is increased. This is because the current efficiency can be reduced.

6 is a conceptual diagram of a third semiconductor layer 500 of a semiconductor device according to an embodiment of the present disclosure.

The third semiconductor layer 500 includes GaN and may be grown in a temperature range of 970 ° C. or more and 1080 ° C. or less. This is because when the growth temperature is lower than 970 ° C, the hole injection efficiency is lowered, and when the growth temperature is higher than 1080 ° C, deterioration of another layer may occur.

The third semiconductor layer 500 may be formed of a plurality of layers, preferably, three layers. In this case, the 3-1 semiconductor layer 510, the 3-2 semiconductor layer 520, and the 3-3 semiconductor layer 530 may be disposed in the order adjacent to the third electron blocking layer 430. .

The 3-1 semiconductor layer 510 is a layer in which the film quality of the 3-2 semiconductor layer 520, which will be described later, is improved and holes are diffused, and have a thickness of 38 nm or more and 52.5 nm or less. This is because when the thickness is less than 38 nm, the hole diffusion efficiency decreases, and when the thickness exceeds 52.5 nm, a problem may occur in which the resistance increases.

The third-2 semiconductor layer 520 is a layer into which holes are substantially injected from the third semiconductor layer 500, and has a thickness of 6 nm or more and 9.45 nm or less, and 6.9E + 19 atoms / cm ³ or more and 7.7. The p-type dopant having a concentration of E + 19 atoms / cm ³ or less can be doped.

The third semiconductor layer 530 is a layer in which holes are injected together with the third-2 semiconductor layer 520 and has a thickness of 0.95 nm or more and 1.05 nm or less, and the p-type dopant is 2.1E + 20 atoms /. It may be doped at a concentration of at least cm ³ and up to 2.4E + 20 atoms / cm ³ .

When the thicknesses of the third semiconductor layer 520 and the third semiconductor layer 530 are less than the above-mentioned ranges, hole injection efficiency may be lowered, and when the thickness is exceeded, a problem of resistance increase may occur.

In addition, since the hole injection efficiency may be improved by changing the concentration of the p-type dopant doped in the 3-2 semiconductor layer 520 and the 3-3 semiconductor layer 530, the p-type dopant is in the above-described concentration range. It may be advantageous to be doped in. 7 is a graph showing an analysis result by secondary ion mass spectrometry (TOF-SIMS) of a conventional semiconductor device.

Conventionally, when fabricating a nitride semiconductor device, a large amount of p-type dopant is doped to dope a p-type dopant having poor doping efficiency in a multi-quantum well region. However, when the amount of the p-type dopant is increased to increase the doping efficiency, the separation of the p-type dopant occurs to increase the operating voltage, and light absorption due to the over-doping of the p-type dopant occurs, Crystal defects are generated due to despreading, resulting in a problem of deterioration of characteristics of the semiconductor device.

When the doping amount of the p-type dopant is increased, the concentration of the p-type dopant doped in the multi-quantum well region (180 nm to 240 nm) is low, and the p-type dopant is doped with the third semiconductor layer 500. Since the concentration of the p-type dopant is maintained at a high concentration up to an adjacent region of the quantum well, that is, from 0 nm to about 180 nm, deterioration of characteristics of the semiconductor device may occur. In particular, since the p-type dopant is present at a high concentration from the third semiconductor layer 500 to the electron blocking layer 400 located at a depth of about 100 nm, light absorption is liable to occur and luminance is lowered.

On the other hand, referring to FIG. 8, which is a graph illustrating an analysis result of a secondary ion mass spectrometry (TOF-SIMS) of a semiconductor device 10 according to an embodiment of the present disclosure, a semiconductor device according to an embodiment of the present invention ( 10) a peak of a concentration profile of the p-type dopant is present in an area adjacent to the second semiconductor layer 300 of the active layer 200.

Specifically, the lowest point of the peak is formed in the second electron blocking layer 420 and the active layer 200. In this case, in FIG. 8, the second electron blocking layer 420 is present in a depth of 64 nm to 87 nm, and the active layer 200 is present in a range of 94.5 nm to 210 nm. The peak of the peak may be formed in an area adjacent to the second semiconductor layer 300 of the active layer 200. That is, the highest point may be present in the outermost barrier layer 223 present in the interval 94.5 nm to 103.5 nm, or may be present in another active layer 200 region adjacent to the outermost barrier layer 223.

In this case, in FIG. 8, the first electron blocking layer 410 is present in the range of 87 nm to 89.5 nm, and the second semiconductor layer 300 is present in the region of 89.5 nm to 94.5 nm.

On the other hand, the semiconductor device 10 according to an embodiment of the present invention is formed with a higher concentration of the p-type dopant doped in the active layer 200 than the conventional semiconductor device, p-type dopant to the last well layer region of the multi-quantum well May be doped.

At this time, a slope in the rear direction (about 70 to 100 nm) of the peak is formed rapidly, thereby preventing the p-type dopant from moving in the direction of the third semiconductor layer 500, thereby preventing deterioration of light absorption characteristics.

Meanwhile, the p-type dopant is present in the third electron blocking layer 430 in the range of about 45 nm to 64 nm, but the concentration of the p-type dopant in the thickness direction is constant. 'Constant' here means that the concentration change in the thickness direction is small, and there is no significant peak. At this time, the concentration of the p-type dopant present in the third electron blocking layer 430 is similar to that of the low-p-type dopant existing in the direction of the third electron blocking layer 430 of the peak.

Therefore, since the concentration of the total p-type dopant doped in the semiconductor device 10 is low, the problem of crystal defects due to the over-doping of the p-type dopant can be solved, and the problem of increasing the operating voltage and device characteristics can be improved. .

The concentration profile of the p-type dopant is obtained by growing the 2-1 electron blocking layer 421 at a temperature of at least 100 ° C. or less than the adjacent first electron blocking layer 410 and the 2-2 electron blocking layer 423. Can lose.

As described above, the p-type dopant is heavily doped in the 2-1 electron blocking layer 421, but the 2-2 electron blocking layer 423 and the first electron adjacent to the 2-1 electron blocking layer 421 are formed. Since the growth temperature of the blocking layer 410 is higher, a doping delay or a dopant diffusion phenomenon of the p-type dopant may occur, so that an actual concentration peak exists in an area adjacent to the second semiconductor layer 300 of the active layer 200. .

The semiconductor device 10 of the present invention has a concentration profile of the p-type dopant as shown in FIG. 8, so that a smaller amount of the p-type dopant than the conventional semiconductor device is doped and doped the p-type dopant in the multi-quantum well region. Efficiency can be improved to improve light output and operating voltage.

9 is a graph illustrating an operating voltage of the semiconductor device 10 according to an embodiment of the present disclosure. Referring to FIG. 9, an operation voltage of the semiconductor device 10 according to an embodiment of the present disclosure is improved. You can check it. For example, when a current of 20 mA is applied, the operating voltage of the embodiment is about 26.5V, and the operating voltages of Comparative Example 1 and Comparative Example 2 are higher than 26.5V. That is, since the operating voltage of the embodiment appears lower, it can be seen that the operating voltage of the embodiment is improved compared to Comparative Example 1 and Comparative Example 2.

10 is a graph showing the light output and the external quantum efficiency of the semiconductor device 10 according to an embodiment of the present invention.

Referring to FIG. 10, it can be seen that the embodiment has improved external quantum efficiency (EQE) when compared with Comparative Example 1 and Comparative Example 2 grown at high temperatures without changing the growth temperature of the electron blocking layer 400. have. This means that the semiconductor device of the embodiment can emit more photons when the same current is applied. Therefore, it can be seen that the light output of the semiconductor device 10 according to the embodiment of the present invention is improved.

In particular, the embodiment has a higher external quantum efficiency in the low current density region compared to Comparative Example 1 and Comparative Example 2, it may be more advantageous when applied to low current density products such as mobile phones. An embodiment of the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope of the technical spirit of the embodiment is possible It will be apparent to those of ordinary skill in the art to which an embodiment belongs.

10: semiconductor device
100: first semiconductor layer
200: active layer
211, 221: well layer
213: barrier layer
223: outermost barrier layer
300: second semiconductor layer
400: electron blocking layer
410: first electron blocking layer
420: second electron blocking layer
421: 2-1 electron blocking layer
423: second-2 electron blocking layer
430: third electron blocking layer
500: third semiconductor layer

Claims (9)

A first semiconductor layer;
An active layer disposed on the first semiconductor layer including a well layer and a barrier layer;
A second semiconductor layer disposed on the active layer;
An electron blocking layer disposed on the second semiconductor layer; And
A third semiconductor layer disposed on the electron blocking layer;
Including,
The electron blocking layer,
A first electron blocking layer, a second electron blocking layer, and a third electron blocking layer sequentially disposed on the second semiconductor layer,
The concentration of the p-type dopant of the second electron blocking layer is higher than that of the p-type dopant of the first electron blocking layer,
And a peak of a concentration profile of the p-type dopant is present in the active layer. The method of claim 1,
The p-type dopant is present in the third electron blocking layer at a concentration lower than the peak, but the concentration of the p-type dopant in the thickness direction is constant. The method of claim 1,
The second electron blocking layer includes a 2-1 electron blocking layer and a 2-2 electron blocking layer sequentially disposed on the first electron blocking layer,
And a concentration of the p-type dopant is higher than that of the 2-2 electron blocking layer. The method of claim 3,
The 2-1 electron blocking layer is grown in a temperature range of more than 660 ℃ to 735 ℃. The method of claim 3,
And a p-type dopant having a concentration range of 1.35E + 20 atoms / cm ³ or more to 1.65E + 20 atoms / cm ³ or less in the 2-1 electron blocking layer. The method of claim 3,
The first electron blocking layer and the 2-2 electron blocking layer are grown in a temperature range of at least 100 ℃ higher than the 2-1 electron blocking layer. The method of claim 3,
The p-type dopant having a lower concentration than the 2-1 electron blocking layer is doped in the second semiconductor layer and the first electron blocking layer. The method of claim 1,
The active layer has a multi quantum well (MQW) structure. The method of claim 8,
And a p-type dopant doped in the second semiconductor layer to the last well layer region of the multi-quantum well.

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