KR20190070046A - Electroluminescence display and driving method thereof - Google Patents

Abstract

The present invention relates to an electroluminescent display and a driving method thereof. The electroluminescent display has a sensing unit supplying a first reference voltage to a sensing line in a reset period set at the end of a sensing mode in which a threshold voltage of a driving device is sensed and resetting a gate-source voltage of the driving device to 0V. The stress of the driving device is minimized during a power-off period, thereby preventing the stress accumulation of the driving device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display device,

The present invention relates to an electroluminescent display device and a driving method thereof, in which there is no stress accumulation of a driving device during a power-off period.

An electroluminescent display device is classified into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, and has a high response speed, a high luminous efficiency, a high brightness and a wide viewing angle There are advantages.

The pixels of the organic light emitting display include an OLED and a driving element for driving the OLED by supplying current to the OLED according to the gate-source voltage. An OLED of an organic light emitting display includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are transferred to the emission layer (EML) to form excitons. As a result, the emission layer (EML) generates visible light .

The driving device may be realized by a TFT having a metal oxide semiconductor field effect transistor (MOSFET) structure. The driving device should have uniform electrical characteristics among all the pixels, but there may be a difference between the pixels due to the process deviation and the device characteristic deviation, and may vary with the elapse of the display driving time. An internal compensation method and an external compensation method may be applied to the electroluminescence display device to compensate for the deviation of electrical characteristics of the driving device. The internal compensation method samples the gate-source voltage (Vgs) of the driving device which varies depending on the electrical characteristics of the driving device and compensates the data voltage by the gate-source voltage thereof. The external compensation method senses the voltage of a pixel which changes according to the electrical characteristics of the driving element and compensates the electrical characteristic deviation of the driving element between the pixels by modulating the data of the input image in the external circuit based on the sensed voltage.

As the display driving period is increased, the gate bias stress of the driving device is accumulated and the electrical characteristics of the driving device may be deteriorated. For example, in an external compensation method of a field emission display, a threshold voltage of a driving device is sensed before the power is turned off. The compensation value is updated with the compensation value of the selected threshold voltage according to the sensed threshold voltage immediately before the power is turned off when the power supply is turned on again. The source voltage Vs of the driving device may be a positive voltage while the gate voltage Vg of the driving device is Vg = 0V before the power is turned off. In this case, the gate-source voltage Vgs of the driving device is a negative voltage, and this voltage is maintained during the off period of the power source. During the off period of the power source, the negative gate bias stress of the driving device accumulates and the driving device deteriorates. If the driving element is deteriorated during the power-off period between the power-off time point and the power-on point, the compensation value obtained at the power-on time point does not reflect additional deterioration of the driving element accumulated during the power- Is not an optimal value for compensating the threshold voltage.

Accordingly, the present invention provides an electroluminescent display device and a method of driving the same, in which the gate-source voltage (Vgs) of the driving device is minimized at the time of power-off to minimize the stress of the driving device during the power-off period.

An electroluminescent display device of the present invention includes: a display panel including a sensing line to which data lines and gate lines are intersected, a plurality of sub-pixels are disposed, and a source of a driving device driving the sub-pixels is connected; And a sensing unit for supplying a first reference voltage to the sensing line and resetting the gate-source voltage of the driving device to 0V during a reset period set at the end of a sensing mode in which a threshold voltage of the driving device is sensed.

The driving method of the electro-luminescence display device may include supplying a first reference voltage to the sensing line during a reset period set at the end of a first sensing mode in which a threshold voltage of the driving device is sensed, To 0V; The gate-source voltage of the driving device is maintained at 0 V during a power-off period until the field-emission display device is powered on again; And sensing the mobility of the driving device in a second sensing mode, which is performed when the field emission display device is powered on again.

The present invention minimizes the stress of the driving element during the power-off period by controlling the gate-source voltage (Vgs) of the driving element to 0 V in the sensor mode (OFF RS) executed at the time of power OFF using the switch of the sensing part . Therefore, according to the present invention, there is no stress accumulation of the driving element during the power-off period.

The present invention can accurately compensate the threshold voltage of the driving device when the power is turned on again with the compensation value selected according to the threshold voltage of the driving device sensed at the power-off time point and is normally driven. As a result, the present invention can improve picture quality and prolong the life of pixels.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit;
3 and 4 are views showing a sensing mode.
5 is a detailed view showing an active section and a vertical blank section.
FIG. 6 is a circuit diagram showing the sensing unit shown in FIG. 2 in detail.
7 is a waveform diagram showing the operation of the pixel circuit in the normal driving mode.
8 is a waveform diagram showing a pixel circuit and a sensing unit in the normal driving mode.
9 is a waveform diagram showing the operation of the pixel circuit in the OFF RS mode.
10A is a waveform diagram showing a pixel circuit and a sensing unit in a sampling interval of the OFF RS mode.
10B is a waveform diagram showing a pixel circuit and a sensing unit in the reset period of the OFF RS mode.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. To fully disclose the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited to those shown in the drawings. Like reference numerals refer to like elements throughout the specification. In the following description of the present invention, detailed description of known related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

Where the term "comprises", "comprising", "having", "having", or the like is used herein, other parts may be added as long as "only" is not used. The singular forms of the components may be construed in plural unless otherwise expressly stated.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two components is described as 'on', 'on top', 'under', or 'next to' Quot; directly " or " direct " may be interposed between those components that are not used.

The first, second, etc. may be used to distinguish the components, but these components are not limited to the function or structure of the component or the names of components attached to the components.

The following embodiments can be combined or combined with each other partly or entirely, and technically various interlocking and driving are possible. Each embodiment may be feasible independently of one another and may be feasible in conjunction.

In the electroluminescent display device of the present invention, the pixel circuit includes a driving element and a switching element. The driving element and the switching element may be implemented as one or more transistors of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor may be an oxide transistor having an oxide semiconductor pattern or an LTPS transistor having a low temperature poly-silicon (LTPS) semiconductor pattern. A transistor is a three-electrode device including a gate, a source, and a drain. The transistor may be implemented as a thin film transistor (TFT) on the display panel 100. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode in which the carrier exits from the TFT. The flow of carriers from the transistor flows from the source to the drain. In the case of an n-channel transistor (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The direction of the current in the n-channel transistor (NMOS) flows from the drain to the source side. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since the holes flow from the source to the drain in the p-channel transistor (PMOS), current flows from the source to the drain. Therefore, it should be noted that the source and the drain of the transistor are not fixed because the source and the drain can be changed according to the applied voltage. In the following description, the source and the drain of the transistor will be referred to as first and second electrodes.

The gate signal of the TFT used as the switch elements swings between the gate on voltage and the gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage is set to a voltage lower than the threshold voltage of the TFT. The TFT is turned-on in response to the gate-on voltage, while turning off in response to the gate-off voltage. In the case of an NMOS, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of PMOS, the gate-on voltage may be the gate-low voltage (VGL) and the gate-off voltage may be the gate-high voltage (VGH).

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device of the present invention will be described focusing on an example in which an external compensation circuit is applied.

An external compensation circuit is applied to the electroluminescence display device of the present invention.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention. 2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit;

1 and 2, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The electroluminescent display device of the present invention operates in a normal driving mode for displaying an input image on a screen and a sensing mode for sensing electrical characteristics of pixels. In the normal drive mode, the display panel drive circuits 110, 112, and 120 write pixel data to the pixels during the active period (AT) of the display drive period in FIG. 3 under the control of the timing controller 130. In the sensing mode, the display panel driving circuits 110, 112, and 120 are turned on at the power-on timing in FIG. 3 under the control of the timing controller 130, during the vertical blank period VB during the display driving period, The electrical characteristics of the driving device DT are sensed and a compensation value is selected according to the sensing result to compensate for the change in the electrical characteristics of the driving device DT.

The screen of the display panel 100 includes an active area AA for displaying an input image. A pixel array is arranged in the active area AA. The pixel array includes a plurality of data lines 102, a plurality of gate lines 104 intersecting the data lines 102, and pixels arranged in a matrix.

Each of the pixels may be divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit.

Touch sensors may be disposed on the display panel 100. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors disposed on the screen of a display panel or embedded in a pixel array as an on-cell type or an add-on type .

The display panel drive circuits 110, 112, and 120 include a data driver 110 and a gate driver 120. A demultiplexer 112 disposed between the data driver 110 and the data lines 102 may be disposed. The demultiplexer 112 may be omitted.

The display panel driving circuits 110, 112 and 120 write data of the input image to the pixels of the display panel 100 under the control of the timing controller (TCON) 130 in the normal driving mode, Display the image. The display panel drive circuits 110, 112, and 120 may further include a touch sensor driver for driving the touch sensors. The touch sensor driving unit is omitted in Fig. In a mobile device or a wearable device, the display panel driving circuit, the timing controller 130, and the power supply circuit can be integrated into one integrated circuit.

2, the data driver 110 generates digital data of the input image received from the timing controller 130 every frame period using a digital-to-analog converter (DAC) To the gamma compensation voltage to output the data voltage Vdata. The data voltage (Vdata) is applied to the pixels through the demultiplexer 112 and the data line 102.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements and distributes the data voltage Vdata output from the data driver 110 to the data lines 102 do. The number of data lines 102 can be reduced because one channel of the data driver 110 is time-division-connected to the plurality of data lines by the demultiplexer 112.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel region on the display panel 100 together with the TFT array of the active area AA. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130. The gate driver 120 may sequentially shift the gate signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may include, but is not limited to, a scan signal SCAN and a sense signal SENSE. The scan signal SCAN and the sensing signal SENS may be synchronized with the data voltage Vdata or the sensing data voltage Vdata of the input image. The data voltage Vdata of the input image is the gradation voltage of the pixel data input in the normal driving mode. The sensing data voltage Vdata is a predetermined voltage set irrespective of the input image data and appropriately charges the gate voltage of the driving element DT to sense the threshold voltage Vth of the driving element DT.

The gate signals SCAN and SENSE may be generated as pulses swinging between the gate-on voltage VGH and the gate-off voltage VGL. VGH = 28V, and VGL = -6V. The switch elements M1 and M2 of the pixel circuit are turned on in response to the gate on voltage VGH of the gate signals SCAN and SENSE.

The timing controller 130 controls the operation timing of the display panel driving circuits 110, 112, and 120 in the normal driving mode and the sensing mode. The timing controller 130 receives digital video data (DATA) of an input video from a host system (not shown) and a timing signal synchronized with the digital video data (DATA). The timing signal received by the timing controller 130 may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system can be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

The timing controller 130 may adjust the frame rate to a frequency equal to or higher than the input frame frequency. For example, the timing controller 130 multiplies the input frame frequency by i times and outputs the operation timing of the display panel driving units 110, 112, and 120 to the frame frequency x i (i is a positive integer larger than 0) Can be controlled. The frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The timing controller 130 generates data timing control signals for controlling the operation timings of the display panel driving circuits 110, 112 and 120 based on the timing signals Vsync, Hsync and DE received from the host system, And controls the driving circuits 110, 112, and 120. The voltage level of the gate timing control signal output from the timing controller 130 may be converted to a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage VGL and converts the high level voltage of the gate timing control signal to the gate high voltage VGH .

The external compensation circuit includes a sensing line 103 connected to the pixel circuit, a sensing unit 111 connected to the pixel circuit, and a compensation unit 131 receiving sensing data (digital data) from the sensing unit 111 . The DAC and the sensing unit 111 may be integrated in an integrated circuit (IC) of the data driver 110. The compensation unit 131 may be embedded in the timing controller 130.

The external compensation circuit initializes the source voltage Vs of the sensing line 103 and the driving element DT, that is, the voltage of the second node n2 as a reference voltage, and then senses the source voltage of the driving element DT It is possible to sense the electrical characteristics (Vth, mu) of the driving element DT. The sensing unit 111 samples the voltage on the sensing line 103 in the sensing mode, converts the voltage to digital data through the ADC, and outputs sensing data.

Compensation values for compensating the threshold voltage Vth and the mobility μ of the driving device DT are stored in a look-up table of the compensation unit 131 for each sub-pixel. The compensation unit 131 inputs the sensing data received through the ADC to the lookup table and modulates the pixel data by adding or multiplying the compensation value output from the lookup table to the pixel data (digital data) of the input image, Compensates for changes in electrical characteristics. The pixel data modulated by the compensation unit 131 is transferred to the data driver 110 and converted into a data voltage Vdata by the DAC of the data driver 110 and supplied to the data line 102. The driving element DT of the pixel circuit is driven by the data voltage Vdata supplied through the data line 102 to generate a current. The current flowing through the driving element DT to the OLED which is the light emitting element is determined according to the gate-source voltage Vgs of the driving element DT.

The pixel circuit includes an OLED, a driving element DT connected to the OLED, a plurality of switch TFTs M1 and M2, and a capacitor Cst, as in the example of Fig. The driving device DT and the switch TFTs M1 and M2 may be implemented by an n-channel transistor (NMOS), but are not limited thereto.

The OLED emits light with a current generated in accordance with the gate-source voltage Vgs of the driving device DT which varies depending on the data voltage Vdata. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the driving element DT through the second node n2 and the cathode of the OLED is connected to the VSS electrode to which the low potential power supply voltage VSS is applied. In FIG. 2, " Coled " is the capacitance of the OLED.

The first switch TFT Ml is turned on according to the scan signal SCAN to connect the data line 102 to the first node n1 to supply the data voltage Vdata to the first node n1, (DT). The first switch TFT Ml includes a gate connected to the first gate line 1041 to which the first scan signal SCAN is applied, a first electrode connected to the data line 102, and a first electrode connected to the first node n1. Two electrodes.

The second switch TFT M2 is turned on according to the sensing signal SENSE to supply the reference voltage VPRES, VPRER to the second node n2. The second switch TFT M2 has a gate connected to the second gate line 1042 to which the sensing signal SENSE is applied, a first electrode connected to the sensing line 103 to which the reference voltages VPRES and VPRER are applied, And a second electrode connected to the second node n2.

The driving element DT supplies current to the OLED in accordance with its gate-source voltage Vgs. The driving element DT has a gate connected to the first node n1, a first electrode (or drain) connected to the VDD line 105 to which the pixel driving voltage VDD is supplied, and a second electrode connected to the OLED (Or source) connected to the anode of the second transistor.

The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst charges the gate-source voltage Vgs of the driving element DT.

3 and 4 are views showing a sensing mode. 5 is a detailed view showing an active section AT and a vertical blank section VB.

Referring to Figs. 3 to 5, the sensing mode is divided into a product before shipment and a shipment after shipment. The electrical characteristics (Vth, mu) of the driving element DT are sensed in each of the subpixels through an external compensation circuit connected to pixels before shipment of the product, and the sensing result is transmitted to the driving element DT Vth, μ) deviations are compensated.

The post-shipment sensing mode may include an ON RF mode performed in a power ON sequence, an RT MODE performed in a vertical blank (VB) during a display driving period, and a power OFF sequence OFF RS mode to be implemented.

The ON RF mode senses the mobility (μ) of the driving device in each of the pixels when the field emission display device is turned on and compares the sensing result with the mobility compensation value measured for each subpixel before shipment of the product And updates the μ compensation value based on the difference. In the pre-shipment sensing mode, the threshold voltage and mobility of the driving elements for each subpixel are sensed, and the threshold voltage compensation value and the mobility compensation value of the driving device are set in a look-up table. The mobility (μ) of the driving device is compensated by the μ compensation value reflecting the mobility sensing result of the driving device for each sub-pixel.

In the RT mode, the mobility (μ) of pixels is detected in real time in a vertical blank interval (VB) every frame period during the display driving period in which an image is displayed, and the μ compensation value Update. The vertical blank period VB is allocated at a predetermined time interval between the active period AT of the (N-1) -th frame period and the active period AT of the N-th frame period.

The OFF RS mode senses the threshold voltage (Vth) of the driving element in each of the pixels when the power of the display device is turned off, and updates the Vth compensation value for each subpixel according to the Vth sensing result. OFF RS mode, the display panel driving circuits 110, 112, and 120 and the external compensation circuit are driven for a predetermined delay time before the power is completely turned off, thereby adjusting the threshold voltage (Vth) of the driving elements in each of the subpixels And updates the Vth compensation value for each subpixel. When the Vth compensation value is updated at the N-th power OFF time (OFF (N)), it can be updated at the N-th power OFF time (OFF (N)) after being maintained in the ON RF mode and the RT mode.

Since the gate-source voltage Vgs of the driving device DT is a negative voltage lower than zero when the power is turned off, the negative gate bias stress of the driving device DT is lower than the negative gate bias voltage of the power- And the driving element DT is deteriorated. The Vth compensation value selected through the sensing result at the Nth power OFF time (OFF (N)) is inaccurate because the threshold voltage shift of the further deteriorated driving device Vth is not reflected during the power-off period. Inaccurate Vth compensation results in image quality degradation. In the OFF RS mode, the threshold voltage (Vth) of the driving device (DT) is sensed in the pixels to update the Vth compensation value for each subpixel, and then the gate-source voltage (Vgs) to 0 (zero) V to prevent further deterioration of the driving element DT in the power-off period.

In Fig. 5, the vertical synchronization signal Vsync defines one frame period. One frame period is the sum of the active interval (AT) and the vertical blank interval (VB). The horizontal synchronization signal (Hsync) defines one horizontal period. The data enable signal DE defines a valid data period including pixel data to be displayed on the screen.

The data enable signal DE is synchronized with the valid data to be displayed on the pixel array of the display panel 100. One pulse period of the data enable signal DE is one horizontal period, and a high logic period of the data enable signal DE represents a data input timing of one pixel line. One horizontal period is a time required to write data to pixels of one pixel line in the display panel 100. [

The timing controller 130 receives the data enable signal DE and the data of the input video during the active period AT. The data enable signal DE and the data of the input video are not present in the vertical blank section VB. One frame of data to be written to all the pixels during the active period (AT) is received by the timing controller (130).

As can be seen from the data enable signal DE, no input data is received on the display device during the vertical blank interval VB. The vertical blank section VB includes a vertical sync time VS, a vertical front porch FP, and a vertical back porch BP. The vertical sync time (VS) is the time from the falling edge of the Vsync to the rising edge, and indicates the start (or end) timing of one screen.

FIG. 6 is a circuit diagram showing the sensing unit shown in FIG. 2 in detail.

6, the sensing unit 111 includes switch elements SW1 to SW3 for switching the reference voltages VPRER and VPRES, a capacitor Csam, a sampling & scalar circuit 112, And an analog to digital converter (hereinafter referred to as " ADC "). In Fig. 6, "Csio" is a capacitor connected to the sensing line 103. The switch elements SW1 to SW3 may be implemented as an n-channel transistor (NMOS).

The reference voltages VPRER and VPRES are divided into a first reference voltage VPRES for initializing the pixel circuit and a second reference voltage VPRER set to a voltage higher than the first reference voltage VPRES. The first reference voltage VPRES is set to the voltage for initializing the driving element DT and the OLED in the sensing mode. The second reference voltage VPRER charges the source voltage Vs of the driving element DT to a voltage higher than 0 V in the normal driving mode. The second reference voltage VPRER is set to provide a voltage margin for setting the compensation voltage of the data voltage Vdata when the threshold voltage is shifted in the negative direction due to the gate bias stress of the driving device DT Lt; RTI ID = 0.0 > 0V. ≪ / RTI > VPRES = 0V, VPRER = 3V, but is not limited thereto.

The first switch element SW1 is turned on according to the high logic voltage H of the first switch control signal SPRE to supply the first reference voltage VPRES to the sensing line 103 . The second switch element SW2 is turned on in accordance with the high logic H of the second switch control signal RPRE to supply the second reference voltage VPRER to the sensing line 103. [ The third switch element M3 is turned on according to the high logic H of the third switch control signal SAM to connect the sensing line 103 to the capacitor Csam. The capacitor Csam is formed between the reference voltage terminal EVREF2 and the node between the input terminal of the third switch element SW3 and the input terminal of the sample & The reference voltage terminal EVREF2 may be set to GND = OV.

The sampling and scaler circuit 112 includes a fourth switch and a voltage scaler (not shown). The fourth switch is alternately turned on with the third switch M3 to supply the sampling voltage charged in the capacitor Csam to the voltage scaler. The voltage scaler adjusts the sampling voltage to within the input voltage range of the ADC.

7 is a waveform diagram showing the operation of the pixel circuit in the normal driving mode. 8 is a waveform diagram showing a pixel circuit and a sensing unit in the normal driving mode. The present invention is not limited to the voltage and time shown in Fig. The voltage and time can be appropriately adjusted depending on the characteristics of the panel and the driving method.

7 and 8, in the normal driving mode, pixels to which pixel data is written in accordance with the gate signals SCAN and SENSE during the active period AT every frame period are sequentially selected one by one, The pixel data is written in the memory cells.

During the active period AT in the normal drive mode, the scan signal SCAN and the sense signal SENSE are generated as the gate-on voltage VGH in synchronization with the data voltage Vdata. The data voltage Vdata is generated at a voltage corresponding to the gray level value of the pixel data of the input image. The highest gradation, that is, the white gradation voltage may be set to 6V as in the example of FIG. 6, but is not limited thereto.

The second switch element SW2 in the sensing part 111 is turned on according to the high logic pulse of the second switch control signal RPRE to generate the second reference voltage VPRER during the active period AT of the normal drive mode, To the sensing line (103). During the active period (AT) of the normal drive mode, the first and third switch elements (SW1, SW3) of the sensing unit (111) remain off.

During the active period AT of the normal driving mode, the gate voltage Vg of the driving element DT is charged to 6V by the data voltage Vdata. At this time, the voltage Vsio of the sensing line, the source voltage Vs of the driving element DT, and the anode voltage of the OLED are charged to the voltage 3V of the second reference voltage VPRER. Therefore, the gate-source voltage Vgs of the driving element DT is Vgs = 3V in the active period AT of the normal driving mode.

9 is a waveform diagram showing the operation of the pixel circuit in the OFF RS mode. 10A is a waveform diagram showing a pixel circuit and a sensing unit in a sampling period. 10B is a waveform diagram showing a pixel circuit and a sensing unit in a reset period. In Figs. 10A and 10B, " F " represents a floating section.

Referring to FIGS. 9 to 10B, the OFF RS mode is divided into an initialization period tini, a sensing period tsens, a sampling period tsam, and a reset period trst.

The first switch control signal SPRE is generated with a pulse of the high logic H and the gate signal SCAN and SENSE is generated with the gate on voltage VGH synchronized with the sensing data voltage Vdata in the initialization period tini, ). Therefore, during the initialization period tini, the first switch element SW1 of the sensing unit 111 and the first and second switch TFTs M1 and M2 of the pixel circuit are turned on. The sensing data voltage Vdata may be generated at a predetermined voltage, for example, 6 V, regardless of the pixel data.

During the initialization period tini, the gate voltage Vg of the driving element DT is charged to 6V by the data voltage Vdata. At this time, the voltage Vsio of the sensing line, the source voltage Vs of the driving element DT, and the anode voltage of the OLED are initialized to the voltage (0V) of the first reference voltage VPRES. Therefore, the gate-source voltage Vgs of the driving element DT is Vgs = 6V in the initialization period tini.

In the sensing period tsens, the first switch control signal SPRE is inverted to a low logic (L) level. During the sensing period tsens, the gate signals SCAN and SENSE are maintained at the gate-on voltage VGH synchronized with the sensing data voltage Vdata. During the sensing period tsens, the switch elements SW1, SW2 and SW2 of the sensing unit 111 are all turned off and the first and second switch TFTs M1 and M2 of the pixel circuit ) Is turned on. The sensing line 103 is floating because the switch elements SW1, SW2, and SW3 of the sensing unit 111 are turned off during the sensing period tsens. The source voltage Vs of the driving element DT and the anode voltage of the OLED and the voltage Vsio of the sensing line 103 are applied to the driving element DT coupled through the capacitor Cst of the pixel circuit, Is started to be charged by the current of the driving element DT which flows in accordance with the gate voltage Vg of the gate electrode of the transistor Q1 and increases to Vdata-Vth = 4.5V.

During the sensing period tsens, the gate voltage Vg of the driving element DT is charged to Vdata = 6V. At this time, the voltage Vsio of the sensing line, the source voltage Vs of the driving element DT, and the anode voltage of the OLED are charged to Vdata-Vth. Therefore, the gate-source voltage Vgs of the driving element DT is Vgs = Vth = 1.5 V in the sensing period tsens, and the threshold voltage Vth of the driving element DT sensed in this way is connected to the capacitor Cst. .

The first and second switch control signals SPRE and RPRE are generated while the third switch control signal SAM is generated with the pulse 91 of the high logic H as shown in FIG. 10A during the sampling period tsam, (L). During the sampling period tsam, the gate signals SCAN and SENSE are maintained at the gate-on voltage VGH synchronized with the sensing data voltage Vdata. Therefore, during the sampling period tsam, the third switch element SW3 of the sensing portion 111 is turned on, and the first and second switch TFTs M1 and M2 of the pixel circuit are turned on.

After the pulse 91 of the third switch control signal SAM in the sampling period tsam, the third switch control signal SAM is inverted to low logic, and the data voltage Vdata is lowered to 0V. The gate voltage Vg of the driving element DT is discharged to 0 V because the data voltage Vdata changes to 0 V during the sampling period tsam. The gate-source voltage Vgs of the driving element DT maintains the threshold voltage Vth of the driving element DT in the sampling period tsam. At this time, the voltage Vsio of the sensing line, the source voltage Vs of the driving element DT, and the anode voltage of the OLED are supplied to the capacitor Csam through the third switch element SW3, The threshold voltage Vth of the charged driving element DT is converted into digital data by the ADC and transmitted to the compensating section 131. [

During the sampling period Tsam, when the third switching device SW3 is turned on, the source voltage Vs = 4.5 V of the driving device is input to the ADC through the capacitor Csam. The ADC converts the source voltage (Vs) of the sensed driving element into digital data and transmits it to the compensating section 131 as sensing data. The compensation unit 131 recognizes the gate voltage Vg of the driving element for each subpixel, that is, the data voltage Vdata, as the pixel data stored in the memory of the timing controller 130. The compensation unit 131 determines Vgs = Vth of the driving element DT for each subpixel based on the difference between the pixel data and the sensing data, and senses the threshold voltage Vth of the driving element.

During the reset period trst, as shown in FIG. 10B, the first switch control signal SPRE is generated with the pulse 93 of the high logic H, and at the same time, the sensing signal SENSE becomes the gate-on voltage VGH Lt; RTI ID = 0.0 > 94 < / RTI > During the reset period trst, the scan signal SCAN is inverted to the gate-off voltage VGL. Therefore, during the reset period trst, the first switch element SW1 of the sensing portion 111 and the second switch TFT M2 of the pixel circuit are turned on to turn on the sensing line 103 and the driving element DT The source and the anode of the OLED are discharged. During the reset period trst, the first switch TFT Ml of the pixel circuit and the second and third switch elements M2 and M3 of the sensing portion 111 are kept off.

During the reset period trst, the gate voltage Vg of the driving element DT is maintained at 0V. At this time, the voltage Vsio of the sensing line, the source voltage Vs of the driving element DT, and the anode voltage of the OLED are connected to the VPRES node and discharged to the first reference voltage VPRES = 0V. Therefore, the gate-source voltage Vgs of the driving element DT changes to 0 V in the reset period trst.

In the reset period trst, the second switch control signal RPRE may be generated as a pulse 92 of high logic prior to the pulse 93 of the first switch control signal SPRE. In this case, after the second switch element SW2 is turned on and the sensing line 103 is adjusted to the second reference voltage VPREP = 3V, it can be discharged to the first reference voltage VPRES = 0V. On the other hand, since the sensing line 103 is initialized to 0 V in the ON RF mode, the pulse 92 can be omitted in the reset period trst of the OFF RS mode.

The gate-source voltage Vgs of the driving element DT is set to 0 V during the reset period trst which is the end time of the OFF RS mode so that the stress of the driving element DT is not accumulated during the power-off period. As a result, since the threshold voltage (Vth) of the driving device (DT) does not change during the power-off period, the Vth compensation value for the threshold voltage (Vth) of the driving device, The threshold voltage change of the driving device can be accurately compensated when the power is turned on again after the period.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: data driver
120: Gate driver 130: Timing controller
111: sensing unit 131: compensation unit
DT: driving element of the pixel circuit M1, M2: switch TFT of the pixel circuit
SW1: first switch element SW2 of sensing part: second switch element of sensing part
SW3: third switch element of sensing part VPRES: first reference voltage
VPRER: Second reference voltage

Claims (10)

A display panel including a sensing line to which data lines and gate lines are intersected, a plurality of sub-pixels are arranged, and a source of a driving element driving the sub-pixels is connected; And
And a sensing unit for supplying a first reference voltage to the sensing line and resetting the gate-source voltage of the driving device to 0 V during a reset period set at the end of a sensing mode in which a threshold voltage of the driving device is sensed Display device. The method according to claim 1,
Wherein the sensing unit supplies a second reference voltage higher than the first reference voltage to the sensing line in a normal driving mode in which data of an input image is written to the subpixels. 3. The method of claim 2,
The sensing unit includes:
A first switch element for supplying the first reference voltage to the sensing line in response to a first switch control signal;
A first switch element for supplying the second reference voltage to the sensing line in accordance with a second switch control signal;
A third switch element for connecting the sensing line to the sampling capacitor according to a third switch control signal; And
And a sample & scale unit connected to the sampling capacitor to adjust the voltage of the sampling capacitor and supply the voltage to the analog-to-digital converter. The method of claim 3,
The first switch element
The first reference voltage is supplied to the sensing line when the sensing mode is started,
And a control unit which is turned off in a sensing period between the initialization period and the reset period to block a current path between the sensing line and the first reference voltage,
And a current path between the sensing line and the first reference voltage is blocked by maintaining an off state in a sampling interval between the sensing period and the reset period,
And turning on the reset period to supply the first reference voltage to the sensing line. 5. The method of claim 4,
Wherein the second switch element comprises:
Maintains the off state in the sensing mode,
And the second reference voltage is turned on in the normal driving mode to supply the second reference voltage to the sensing line. 6. The method of claim 5,
Wherein the third switch element comprises:
Turning on the sampling period to couple the sensing line to the sampling capacitor,
The sensing period, and the reset period. The method according to claim 1,
Wherein the sensing mode operates the sub-pixels and the sensing unit for a predetermined delay time when the power of the EL display is turned off, thereby sensing a threshold voltage of the driving device for each sub-pixel. The method according to claim 1,
Each of the sub-
A light emitting element emitting light by a current flowing in accordance with the gate-source voltage of the driving element;
A first switch transistor which is turned on in accordance with a scan signal synchronized with a data voltage of the input image or a data voltage for sensing to connect a data line supplied with the data voltage or the sensing data voltage of the input image to the gate of the driving device;
A second switch transistor which is turned on according to a sensing signal synchronized with a data voltage of the input image or a sensing data voltage to connect the sensing line to a source of the driving device and an anode of the light emitting device; And
And a capacitor connected between the source and the gate of the driving element,
A predetermined pixel driving voltage is supplied to the drain of the driving element,
Wherein the data voltage of the input image is supplied to the subpixels in the normal driving mode and the sensing data voltage is supplied to the subpixels in the sensing mode. 9. The method of claim 8,
The first and second switch transistors are turned on in the initialization period, the sensing period, and the sampling period of the sensing mode, while the first and second switch transistors are turned off in the reset period,
The sensing data voltage is supplied to the subpixels at a predetermined voltage higher than 0 V in the sensing period, the sensing period, and the sampling period of the sensing mode, Display device. There is provided a driving method of a field emission display including a display panel including a sensing line to which data lines and gate lines intersect and a plurality of subpixels are arranged and a source of a driving element driving the subpixels is connected,
Resetting the gate-source voltage of the driving device to 0V by supplying a first reference voltage to the sensing line during a reset period set at the end of the first sensing mode in which the threshold voltage of the driving device is sensed;
The gate-source voltage of the driving device is maintained at 0 V during a power-off period until the field-emission display device is powered on again; And
Sensing the mobility of the driving element in a second sensing mode when the power supply of the field emission display is turned on again.

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