KR20190063233A - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting device which can reduce heating of a display panel by optimizing voltage applied to sub-pixels by color. The organic light emitting device comprises: a display panel in which a plurality of data lines and a plurality of gate lines are placed, and a plurality of sub-pixels are placed; a data driver which drives the plurality of data lines; a gate driver which drives the plurality of gate lines; and a timing control unit which controls the data driver and the gate driver. In addition, the display panel comprises: a first high-potential voltage line in which four sub-pixels including white (W), red (R), blue (B), and green (G) form one pixel, and which applies a first power to at least one sub-pixel in one pixel; and a second high-potential voltage line which applies a second power to the remaining sub-pixels through a different layer from a first high-potential voltage.

Description

[0001] The present invention relates to an organic light emitting display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display, and more particularly, to an organic light emitting diode (OLED) display capable of reducing the number of display pixels by optimizing a voltage applied to each subpixel.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. Recently, a liquid crystal display device, a plasma display device, an organic light emitting display device Organic Light Emitting Display Device) are being utilized.

When the scan signals, the data signals, the power supply, and the like are supplied to the subpixels arranged in a matrix form, the transistors included in the selected subpixel are driven. The organic light emitting diode (OLED) disposed in the sub-pixel emits light corresponding to the current generated at this time, thereby displaying an image.

Some of the organic light emitting display devices are designed to have a sub-pixel structure including red, white, blue, and green in order to increase the light efficiency and prevent the decline in luminance and color degradation of pure color.

Also, when white is implemented in a display panel of an organic light emitting display device, red, blue, and green subpixels are also emitted in consideration of luminance enhancement of white and color coordinate characteristics.

For example, when red (R), white (W), blue (B) and green (B) subpixels are defined as one pixel and white is implemented for each pixel , Red (R), blue (B), and green (B) subpixels emit light with a predetermined gradation voltage while emitting white (W) subpixels.

However, in order for the organic light emitting display to realize white color, it is necessary to emit three or four subpixels for each pixel. Therefore, there is a problem that consumption current of the display panel increases with severe heat generation. Or problems such as after-image and black spots occur.

An object of the present invention is to provide an organic light emitting display device capable of supplying an optimal voltage to a driving transistor.

It is another object of the present invention to provide an organic light emitting display capable of reducing the heat generation of a display panel.

Another object of the present invention is to reduce current consumption of an organic light emitting display.

According to an aspect of the present invention, there is provided an OLED display comprising: a display panel having a plurality of data lines and a plurality of gate lines arranged therein and having a plurality of subpixels; A data driver for driving the plurality of data lines; A gate driver for driving the plurality of gate lines; And a timing controller for controlling the data driver and the gate driver, wherein the display panel includes four sub-pixels of white (W), red (R), blue (B), and green (G) A first high potential voltage line for applying a first power to at least one subpixel of one pixel; And a second high-potential voltage line for applying a second power to the remaining sub-pixels through a different layer from the first high-potential voltage.

In the OLED display according to the preferred embodiment of the present invention, subpixels of the same color of two adjacent pixels are connected to the first high-potential voltage line, while the second high- Can be connected.

In the OLED display according to the present invention, two sub-pixels connected to the first high-potential voltage line are connected to a first sub-pixel SP1 and a fourth sub-pixel SP1 connected to the (4n-3) th data line (SP2) connected to the second data line, and the two subpixels connected to the second high potential voltage line are connected to the third subpixel (SP3) connected to the (4n-1) And a fourth sub-pixel SP4 connected to the second sub-pixel SP4.

In the organic light emitting diode display according to the present invention, the first high potential voltage line is composed of two sub pixels in the horizontal direction of 2m-1 pixels (hereinafter, "m" is a natural number) The second high potential voltage line applies a first power to the subpixels, and the second high potential voltage line is a subpixel of a second 2m-th pixel in the horizontal direction (hereinafter referred to as " m " And the second power source can be applied to the other two sub-pixels.

In the OLED display according to the preferred embodiment of the present invention, four sub-pixels connected to the first high-potential voltage line are connected to a first sub-pixel SP1 connected to a 4n-3th data line of a 2m- A second sub-pixel SP2 connected to the 4n-2 th data line, a first sub-pixel SP1 connected to the 4n-3th data line of the 2m-th pixel in the horizontal direction, (SP2) connected to the second high-potential voltage line, the fourth sub-pixel connected to the second high-potential voltage line is connected to the (4n-1) th data line of the (2m-1) A fourth sub-pixel SP4 connected to the 4n-th data line, a third sub-pixel SP3 connected to the 4n-1th data line of the 2m-th pixel in the horizontal direction, ).

In the organic light emitting display according to the present invention, the wirings connected to the drain terminal of each driving transistor of each subpixel connected to the first high potential voltage line are formed in the same layer as the gate layer of each driving transistor And the wiring connected to the drain terminal of each driving transistor of each sub pixel connected to the second high potential voltage line may be formed in the same layer as the light shield layer of each driving transistor.

The organic light emitting diode display according to the present invention may exhibit the following effects.

First, heat generated by the display panel of the organic light emitting display device can be reduced.

Second, an optimal voltage can be supplied to the driving transistor of the organic light emitting display.

Third, the current consumption of the organic light emitting display device can be reduced.

1 is a schematic system configuration diagram of an organic light emitting diode display according to the present invention.
2A and 2B illustrate an organic light emitting display subpixel structure according to an embodiment of the present invention.
3 is a plan view of a subpixel and a driving voltage supply line of an OLED display according to the present invention.
4 is a circuit diagram showing subpixels and driving voltage supply lines of the organic light emitting diode display according to the present invention.
5A and 5B are cross-sectional views illustrating a connection state between first and second driving voltage supply lines and driving transistor connection patterns of the OLED display according to the present invention.

For specific embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be embodied in various forms, And should not be construed as limited to the embodiments described.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises ", or" having ", and the like, are intended to specify the presence of stated features, integers, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be construed to indicate meaning consistent with the meaning of the context in the relevant art and are to be construed as either ideal or overly formal in meaning unless expressly defined in the present application Do not.

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently than the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic system configuration diagram of an organic light emitting diode display according to the present invention, and FIGS. 2A and 2B are exemplary views of a subpixel structure of an organic light emitting diode display according to an embodiment of the present invention.

1, a plurality of data lines DL and a plurality of gate lines GL are arranged, and a plurality of sub pixels (SPs) are arranged A data driver 120 for driving a plurality of data lines DL; a gate driver 130 for driving a plurality of gate lines GL; a data driver 120 and a gate driver A timing controller 140 for controlling the controller 130, and the like.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The timing controller 140 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, And controls the display driving data at a proper time in accordance with the scan signal.

The data driver 120 drives the plurality of data lines DL by supplying the driving data voltage Vdata to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The gate driver 130 sequentially supplies the scan signal of the On voltage or the Off voltage to the plurality of gate lines GL under the control of the timing controller 140, And sequentially drives the line GL. Here, the gate driver 130 is also referred to as a " scan driver ".

The data driver 120 converts image data received from the timing controller 140 into analog data voltages and supplies the data voltages to a plurality of data lines DL when a specific gate line is opened by the gate driver 130.

1, the data driver 120 is located only on one side (e.g., the upper side or the lower side) of the display panel 110. However, the data driver 120 may be disposed on both sides of the display panel 110 And the lower side).

1, the gate driver 130 is located only on one side (e.g., the left side or the right side) of the display panel 110. However, the gate driver 130 may be provided on both sides of the display panel 110 The left side and the right side).

The timing control unit 140 includes a timing control unit 140 for generating various kinds of signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, a clock signal CLK, Timing signals from the outside (e.g., the host system).

The timing controller 140 may convert the input image data input from the outside into the data signal format used by the data driver 120 and output the converted image data. The timing controller 140 may further include a data driver 120 and a gate driver 130, A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the data driver 120 and the gate driver 130, .

For example, in order to control the gate driver 130, the timing controller 140 may control a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver ICs constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

The timing controller 140 may control the data driver 120 such as a data start pulse SSP, a source sampling clock SSC, a data output enable signal SSC, SOE (Source Output Enable), and the like.

Here, the data start pulse SSP controls the data sampling start timing of one or more data driver ICs constituting the data driver 120. The data sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the data driver ICs. The data output enable signal SOE controls the output timing of the data driver 120.

The data driver 120 may include at least one data driver integrated circuit (SDIC) to drive a plurality of data lines.

Each data driver integrated circuit (SDIC) includes a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, a gamma voltage generator, and the like .

Each data driver IC (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The gate driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

Each subpixel SP disposed on the display panel 110 may include a circuit element such as a transistor.

For example, in the display panel 110, each sub-pixel SP is composed of an organic light emitting diode (OLED) and a circuit element such as a driving transistor (DT) for driving the organic light emitting diode .

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on a providing function, a design method, and the like.

Referring to FIGS. 2A and 2B, in the organic light emitting diode display 100 according to the present invention, each sub pixel includes an organic light emitting diode (OLED), an organic light emitting diode (OLED) And a reference voltage line RVL (reference voltage line) for supplying a reference voltage Vref to the first node N1 of the driving transistor DT, A second transistor T2 electrically connected between a second node N2 of the driving transistor DT and a data line DL supplying a data voltage Vdata; And a storage capacitor Cst (storage capacitor) electrically connected between the first node N1 and the second node N2 of the data driver DT.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

The driving transistor DT drives the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

The first node N1 of the driving transistor DT may be electrically connected to the first electrode of the organic light emitting diode OLED and may be a data node or a drain node. The second node N2 of the driving transistor DT may be electrically connected to the data node or the drain node of the second transistor T2 and may be a gate node. The driving transistor DT may be electrically connected to a driving voltage line (DVL) for supplying a driving voltage EVDD, and may be a drain node or a data node.

2A, the first transistor T1 may be turned on by a sensing signal SENSE to apply a reference voltage Vref to the first node N1 of the driving transistor DT .

In addition, the first transistor T1 may be utilized as a voltage sensing path to the first node N1 of the driving transistor DT when turned on.

The second transistor T2 transfers the data voltage Vdata supplied through the data line DL to the second node N2 of the driving transistor DT when the second transistor T2 is turned on by the scan signal SCAN.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DT so that the data voltage corresponding to the video signal voltage or the voltage corresponding thereto is applied for one frame time I can keep it.

The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DT, And is an external capacitor intentionally designed outside the driving transistor DT.

On the other hand, as shown in FIG. 2B, the first transistor T1 and the second transistor T2 may be controlled together by a single scan signal SCAN.

That is, the first transistor T1 and the second transistor T2 are connected to the same gate line GL and gate nodes thereof are supplied with the same scan signal SCAN, and on / off can be controlled.

The reference voltage line RVL electrically connected to the drain node or the data node of the first transistor Tl may be arranged in one sub pixel column or in two or more sub pixel columns, And may be arranged one by one.

For example, when one pixel is composed of four subpixels (red subpixel, white subpixel, blue subpixel, green subpixel), the reference voltage line RVL is divided into four subpixel columns , A white subpixel column, a blue subpixel column, and a green subpixel column).

FIG. 3 is a plan view showing subpixels and a driving voltage supply line of the organic light emitting display according to the present invention, and FIG. 4 is a circuit diagram showing subpixels and driving voltage supply lines of the organic light emitting display according to the present invention.

Although FIGS. 3 and 4 illustrate the first pixel P1 and the second pixel P2 by way of example, this arrangement is the same for the third pixel P3 and the fourth pixel P4, In the horizontal direction. On the other hand, the configuration between the upper and lower pixels in the vertical direction and the wiring are formed in the same form.

As shown in the drawing, the first pixel P1 includes green subpixels SP1 (# 1-1), red subpixels SP2 (# 1-2), white subpixels SP3 (# 1-3) And a blue sub-pixel SP4 (# 1-4). In the following description, the colors of the subpixels SP1, SP2, SP3, and SP4 are arbitrarily arranged in order of description, and the present invention is not limited to the arrangement order of subpixels.

The second pixel P2 includes a green subpixel SP1 (# 2-1), a red subpixel SP2 (# 2-2), a white subpixel SP3 (# 2-3) SP4) (# 2-4).

The first high potential voltage line EVDD # 1 of the first pixel P1 portion is connected to the green subpixel SP1 (# 1-1) and the red subpixel SP2 (# 1- 2 and the second high potential voltage line EVDD # 2 is connected to the white subpixel SP3 (# 1-3) and the blue subpixel SP4 (# 1-4) of the first pixel P1, Lt; / RTI >

The first high potential voltage line EVDD # 1 of the second pixel P2 portion is connected to the green subpixel SP1 (# 2-1) and the red subpixel SP2 (# 2- 2 and the second high potential voltage line EVDD # 2 is connected to the white subpixel SP3 (# 2-3) and the blue subpixel SP4 (# 2-4) of the second pixel P1, Lt; / RTI >

A plurality of data voltage supply lines DL (4n-3) (hereinafter, "n" is a natural number), DL (4n-2), DL (4n-1), DL (4n) The drive signal of each sub-pixel is transmitted.

At this time, the first sub-pixel SP1 is connected to the first data line DL1 of the first pixel P1 and the second sub-pixel SP2 is connected to the second data line DL2. The third subpixel SP3 (# 1-3) is connected to the third data line DL3 and the fourth subpixel SP4 (# 1-4) is connected to the fourth data line DL4 do.

The first subpixel SP1 (# 2-1) is connected to the first data line DL5 of the second pixel P2 and the second subpixel SP2 (# 2-2) is connected to the second data line DL6. The third subpixel SP3 (# 2-3) is connected to the third data line DL7, and the fourth subpixel SP4 (# 2-4) is connected to the fourth data line DL8.

At this time, the first subpixel SP1 (# 1-1) of the first pixel P1 and the first subpixel SP1 (# 2-1) of the second pixel P2 are of the same color, The second subpixel SP2 (# 1-2) of the pixel P1 and the second subpixel SP2 (# 2-2) of the second pixel P2 are of the same color and the first subpixel SP2 The third subpixel SP3 (# 1-3) of the first pixel P1 and the third subpixel SP3 (# 2-3) of the second pixel P2 are of the same color, The pixels SP4 (# 1-4) and the fourth subpixel SP4 (# 2-4) of the second pixel P2 have the same color.

At this time, the first sub-pixel SP1 may be a green (G) sub-pixel, the second sub-pixel SP2 may be a red (R) sub-pixel, W) subpixel, and the fourth subpixel SP4 may be a blue (B) subpixel.

Is connected to the drain terminal of each driving transistor DT of each of the subpixels # 1-1, # 1-2, # 2-1, and # 2-2 connected to the first high potential voltage line EVDD # 1 (# 1-3, # 1-4, # 2-3) connected to the second high potential voltage line (EVDD # 2) are connected through the first contact hole (CH1) , # 2-4) are connected to each other through the second contact hole (CH2).

A scan line SCAN and a sense line SENSE are connected to the sub-pixels SP1 to SP4 of the pixels P1 and P2. A gate terminal of the second transistor T2 included in each subpixel is connected to the scan line SCAN and a gate terminal of the first transistor T1 included in each subpixel is connected to the sensing line SENSE.

5A and 5 are cross-sectional views illustrating a connection state between first and second driving voltage supply lines and driving transistor connection patterns of the OLED display according to the present invention.

5A is a timing chart of the first high potential voltage line EVDD # 1 and the driving transistors DT of the sub pixels # 1-1, # 1-2, # 2-1, And the wiring L1 connected to the drain terminal. That is, the wiring L1 connected to the drain terminal of the first high potential voltage line EVDD # 1 and the driving transistor DT is formed in the same layer as the gate layer of each driving transistor. According to this configuration, the driving current flows from the first high potential voltage line (EVDD # 1) along the wiring L1 formed on the same layer as the gate line layer.

On the other hand, the line L2 connected to the drain terminal of each driving transistor of each subpixel connected to the second high potential voltage line EVDD # 1 is connected to the same layer as the light shield layer of each driving transistor As shown in FIG. According to this configuration, the driving current flows from the second high potential voltage line (EVDD # 2) along the wiring (L2) formed on the same layer as the light shielding layer.

The high-potential voltage lines at the drain terminal of the driving transistor of each subpixel are provided through different laminated layers, so that a short circuit does not occur. The potentials supplied through the respective high potential voltage lines may be different from each other. That is, a first high potential voltage having a first potential is applied to each of the sub-pixels SP1, SP2 (# 1-1, # 1-2, # 2-1, # 2-2) And the first classics having the second potential are supplied to the subpixels SP3 and SP4 (# 1-3, # 1-4, # 2-3, # 2-4) of each of the pixels P1 and P2, The above voltage is supplied.

In this embodiment, the first high potential voltage of the first potential is supplied to the green subpixel G and the red subpixel R, and the first high potential voltage of the blue subpixel W and the blue subpixel B are supplied to the green subpixel G and the red subpixel R, Although two high potential voltages are provided as examples, the arrangement of subpixels may be implemented in other forms. That is, the first high potential voltage of the first potential may be supplied to the blue subpixel B and the red subpixel R or the blue subpixel B and the green subpixel G. [ The combination can be made in various ways.

In addition, although two subpixels are connected to the first high potential voltage line (EVDD # 1) and the second high potential voltage line (EVDD # 2), respectively, a different number of subpixels may be connected. For example, one subpixel may be connected to the first high potential voltage line EVDD # 1 and three subpixels may be connected to the second high potential voltage line EVDD # 2. Also in this case, the arrangement of the colors may appear in various combinations. For example, the first high potential voltage of the first potential is supplied to the white subpixel W and the second high potential voltage of the second potential is supplied to the green subpixel G, the red subpixel R, 2 It is also possible to supply a high potential voltage.

As described above, the voltages applied to the organic light emitting diode and the driving transistor can be optimized by supplying different high-potential voltages to the subpixels for each color. That is, conventionally, all the high potential voltages supplied to the mode subpixels in one pixel are the same, and thus the highest potential voltage is always provided to drive the organic light emitting diode. However, according to the present invention, different high-potential voltages can be provided depending on two colors of subpixels or the colors of one pixel and three remaining pixels, so that the panel can be prevented from being heated, .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100: organic light emitting display device 110: display panel
120: scan driver 130: data driver
140:

Claims (6)

A display panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of subpixels are arranged;
A data driver for driving the plurality of data lines;
A gate driver for driving the plurality of gate lines; And
And a timing controller for controlling the data driver and the gate driver,
The display panel includes four subpixels constituted by white (W), red (R), blue (B), and green (G)
A first high potential voltage line for applying a first power to at least one subpixel of one pixel; And
And a second high potential voltage line for applying a second power to the remaining sub-pixels through a different layer from the first high potential voltage. The method according to claim 1,
Wherein the subpixels of the same color of two adjacent pixels are connected to the first high potential voltage line and the subpixels of the same color of the adjacent two pixels are connected to the second high potential voltage line. Device. 3. The method of claim 2,
The two subpixels connected to the first high potential voltage line are connected to the first subpixel SP1 connected to the 4n-3th data line (hereinafter, "n" is a natural number) and the second subpixel SP1 connected to the Pixel SP2,
And two subpixels connected to the second high potential voltage line are a third subpixel SP3 connected to the (4n-1) th data line and a fourth subpixel SP4 connected to the (4n) th data line. Emitting display device. 3. The method of claim 2,
The first high potential voltage line applies a first power to two sub pixels of a 2m-th horizontal pixel in the same color as two sub pixels of a 2m-1th pixel in the horizontal direction (hereinafter, "m" is a natural number) ,
The second high-potential voltage line supplies a second power source to two other sub-pixels of the 2m-th horizontal pixel of the same color as the other two sub-pixels of the 2m-1th horizontal pixel (hereinafter, "m" And the organic light emitting display device. 5. The method of claim 4,
The four subpixels connected to the first high potential voltage line include a first subpixel SP1 connected to the 4n-3th data line of the (2m-1) -th pixel in the horizontal direction and a second subpixel SP1 connected to the A first sub-pixel SP1 connected to the 4n-3th data line of the 2m-th pixel in the horizontal direction and a second sub-pixel SP2 connected to the 4n-2th data line,
The fourth subpixel connected to the second high potential voltage line is connected to the fourth subpixel SP3 connected to the (4n-1) th data line of the (2m-1) Pixel SP4 connected to the 4n-th data line and the third sub-pixel SP3 connected to the 4n-1th data line of the 2m-th pixel in the horizontal direction, and a fourth sub- . The method according to claim 1,
The wiring connected to the drain terminal of each driving transistor of each subpixel connected to the first high potential voltage line is formed on the same layer as the gate layer of each driving transistor,
And the wiring connected to the drain terminal of each driving transistor of each subpixel connected to the second high potential voltage line is formed in the same layer as the light shield layer of each driving transistor. Device.

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