KR20160086792A - Method for driving of the display device - Google Patents

Abstract

The present invention relates to a method for driving a display device to allow a 2D image to be maintained with the same resolution as a 3D image by applying a double pixel driving method. The method for driving a display device according to the embodiment of the present invention applies second image data to a total even sub pixel when a first image is emitted in a total odd sub pixel in an odd frame period, applies the first image data to the total odd sub pixels when a second image is emitted in a total even sub pixel in an even frame period. Also, the method inserts a block image between the period of emitting the first image and the period of emitting the second image.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of driving a display device,

The present invention relates to a method of driving a display device.

2. Description of the Related Art As an information society has developed, demands for a display device for displaying an image have been increasing in various forms. In recent years, a liquid crystal display (LCD), a plasma display (Plasma Display) OLED (Organic Light Emitting Diode Display) and the like.

On the other hand, in the display panel of such a display device, elements such as transistors, capacitors or organic light emitting diodes are formed for each subpixel. In the manufacturing process of the display panel, (Short) or disconnection (open, disconnection), and a pixel defect in which the subpixel becomes a luminescent spot or a dark spot may occur.

Conventionally, such a pixel defect has been subjected to a repair process in which a defective subpixel which has become a bright spot or a dark spot is made an abnormal subpixel which does not operate at all. That is, in the conventional repair processing method, a bad subpixel which has become a bright spot or a dark spot is made an abnormal subpixel which does not operate.

In such a conventional repair processing method, the larger the size of the subpixel subjected to the repair processing, or the larger the number of the subpixels subjected to the repair processing, the lower the quality of the screen. In a serious case, the display panel itself should be discarded .

In view of the foregoing, an object of the present invention is to provide a method of driving a display device in which a 2D image and a 3D image are maintained at the same resolution by applying a double-pixel driving method.

The driving method of a display device according to an embodiment of the present invention is a method of driving a display device that applies second image data to all non-subpixels when a first image is emitted in all odd subpixels in an odd frame period, And applies the first image data to the entire odd subpixel when the second image is emitted from the pixel. At the same time, a black image is inserted between the period in which the first image is emitted and the period in which the second image is emitted.

As described above, according to the present invention, the driving method of the display apparatus according to the embodiment of the present invention allows the light emission of the right eye image and the program of the left eye image data to be simultaneously performed, and the program of the light emission of the left eye image and the program of the right eye image data So that it is not necessary to apply the black data. Therefore, the emission time of the right eye image and the left eye image can be increased. Accordingly, the left eye image and the right eye image are both emitted based on the driving frequency of 60 Hz or 120 Hz, thereby enhancing the brightness of the 3D image.

According to the present invention, the driving method of the display device of the present invention is advantageous in that the brightness of the 3D image can be doubled compared to the driving method of the display device according to the related art based on the same driving frequency. That is, in the display device according to the related art, the resolution of the 3D image compared with the resolution of the 2D image is reduced to ½, whereas the display device according to the embodiment of the present invention applies the double pixel driving method, It has the advantage of maintaining the same resolution.

1 is a schematic system configuration diagram of a display device according to embodiments.
2 is a schematic diagram of a structure for a subpixel of a display device according to embodiments.
3 is a conceptual diagram of repair processing for subpixels of a display device according to embodiments.
4 is a schematic diagram of a subpixel structure in accordance with one embodiment.
5 and 6 are equivalent circuit diagrams of subpixels not subjected to repair processing under a subpixel structure according to an embodiment.
FIG. 7 is a timing diagram of two scan signals applied to subpixels that have not undergone repair processing, under a subpixel structure according to an embodiment.
8 and 9 are equivalent circuit diagrams of subpixels that have undergone repair processing under a subpixel structure according to an embodiment.
10 is a schematic diagram of a structure for a subpixel according to another embodiment.
11 and 12 are equivalent circuit diagrams of subpixels not subjected to repair processing under a subpixel structure according to another embodiment.
FIG. 13 is a timing diagram of two scan signals applied to a subpixel not subjected to a repair process under a subpixel structure according to another embodiment.
Figs. 14 and 15 are equivalent circuit diagrams of subpixels subjected to repair processing under a subpixel structure according to another embodiment.
16 and 17 are two exemplary views of a reference voltage application structure according to embodiments.
18 is a view showing a 3D image driving method of a general display device of a shutter glass type.
19 is a diagram illustrating odd subpixels and even subpixels of a display device according to an embodiment of the present invention.
20 is a diagram illustrating an example of a 3D simultaneous light emission driving method of a display apparatus according to an embodiment of the present invention.
FIG. 21 is a diagram illustrating a data application and emission method of the 3D simultaneous light emission driving method of the display device according to the embodiment of the present invention.
22 is a diagram showing another example of a method of driving a display device according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display device 100 according to embodiments.

Referring to FIG. 1, a display device 100 according to embodiments includes a display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like.

1, the display panel 110 includes m (m: natural number) data lines DL1, DL2, ..., DLm and 2n (n: natural number) gate lines GL1_1, GL1_2, GL2_1, GL2_2, ..., GLn_1, and GLn_2 are formed.

Further, m x n sub pixels (SP: Sub Pixel: SPji, 1? I? M, 1? J? N) are formed in the display panel 110. Here, each subpixel is defined by one data line and two gate lines.

Referring to FIG. 1, the data driver 120 drives m data lines DL1, DL2, ..., DLm.

The gate driver 130 drives 2n gate lines GL1_1, GL1_2, GL2_1, GL2_2, ..., GLn_1, and GLn_2.

The timing controller 140 outputs various kinds of control information to control the data driver 120 and the gate driver 130.

The data driver 120 may include a plurality of data driver ICs (also referred to as source driver ICs), which may be a tape automated bonding (TAB) May be connected to a bonding pad of the display panel 110 by a chip on glass (COG) method, or may be formed by being integrated in the display panel 110.

1, the gate driver 130 may be located on one side of the display panel 110, or on both sides of the display panel 110 in two, depending on the driving method.

The gate driving unit 130 may include a plurality of gate driving integrated circuits such as a tape automated bonding (TAB) or a chip on glass (COG) Or may be directly formed on the display panel 110 or may be formed on the display panel 110 by being integrated with the bonding pad of the display panel 110 or implemented in a GIP (Gate In Panel) have.

M x n subpixels (SPji, 1? I? M, 1? J? N) formed in the display panel 110 according to the present embodiments are divided into two partial sub- Pixel). Such a sub-pixel structure will be described in detail below.

2 is a schematic diagram of a structure for a subpixel of the display device 100 according to the embodiments.

2, each of the m × n sub-pixels (SPji, 1≤i≤m, 1≤j≤≤n) includes one data line DLi and two gate lines GLj_1 and GLj_2. Lt; / RTI >

Referring to FIG. 2, each of the m x n subpixels SPji includes a first partial sub-pixel PSP1 connected to the odd-numbered gate lines GLj_1 of the two gate lines GLj_1 and GLj_2, And a second partial sub pixel (PSP2) connected to the even gate line GLj_2 of the two gate lines GLj_1 and GLj_2.

Here, each of the first partial subpixel PSP1 and the second partial subpixel PSP2 may have the same structure or may be symmetrical with respect to the boundary point. For example, when the display apparatus 100 is an organic light emitting display, each of the first partial subpixel PSP1 and the second partial subpixel PSP2 includes a first partial subpixel PSP1 and a second partial subpixel PSP2, (Transistor and capacitor forming portion) of the pixel PSP2 and the light emitting portion (the portion where the anode electrode is formed and light is emitted) may be the same structure or may be symmetrical to each other.

2, in the display device 100 according to the embodiments, in each of the m sub-pixels of the m × n sub-pixels, one of the first partial sub-pixel PSP1 and the second partial sub- ) Are all normal partial subpixels that can operate normally.

Here, since both the first partial subpixel PSP1 and the second partial subpixel PSP2 are normal partial subpixels, both the first partial subpixel PSP1 and the second partial subpixel PSP2 are displayed on the image display It may not be used.

For example, although the first partial subpixel PSP1 and the second partial subpixel PSP2 may be used for image display at the same time for every frame, the first partial subpixel PSP1 and the second partial subpixel PSP2 Pixel PSP1 and the second partial subpixel PSP2 are actually used for image display while the other one is used for displaying a specific event For example, a repair process).

On the other hand, in at least one subpixel out of the m x n subpixels (SPji), the partial subpixel of any one of the first partial subpixel PSP1 and the second partial subpixel PSP2 can not be normally operated An abnormal partial subpixel (also referred to as a " Dead Partial Subpixel "), and the other partial subpixel may be a normal partial subpixel that can operate normally.

For example, an anode electrode or a cathode electrode of the first organic light emitting diode OLED1 in the first partial subpixel PSP1 may be cut out among m × n subpixels, There may be at least one subpixel in which the anode electrode or the cathode electrode of the second organic light emitting diode OLED2 is cut in the two-part subpixel PSP2.

For example, when the anode electrode or the cathode electrode of the first organic light emitting diode OLED1 is cut in the first partial sub-pixel PSP1, the first partial sub- This is an abnormal partial subpixel (dead partial subpixel). At this time, the anode electrode or the cathode electrode of the second organic light emitting diode OLED2 in the second partial sub-pixel PSP2 is a normal partial sub-pixel which is not cut.

In another example, when the anode electrode or the cathode electrode of the second organic light emitting diode OLED2 is cut in the second partial sub-pixel PS2, the second partial sub-pixel PSP2 is connected to the abnormal partial sub- Subpixel). At this time, the anode electrode or the cathode electrode of the first organic light emitting diode OLED1 in the first partial sub-pixel PSP1 is a normal partial sub-pixel that is not cut.

As described above, the subpixel in which any of the partial subpixels of the first partial subpixel PSP1 and the second partial subpixel PSP2 corresponds to the abnormal partial subpixel can be used in the panel manufacturing process step In the after service process, it may be "Repaired Sub Pixel ". This will be described with reference to FIG.

3 is a conceptual diagram of repair processing for subpixels of the display apparatus 100 according to the embodiments.

Referring to FIGS. 3A and 3B, at least one subpixel (for example, DL2) among m.times.n subpixels SPji on the display panel 110 during the panel manufacturing process or after use of the product after shipment, Included in the internal circuit of any one of the first partial subpixel PSP1 and the second partial subpixel PSP2 in the subpixel PSP1 connected to the first partial subpixel PSP1, the subpixel SP2 connected to GL2_1 and GL2_2, Etc. may become electrically short or open due to a foreign substance in the process and a pixel defect may occur where the area of the corresponding partial subpixel (e.g., PSP1) becomes a luminescent spot or a dark spot.

Such defects can be found in the panel manufacturing process before shipment or after-sales service after shipment.

3 (a) and 3 (b), when repairing a partial sub-pixel (for example, PSP1) in which a defect is caused by a lance spot or a dark spot using a repair device, , And can repair the corresponding sub-pixel (e.g., SP22).

3 (a) and 3 (b), in the corresponding subpixel (for example, SP22) that has been subjected to the repair processing, the first partial subpixel PSP1 and the second partial subpixel PSP2, A partial subpixel (e.g., PSP1) is an abnormal partial subpixel, i.e., a dead partial subpixel (DEAD PSP) that can not be used for image display.

In the corresponding subpixel (for example, SP22) that has undergone the repair processing, the remaining partial subpixels except the cut partial subpixel (e.g., PSP1) among the first partial subpixel PSP1 and the second partial subpixel PSP2 : PSP2) can be used for image display.

Therefore, even if the bright spot or the dark spot is generated and the repair process is performed, one of the first partial subpixel PSP1 and the second partial subpixel PSP2 becomes the dead partial subpixel, but the other one can operate normally, A subpixel (e.g., SP22) that has undergone a repair process can operate as a normal subpixel.

On the other hand, as the partial subpixel (e.g., PSP1) of either the first partial subpixel PSP1 or the second partial subpixel PSP2 is cut, the luminance of the corresponding subpixel (e.g., SP22) may drop .

In order to compensate for the reduction in the luminance of the subpixel (for example, SP22) subjected to the repair processing, the display device 100 according to the embodiments calculates the data to be supplied to the subpixel (for example, SP22) (E.g., SP22) by supplying the data voltage to the operable partial subpixel (e.g., PSP2) of the repaired subpixel (e.g., SP22), and to compensate the brightness of the repaired subpixel .

In this way, in order to compensate the luminance of the repaired sub-pixel (for example, SP22), the display device 100 according to the embodiments stores information about the sub-pixel (for example, SP22) .

Accordingly, the corresponding subpixel (e.g., SP22) that has undergone the repair process can operate more like the other normal normal subpixels that have not undergone repair processing since no bright spots or dark spots have occurred.

The display device 100 according to the embodiments having the above-described surveillance pixel structure can be applied to various display devices such as an organic light emitting display (OLED), a liquid crystal display device (LCD), a plasma display ) And the like. Hereinafter, for convenience of explanation, an organic light emitting display device will be described by way of example.

Some embodiments of the subpixel structure described above are described below.

4 to 9, a first partial subpixel PSP1 and a second partial subpixel PSP2 constituting one subpixel SP commonly supply a driving voltage VDD (Driving Voltage) A display device 100 according to an embodiment having a "common drive voltage line structure" will be described. 10 to 15, when the first partial subpixel PSP1 and the second partial subpixel PSP2 constituting one subpixel SP are supplied with separate driving voltages VDD1 and VDD2, A display device 100 according to an embodiment having an "individual driving voltage line structure" will be described.

4 is a schematic diagram of a subpixel structure in accordance with one embodiment.

4, the sub-pixels (SPji, i = 1, 2, ..., m, j = 1, 2, ..., n) receive the first scan signal SCAN j_1 from the odd gate line GLj_1, And a second partial subpixel PSP2 for receiving the second scan signal SCAN j_2 from the even gate line GLj_2.

4, the first partial subpixel PSP1 and the second partial subpixel PSP2 are connected in common to one common data line DLi to generate a data voltage Vdata from the common data line DLi ) Are commonly applied.

4, each of the first partial subpixel PSP1 and the second partial subpixel PSP2 includes an internal circuit structure (for example, a sensing transistor (RVL) for supplying a reference voltage (Vref) in accordance with a predetermined reference voltage (for example, a case where the reference voltage is included).

Referring to FIG. 4, in the subpixel according to the embodiment, the first partial subpixel PSP1 and the second partial subpixel PSP2 receive the driving voltage VDD from one common driving voltage line DVL At the same time, they are commonly granted.

Namely, all of the m x n sub-pixels (SPji, 1? I? M, 1? J? N) formed in the display panel 110 are the same as the common drive voltage line structure "

On the other hand, at least one subpixel that has undergone repair processing may be present among the m x n subpixels (SPji, 1? I? M, 1? J? N) formed in the display panel 110.

In other words, the display panel 110 is provided with sub-pixels PSP1 and PSP2 which are composed of the first partial subpixel PSP1 and the second partial subpixel PSP2 which are normally operable, One of the first partial subpixel PSP1 and the second partial subpixel PSP2 can be normally operated but the other one can not be normally operated (Hereinafter referred to as "repair-processed subpixel" as a subpixel subjected to a repair processing and having undergone a defect occurrence in one of PSP1 and PSP2) is mixedly formed.

Hereinafter, subpixels that have not undergone repair processing and subpixels that have undergone repair processing under the common drive voltage line structure as shown in FIG. 4 will be described in more detail. However, it is assumed that the display apparatus 100 is an organic light emitting display apparatus.

On the other hand, each sub-pixel of the organic light emitting display device may have a 2T (Transistor) 1C (Capacitor) structure basically including two transistors (a driving transistor and a switching transistor) and a capacitor (See FIG. 5), and in some cases, a 3T1C structure (see FIG. 6) including three transistors (a driving transistor, a switching transistor, and a sensing transistor) and one capacitor (storage capacitor). In addition to this, it may be formed to include four or more transistors and two or more capacitors.

Here, in each sub-pixel of the organic light emitting diode display, the driving transistor DT is turned on to supply a current to the organic light emitting diode OLED to emit the organic light emitting diode OLED. The switching transistor SWT applies the data voltage Vdata supplied through the common data line DLi to the first node (gate node) of the driving transistor DT to turn on the driving transistor DT / Off can be controlled. A capacitor Cst (also referred to as a storage capacitor) is a capacitor that maintains a potential difference between its both ends during one frame period, that is, a potential difference between a gate node of the driving transistor DT and a source node (or a drain node) It plays a role. The sensing transistor included in the 3T1C sub-pixel structure has a role of applying a constant positive voltage (e.g., a reference voltage Vref) to the source node (or drain node) of the driving transistor DT, The voltage of the source node (or the drain node) of the driving transistor DT is turned on to sense and compensate the threshold voltage (Vth) or the mobility of the driving transistor DT, (For example, an analog-to-digital converter (ADC), etc.) through a line (eg, a common reference voltage line (RVL)).

5 is an equivalent circuit diagram for a sub-pixel of a 2T1C structure that has not been repaired under a sub-pixel structure according to an embodiment.

Referring to FIG. 5, a sub-pixel having a 2T1C structure that has not undergone repair processing is composed of a first partial sub-pixel PSP1 and a second partial sub-pixel PSP2.

Referring to FIG. 5, the first partial sub-pixel PSP1 includes a first organic light emitting diode (OLED1), a first driving transistor DT1 for driving the first organic light emitting diode OLED1 And the first scan signal SCAN j_1 supplied through the first gate line GLj_1 and the first scan signal SCAN j_1 is supplied to the common data line DLi and the first node of the first drive transistor DT1 A first switching transistor SWT1 connected between a first node N1 and a third node N3 of the first driving transistor DT1 and a common driving voltage line DVL, And a first capacitor Cst1 connected between the source node and the drain node to be connected.

Referring to FIG. 5, the second partial sub-pixel PSP2 includes a second organic light emitting diode OLED2, a second driving transistor DT2 for driving a second organic light emitting diode (OLED2) And the second scan signal SCAN j_2 supplied through the second gate line GLj_2 and is supplied to the first node N1 of the common data line DLi and the second drive transistor DT2 A second switching transistor SW2 connected between the first node N1 and the third node N3 of the second driving transistor DT2 and a common driving voltage line DVL, And a second capacitor (Cst2, First Capacitor) connected between the source node and the drain node.

5, a common driving voltage (VDD) is applied to the display panel 110 by a first driving transistor DT1 and a second driving transistor DT2 to commonly apply a driving voltage VDD through a third node N3, Line DVL is formed.

FIG. 6 is an equivalent circuit diagram for a sub-pixel that has not undergone repair processing of a 2T1C structure under a sub-pixel structure according to an embodiment.

Referring to FIG. 6, a sub-pixel having a 2T1C structure that has not been repaired is made up of a first partial sub-pixel PSP1 and a second partial sub-pixel PSP2.

Referring to FIG. 6, the first partial sub-pixel PSP1 includes a first organic light emitting diode OLED1, a first driving transistor DT1 for driving the first organic light emitting diode OLED1, And is connected between the common data line DLi and the first node N1 (gate node) of the first driving transistor DT1, which is controlled by the first scan signal SCAN j_1 supplied through the line GLj_1, The switching transistor SWT1 is controlled by the first scan signal SCAN j_1 supplied through the first gate line GLj_1 and the application node of the reference voltage Vref supplied from the common reference voltage line RVL Connected between the second node N2 of the first driving transistor DT1 (the source node or the drain node connected to the first organic light emitting diode OLED1) of the first driving transistor DT1 and the first sensing transistor SENT1 (First sensing transistor) and a first node N1 and a second node N2 of the first driving transistor DT1 And a connected first capacitor (Cst1).

Referring to FIG. 6, the second partial sub-pixel PSP2 includes a second organic light emitting diode OLED2, a second driving transistor DT2 for driving the second organic light emitting diode OLED2, Is connected between the common data line DLi and the first node N1 '(gate node) of the second driving transistor DT2 and is controlled by the second scan signal SCAN j_2 supplied through the line GLj_2. 2 of the reference voltage Vref supplied from the common reference voltage line RVL and the second scan signal SCAN j_2 supplied through the second gate line GLj_2, A second sensing transistor SENT2 (Second Sensing Transistor) connected between the second node N2 '(the source node or the drain node) of the second driving transistor DT2 and the second driving transistor DT2 (the left point of SENT2 in Fig. 6) And a second capacitor Cst2 connected between the first node N1 'and the second node N2' of the driving transistor DT2.

Referring to FIG. 6, a driving voltage VDD is applied to the display panel 110 by the first driving transistor DT1 and the second driving transistor DT2 to the drain node of the third node N3, A common driving voltage line (DVL) for common application is formed.

FIG. 7 is a timing diagram of two scan signals applied to subpixels that have not undergone repair processing, under a subpixel structure according to an embodiment.

Referring to FIG. 7A, in a sub-pixel structure according to an embodiment, a first scan signal SCAN j_1 supplied from the first gate line GLj_1 to the first partial subpixel PSP1, The second scan signal SCAN j_2 supplied from the second gate line GLj_2 to the second partial subpixel PSP2 may be the same scan signal. That is, the timing of the high level voltage VGHL of the first scan signal SCAN j_1 and the second scan signal SCAN j_2 is the same.

Referring to FIG. 7B, in the sub-pixel structure according to the embodiment, the first scan signal SCAN j_1 supplied from the first gate line GLj_1 to the first partial sub-pixel PSP1, And the second scan signal SCAN j_2 supplied from the second gate line GLj_2 to the second partial subpixel PSP2 may be different scan signals. That is, the timing of the high level voltage VGHL of the first scan signal SCAN j_1 and the second scan signal SCAN j_2 may be different from each other.

For example, the first scan signal SCAN j_1, j = 1, 2, ..., n is divided into odd gate lines GLj_1, j = 1, 2, ..., n in an odd frame period The second scan signal SCAN j_2, j = 1, 2, ..., n is a scan signal in which the high level voltage VGHL is output, and the even scan line GLj_2, j = 1, 2, ..., n).

In this case, the first partial sub-pixel PSP1 may be operated in the odd-numbered frame period and the second partial sub-pixel PSP2 may be operated in the even-numbered frame period.

8 is an equivalent circuit diagram of a repaired Sub Pixel with a 2T1C structure under a subpixel structure according to an embodiment. 9 is an equivalent circuit diagram of a repaired sub pixel having a 3T1C structure under a subpixel structure according to an embodiment. However, it is assumed that the first partial subpixel PSP1 is laser cut due to the occurrence of a luminescent spot or dark spot in the first partial subpixel PSP1.

Referring to FIGS. 8 and 9, a repaired sub pixel having at least one of mxn subpixels has a first partial subpixel PSP1, which is assumed to have a luminescent spot or a dark spot, It is cut. Thus, the first partial subpixel PSP1 is the dead partial subpixel (Dead PSP).

The cutting point CP at which the first partial sub-pixel PSP1 is cut may be a first electrode (an anode electrode or a cathode electrode) of the first organic light emitting diode OLED1. The cutting point CP may be connected to the first switching transistor SWT1 in the common data line DLi at a point where the driving voltage VDD is supplied from the common driving voltage line DVL to the first driving transistor DT1, And a point at which a current does not flow from the first partial sub-pixel PSP1 to the first organic light emitting diode OLED1 may be a point at which the data voltage Vdata is supplied to the first partial sub- Lt; / RTI >

When the cutting point CP at which the first partial subpixel PSP1 is cut is the first electrode (anode electrode or cathode electrode) of the first organic light emitting diode OLED1, In the partial subpixel PSP1, the first electrode (anode electrode or cathode electrode) of the first organic light emitting diode OLED1 is cut.

On the other hand, as shown in FIGS. 8 and 9, when the first partial subpixel PSP1 is subjected to the cutting process, since the subpixel SP region is displayed only by the second partial subpixel PSP2, .

Accordingly, the timing controller 140 stores information on at least one subpixel subjected to the repair processing, and uses this information and the image data for each subpixel to reduce the luminance of at least one subpixel subjected to the repair processing And outputs the modified video data to the data driver 120. The data driver 120 may be configured to generate the video data.

The data driver 120 receives the changed video data from the timing controller 140 and outputs a data voltage that can compensate for the luminance reduction of at least one subpixel subjected to the repair process to the common data line DLi .

As described above, one of the first partial subpixel PSP1 and the second partial subpixel PSP2, even if the subpixel has undergone the repair processing due to the occurrence of a bright spot or a dark spot as shown in Figs. 8 and 9, Pixel becomes a dead partial subpixel, but the other PSP2 can operate normally, so that it can operate as a normal subpixel.

Further, the corresponding subpixel subjected to the repair processing can perform an image display operation more like a normal normal subpixel not subjected to repair processing through luminance compensation.

10 to 15, the first partial subpixel PSP1 and the second partial subpixel PSP2 constituting one subpixel SP supply separate driving voltages VDD1 and VDD2. A display device 100 according to an embodiment having an "individual drive voltage line structure"

10 is a schematic diagram of a structure for a subpixel according to another embodiment.

10, each subpixel (SPji, i = 1, 2, ..., m, j = 1, 2, ..., n) receives a first scan signal SCAN j_1 from an odd gate line GLj_1, And a second partial subpixel PSP2 for receiving the second scan signal SCAN j_2 from the even gate line GLj_2.

Referring to FIG. 10, the first partial subpixel PSP1 and the second partial subpixel PSP2 are connected in common to one common data line DLi.

10, each of the first partial subpixel PSP1 and the second partial subpixel PSP2 has an internal circuit structure (for example, a sensing transistor (Vref) supplied from one common reference voltage line (RVL) in common, in accordance with the reference voltage (RVL). Here, the application structure of the reference voltage Vref will be described in more detail with reference to FIG. 16 and FIG.

10, in the subpixel according to another embodiment, the first partial sub-pixel PSP1 receives the first driving voltage VDD1 from the first driving voltage line DVL1, PSP2 receive the second driving voltage VDD2 from the second driving voltage line DVL2.

That is, all of the m x n subpixels (SPji, 1? I? M, 1? J? N) formed in the display panel 110, as shown in Fig. 10, Structure ".

On the other hand, at least one subpixel that has undergone repair processing may be present among the m x n subpixels (SPji, 1? I? M, 1? J? N) formed in the display panel 110.

In other words, the display panel 110 is provided with sub-pixels PSP1 and PSP2 which are composed of the first partial subpixel PSP1 and the second partial subpixel PSP2 which are normally operable, One of the first partial subpixel PSP1 and the second partial subpixel PSP2 can be normally operated but the other one can not be normally operated (Hereinafter referred to as "repair-processed subpixel" as a subpixel subjected to a repair processing and having undergone a defect occurrence in one of PSP1 and PSP2) is mixedly formed.

Hereinafter, the subpixels not subjected to the repair processing and the subpixels subjected to the repair processing will be described in more detail with reference to FIG. 10, under the individual drive voltage line structure. However, it is assumed that the display apparatus 100 is an organic light emitting display apparatus.

On the other hand, each subpixel of the organic light emitting display device can basically have a 2T1C structure including two transistors (a driving transistor and a switching transistor) and one capacitor (storage capacitor) (see Fig. 11) Therefore, it may have a 3T1C structure (refer to FIG. 12) including three transistors (a driving transistor, a switching transistor, and a sensing transistor) and one capacitor (storage capacitor). In addition to this, it may be formed to include four or more transistors and two or more capacitors.

11 is an equivalent circuit diagram of a sub-pixel of a 2T1C structure that has not been subjected to a repair process under a sub-pixel structure according to another embodiment.

Referring to FIG. 11, a sub-pixel having a 2T1C structure that has not undergone a repair process is composed of a first partial sub-pixel PSP1 and a second partial sub-pixel PSP2.

Referring to FIG. 11, the first partial sub-pixel PSP1 includes a first organic light emitting diode OLED1, a first driving transistor DT1 for driving the first organic light emitting diode OLED1, A first switching transistor SWT1 which is controlled by the signal SCAN j_1 and is connected between the common data line and the first node N1 of the first driving transistor DT1, And a first capacitor Cst1 connected between a node N1 (gate node) and a third node (N3, a drain node or a source node).

Referring to FIG. 11, the second partial sub-pixel PSP2 includes a second organic light emitting diode OLED2, a second driving transistor DT2 for driving the second organic light emitting diode OLED2, A second switching transistor SWT2 which is controlled by the signal SCAN j_2 and is connected between the common data line DLi and the first node N1 '(gate node) of the second driving transistor DT2, And a second capacitor Cst2 connected between a first node N1 'of the transistor DT2 and a third node N3', a drain node or a source node.

11, a first driving voltage VDD1 and a second driving voltage VDD2 are applied to the third node N3 and N3 'of the first driving transistor DT1 and the second driving transistor DT2, respectively, A first driving voltage line DVL1 and a second driving voltage line DVL2 for applying the driving voltage VDD2 are formed.

12 is an equivalent circuit diagram of a sub-pixel of a 3T1C structure that has not been subjected to a repair process under a sub-pixel structure according to another embodiment.

Referring to FIG. 12, a sub-pixel of a 3T1C structure that has not undergone repair processing is composed of a first partial sub-pixel PSP1 and a second partial sub-pixel PSP2.

Referring to FIG. 12, the first partial sub-pixel PSP1 includes a first organic light emitting diode OLED1, a first driving transistor DT1 for driving the first organic light emitting diode OLED1, A first switching transistor SWT1 controlled by a signal SCAN j_1 and connected between a common data line and a first node N1 (gate node) of the first driving transistor DT1, 12) of the reference voltage Vref supplied from the common reference voltage line RVL and the second node N2 of the first driving transistor DT1 And a first capacitor Cst1 connected between the first node N1 and the second node N2 of the first driving transistor DT1. The first sensing transistor SENT1 is connected between the first node N1 and the second node N2, .

Referring to FIG. 12, the second partial sub-pixel PSP2 includes a second organic light emitting diode OLED2, a second driving transistor DT2 for driving the second organic light emitting diode OLED2, A second switching transistor SWT2 controlled by the signal SCAN j_2 and connected between the common data line DLi and the first node N1 '(gate node) of the second driving transistor DT2, (The left point of SENT2 on Fig. 12) of the reference voltage Vref supplied from the common reference voltage line RVL and the second node of the second driving transistor DT2, which are controlled by the signal SCAN j_2, Connected between the first node N1 'and the second node N' of the second driving transistor DT2, a second sensing transistor SWT2 connected between the first node N1 'and the second node N2' (source node or drain node) And a capacitor Cst2.

12, a first driving voltage VDD1 for applying a first driving voltage VDD1 to a drain node of the first driving transistor DT1 or a third node N3 corresponding to a source node is applied to the display panel 110, And the second driving voltage line DVL2 for applying the second driving voltage VDD2 to the third node N3 'corresponding to the drain node or the source node of the second driving transistor DT2. Is formed.

FIG. 13 is a timing diagram of two scan signals applied to a subpixel not subjected to a repair process under a subpixel structure according to another embodiment.

13A, in a sub-pixel structure according to another embodiment, a first scan signal SCAN j_1 supplied from the first gate line GLj_1 to the first partial sub-pixel PSP1, The second scan signal SCAN j_2 supplied from the second gate line GLj_2 to the second partial subpixel PSP2 may be the same scan signal. That is, the timing of the high level voltage VGHL of the first scan signal SCAN j_1 and the second scan signal SCAN j_2 is the same.

Referring to FIG. 13B, in the subpixel structure according to another embodiment, a first scan signal SCAN j_1 supplied from the first gate line GLj_1 to the first partial subpixel PSP1, And the second scan signal SCAN j_2 supplied from the second gate line GLj_2 to the second partial subpixel PSP2 may be different scan signals. That is, the timing of the high level voltage VGHL of the first scan signal SCAN j_1 and the second scan signal SCAN j_2 may be different from each other.

For example, the first scan signal SCAN j_1, j = 1, 2, ..., n is divided into odd gate lines GLj_1, j = 1, 2, ..., n in an odd frame period The second scan signal SCAN j_2, j = 1, 2, ..., n is a scan signal in which the high level voltage VGHL is output, and the even scan line GLj_2, j = 1, 2, ..., n).

In this case, the first partial sub-pixel PSP1 may be operated in the odd-numbered frame period and the second partial sub-pixel PSP2 may be operated in the even-numbered frame period.

FIG. 14 is an equivalent circuit diagram of a repaired Sub Pixel with a 2T1C structure under a subpixel structure according to another embodiment. FIG. 15 is an equivalent circuit diagram of a repaired Sub Pixel with a 3T1C structure under a subpixel structure according to another embodiment. However, it is assumed that the first partial subpixel PSP1 is laser cut due to the occurrence of a luminescent spot or dark spot in the first partial subpixel PSP1.

Referring to FIGS. 14 and 15, a repaired sub pixel having at least one of mxn subpixels has a first partial subpixel PSP1, which is assumed to have a luminescent spot or dark spot, It is cut. Thus, the first partial subpixel PSP1 is the dead partial subpixel (Dead PSP).

The cutting point CP at which the first partial sub-pixel PSP1 is cut may be a first electrode (an anode electrode or a cathode electrode) of the first organic light emitting diode OLED1.

The cutting point CP may be connected to the first switching transistor SWT1 in the common data line DLi at a point where the driving voltage VDD is supplied from the common driving voltage line DVL to the first driving transistor DT1, And a point at which a current does not flow from the first partial sub-pixel PSP1 to the first organic light emitting diode OLED1 may be a point at which the data voltage Vdata is supplied to the first partial sub- Lt; / RTI >

When the cutting point CP at which the first partial subpixel PSP1 is cut is the first electrode (anode electrode or cathode electrode) of the first organic light emitting diode OLED1, In the partial subpixel PSP1, the first electrode (anode electrode or cathode electrode) of the first organic light emitting diode OLED1 is cut.

On the other hand, as shown in FIGS. 14 and 15, when the first partial subpixel PSP1 is cut, since the subpixel SP is displayed only by the second partial subpixel PSP2, can do.

Accordingly, the timing controller 140 stores information on at least one subpixel subjected to the repair processing, and uses this information and the image data for each subpixel to reduce the luminance of at least one subpixel subjected to the repair processing And outputs the modified video data to the data driver 120. The data driver 120 may be configured to generate the video data.

The data driver 120 receives the changed video data from the timing controller 140 and outputs a data voltage that can compensate for the luminance reduction of at least one subpixel subjected to the repair process to the common data line DLi .

As described above, one of the first partial subpixel PSP1 and the second partial subpixel PSP2, even if the subpixel has undergone the repair processing due to the occurrence of a bright spot or a dark spot as shown in Figs. 14 and 15, Pixel becomes a dead partial subpixel, but the other PSP2 can operate normally, so that it can operate as a normal subpixel.

Further, the corresponding subpixel subjected to the repair processing can perform an image display operation more like a normal normal subpixel not subjected to repair processing through luminance compensation.

16 and 17, the reference voltage Vref is commonly applied to the first partial subpixel PSP1 and the second partial subpixel PSP2 of each subpixel SPji The reference voltage applying structure will be described.

16 and 17 are two exemplary views of a reference voltage application structure according to embodiments. The subpixel placement illustrated in Figs. 16 and 17 is the same.

First, a first reference voltage application structure will be described with reference to FIG.

Referring to FIG. 16, a common reference voltage line RVL may be formed for each one sub-pixel column.

Referring to the example of FIG. 16, SP11, SP21, and SP31 are a set of subpixels in the first column (i = 1), that is, three subpixels included in the first subpixel column. SP12, SP22 and SP32 are the set of subpixels in the second column (i = 2), i.e., three subpixels included in the second subpixel column. SP13, SP23 and SP33 are the set of subpixels in the third column (i = 3), i.e., three subpixels included in the third subpixel column. SP14, SP24 and SP34 are the set of subpixels in the fourth column (i = 4), i.e., three subpixels included in the fourth subpixel column.

16, the first partial subpixel PSP1 and the second subpixel PSP2 of each subpixel included in one subpixel column are connected to the common reference voltage line RVL by a reference voltage Vref .

For example, SP11, SP21, and SP31 included in the first subpixel column (a set of subpixels with i = 1) are supplied from the common reference voltage line RVL1 disposed corresponding to the first subpixel column to the reference voltage Vref ). SP12, SP22 and SP32 included in the second subpixel column (the set of subpixels with i = 2) are supplied with the reference voltage Vref from the common reference voltage line RVL2 arranged corresponding to the second subpixel column . SP13, SP23 and SP33 included in the third subpixel column (the set of subpixels with i = 3) are supplied with the reference voltage Vref from the common reference voltage line RVL3 arranged corresponding to the third subpixel column . SP14, SP24, and SP34 included in the fourth subpixel column (a set of subpixels with i = 4) receive the reference voltage Vref from the common reference voltage line RVL4 arranged corresponding to the fourth subpixel column .

On the other hand, unlike the arrangement structure of the common reference voltage line (RVL) shown in FIG. 16, as shown in FIG. 17, the common reference voltage line RVL may be formed by sharing one . 17, when the common reference voltage line RVL is formed for every four sub-pixel columns, the common reference voltage line RVL may be formed between the second sub-pixel row and the third sub-pixel column .

Referring to FIG. 17, a connection pattern (CP) connected to the common reference voltage line RVL may be formed as an application structure of the reference voltage Vref. Here, the connection pattern can also be seen as part of the common reference voltage line (RVL). That is, the common reference voltage line RVL described herein may be a concept that further includes a separate connection pattern.

Referring to FIG. 17, a connection pattern CP is formed in a direction intersecting the common reference voltage line RVL, and may be formed between two sub-pixels.

17, when two subpixels are any first subpixel (e.g., SP21) and a second subpixel (e.g., SP31), a first subpixel (e.g., SP21) and a second subpixel The connection pattern CP23 formed between the first partial subpixel PSP2 and the second partial subpixel SP31 of the first subpixel PSP2 The reference voltage Vref supplied from the common reference voltage line RVL can be commonly applied.

17, the first partial subpixel PSP1 and the second partial subpixel PSP2 of the subpixel included in the second subpixel column and the third subpixel column immediately adjacent to the common reference voltage line RVL, May directly receive the reference voltage Vref from the common reference voltage line RVL without a connection pattern (CP) structure.

According to the reference voltage application structure as shown in FIG. 17, although one subpixel is divided into two partial subpixels PSP1 and PSP2, two partial subpixels PSP1 and PSP2 each have a reference voltage Vref of the display panel 110 is designed to have a common structure, the reduction of the aperture ratio of the display panel 110 can be considerably reduced.

16 and 17, SP11, SP12, SP13 and SP14 may be, for example, four subpixels constituting one pixel and may be red, white, green and blue subpixels.

2. Description of the Related Art [0002] In recent years, as users' demands for realistic images have increased, display devices capable of realizing not only 2D (two-dimensional) images but also 3D (three-dimensional) images have been developed. A display device for displaying a 3D image implements a 3D image using a viewer's binocular parallax display. At this time, a shutter glass method, a lenticular lens method, a patterned retarder (PR) method using polarizing glasses, and the like have been developed as driving methods for displaying 3D images. Hereinafter, a 3D image driving method using a shutter glass system will be described.

18 is a view showing a 3D image driving method of a general display device of a shutter glass type.

Referring to FIG. 18, a typical display apparatus using a shutter glass system realizes a 3D image by allowing a left eye image and a right eye image to be recognized by a left eye and a right eye of a viewer with a time difference.

In the odd frame period, when an image is displayed on the display panel, the left eye lens of the shutter glass is turned on and the right eye lens is turned off so that the image is recognized in the left eye of the viewer. Conversely, when an image is displayed on the display panel in the even frame period, the right eye lens of the shutter glass is turned on and the left eye lens is turned off so that the image is recognized in the right eye of the viewer.

On the other hand, when the 2D image is implemented, both the left eye lens and the right eye lens of the shutter glass are turned on during the odd frame period and the even frame period, thereby allowing the viewer to recognize the 2D image.

Hereinafter, the image recognized in the left eye of the viewer is referred to as a left eye image, and the image recognized in the right eye is referred to as a right eye image. Thus, the left eye image recognized in the left eye and the right eye image recognized in the right eye are fused with a time difference, and the viewer views the 3D image.

Here, a black image is inserted between the left eye image and the right eye image (black insertion) so that the left eye image and the right eye image displayed on the display panel do not overlap each other. At this time, the period of the black image is required by the time when the shutter glass is turned off.

In general, in the 3D image driving method using a shutter glass method, the left eye images are sequentially emitted in the odd frame period, and then the black data is sequentially applied. Thereafter, the right eye images are successively emitted in the even frame period. Thus, the left eye image data, the black image data, and the right eye image data are sequentially applied.

Accordingly, the emission duty is reduced by the time that the black image data is successively applied between the left eye image and the right eye image, and the luminance is lowered when the 3D image is driven in comparison with the 2D image driving. In order to prevent the left eye image and the right eye image from overlapping, black image data should be applied for the same time as the left eye image and the right eye image.

When the 3D image is driven at the same resolution as the 2D image, the frequency is reduced due to the application of the black data. On the other hand, when the frequencies of the 2D image and the 3D image are the same, the resolution of the 3D image relative to the 2D image is reduced to ½.

19 is a diagram illustrating odd subpixels and even subpixels of a display device according to an embodiment of the present invention. The pixel of the organic light emitting display may be composed of red, green, and blue subpixels of three colors, or red, green, blue, and white subpixels of four colors. FIG. 19 shows one subpixel among all the subpixels of the organic light emitting display, and each subpixel is composed of a first partial subpixel and a second partial subpixel as a double pixel structure . Hereinafter, the first partial subpixel will be referred to as an odd subpixel, and the second partial subpixel will be referred to as an even subpixel.

Referring to FIG. 19, each subpixel of the OLED display is composed of an odd subpixel and an even subpixel. Each of the odd subpixel and even subpixel includes organic light emitting diodes OLED1 and OLED2 and a driving circuit for driving the organic light emitting diodes OLED1 and OLED2.

The driving circuit of the odd subpixel and even subpixel can be configured with a 3Tr-1Cap structure including three transistors and one storage capacitor. The three transistors include the driving transistors DT1 and DT2, the switching transistors SWT1 and SWT2, and the sensing transistor (see Fig. 19).

In some cases, the driving circuit of the odd subpixel and even subpixel may be configured with a 2Tr1Cap structure including two transistors (a driving transistor, a switching transistor) and a storage capacitor (see FIG. 11).

In addition to this, the driving circuit of the odd subpixel and even subpixel may include four or more transistors and two or more capacitors.

Specifically, the odd sub-pixel includes a first organic light emitting diode OLED1, a first driving transistor DT1 for driving the first organic light emitting diode OLED1, a first switching transistor SWT1, (SENT1) and a first storage capacitor (Cst1).

The gate electrode of the first switching transistor SWT1 is connected to the first gate line, the source electrode thereof is connected to the data line, and the drain electrode thereof is connected to the first node N1 of the first driving transistor DT1. The first switching transistor SWT1 is turned on and off by the first scan signal scan1.

The gate electrode of the first sensing transistor SENT1 is connected to the first gate line, the source electrode thereof is connected to the node to which the reference voltage Ref is applied, and the drain electrode is connected to the second node of the first driving transistor DT1 N2. The first sensing transistor SENT1 is turned on and off by the first scan signal scan1.

The first storage capacitor Cst1 is connected between the first node N1 and the second node N2.

The display panel is provided with a plurality of first driving voltage lines for applying the first driving voltage VDD1 to the first driving transistor DT1 through the third node N3. The first driving transistor DT1 is turned on by a signal input from the first node N1 and supplies a driving current to the first organic light emitting diode OLED1. And the first organic light emitting diode OLED1 emits light by the driving current.

Subsequently, the even subpixel includes a second organic light emitting diode OLED2, a second driving transistor DT2 for driving the second organic light emitting diode OLED2, a second switching transistor SWT2, a second sensing transistor SENT2 and a second storage capacitor Cst2.

The gate electrode of the second switching transistor SWT2 is connected to the second gate line, the source electrode thereof is connected to the data line, and the drain electrode thereof is connected to the first node N1 of the second driving transistor DT2. The second switching transistor SWT2 is turned on and off by the second scan signal scan2.

The source electrode of the second sensing transistor SENT2 is connected to the node to which the reference voltage Ref is applied and the drain electrode of the second sensing transistor SENT2 is connected to the second node of the second driving transistor DT2 N2. The second sensing transistor SENT2 is turned on and off by the second scan signal scan1.

The second storage capacitor Cst2 is connected between the first node N1 and the second node N2.

The display panel is provided with a plurality of second driving voltage lines for applying the second driving voltage VDD2 to the second driving transistor DT2 through the third node N3. The second driving transistor DT2 is turned on by a signal input from the first node N1 to supply a driving current to the second organic light emitting diode OLED2. And the second organic light emitting diode OLED2 emits light by the driving current.

Here, gate lines and driving power supply lines are disposed for the odd subpixel and the even subpixel, respectively. On the other hand, one data line is shared by odd subpixel and even subpixel, and one reference voltage line is shared by odd subpixel and even subpixel.

FIG. 20 is a view showing an example of a 3D simultaneous light emission drive method of a display device according to an embodiment of the present invention, FIG. 21 is a diagram illustrating a method of driving a 3D simultaneous light emission of a display device according to an embodiment of the present invention, Fig.

Referring to FIGS. 20 and 21, the conventional shutter glass type 3D image driving method has a disadvantage in that luminance is reduced when a 3D image is driven. On the other hand, in the driving method of the display device according to the embodiment of the present invention, when the driving frequency of 60 Hz or 120 Hz is used as a reference, all the odd subpixels are simultaneously emitted, and the luminance of the 3D image is increased There is an advantage that can be made.

A display device according to an embodiment of the present invention simultaneously emits odd subpixels configured in all subpixels in an odd frame period in a double pixel structure in which one subpixel is composed of odd subpixel and even subpixel, And simultaneously emits even-numbered subpixels constituted in all subpixels in a frame period to realize a 3D image.

(Scan 1-1, scan 2-1, scan 3-1) supplied to the first gate lines arranged in the odd subpixels in the double pixel structure and the second scan signals The second scan signals (scan 1-2, scan 2-2, scan 3-2) supplied to the lines may be different signals. That is, the timing of the high level voltages of the first scan signals (scan 1-1, scan 2-1, scan 3-1) and the second scan signals (scan 1-2, scan 2-2, scan 3-2) May be different.

For example, the first scan signals (scan 1-1, scan 2-1, scan 3-1) are signals applied to the first gate line of the odd subpixel in the even frame period, and the second scan signals scan 1 -2, scan 2-2, and scan 3-2 are signals supplied to the second gate line of the even subpixel in the odd frame period. Accordingly, a data voltage is applied to the odd subpixels in the even frame period, and a data voltage is applied to the even subpixels in the odd frame period. That is, data of odd subpixels is programmed during the even frame period and data of even subpixels is applied (programmed) during the odd frame period.

≪ Description of operation of right eye video emission &

During the even frame period, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed in real time (RT). As another example, in the even frame period, the threshold voltage of the second driving transistor DT2 disposed in a specific sub-pixel may be sensed in real time.

Then, the left eye image is emitted in all even subpixels.

The first scan signals (scan 1-1, scan 2-1, scan 3-1) are sequentially applied to all odd subpixels when the left eye image is emitted in all even subpixels in the even frame period, The right eye image data is sequentially applied to the odd subpixels turned on by the scan signals (scan 1-1, scan 2-1, scan 3-1). That is, when emitting a left eye image in all even subpixels, right eye image data is sequentially applied to all odd subpixels.

Then, a black image is inserted (BI) to prevent the left eye image and the right eye image from overlapping each other. A first low driving voltage VDD1 is applied to the first driving voltage line so that black is displayed in all odd subpixels to insert a black image. In addition, a second low driving voltage VDD2 is applied to the second driving voltage line so that black is displayed in the entire non-subpixels to insert a black image.

Then, the threshold voltage of the first driving transistor DT1 arranged in all odd subpixels is sensed (RT) in the odd frame period. That is, the threshold voltage of the first driving transistor DT1 arranged in all the odd subpixels is sensed in real time in the interval between the even frame and the odd frame. As another example, the threshold voltage of the first driving transistor DT1 arranged in a certain odd subpixel in the odd frame period may be sensed in real time (RT).

Here, the period of sensing (RT) the threshold voltage of the first driving transistor DT1 arranged in all the odd subpixels in real time does not overlap with the period of applying the left eye image data to all the even subpixels.

Then, the first driving voltage VDD1 is applied to the first driving voltage line to simultaneously emit all the odd subpixels. The video data of the entire odd subpixel is programmed in the previous even frame period, and the entire odd subpixel can be simultaneously emitted by the first driving voltage VDD1. That is, the right eye image is emitted in the entire odd subpixel in the odd frame period. At this time, the right eye lens of the shutter glass is turned on and the left eye lens is turned off so that the right eye image is recognized on the right side of the viewer.

When the right eye image is emitted in the entire odd subpixel, the second scan signals (scan 1-2, scan 2-2, scan 3-2) are sequentially applied to all the even subpixels, and the second scan signal scan 1 2, scan 2 - 2, and scan 3 - 2, sequentially apply the left eye image data to the even subpixels turned on. That is, the left eye image data is programmed to all even subpixels.

<Explanation of operation of left eye image emission>

During the odd frame period, the threshold voltage of the first driving transistor DT1 arranged in all the odd subpixels is sensed in real time (RT). As another example, in the odd frame period, the threshold voltage of the first driving transistor DT1 disposed in a certain odd subpixel may be sensed in real time (RT).

Then, the right eye image is emitted in all the odd subpixels.

The second scan signals (scan 1-2, scan 2-2, scan 3-2) are sequentially applied to all the even subpixels when the right eye image is emitted in all odd subpixels in the odd frame period, The left eye image data is sequentially applied to the even subpixels turned on by the scan signals (scan 1-2, scan 2-2, and scan 3-2). That is, when the right eye image is emitted in all the odd subpixels, the left eye image data is sequentially applied to all the even subpixels.

Then, a low voltage is applied to all the first driving voltage lines to prevent all the odd subpixels from emitting light in order to prevent the left eye image and the right eye image from overlapping. At the same time, a low voltage is applied to all the second driving voltage lines so that all even subpixels do not emit light. That is, the black image is inserted (BI) in the odd frame period and the even frame period period.

Then, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed (RT) in the even frame period. That is, since the emission of the left eye image and the emission of the right eye image are alternately performed, the threshold voltage of the second driving transistor DT2 arranged in all the even subpixels in the interval between the odd frame and the even frame is sensed in real time (RT) do. As another example, the threshold voltage of the second driving transistor DT2 arranged in a specific sub-pixel may be sensed (RT) in the even frame period.

Here, the period for sensing (RT) the threshold voltage of the second driving transistor DT2 arranged in all even subpixels in real time does not overlap the period for applying right eye image data to all odd subpixels.

Then, a second high driving voltage VDD2 is applied to the second driving voltage line to simultaneously emit all the even subpixels. The left eye image data is programmed in the entire odd sub-pixel in the previous odd frame period, so that the entire odd sub-pixel can be simultaneously emitted by the second driving voltage VDD2. That is, the left eye image is emitted in the entire even subpixel in the even frame period. At this time, the left eye lens of the shutter glass is turned on, and the right eye lens is turned off so that the right eye image is recognized on the left eye of the viewer.

When the left eye image is emitted from the entire even subpixel, the first scan signals (scan 1-1, scan 2-1, scan 3-1) are sequentially applied to all the odd subpixels, and the first scan signal scan 1 -1, scan 2-1, and scan 3-1, respectively.

As described above, in the odd frame period, the right odd subpixels are simultaneously emitted to display the right eye image. When the right eye image is emitted in the entire odd subpixel, the left eye image data is applied to all the even subpixels. That is, the light emission of the left eye image and the application (program) of the right eye image data are simultaneously performed.

Between the odd frame period and the even frame period, a black image is inserted (BI).

Then, in the even frame period, the entire sub-pixel is simultaneously emitted to display the left eye image. When emitting the left eye image in the entire even subpixel, right eye image data is applied to the entire odd subpixel. That is, the light emission of the right eye image and the biasing of the left eye image data are simultaneously performed.

The driving method of the display device according to the embodiment of the present invention may apply the first high driving voltage VDD1 to the first driving voltage line to simultaneously emit the right eye image in all the odd subpixels. Then, a second high driving voltage (VDD2) is applied to the second driving voltage line to simultaneously emit the left eye image in all the even sub-pixels. During the insertion (BI) period of the black image, a first low driving voltage VDD1 is applied to the first driving voltage line so that black is displayed in all odd subpixels. In addition, a second low driving voltage VDD2 is applied to the second driving voltage line so that black is displayed in the entire non-sub-pixel.

Referring to the point of time when the black image is inserted (BI), the threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed after the black image is inserted (BI). After the black image is inserted (BI), the threshold voltage of the driving transistors of all the even subpixels or some even subpixels is sensed.

In this manner, the first driving voltage VDD1 and the second driving voltage VDD2 are swung (high and low) to control the light emission and the non-light emission of the entire odd subpixel and all the even subpixels.

[Table 1]

Referring to Table 1, 2D and 3D resolutions and luminance of a conventional display device and a display device according to an embodiment of the present invention are shown in comparison.

A method of driving a display device according to an exemplary embodiment of the present invention allows light emission of a right eye image and application (program) of left eye image data to be simultaneously performed, and simultaneous application of light emission of a left eye image and right eye image data It is not necessary to apply black data. Therefore, the emission time of the right eye image and the left eye image can be increased. Accordingly, the left eye image and the right eye image are both emitted based on the driving frequency of 60 Hz or 120 Hz, thereby enhancing the brightness of the 3D image. The display device and the driving method thereof according to the present invention are advantageous in that the luminance of a 3D image can be doubled based on the same driving frequency as compared with the display device according to the related art and the driving method thereof.

The display apparatus according to the related art reduces the resolution of the 3D image compared to the resolution of the 2D image to ½. On the other hand, the display device according to the embodiment of the present invention is advantageous in that the 2D image and the 3D image maintain the same resolution by applying the double pixel driving method.

22 is a diagram showing another example of a method of driving a display device according to an embodiment of the present invention.

20 and 22, a method of driving a display device according to an embodiment of the present invention is a method of driving a display device in a double pixel structure in which one subpixel is composed of odd subpixel and even subpixel Simultaneously emits odd subpixels configured in all subpixels, and simultaneously emits even subpixels configured in all subpixels in the even frame period to implement a 3D image.

The first scan signals scan 1-1, scan 2-1, scan 3-1 are signals applied to the first gate line of the odd subpixel in the even frame period, and the second scan signals scan 1-2, scan 2-2 and scan 3-2 are signals supplied to the second gate line of the even subpixel in the odd frame period. Accordingly, a data voltage is applied to the odd subpixels in the even frame period, and a data voltage is applied to the even subpixels in the odd frame period. That is, data of odd subpixels are applied (programmed) during the even frame period and data of even subpixels are applied (programmed) during the odd frame period.

&Lt; Description of operation of right eye video emission &

The first scan signals (scan 1-1, scan 2-1, scan 3-1) are sequentially applied to all odd subpixels when the left eye image is emitted in all even subpixels in the even frame period, The right eye image data is sequentially applied to the odd subpixels turned on by the scan signals (scan 1-1, scan 2-1, scan 3-1). That is, when emitting a left eye image in all even subpixels, right eye image data is sequentially applied to all odd subpixels.

Then, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed (RT). That is, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed in real time after emitting the left eye image in all even subpixels. As another example, the threshold voltage of the second driving transistor DT2 arranged in a specific sub-pixel may be sensed (RT).

Here, the period for sensing (RT) the threshold voltage of the second driving transistor DT2 arranged in all even subpixels in real time does not overlap the period for applying right eye image data to all odd subpixels.

Then, a black image is inserted (BI) to prevent the left eye image and the right eye image from overlapping each other. A first low driving voltage VDD1 is applied to the first driving voltage line so that black is displayed in all odd subpixels to insert a black image. In addition, a second low driving voltage VDD2 is applied to the second driving voltage line so that black is displayed in the entire non-subpixels to insert a black image.

Then, the first driving voltage VDD1 is applied to the first driving voltage line to simultaneously emit all the odd subpixels. The video data of the entire odd subpixel is applied (programmed) during the previous even frame period, so that the entire odd subpixel can be simultaneously emitted by the first driving voltage VDD1. That is, the right eye image is emitted in the entire odd subpixel in the odd frame period. At this time, the right eye lens of the shutter glass is turned on and the left eye lens is turned off so that the right eye image is recognized on the right side of the viewer.

Then, the threshold voltage of the first driving transistor DT1 arranged in all the odd subpixels is sensed (RT). That is, the threshold voltage of the first driving transistor DT1 disposed in all the odd subpixels after the right eye image is emitted in all the odd subpixels is sensed in real time (RT). As another example, the threshold voltage of the first driving transistor DT1 arranged in a certain odd subpixel may be sensed (RT).

Here, the period of sensing (RT) the threshold voltage of the first driving transistor DT1 arranged in all the odd subpixels in real time does not overlap with the period of applying the left eye image data to all the even subpixels.

When the right eye image is emitted in the entire odd subpixel, the second scan signals (scan 1-2, scan 2-2, scan 3-2) are sequentially applied to all the even subpixels, and the second scan signal scan 1 2, scan 2 - 2, and scan 3 - 2, sequentially apply the left eye image data to the even subpixels turned on. That is, the left eye image data is applied (programmed) to all even subpixels.

<Explanation of operation of left eye image emission>

The second scan signals (scan 1-2, scan 2-2, scan 3-2) are sequentially applied to all the even subpixels when the right eye image is emitted in all odd subpixels in the odd frame period, The left eye image data is sequentially applied to the even subpixels turned on by the scan signals (scan 1-2, scan 2-2, and scan 3-2). That is, when the right eye image is emitted in all the odd subpixels, the left eye image data is sequentially applied to all the even subpixels.

Then, a low voltage is applied to all the first driving voltage lines to prevent all the odd subpixels from emitting light in order to prevent the left eye image and the right eye image from overlapping. At the same time, a low voltage is applied to all the second driving voltage lines so that all even subpixels do not emit light. That is, the black image is inserted (BI) in the odd frame period and the even frame period period.

Then, a second high driving voltage VDD2 is applied to the second driving voltage line to simultaneously emit all the even subpixels. Eye video data is applied (programmed) to the entire even sub-pixel during the previous odd frame period, so that all the even sub-pixels can be simultaneously emitted by the second driving voltage VDD2. That is, the left eye image is emitted in the entire even subpixel in the even frame period. At this time, the left eye lens of the shutter glass is turned on, and the right eye lens is turned off so that the right eye image is recognized on the left eye of the viewer.

When the left eye image is emitted from the entire even subpixel, the first scan signals (scan 1-1, scan 2-1, scan 3-1) are sequentially applied to all the odd subpixels, and the first scan signal scan 1 -1, scan 2-1, and scan 3-1, respectively. That is, when the left eye image is emitted in the entire even subpixel in the even frame period, the right eye image data is applied (programmed) to the entire odd subpixel.

Then, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed (RT) in the even frame period. That is, after all the even subpixels are emitted, the threshold voltage of the second driving transistor DT2 arranged in all even subpixels is sensed in real time (RT). As another example, the threshold voltage of the second driving transistor DT2 arranged in a specific sub-pixel may be sensed (RT) in the even frame period.

Here, the period for sensing (RT) the threshold voltage of the second driving transistor DT2 arranged in all even subpixels in real time does not overlap the period for applying right eye image data to all odd subpixels.

As described above, during the even frame period, all the even sub-pixels are simultaneously emitted to display the left eye image. When emitting the left eye image in the entire even subpixel, right eye image data is applied to the entire odd subpixel. That is, the light emission of the left eye image and the application (program) of the right eye image data are simultaneously performed.

Between the odd frame period and the even frame period, a black image is inserted (BI).

During the insertion (BI) period of the black image, a first low driving voltage VDD1 is applied to the first driving voltage line so that black is displayed in all odd subpixels. In addition, a second low driving voltage VDD2 is applied to the second driving voltage line so that black is displayed in the entire non-sub-pixel.

Referring to the point of time when the black image is inserted (BI), the threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed before the black image is inserted (BI). Then, before the black image BI is inserted, the threshold voltage of the driving transistor of the entire even subpixel or some even subpixels is sensed.

After the left eye image is emitted, the threshold voltage of the driving transistors of all the even subpixels or some even subpixels is sensed, so that the sensing lines of the even pixels can be prevented from being reflected on the screen. After the right eye image is emitted, the threshold voltages of the driving transistors of all the odd subpixels or some odd subpixels are sensed, so that the sensing lines of the odd pixels can be prevented from being reflected on the screen.

In this manner, the first driving voltage VDD1 and the second driving voltage VDD2 are swung (high and low) to control the light emission and the non-light emission of the entire odd subpixel and all the even subpixels.

The driving method of the display apparatus according to the embodiment of the present invention is characterized in that the light emission of the right eye image and the program of the left eye image data are concurrently performed and the light emission of the left eye image and the program of the right eye image data are simultaneously performed, There is no. Therefore, the emission time of the right eye image and the left eye image can be increased. Accordingly, the left eye image and the right eye image are both emitted based on the driving frequency of 60 Hz or 120 Hz, thereby enhancing the brightness of the 3D image. The display device and the driving method thereof according to the present invention are advantageous in that the luminance of a 3D image can be doubled based on the same driving frequency as compared with the display device according to the related art and the driving method thereof.

The display apparatus according to the related art reduces the resolution of the 3D image compared to the resolution of the 2D image to ½. On the other hand, the display device according to the embodiment of the present invention is advantageous in that the 2D image and the 3D image maintain the same resolution by applying the double pixel driving method.

As described above, according to the present invention, there is an effect of providing the display device 100 and the display panel 110 having the sub-pixel structure that enables normal use even after the defective sub-pixel that has become the bright spot or the dark spot is repaired .

Further, according to the present invention, it is possible to provide a display device (100) and a display panel (110) capable of compensating for a reduction in luminance of a subpixel subjected to a repair process.

In addition, according to the present invention, it is possible to provide a display device 100 and a display panel 110 having a sub-pixel structure, which enables a repair process to be easily and quickly performed on a defective sub-pixel that has become a bright spot or a dark spot.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: Timing controller

Claims (8)

Emitting the first image in the entire odd subpixel during the odd frame period and applying the second image data to the entire even subpixel;
Emitting the second image in the entire even subpixel during the even frame period and applying the first image data to the entire odd subpixel; And
And inserting a black image between a period during which the first image is emitted and a period during which the second image is emitted. The method according to claim 1,
A first high driving voltage is supplied to the entire odd subpixel in the odd frame period to simultaneously emit the entire odd subpixel,
And supplying a second high driving voltage to the whole even subpixel in the even frame period to simultaneously emit the entire even subpixel. The method according to claim 1,
In the step of inserting the black image,
A first row driving voltage is supplied to the entire odd subpixel, and a second row driving voltage is supplied to the entire even subpixel. The method according to claim 1,
The threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed after the first image is emitted in the entire odd subpixel,
And a threshold voltage of the driving transistor of the even-numbered sub-pixel or the even-numbered sub-pixel is sensed after the second image is emitted from the entire even sub-pixel. The method according to claim 1,
A threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed before the first video is emitted in the entire odd subpixel,
And a threshold voltage of the driving transistor of the even-numbered subpixel or some even-numbered subpixels is sensed before the second image is emitted in the entire even subpixel. The method according to claim 1,
Before the black image is inserted, the threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed,
And a threshold voltage of the driving transistor of the entire even subpixel or some even subpixels before the black image is inserted. The method according to claim 1,
After the black image is inserted, the threshold voltage of the driving transistor of the entire odd subpixel or a part of the odd subpixel is sensed,
And a threshold voltage of a driving transistor of the entire even subpixel or some even subpixels after the black image is inserted. 8. The method according to any one of claims 4 to 7,
A period for sensing the threshold voltage of the driving transistor of the all or some even subpixels and a period for applying the first video data to the entire odd subpixel do not overlap,
Wherein the period for sensing the threshold voltage of the driving transistor of the all or a part of the odd subpixels does not overlap the period for applying the second video data to the whole even subpixels.

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