KR20190044159A - Thin film trnasistor comprising oxide semiconductor layer, method for manufacturing the same and display device comprising the same - Google Patents

Abstract

According to an embodiment of the present invention, a thin-film transistor comprises: a gate electrode disposed on a substrate; an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode while being isolated from the gate electrode; a gate insulation film disposed between the gate electrode and the oxide semiconductor layer; a source electrode connected to the oxide semiconductor layer; and a drain electrode connected to the oxide semiconductor layer while being spaced apart from the source electrode. The oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), wherein the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25. Thus, excellent mobility and drive characteristics can be achieved.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor including an oxide semiconductor layer, a method of manufacturing the same, and a display device including the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a thin film transistor including an oxide semiconductor layer, a method of manufacturing such a thin film transistor, and a display apparatus including such a thin film transistor.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it can be used as a switching element of a display device such as a liquid crystal display device or an organic light emitting device It is widely used.

The thin film transistor includes an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and a polycrystalline silicon thin film transistor in which an oxide semiconductor is used as an active layer Oxide semiconductor thin film transistor.

In the case of an amorphous silicon thin film transistor (a-Si TFT), since amorphous silicon is deposited in a short time to form an active layer, the manufacturing process time is short and the production cost is low. On the other hand, The current driving capability is low and the threshold voltage is changed. Therefore, the organic EL device has a disadvantage that its use is limited to the active matrix organic light emitting device (AMOLED) and the like.

A polycrystalline silicon thin film transistor (poly-Si TFT) is formed by crystallizing amorphous silicon after the amorphous silicon is deposited. Since a process for crystallizing amorphous silicon is required in the process of manufacturing a polycrystalline silicon thin film transistor, the manufacturing cost is increased due to an increase in the number of processes, and a crystallization process is performed at a high process temperature. Therefore, the polycrystalline silicon thin film transistor is applied to a large- There is a difficulty in having. Further, due to the polycrystalline characteristics, it is difficult to secure the uniformity of the polycrystalline silicon thin film transistor.

In the case of an oxide semiconductor thin film transistor (TFT), since the oxide forming the active layer can be formed at a relatively low temperature, the mobility is high, and the resistance of the oxide varies with the content of oxygen, The physical properties can be easily obtained. Further, due to the nature of the oxide, the oxide semiconductor is transparent, which is also advantageous for realizing a transparent display. As a material of such an oxide semiconductor, there is zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO ₄ ) and the like.

1. [Thin Film Transistor] Korean Unexamined Patent Application Publication No. 10-2015-0027164 2. [Thin Film Transistor] Korean Unexamined Patent Application Publication No. 10-2016-0098360

One embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor layer containing tin (Sn) and having excellent mobility and reliability.

Another embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor layer formed by evaporation and heat treatment at a predetermined temperature and having a predetermined thickness, and having excellent reliability against heat and light.

Another embodiment of the present invention is to provide a method of manufacturing such a thin film transistor and a display device including such a thin film transistor.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a gate electrode disposed on a substrate; an oxide semiconductor layer insulated from the gate electrode to overlap at least a part of the gate electrode; A source electrode connected to the oxide semiconductor layer, and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer, wherein the oxide semiconductor layer is formed of a material selected from the group consisting of indium (In), gallium (Ga), zinc (In) and zinc (Zn), tin (Sn), and oxygen (O), wherein the content of indium (In) is larger than the content of gallium (Ga) Zn) is substantially the same and the ratio (Sn / In) of the tin (Sn) to the indium (In) is 0.1 to 0.25.

The oxide semiconductor layer has a thickness of 20 nm or more.

The oxide semiconductor layer has crystallinity in the C-axis direction.

The oxide semiconductor layer has a hole mobility of 18 cm ² / V · s or more.

The oxide semiconductor layer has a carrier concentration of 5 x 10 ¹⁷ / cm ³ or more.

The oxide semiconductor layer has a density of 6.5 g / cm < ³ > or more.

The oxide semiconductor layer has a spin density of 2.0 x 10 ¹⁷ spins / cm ³ or less.

The oxide semiconductor layer has a spin density of 1.5 x 10 ¹⁷ spins / cm ³ or more.

The oxide semiconductor layer has a first layer and a second layer which are sequentially stacked, and the oxygen (O) content of the second layer is larger than the oxygen (O) content of the first layer.

The second layer has a thickness of 5 to 20% of the thickness of the oxide semiconductor layer.

The second layer has an oxygen content of 1.2 to 2.5 times the first layer.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate electrode on a substrate; forming an oxide semiconductor layer insulated from the gate electrode to overlap at least a part of the gate electrode; And forming a source electrode and a drain electrode spaced apart from each other, the oxide semiconductor layer being formed of indium (In), gallium (GaIn) Wherein the indium (In) content is greater than the gallium (Ga) content, and the indium (In) And the zinc (Zn) content is substantially the same, and the ratio (Sn / In) of the tin (Sn) to the indium (In) is 0.1 to 0.25.

The oxide semiconductor layer is formed by deposition, and the deposition is performed at a temperature of 150 캜 or higher.

The oxide semiconductor layer has a thickness of 20 nm or more.

And plasma processing the oxide semiconductor layer.

N ₂ O gas is used in the plasma treatment step.

In the plasma treatment step, an energy of 2.0 to 2.5 kW / m ² is applied.

The method of fabricating the thin film transistor further includes a step of annealing the oxide semiconductor layer at a temperature of 350 ° C or higher after the step of forming the oxide semiconductor layer.

In the method of manufacturing the thin film transistor, the gate electrode, the gate insulating film, and the oxide semiconductor layer may be sequentially formed on the substrate.

In the method of manufacturing the thin film transistor, the oxide semiconductor layer, the gate insulating film, and the gate electrode may be sequentially formed on the substrate.

According to another embodiment of the present invention, there is provided a thin film transistor including a substrate, a thin film transistor disposed on the substrate, and a first electrode connected to the thin film transistor, wherein the thin film transistor includes: a gate electrode disposed on the substrate; A source electrode connected to the oxide semiconductor layer, and a source electrode connected to the oxide semiconductor layer, the source electrode connected to the source electrode, and the gate electrode, Wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O) ) Is greater than the content of gallium (Ga), the content of indium (In) and zinc (Zn) is substantially the same, and the content of indium (In) Ratio (Sn / In) of the seat (Sn) provides a range of 0.1 to 0.25, a display device.

The display device further includes an organic layer disposed on the first electrode and including an organic light emitting layer, and a second electrode disposed on the organic layer.

The display device further includes a liquid crystal layer disposed on the first electrode and a second electrode disposed on the liquid crystal layer.

A thin film transistor according to an embodiment of the present invention includes an oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), and tin (Sn) mixed at a predetermined ratio and having a predetermined thickness Therefore, it has excellent mobility and driving characteristics, and has excellent reliability against heat or light. In addition, according to an embodiment of the present invention, the oxide semiconductor layer is formed by deposition and heat treatment at a predetermined temperature, and has excellent mobility and crystallinity, and reliability is prevented from deteriorating.

The display device according to another embodiment of the present invention includes such a thin film transistor and has excellent driving characteristics.

In addition to the effects noted above, other features and advantages of the invention will be set forth hereinafter, or may be apparent to those skilled in the art to which the invention pertains from such teachings and descriptions.

1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
2 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
3 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
6 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
7A to 7F are cross-sectional views illustrating a manufacturing process of a thin film transistor according to another embodiment of the present invention.
8 is a schematic cross-sectional view of a display device according to another embodiment of the present invention.
9 is a schematic cross-sectional view of a display device according to another embodiment of the present invention.
10, 11 and 12 show the results of measuring the threshold voltage (Vth) for the thin film transistors of Comparative Examples 1, 2 and 3, respectively.
13, 14 and 15 show the results of the threshold voltage (Vth) measurement for the thin film transistors of Comparative Example 4 and Embodiments 1 and 2, respectively.
16 shows the result of measuring the spin density of the oxide semiconductor layer samples.
17 shows the results of measurement of packing density for samples of oxide semiconductor layers.
18A to 18E are transmission electron microscope (TEM) photographs of the samples of the oxide semiconductor layer, respectively.
FIG. 19 shows X-ray diffraction (XRD) analysis results for the oxide semiconductor layer.
20 and 21 are the results of measuring the threshold voltage (Vth) of the thin film transistor manufactured using the sample of the oxide semiconductor layer.
22 shows the measurement results of the hole mobility and the carrier concentration for the sample of the oxide semiconductor layer.
23 shows the results of measurement of the packing density and the spin density of the oxide semiconductor layer with respect to the sample.
FIG. 24 shows Hall mobility and threshold voltage (Vth) measurement results of the thin film transistor.
25 shows the results of PBTS and NBTIS measurements of the thin film transistor.
26, 27, 28, 29, and 30 are the results of measuring the threshold voltage (Vth) of the thin film transistor including the oxide semiconductor layer manufactured according to the composition of Table 4, respectively.
31, 32, and 33 are the results of measuring the threshold voltage (Vth) for the thin film transistors S31, S32, and S33, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. And the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited to those shown in the drawings. Like elements throughout the specification may be referred to by like reference numerals. In the following description of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

Where the terms "comprises", "having", "comprising", and the like are used herein, other portions may be added unless the expression "only" is used. Where an element is referred to in the singular, it includes the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms " first horizontal axis direction ", " second horizontal axis direction ", and " vertical axis direction " should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term " at least one " includes all possible combinations from one or more related items. For example, the meaning of " at least one of the first item, the second item and the third item " means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, a thin film transistor, a method of manufacturing the same, and a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of the drawings, the same constituent elements may have the same sign as possible even if they are displayed on different drawings

1 is a schematic cross-sectional view of a thin film transistor 100 according to an embodiment of the present invention.

The thin film transistor 100 according to an embodiment of the present invention includes a gate electrode 110 disposed on a substrate 101 and an oxide 110 which is insulated from the gate electrode 110 to overlap at least a part of the electrode of the gate electrode 110, A gate insulating layer 150 disposed between the gate electrode 110 and the oxide semiconductor layer 120, a source electrode 130 connected to the oxide semiconductor layer 120, and a source electrode 130, And a drain electrode 140 connected to the oxide semiconductor layer 120.

As the substrate 101, glass or plastic may be used. Transparent plastic having a flexible property as plastic, for example, polyimide, may be used.

When polyimide is used as the substrate 101, a heat-resistant polyimide that can withstand high temperatures can be used, considering that a high-temperature deposition process is performed on the substrate 101. In this case, in order to form a thin film transistor, a process such as vapor deposition, etching, etc. may be performed in a state where the polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

A buffer layer may be disposed on the substrate 101 (not shown). The buffer layer may be a single layer or may be formed by stacking a plurality of layers made of different materials. The buffer layer disposed on the substrate 101 is referred to as a protective film. The buffer layer may be omitted.

The gate electrode 110 is disposed on the substrate 101. The gate electrode 110 may be formed of an aluminum-based metal such as aluminum or aluminum alloy, a silver-based metal such as silver or silver alloy, a copper-based metal such as copper or copper alloy, a molybdenum (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti), for example, molybdenum series metals such as molybdenum (Mo) or molybdenum alloy. The gate electrode 110 may have a multilayer structure including at least two conductive films having different physical properties.

A gate insulating film 150 is disposed on the gate electrode 110. The gate insulating layer 150 serves as an insulating layer between the oxide semiconductor layer 120 and the gate electrode 110.

The gate insulating layer 150 may include at least one of silicon oxide and silicon nitride. The gate insulating film 150 may include aluminum oxide (Al ₂ O ₃ )

The gate insulating film 150 may have a single film structure or may have a multi-film structure. For example, the gate insulating film 150 may be formed independently of the aluminum oxide layer, the silicon oxide layer, and the silicon nitride layer, and they may be stacked to form the gate insulating film 150.

Referring to FIG. 1, the gate insulating layer 150 includes two insulating layers 151 and 152. The two insulating films 151 and 152 may be referred to as a first gate insulating film 151 and a second gate insulating film 152, respectively. However, the structure of the gate insulating layer 150 is not limited thereto, and the gate insulating layer 150 may be a single layer or a three or more layer.

According to an embodiment of the present invention, the oxide semiconductor layer 120 is disposed on the gate insulating layer 120. The oxide semiconductor layer 120 is insulated from the gate electrode 110 and at least partially overlaps with the gate electrode 110.

The oxide semiconductor layer 120 includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O). Indium (In), gallium (Ga), zinc (Zn) and tin (Sn) are metals based on 4s orbital and can have oxygen and semiconductor properties.

The oxide semiconductor layer 120 according to an embodiment of the present invention including indium (In), gallium (Ga), zinc (Zn), and tin (Sn) is also referred to as an IGZTO semiconductor layer.

According to an embodiment of the present invention, the content of indium (In) in the oxide semiconductor layer 120 is larger than the content of gallium (Ga), the content of indium (In) and the content of zinc (Zn) Do. Here, the content of each component is determined on the basis of the number of atoms and can be expressed as atom% (at%). The same is applied hereinafter.

Indium (In) may have a content of 1.5 to 5 times as much as gallium (Ga). More specifically, indium (In) may have an amount of 2 to 4 times as much as gallium (Ga).

On the atomic number basis, indium (In) and zinc (Zn) have substantially the same content. Here, " substantially the same amount " means the same amount within an error range. For example, indium (In) and zinc (Zn) may have substantially the same content within an error range of ± 10%. More specifically, indium (In) may have a content of 0.9 to 1.1 times as much as zinc (Zn).

The oxide semiconductor layer 120 according to an embodiment of the present invention includes a relatively small amount of tin (Sn). According to one embodiment of the present invention, the content ratio (Sn / In) of tin (Sn) to indium (In) is 0.1 to 0.25. On the atomic number basis, indium (In) may have an amount of 4 to 10 times the amount of tin (Sn).

For example, indium (In) is 30 to 50%, gallium (Ga) is 10 to 20%, zinc (Zn) and tin (Sn) (Zn) of 20 to 50%, and tin (Sn) of 5 to 20%.

The hole density, the carrier density, the packing density, and the NBTIS (Negative) of the oxide semiconductor layer 120, when the content ratio Sn / In of indium (In) Bias Temperature Illuminance Stress may be decreased, spin density may be increased, defects may be increased, and threshold voltage change (Vth) and positive bias temperature stress (PBTS) may be increased.

Herein, NBTIS refers to a stress due to a negative bias voltage, a constant temperature and a constant illumination condition, and generally has a negative value. When NBTIS becomes small, it corresponds to the case where the absolute value of negative (-) of NBTIS becomes large. When the NBTIS becomes small (or the NBTIS absolute value becomes large), the stress of the oxide semiconductor layer 120 or the thin film transistor 100 with respect to temperature and light increases, and the reliability can be reduced.

The PBTS is a positive (+) bias voltage and a stress under the condition that a constant temperature is applied, and generally has a positive value. When the PBTS is increased, the stress of the oxide semiconductor layer 120 or the thin film transistor 100 is increased, and the change (? Vth) of the threshold voltage can be increased.

On the other hand, even if the content ratio (Sn / In) of tin (Sn) to indium (In) exceeds 0.25, the hole mobility and carrier concentration of the oxide semiconductor layer 120 are no longer And the saturation state is maintained without the effect of increasing the tin (Sn) content. On the other hand, when the content ratio (Sn / In) of tin (Sn) to indium (In) exceeds 0.25, the density of the oxide semiconductor layer 120 is decreased, the spin density is increased and defects are increased, Stress increases in the oxide semiconductor layer 120 and the thin film transistor 100 due to increase in the absolute value of the NBTIS and increase in the PBTS and the change in the threshold voltage DELTA Vth becomes larger and the s- .

A sub-threshold swing (s-factor) is a graph of the drain current characteristics with respect to the gate voltage, which represents the reciprocal of the slope in the section operating as the switching element. When the S-factor is increased, the slope of the drain current characteristic graph with respect to the gate voltage is reduced, and the switching characteristic of the thin film transistor 100 is lowered.

The oxide semiconductor layer 120 according to an embodiment of the present invention includes 10 to 25% of tin (Sn) (0.1? Sn / In? 0.25) relative to indium (In) ) Characteristics and reliability. In addition, the thin film transistor 100 according to an embodiment of the present invention including the oxide semiconductor layer 120 has excellent mobility and threshold voltage characteristics, has low PBTS and NBTIS size (absolute value), and has excellent reliability .

According to one embodiment of the present invention, the oxide semiconductor layer 120 has a thickness of 20 nm or more. When the thickness of the oxide semiconductor layer 120 is less than 20 nm, the threshold voltage Vth increases, the PBTS increases, the NBTIS decreases, the s-factor increases, and the dispersion of the threshold voltage Vth becomes . The dispersion of the threshold voltage Vth can be evaluated at a point where the drain current is 10 < ^-9 > A, which is the degree of change in the threshold voltage Vth. If the scattering of the threshold voltage Vth is large, the uniformity of the threshold voltage Vth is lowered and the threshold voltage Vth of the thin film transistor does not have a specific value, and thus the switching characteristic of the thin film transistor 100 is lowered, .

If the thickness of the oxide semiconductor layer 120 is excessively increased, it is disadvantageous for thinning the thin film transistor 100. Therefore, the thickness of the oxide semiconductor layer 120 can be adjusted to 50 nm or less. More specifically, the thickness of the oxide semiconductor layer 120 may be adjusted to 40 nm or less, or 30 nm or less. However, the embodiment of the present invention is not limited thereto, and the thickness of the oxide semiconductor layer 120 may be varied as needed.

According to one embodiment of the present invention, the oxide semiconductor layer 120 has crystallinity in the C-axis direction. More specifically, the oxide semiconductor layer 120 according to an embodiment of the present invention may have a plurality of crystalline parts. The crystal part means a region having crystallinity. The C axis is oriented in a direction (normal line) substantially perpendicular to the surface of the oxide semiconductor layer 120. [

The crystallinity of the oxide semiconductor layer 120 can be formed by heat treatment or the like performed during the film formation of the oxide semiconductor layer 120. As described above, the thin film transistor 100 including the oxide semiconductor layer 120 having crystallinity has a small variation in characteristics due to irradiation of visible light or ultraviolet light. The crystalline oxide semiconductor layer 120 has a defect density lower than that of the microcrystalline oxide semiconductor layer and the degradation of mobility in the oxide semiconductor layer 120 is suppressed. Crystallinity can be observed by a transmission electron microscope (TEM).

When an X-ray diffraction (XRD) analysis is performed on the oxide semiconductor layer 120 according to an embodiment of the present invention, a peak appears near the diffraction angle 2? ). The peak at a diffraction angle (2?) Of 32 corresponds to the crystallinity in the C-axis direction.

According to an embodiment of the present invention, the oxide semiconductor layer 120 has a Hall mobility of 18 cm ² / V · s or more. When the oxide semiconductor layer 120 has a hole mobility of 18 cm ² / V · s or more, the thin film transistor 100 can have excellent current characteristics. According to an embodiment of the present invention, the content of indium (In), gallium (Ga), zinc (Zn), and tin (Sn) ^It is possible to have an excellent hole mobility of ² / V · s or more. More specifically, the oxide semiconductor layer 120 may have a Hall mobility of 20 cm ² / V · s or more.

Since the oxide semiconductor layer 120 according to an embodiment of the present invention has excellent hole mobility, the thin film transistor 100 can have excellent current characteristics. Accordingly, the thin film transistor 100 according to one embodiment of the present invention can be applied to a large-area display device or a high-resolution display device, so that the display device can have excellent display characteristics.

Further, the oxide semiconductor layer 120 has a carrier concentration of 5 x 10 < ¹⁷ > / cm < ³ > or more. More specifically, the oxide semiconductor layer 120 may have a carrier concentration of 5 x 10 ¹⁷ / cm ³ to 1 x 10 ¹⁹ / cm ³ . The carrier concentration can be controlled by controlling the content of indium (In), gallium (Ga), zinc (Zn) and tin (Sn), the deposition temperature and the heat treatment temperature.

The oxide semiconductor layer 120 according to an embodiment of the present invention has a packing density of 6.5 g / cm < ³ > or more. In particular, the oxide semiconductor layer 120 according to an embodiment of the present invention may have a density of 6.5 to 7.0 g / cm < ³ >. More specifically, the oxide semiconductor layer 120 may have a density ranging from 6.5 to 6.8 g / cm < ³ >.

An IGZO-based oxide semiconductor generally used as an oxide semiconductor material has a density of about 6.3 g / cm < ^{3 &} gt ;. On the other hand, the oxide semiconductor layer 120 according to an embodiment of the present invention may have a density of 6.5 g / cm ³ or more. Accordingly, the oxide semiconductor layer 120 according to an embodiment of the present invention may have crystallinity, and the thin film transistor 100 including the oxide semiconductor layer 120 may be resistant to irradiation of visible light or ultraviolet light Lt; / RTI > As a result, fluctuations in the characteristics of the thin film transistor 100 due to irradiation of visible light and ultraviolet light are reduced and reliability is improved.

The oxide semiconductor layer 120 according to an embodiment of the present invention has a spin density of 2.0 x 10 ¹⁷ spins / cm ³ or less. The spin density can be a measure for determining the defect density of the oxide semiconductor layer 120. Here, the defect density means the degree of defects of the atoms in the oxide semiconductor layer 120. More specifically, the defect density may correspond to the degree of defect of the oxygen (O) atoms. When the spin density of the oxide semiconductor layer 120 is 2.0 x 10 ¹⁷ spins / cm ³ or less, oxygen defects such as C-vacancy are prevented and the oxide semiconductor layer 120 is made conductive Is prevented.

More specifically, the oxide semiconductor layer 120 according to an embodiment of the present invention may have a spin density of 1.5 x 10 ¹⁷ spins / cm ³ or more. That is, the oxide semiconductor layer 120 may have a spin density of 1.5 x 10 ¹⁷ to 2.0 x 10 ¹⁷ spins / cm ³ .

The oxide semiconductor layer 120 according to an embodiment of the present invention having the above characteristics can form a short channel having a channel length of 4 μm or less. Here, the channel length may be defined as a distance between the source electrode 130 and the drain electrode 140. Therefore, when the oxide semiconductor layer 120 according to an embodiment of the present invention is used, the area of the thin film transistor 100 can be reduced, and a display device with an ultra-high density or an ultra-high resolution can be manufactured.

The source electrode 130 is connected to the oxide semiconductor layer 120 and the drain electrode 140 is separated from the source electrode 130 and connected to the oxide semiconductor layer 120. Referring to FIG. 1, a source electrode 130 and a drain electrode 140 are disposed on a gate insulating layer 150, and at least partially overlap with the oxide semiconductor layer 120, respectively.

The source electrode 130 and the drain electrode 140 may be formed of at least one selected from the group consisting of Mo, Al, Cr, Au, Ti, Cu), and alloys thereof. The source electrode 130 and the drain electrode 140 may be formed of a single layer made of a metal or a metal alloy, respectively, or may be formed of multiple layers of two or more layers.

As shown in FIG. 1, a structure in which the gate electrode 110 is disposed under the oxide semiconductor layer 120 is also referred to as a bottom gate structure. Here, the oxide semiconductor layer 120, the gate electrode 110, the source electrode 130, and the drain electrode 140 form the thin film transistor 100.

2 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Hereinafter, in order to avoid duplication, descriptions of the components already described are omitted.

The oxide semiconductor layer 120 according to another embodiment of the present invention has a multi-layer stacked structure. Referring to FIG. 2, the oxide semiconductor layer 120 has a first layer 121 and a second layer 122 which are sequentially stacked. The oxygen (O) content of the second layer (122) is greater than the oxygen (O) content of the first layer (121). For example, the second layer 122 may have an oxygen content of 1.2 to 2.5 times the first layer 121. Therefore, even if oxygen loss is generated in the second layer 122, the second layer 122 can maintain the three-dimensional content enough to exhibit semiconductor characteristics.

Referring to FIG. 2, an upper portion of the second layer 122 is exposed from the source electrode 130 and the drain electrode 140, and may be in contact with a further formed insulating layer or the like. At this time, oxygen loss may occur in the second layer 122. However, since oxygen (O) content in the second layer 122 is greater than oxygen (O) content in the first layer 121, even if oxygen loss occurs in the second layer 122, Can maintain excellent semiconductor characteristics.

According to another embodiment of the present invention, a channel region may be formed in the second layer 122 of the oxide semiconductor layer 120. The channel region may be formed in the first layer 121 of the oxide semiconductor layer 120.

The thickness of the second layer 122 is not particularly limited. The second layer 122 may have a thickness of 5 to 20% of the thickness of the oxide semiconductor layer 120 in consideration of characteristics of the manufacturing process and stability of the channel region. However, the thickness of the second layer 122 may be less than 5% of the thickness of the oxide semiconductor layer 120, or more than 20% of the thickness of the oxide semiconductor layer 120 It is possible.

3 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention.

The thin film transistor 300 shown in FIG. 3 includes a buffer layer 160 disposed on a substrate 101, an oxide semiconductor layer 120 disposed on the buffer layer 160, and an oxide semiconductor layer 120, A gate insulating layer 150 disposed between the gate electrode 110 and the oxide semiconductor layer 120 and an interlayer insulating layer 150 disposed on the gate electrode 110 A source electrode 130 connected to the oxide semiconductor layer 120 and a drain electrode 140 separated from the source electrode 130 and connected to the oxide semiconductor layer 120.

The buffer layer 160 may include at least one of silicon oxide and silicon nitride. The buffer layer 160 has excellent insulating properties, excellent moisture and oxygen barrier properties and planarization characteristics and protects the oxide semiconductor layer 120.

The buffer layer 160 may be formed of a single film or may have a laminated structure in which two or more films are stacked. A light blocking layer (not shown) may be disposed between the substrate 101 and the buffer layer 160 or the buffer layer 160. The light blocking layer protects the oxide semiconductor layer 120 from light

The oxide semiconductor layer 120 includes indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O). The content of indium (In) , The content of indium (In) and the content of zinc (Zn) are substantially the same and the content ratio (Sn / In) of tin (Sn) to indium (In) is 0.1 to 0.25.

A gate insulating film 150 is disposed on the oxide semiconductor layer 120 and a gate electrode 110 is disposed on the gate insulating film 150. The gate electrode 110 is insulated from the oxide semiconductor layer 120 by the gate insulating layer 150. In FIG. 3, a gate insulating film 150 made of a single layer is shown.

An interlayer insulating film 170 is disposed on the gate electrode 110. The interlayer insulating film 170 is made of an insulating material. Specifically, the interlayer insulating layer 170 may be formed of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

A source electrode 130 and a drain electrode 140 are disposed on the interlayer insulating film 170. The source electrode 130 and the drain electrode 140 are separated from each other and connected to the oxide semiconductor layer 120, respectively. Referring to FIG. 3, the source electrode 130 and the drain electrode 140 are connected to the oxide semiconductor layer 120 through a contact hole formed in the interlayer insulating layer 170, respectively.

As shown in FIG. 3, the structure in which the gate electrode 110 is disposed on the oxide semiconductor layer 120 is also referred to as a top gate structure. The oxide semiconductor layer 120, the gate electrode 110, the source electrode 130, and the drain electrode 140 form the thin film transistor 200.

4 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present invention. The thin film transistor 400 shown in FIG. 4 has an oxide semiconductor layer 120 made of a multilayer structure, as compared with the thin film transistor 300 shown in FIG.

Referring to FIG. 4, the oxide semiconductor layer 120 includes a first layer 121 and a second layer 122 which are sequentially stacked. Here, the oxygen (O) content of the second layer 122 is greater than the oxygen (O) content of the first layer 121. The upper portion of the second layer 122 is in contact with the interlayer insulating film 170. Even if oxygen loss is generated in the second layer 122 due to contact with the interlayer insulating film 170 because the second layer 122 contains a relatively large amount of oxygen O, Can maintain excellent semiconductor characteristics.

5 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present invention.

The thin film transistor 500 shown in FIG. 5 further includes an etch stopper 180 disposed on the oxide semiconductor layer 120, as compared with the thin film transistor 100 shown in FIG. The etch stopper 180 may be made of an insulating material, for example, silicon oxide. The etch stopper 180 may protect the channel region of the oxide semiconductor layer 120. As described above, the oxide semiconductor layer 120 according to an embodiment of the present invention can be applied to the thin film transistor 500 of the etch stopper structure.

6 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present invention.

The thin film transistor 500 shown in FIG. 6 further includes an etch stopper 180 disposed on the oxide semiconductor layer 120, as compared with the thin film transistor 200 shown in FIG. More specifically, the etch stopper 180 is disposed on the second layer 122 of the oxide semiconductor layer 120. The etch stopper 180 may be made of an insulating material, for example, silicon oxide, and may protect the channel region of the oxide semiconductor layer 120.

Hereinafter, a method of manufacturing the thin film transistor 200 will be described with reference to FIGS. 7A to 7F.

7A to 7F are a manufacturing process diagram of the thin film transistor 200 according to an embodiment of the present invention.

Referring to FIG. 7A, a gate electrode 110 is formed on a substrate 101.

Although not shown, a buffer layer (not shown) may be formed on the substrate 101 before the formation of the gate electrode 110, and the gate electrode 110 may be formed on the buffer layer.

Glass can be used as the substrate 101, and transparent plastic that can be bent or rolled can be used. An example of the plastic used as the substrate 101 is polyimide. When plastic is used as the substrate 101, the manufacturing process can be performed with the substrate 101 disposed on a carrier substrate made of a highly durable material.

The gate electrode 110 may be formed of an aluminum-based metal such as aluminum or aluminum alloy, a silver-based metal such as silver or silver alloy, a copper-based metal such as copper or copper alloy, a molybdenum (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti), for example, molybdenum series metals such as molybdenum (Mo) or molybdenum alloy.

Referring to FIG. 7B, a gate insulating layer 150 is formed on the gate electrode 110.

The gate insulating film 150 shown in FIG. 7B includes two insulating films 151 and 152. The two insulating films 151 and 152 may be referred to as a first gate insulating film 151 and a second gate insulating film 152, respectively. However, the structure of the gate insulating film 150 is not limited thereto, and the gate insulating film 150 may be formed of a single film or a film of three or more layers.

The gate insulating film 150 may include at least one of silicon oxide, silicon nitride, and aluminum oxide (Al ₂ O ₃ ). For example, silicon oxide, silicon nitride and aluminum oxide (Al ₂ O ₃₎ of the first gate insulating film 151 by at least one is formed, the above silicon oxide, silicon nitride and aluminum oxide (Al ₂ O ₃₎ The second gate insulating film 152 may be formed.

Referring to FIG. 7C, an oxide semiconductor layer 120 is formed on the gate insulating layer 150. The oxide semiconductor layer 120 includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O).

The oxide semiconductor layer 120 may be formed by vapor deposition. An evaporation source including indium (In), gallium (Ga), zinc (Zn), and tin (Sn) may be used for the deposition. For example, indium oxide, gallium oxide, zinc oxide and tin oxide may be used for the deposition. Alternatively, indium-zinc oxide, indium-tin oxide, indium-gallium oxide, gallium-zinc oxide and the like may be used for the deposition.

The content of indium (In) is greater than that of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content of indium (In) (Sn / In) of 0.1 to 0.25 can be made.

Deposition occurs at temperatures above 150 ° C. More specifically, the deposition may be performed at a temperature of 150 to 250 ° C. According to an embodiment of the present invention, since the oxide semiconductor layer 120 is formed by high-temperature deposition at a high temperature of 150 ° C or higher, the oxide semiconductor layer 120 has a packing density of 6.5 g / cm ³ or more And can have crystallinity in the C-axis direction and have a spin density of 2.0 x 10 ¹⁷ spins / cm ³ or less, thereby having a low defect density.

When the deposition is performed at a temperature lower than 150 캜, the oxide semiconductor layer 120 may have a packing density of less than 6.5 g / cm ³ , have no crystallinity in the C-axis direction, or have a packing density of 2.0 x 10 ¹⁷ spins / cm < ³ > and can have a high defect density. Accordingly, the PBTS characteristic and the NBTIS characteristic of the oxide semiconductor layer 120 may be degraded.

The oxide semiconductor layer 120 is formed to a thickness of 20 nm or more. When the thickness of the oxide semiconductor layer 120 is less than 20 nm, the scattering of the threshold voltage Vth, PBTS, s-factor and threshold voltage Vth may increase. The oxide semiconductor layer 120 may be formed to a thickness of 20 to 50 nm, more specifically, a thickness of 20 to 40 nm, or a thickness of 20 to 30 nm.

Referring to FIG. 7D, a source electrode 130 and a drain electrode 140 are formed on the oxide semiconductor 120. The source electrode 130 and the drain electrode 140 are separated from each other and connected to the oxide semiconductor layer 120, respectively.

Referring to FIG. 7E, the oxide semiconductor layer 120 is subjected to plasma treatment. The plasma treatment may be performed using N ₂ O gas. An energy of 2.0 to 2.5 kW / m < ² > may be applied in the plasma treatment step. More specifically, an energy of 2.0 to 2.5 kW / m ² is applied to the N ₂ O gas, and the oxide semiconductor layer 120 is subjected to plasma treatment. The thin film transistor 200 having the oxide semiconductor layer 120 plasma-treated in this way can have excellent driving characteristics even under adverse conditions such as oxygen deficiency.

When the plasma processing energy is less than 2.0 kW / m ² . The driving characteristics of the thin film transistor may be degraded under the bad conditions. On the other hand, when plasma treatment is performed at an energy exceeding 2.5 kW / m ² , the reliability of the thin film transistor may be lowered due to the rise of the PBTS.

Referring to FIG. 7F, a second layer 122 is formed on the oxide semiconductor layer 120 by plasma treatment. Specifically, oxygen is injected into the upper portion of the oxide semiconductor layer 120 by the plasma treatment, and a part of the oxide semiconductor layer 120 becomes the second layer 122. At this time, the region of the oxide semiconductor layer 120, which is not affected by the plasma treatment or becomes less, becomes the first layer 121. The first layer 121 has the same or similar composition as the oxide semiconductor layer 120 before the plasma treatment.

The second layer 122 contains a greater amount of oxygen (O) than the first layer 121. For example, the second layer 122 may have an oxygen content of 1.2 to 2.5 times the first layer 121.

The second layer 122 formed by the plasma treatment may have a thickness of 5 to 20% of the entire thickness of the oxide semiconductor layer 120.

The plasma treatment process may be omitted. When the plasma processing process is omitted, the thin film transistor 100 as shown in FIG. 1 may be formed.

Next, the oxide semiconductor layer 120 may be heat-treated. In the case where the plasma treatment for the oxide semiconductor layer 120 is not performed, a heat treatment process may be performed subsequent to the formation of the oxide semiconductor layer 120.

The heat treatment is carried out at a temperature of 350 ° C or higher. More specifically, the heat treatment can be performed at a temperature of 350 to 450 캜.

The oxide semiconductor layer 120 has a packing density of at least 6.5 g / cm ³ , a crystallinity in the C-axis direction, and a spin density of less than 2.0 x 10 ¹⁷ spins / cm ³ by heat treatment at a temperature of 350 ° C or higher. ), And can have a low defect density.

If the heat treatment temperature is lower than 350 ℃, the oxide semiconductor layer 120 is 6.5 g / cm density of less than ³ (packing density) branches, or not have the crystalline properties of the C-axis direction, ^{or, 2.0 x 10 17 spins / cm} 3 Spin density < / RTI > and can have a high defect density. Accordingly, the PBTS characteristic and the NBTIS characteristic of the oxide semiconductor layer 120 may be degraded.

If the heat treatment temperature exceeds 450 ° C, the oxide semiconductor layer 120 or the thin film transistor 200 may be damaged by heat, and excessive heat treatment may be required. For example, the heat treatment temperature may be 400 ° C.

By this heat treatment, the thin film transistor 200 shown in Fig. 2 can be completed. Although not shown, an etch stopper 180 may be formed on the oxide semiconductor layer 120 (see FIGS. 5 and 6).

7A to 7F show a manufacturing process of a thin film transistor 200 having a bottom gate structure in which a gate electrode 110, a gate insulating film 150 and an oxide semiconductor layer 120 are sequentially formed on a substrate 101, However, the manufacturing method of the thin film transistor is not limited thereto.

The oxide semiconductor layer 120, the gate insulating film 150, and the gate electrode 110 may be sequentially formed on the substrate 101. [ In this case, the thin film transistors 300 and 400 of the top gate structure as shown in FIG. 3 or 4 can be manufactured.

8 is a schematic cross-sectional view of a display device 700 according to another embodiment of the present invention.

A display device 700 according to another embodiment of the present invention includes a substrate 101, a thin film transistor 100, and an organic light emitting diode 270 connected to the thin film transistor 100.

Although the display device 700 including the thin film transistor 100 of FIG. 1 is shown in FIG. 8, in addition to the thin film transistor 100 of FIG. 1, the thin film transistors 200, 300, 400, 500, and 600 may be applied to the display device 700 of FIG.

8, a display device 700 according to another embodiment of the present invention includes a substrate 101, a thin film transistor 100 disposed on the substrate 101, a first thin film transistor 100 connected to the thin film transistor 100, And an electrode 271. The display device 700 also includes an organic layer 272 disposed on the first electrode 271 and a second electrode 273 disposed on the organic layer 272. [

Specifically, the substrate 101 may be made of glass or plastic. A buffer layer 191 is disposed on the substrate 101. The buffer layer 191 may be omitted.

The thin film transistor 100 is disposed on the buffer layer 191 on the substrate 101. The thin film transistor 100 includes a gate electrode 110 disposed on a substrate 101, an oxide semiconductor layer 120 which is insulated from the gate electrode 110 to overlap at least a part of the electrode of the gate electrode 110, A gate insulating layer 150 disposed between the gate insulating layer 110 and the oxide semiconductor layer 120, a source electrode 130 connected to the oxide semiconductor layer 120, and a source electrode 130 and is connected to the oxide semiconductor layer 120 Drain electrodes 140 are formed.

The planarizing film 190 is disposed on the thin film transistor 100 to planarize the upper portion of the substrate 101. The planarizing film 190 may be formed of an organic insulating material such as acrylic resin having photosensitivity, but is not limited thereto.

The first electrode 271 is disposed on the planarization film 190. The first electrode 271 is connected to the drain electrode 140 of the thin film transistor layer 100 through a contact hole provided in the planarization layer 190.

The bank layer 250 is disposed on the first electrode 271 and the planarizing film 190 to define a pixel region or a light emitting region. For example, the bank layer 250 can be defined by the bank layer 250 by arranging the bank layer 250 in a matrix structure in a boundary region between a plurality of pixels.

The organic layer 272 is disposed on the first electrode 271. The organic layer 272 may also be disposed on the bank layer 250. That is, the organic layer 272 may not be separated for each pixel but may be connected to each other between adjacent pixels.

The organic layer 272 includes an organic light emitting layer. The organic layer 272 may include one organic light emitting layer, and may include two organic light emitting layers stacked one above the other or an organic light emitting layer. In this organic layer 272, light having any one of red, green, and blue colors may be emitted, and white light may be emitted.

The second electrode 273 is disposed on the organic layer 272.

The first electrode 271, the organic layer 272, and the second electrode 273 may be laminated to form the organic light emitting diode 270. [ The organic light emitting diode 270 may serve as a light amount adjusting layer in the display device 700.

Although not shown, when the organic layer 272 emits white light, the individual pixels may include a color filter for filtering the white light emitted from the organic layer 272 by wavelength. A color filter is formed on the movement path of the light. A color filter is disposed below the organic layer 272 and a light emission from the organic layer 272 is emitted when the light emitted from the organic layer 272 travels toward the lower substrate 101 in a so- A color filter is disposed on the organic layer 272 in the case of the so-called top emission method in which the light is emitted toward the upper second electrode 273.

9 is a schematic cross-sectional view of a display device 800 according to another embodiment of the present invention.

9, a display device 800 according to another embodiment of the present invention includes a substrate 101, a thin film transistor 100 disposed on the substrate 101, a first thin film transistor 100 connected to the thin film transistor 100, Electrode 381 as shown in FIG. The display device 800 also includes a liquid crystal layer 382 on the first electrode 381 and a second electrode 383 on the liquid crystal layer 382.

The liquid crystal layer 382 serves as a light amount adjusting layer. Thus, the display device 800 shown in Fig. 9 is a liquid crystal display device including a liquid crystal layer 382. Fig.

9 includes a substrate 101, a thin film transistor 100, a planarization film 190, a first electrode 381, a liquid crystal layer 382, a second electrode 383, A barrier layer 320, color filters 341 and 342, a light shielding portion 350, and an opposing substrate 102.

The substrate 101 may be made of glass or plastic.

The thin film transistor 100 is disposed on the substrate 101. [

9, a buffer layer 191 is disposed on a substrate 101, a gate electrode 110 is disposed on a buffer layer 191, a first gate insulating film 151 and a second gate insulating film A gate insulating film 150 made of a second gate insulating film 152 is disposed and an oxide semiconductor layer 120 is disposed on the gate insulating film 150. A source electrode 130 and a drain An electrode 140 is disposed and a planarization film 190 is disposed on the source electrode 130 and the drain electrode 140.

A bottom gate structure thin film transistor 100 in which a gate electrode 110 is disposed under an oxide semiconductor layer 120 is shown in FIG. 9, but the present invention is not limited thereto . A thin film transistor having a top gate structure in which the gate electrode 110 is disposed on the oxide semiconductor layer 120 may be used. More specifically, in addition to the thin film transistor 100 shown in FIG. 1, the thin film transistors 200, 300, 400, 500, and 600 disclosed in FIGS. 2 to 6 may be applied to the display device 800 of FIG.

The planarizing film 190 is disposed on the thin film transistor 100 to planarize the upper portion of the substrate 101. The planarizing film 190 may be formed of an organic insulating material such as acrylic resin having photosensitivity, but is not limited thereto.

The first electrode 381 is disposed on the planarization film 190. The first electrode 381 is connected to the drain electrode 140 of the thin film transistor layer 100 through the contact hole CH provided in the planarization layer 190.

The counter substrate 102 is disposed opposite to the substrate 101. [

The light shielding portion 350 is disposed on the counter substrate 102. The light shielding portion 350 has a plurality of openings. The plurality of openings are arranged corresponding to the first electrode 381 which is a pixel electrode. The light shielding portion 350 shields light from the portions excluding the openings. The light shielding portion 350 is not necessarily required, and may be omitted.

The color filters 341 and 342 are disposed on the counter substrate 102 and selectively block the wavelength of the light incident from the backlight unit (not shown). Specifically, the color filters 341 and 342 may be disposed in a plurality of openings defined by the light shielding portion 350. [

Each of the color filters 341 and 342 can represent any one of red, green, and blue colors. Each of the color filters 341 and 342 may represent a color other than red, green, and blue.

The barrier layer 320 may be disposed on the color filters 341 and 342 and the light-shielding portion 350. The barrier layer 320 may be omitted.

The second electrode 383 is disposed on the barrier layer 320. For example, the second electrode 383 may be located on the front surface of the counter substrate 102. The second electrode 383 may be formed of a transparent conductive material such as ITO or IZO.

The first electrode 381 and the second electrode 383 are opposed to each other and a liquid crystal layer 382 is disposed therebetween. The second electrode 383 applies an electric field to the liquid crystal layer 382 together with the first electrode 381.

When the opposing surfaces between the substrate 101 and the opposing substrate 102 are defined as the upper surface of the substrate and the surfaces located on opposite sides of the upper surface are respectively defined as the lower surface of the substrate, And the polarizing plate may be disposed on the lower surface of the counter substrate 102, respectively.

Hereinafter, the present invention will be described in more detail with reference to Examples, Comparative Examples and Test Examples.

[Comparative Example 1-3]

A thin film transistor of Comparative Example 1-3 having the structure shown in Fig. 1 was fabricated.

Specifically, a 100 nm thick gate electrode 150 made of an alloy of Mo / Ti is formed on a glass substrate 101, and a first gate insulating film 151 made of silicon oxide and a silicon nitride 2 gate insulating film 152 was formed and an oxide semiconductor layer 120 having a thickness of 30 nm was formed according to the composition ratio shown in Table 1. [ Next, a source electrode 130 and a drain electrode 140 having a thickness of 100 nm were formed using a Mo / Ti alloy.

The threshold voltage (Vth), mobility (Hall Mobility) and NBTIS of the thin film transistor of Comparative Example 1-3 thus prepared were measured.

For measuring the threshold voltage (Vth), the drain current (Ids) was measured while applying a gate voltage (Vgs) in the range of -20V to + 20V. A voltage of 10 V was applied between the source electrode 130 and the drain electrode 140. 10, 11 and 12 show the results of measuring the threshold voltage (Vth) for the thin film transistors of Comparative Examples 1, 2 and 3, respectively.

Also, Hall mobility was measured according to the Hall measurement method. NBTIS was measured by applying a negative bias voltage while irradiating a thin film transistor of Comparative Examples 1, 2, and 3 at a temperature of 60 占 폚 with a visible light of 4500 nits (white light). The results are shown in Table 1 below.

Comparative Example 1 Comparative Example 2 Comparative Example 3 Oxide semiconductor
Composition ratio In: Ga: Zn
(1: 1: 1) In: Ga
(9: 1) In: Sn: Zn
(2.6: 1: 3) Hole mobility (cm ² / V · s) 10 16 19 NBTIS (V) -0.4 -12 -9

10, 11, and 12, "Initial" represents an initial current change, "Before Stress" represents a current change before temperature and light are applied, "After Stress" represents a temperature of 60 ° C. and 4500 nit (White light) of the light-receiving layer.

10, 11, 12 and Table 1, the thin film transistor of Comparative Example 1 has good NBTIS characteristics, but has poor hole mobility characteristics, and the thin film transistors of Comparative Examples 2 and 3 have poor NBTIS characteristics .

[Comparative Example 4 and Example 1-2]

In order to confirm the characteristics of the thin film transistor according to the thickness of the oxide semiconductor layer 120, a thin film transistor having the structure shown in FIG. 1 was manufactured (Comparative Example 4, Examples 1 and 2). A thin film transistor was fabricated in the same manner as the thin film transistor of Comparative Example 1 except that the composition of the oxide semiconductor layer 120 was varied. Hereinafter, unless otherwise stated, the thin film transistor has the structure of FIG. 1 and can be manufactured in the same manner as the thin film transistor of Comparative Example 1. [

Specifically, a comparison with an oxide semiconductor layer 120 in which indium (In), gallium (Ga), zinc (Zn) and tin (Sn) are mixed in a ratio of 4: 1: 4: Thin film transistors of Example 4 and Example 1-2 were fabricated. At this time, the thicknesses of the oxide semiconductor layer 120 in Comparative Example 4, Example 1, and Example 2 were set to 10 nm, 20 nm, and 30 nm, respectively.

For measuring the threshold voltage (Vth), the drain current (Ids) of the thin film transistor according to Comparative Example 4 and Example 1-2 was measured while applying a gate voltage (Vgs) in the range of -20V to + 20V. A voltage of 10 V was applied between the source electrode 130 and the drain electrode 140. The threshold voltage (Vth) was measured nine times. 13, 14 and 15 show the results of measuring the threshold voltage (Vth) for the thin film transistor of Comparative Example 4 and Embodiments 1 and 2.

For measurement of the threshold voltage (Vth) scattering, the gate voltage (Vgs) was measured at a point where the drain current (Ids) was 10 ^-9 A. That is, the difference between the maximum value and the minimum value of the gate voltage (Vgs) measured at the point where the drain current Ids is 10 ^-9 A is defined as "dispersion of the threshold voltage (Vth)". PBTS was also measured while applying a positive bias voltage to the thin film transistors of Comparative Example 4 and Example 1-2 under a temperature stress of 60 占 폚. The results are shown in Table 2.

Comparative Example 4 Example 1 Example 2 The thickness (nm) of the oxide semiconductor layer 10 20 30 The average threshold voltage (V) 3.76 1.76 1.45 The scattering of the threshold voltage (V) 3.84 1.39 0.74 PBTS (V) 4.17 2.10 1.75

13, 14, 15 and Table 2, since the thin film transistor of Comparative Example 4 has a large dispersion of the threshold voltage Vth, the uniformity of the threshold voltage Vth is low, the driving characteristics are poor, Reliability is poor.

On the other hand, the thin film transistors according to Embodiments 1 and 2 have small drift of the threshold voltage (Vth), have excellent driving characteristics, and have small reliability of PBTS.

[Evaluation of deposition temperature and heat treatment temperature]

Gallium (Ga), zinc (Zn) and tin (Sn) in a ratio of 4: 1: 4: 1 in order to confirm the characteristics of the oxide semiconductor layer 120 according to the deposition temperature and the heat treatment temperature. Atoms / cm < 2 >) to produce samples of the oxide semiconductor layer 120 having a thickness of 30 nm. S11, S12, S13, S14, S15 and S16 of the oxide semiconductor layer 120 were prepared by adjusting the deposition temperature for forming the oxide semiconductor layer 120 and the post-deposition heat treatment temperature as shown in Table 3.

S11 S12 S13 S14 S15 S16 Deposition temperature (캜) Room temperature Room temperature 100 150 200 250 Heat treatment temperature (캜) 350 400 400 400 400 400

The spin density of the samples S11, S12, S13, S14 and S15 of the oxide semiconductor layer 120 was measured and the packing density or the volume density was measured for S11, S12, S13, S14, S15 and S16 ) Were measured. 16 shows a result of measurement of the spin density for the samples of the oxide semiconductor layer 120, and FIG. 17 shows the results of measurement of the packing density of the samples of the oxide semiconductor layer 120. 16 and 17, "deposition (° C)" represents the deposition temperature, and "post-heat treatment (° C)" represents the post-deposition heat treatment temperature,

16, the spin that even if heat treatment at a temperature of 350 ℃, a sample S11 of the oxide semiconductor layer 120 is formed by vapor deposition at room temperature (30 ℃ ± 20 ℃) is greater than the 2.0 x 10 ¹⁷ spins / cm ³ Density. The spin density can be a measure for determining the defect density of the oxide semiconductor layer 120. The defect density indicates the degree of defect of an atom in the oxide semiconductor layer 120, and may correspond to a degree of defect of an oxygen (O) atom, for example. S11 with a spin density exceeding 2.0 x 10 < ¹⁷ > spins / cm < ³ > may cause conductivization due to oxygen defects.

Referring to Figure 17, it is deposited at a temperature less than 150 ℃ samples S11, S12 and S13 formed in the oxide semiconductor layer 120 has a density of less than 6.5 g / cm ^3. When the oxide semiconductor layer 120 has a density of less than 6.5 g / cm ³ , atomic defects may be induced, and conducive to the channel region of the oxide semiconductor layer 120.

On the other hand, is formed by deposition from at least 150 ℃ temperature, over 350 ℃ temperature, for example, a sample of the oxide semiconductor layer 120 is heat-treated at 400 ℃ S14, S15 and S16 is 2.0 x 10 ¹⁷ spins / cm ³ spins in the following Density and a packing density of 6.5 g / cm < ³ > or more.

18A to 18E are transmission electron microscope (TEM) photographs of the samples of the oxide semiconductor layer 120, respectively. More specifically, FIGS. 18A, 18B, 18C, 18D and 18E are transmission electron microscope (TEM) images of the samples S12, S13, S14, S15 and S16 of the oxide semiconductor layer 120, respectively. The crystallinity of the samples can be confirmed by transmission electron microscopy (TEM) photographs.

Referring to Figs. 18D and 18E, it is confirmed that the samples S15 and S16 have crystallinity in the C-axis direction. Referring to FIG. 18C, it can be seen that crystallinity begins to occur along the C-axis direction in the sample S14. That is, the oxide semiconductor layer 120 formed by being deposited at a temperature of 150 ° C or higher and heat-treated at a temperature of 350 ° C or higher (400 ° C) has crystallinity in the C axis direction. On the other hand, it can be confirmed that the samples S12 and S13 have no crystallinity in the C axis direction.

Specifically, the samples S14, S15 and S16 of the oxide semiconductor layer 120 according to an embodiment of the present invention have crystallinity in the C-axis direction. Here, the C axis is oriented in a direction (normal line) substantially perpendicular to the surface of the oxide semiconductor layer 120. The oxide semiconductor layer 120 having crystallinity has a defect density lower than that of the microcrystalline oxide semiconductor layer and the lowering of the mobility in the oxide semiconductor layer 120 is suppressed.

19 is an X-ray diffraction (XRD) analysis result of the oxide semiconductor layer 120. FIG.

More specifically, FIG. 19 shows X-ray diffraction (XRD) analysis results of the sample S15 of the oxide semiconductor layer 120. FIG. Referring to Fig. 19, a peak appears near the diffraction angle 2 &thetas; 32 DEG. The peak near the diffraction angle (2 [Theta]) 32 [deg.] Corresponds to the C-axis crystallinity. The thin film transistor 100 including the oxide semiconductor layer 120 having such crystallinity is prevented or suppressed from fluctuation in driving characteristics due to irradiation of visible light or ultraviolet light

20 and 21 are the results of measuring the threshold voltage (Vth) of the thin film transistor manufactured using the sample of the oxide semiconductor layer. 20 is a graph showing a threshold voltage (Vth) of a thin film transistor fabricated using the sample S12 of the oxide semiconductor layer 120, and FIG. 21 is a graph showing a threshold voltage (Vth) of the thin film transistor fabricated using the sample S15 of the oxide semiconductor layer 120. FIG. (Vth) of FIG.

The samples S12 and S15 of the oxide semiconductor layer 120 were used to fabricate thin film transistors having the structure of FIG. 1 by the method described in Comparative Example 1, respectively. Then, for the threshold voltage (Vth) measurement, The drain current Ids was measured while applying the gate voltage Vgs of the gate electrode. At this time, the voltage between the source electrode 130 and the drain electrode 140 was maintained at 10V. The threshold voltage (Vth) was measured nine times.

Referring to FIG. 20, a thin film transistor manufactured using the sample S12 of the oxide semiconductor layer 120 is difficult to be used as an element because the scattering of the threshold voltage (Vth) is large. On the other hand, referring to FIG. 21, it can be seen that the thin film transistor fabricated using the sample S15 of the oxide semiconductor layer 120 has good transistor characteristics.

[Characteristic evaluation of oxide semiconductor layer according to tin (Sn) content]

(In), gallium (Ga), and zinc (Zn) in a ratio of 4: 1: 4 (atomic number ratio) in order to confirm the characteristics of the oxide semiconductor layer 120 according to the content of Sn. And an oxide semiconductor layer 120 and a thin film transistor as shown in Table 4 were manufactured (S21, S22, S23, S24, and S25), and the ratio (Sn / In) of tin (Sn) to indium (In) In Table 4, the ratio (Sn / In) of tin (Sn) to indium (In) is expressed in%. The percentages expressed in% can be obtained from the following equation (1).

[Formula 1]

Sn / In ratio (%) = [(number of atoms of Sn) / (number of atoms of In)] x 100

S21 S22 S23 S24 S25 Sn / In ratio (%) 0 10.8 23.1 56.8 100 In: Ga: Zn 4: 1: 4 4: 1: 4 4: 1: 4 4: 1: 4 4: 1: 4

FIG. 22 shows the hole mobility and carrier concentration measurement results for the sample of the oxide semiconductor layer 120. Specifically, the Hall mobility and the carrier concentration of the samples S21, S22, S23, S24, and S25 of the oxide semiconductor layer 120 were measured and the results are shown in FIG.

22, when the ratio (Sn / In) of tin (Sn) to indium (In) is less than 10%, the hole mobility of the oxide semiconductor layer 120 is less than 18 cm ² / V · s, And the concentration is less than 5 x 10 ¹⁷ / cm ³ . It can also be seen that the hole mobility and carrier concentration do not further increase even when the ratio (Sn / In) of tin (Sn) to indium (In) exceeds 25%.

 23 shows the results of measurement of the packing density and the spin density of the oxide semiconductor layer 120 with respect to the sample. Specifically, the density and the spin density of the samples S21, S22, S23, S24 and S25 of the oxide semiconductor layer 120 were measured, and the results are shown in Fig.

23, in the case of the samples S22 and S23 of the oxide semiconductor layer 120 having a ratio (Sn / In) of tin (Sn) to indium (In / Sn) of 10 to 25% cm < ^{3 &} gt ;. When the ratio (Sn / In) of tin (Sn) to indium (In) is reduced to less than 10% (S21), the density and spin density of the oxide semiconductor layer 120 decrease. In addition, when the ratio (Sn / In) of tin (Sn) to indium (In) increases by more than 25% (S24 and S25), the density and spin density of the oxide semiconductor layer 120 decrease Can be confirmed.

FIG. 24 shows Hall mobility and threshold voltage (Vth) measurement results of the thin film transistor. Specifically, FIG. 24 shows Hall mobility and threshold voltage (Vth) measurement results of thin film transistors each including samples of the oxide semiconductor layer 120 manufactured according to the composition of Table 4.

Referring to FIG. 24, when the ratio (Sn / In) of tin (Sn) to indium (In) is less than 10%, the hole mobility of the oxide semiconductor layer 120 is lowered to less than 18 cm ² / V · s , The threshold voltage (Vth) rises. In addition, even if the ratio (Sn / In) of tin (Sn) to indium (In) exceeds 25%, the hole mobility does not increase, while the threshold voltage Vth decreases to a negative value .

25 shows the results of PBTS and NBTIS measurements of the thin film transistor.

Referring to FIG. 25, the PBTS of the thin film transistor including the oxide semiconductor layer in which the ratio (Sn / In) of tin (Sn) to indium (In / Sn) is less than 10% increases and the absolute value of NBTIS also increases. In addition, when the oxide semiconductor layer contains a tin (Sn) ratio (Sn / In) of more than 25% to indium (In), the PBTS of the thin film transistor increases and the absolute value of NBTIS increases again. (Sn / In) of indium (In) corresponding to S24 is 56.8%, the behavior of the NBTIS of the thin film transistor is abnormally reversed, and the measurement of NBTIS is impossible (X region).

FIGS. 26, 27, 28, 29 and 30 show threshold voltage (Vth) measurement results of the thin film transistor including the oxide semiconductor layer 120 manufactured according to the composition of Table 4, respectively.

Table 5 shows the results of measurement of threshold voltage (Vth), hole mobility, s-factor, PBTS and NBTIS of the thin film transistor including the oxide semiconductor layer 120 manufactured according to the composition of Table 4. [

S21 S22 S23 S24 S25 The threshold voltage Vth (V) 1.42 0.64 1.11 -4.01 -0.65 Hole mobility (cm ² / V · s) 16.9 18.0 21.0 21.6 23.8 s-factor 0.138 0.134 0.155 0.279 0.310 PBTS (V) 5.63 4.68 2.01 1.21 3.93 NBTIS (V) -2.81 -2.9 -1.87 Abnormal backwardness -5.12

The s-factor represents the reciprocal of the slope in the section operating as the switching element in the graph of the drain current characteristic versus the gate voltage. The S-factors measured using Figures 26, 27, 28, 29 and 30 are as described in Table 5. < tb > < TABLE > Referring to Table 5, when the ratio (Sn / In) of tin (Sn) to indium (In) exceeds 25%, it can be seen that the s-factor increases and the switching characteristics of the thin film transistor are deteriorated.

In order to test the stability improvement of the oxide semiconductor layer 120 by the plasma treatment, three thin film transistors having the oxide semiconductor layer 120 according to the composition of S23 in Table 4 are manufactured (S31, S32, S33) _The oxide semiconductor layer 120 was subjected to plasma treatment using ₂ O gas. The intensity of the plasma treatment is shown in Table 6 below. In addition, insulated in order to determine the driving characteristics of the thin film transient jitter, silicon oxide having an excessive lack of oxygen to the plasma treated oxide semiconductor layer (120), (SiO _2-x H _x, where x is 0.5 or more) under the bad condition Layer.

Then, the scattering of the threshold voltage (Vth), the hole mobility, the s-factor, the PBTS and the NBTIS were measured for the thin film transistors S31, S32 and S33.

S31 S32 S33 Plasma intensity (kW / m ² ) 1.15 2.01 2.88 (V) of the threshold voltage (Vth) 9.43 0.88 1.32 Hole mobility (cm ² / V · s) Not measurable 30.3 25.3 s-factor 1.42 0.58 0.62 PBTS (V) Not measurable 1.86 3.23 NBTIS (V) Not measurable -4.09 -4.08

FIGS. 31, 32 and 33 show the results of the threshold voltage (Vth) measurement for the thin film transistors S31, S32, and S33, respectively.

When the oxide semiconductor layer 120 is subjected to the N ₂ O plasma treatment at an energy of less than 2.0 kW / m ² , the threshold voltage of the thin film transistor The voltage scattering is increased, the s-factor is increased, the behavior of the thin film transistor is unstable, and the hole mobility, PBTS and NBTIS can not be measured.

On the other hand, when the N ₂ O plasma treatment is performed on the oxide semiconductor layer 120 at an energy of 2.0 kW / m ² or more, even if a bad silicon oxide having an excessive oxygen deficiency is formed on the oxide semiconductor layer 120, It can be confirmed that the driving characteristics are maintained well. Generally, it is known that the s-factor of a thin film transistor is lowered in N ₂ O plasma processing. However, in the case of the thin film transistor according to an embodiment of the present invention, it can be seen that the s-factor of the thin film transistor can be maintained at a satisfactory level in the N ₂ O plasma process.

However, when the N ₂ O plasma treatment is performed at an energy exceeding 2.5 kW / m ² , PBTS rises and the reliability of the thin film transistor is lowered.

Thus, the plasma processing energy can be adjusted to a range of 2.0 to 2.5 kW / m < ² >.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art. Accordingly, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalence of the claims are to be construed as being included within the scope of the present invention.

100, 200, 300, 400, 500, 600: Thin film transistor
101: substrate 102: opposing substrate
110: gate electrode 120: oxide semiconductor layer
130: source electrode 140: drain electrode
150: gate insulating film 151: first gate insulating film
152: second gate insulating film 180: etch stopper
190: planarization layer 191: buffer layer
250: bank layer 270: organic light emitting element
271, 381: first electrode 272: organic layer
273, 383: second electrode 341, 342: color filter
350: shielding part 382: liquid crystal layer
700, 800: Display device

Claims (17)

A gate electrode disposed on the substrate;
An oxide semiconductor layer which is insulated from the gate electrode and overlaps at least part of the gate electrode;
A gate insulating film disposed between the gate electrode and the oxide semiconductor layer;
A source electrode connected to the oxide semiconductor layer; And
And a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer,
Wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)
In the oxide semiconductor layer, the content of indium (In) is greater than the content of gallium (Ga)
The content of indium (In) and zinc (Zn) is substantially the same,
Wherein a ratio (Sn / In) of the tin (Sn) to the indium (In) is 0.1 to 0.25,
Thin film transistor. The method according to claim 1,
Wherein the oxide semiconductor layer has a thickness of 20 nm or more. The method according to claim 1,
Wherein the oxide semiconductor layer has a Hall mobility of 18 cm ² / V · s or more. The method according to claim 1,
Wherein the oxide semiconductor layer has a carrier concentration of 5 x 10 < ¹⁷ > / cm < ³ > or more. The method according to claim 1,
Wherein the oxide semiconductor layer has a density of 6.5 g / cm < ³ > or more. The method according to claim 1,
Wherein the oxide semiconductor layer has a spin density of 2.0 x 10 ¹⁷ spins / cm ³ or less. The method according to claim 1,
Wherein the oxide semiconductor layer has a first layer and a second layer which are sequentially stacked,
Wherein the oxygen (O) content of the second layer is greater than the oxygen (O) content of the first layer. 8. The method of claim 7,
And the second layer has a thickness of 5 to 20% of the thickness of the oxide semiconductor layer. Forming a gate electrode on the substrate;
Forming an oxide semiconductor layer that is insulated from the gate electrode and overlaps at least a part of the gate electrode;
Forming a gate insulating layer between the gate electrode and the oxide semiconductor layer; And
And forming a source electrode and a drain electrode that are connected to the oxide semiconductor layer and are spaced apart from each other,
Wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)
In the oxide semiconductor layer, the content of indium (In) is greater than the content of gallium (Ga)
The content of indium (In) and zinc (Zn) is substantially the same,
Wherein a ratio (Sn / In) of the tin (Sn) to the indium (In) is 0.1 to 0.25,
A method of manufacturing a thin film transistor. 10. The method of claim 9,
The oxide semiconductor layer is formed by vapor deposition,
The deposition may be performed at a temperature of 150 < 0 &
A method of manufacturing a thin film transistor. 10. The method of claim 9,
Wherein the oxide semiconductor layer has a thickness of 20 nm or more,
A method of manufacturing a thin film transistor. 10. The method of claim 9,
Further comprising plasma processing the oxide semiconductor layer.
A method of manufacturing a thin film transistor. 13. The method of claim 12,
In the plasma treatment step, an energy of 2.0 to 2.5 kW / m < ² >
A method of manufacturing a thin film transistor. 10. The method of claim 9,
Further comprising the step of heat-treating the oxide semiconductor layer at a temperature of 350 DEG C or higher after the step of forming the oxide semiconductor layer. 10. The method of claim 9,
Wherein the gate electrode, the gate insulating film, and the oxide semiconductor layer are sequentially formed on the substrate,
A method of manufacturing a thin film transistor. 10. The method of claim 9,
Wherein the oxide semiconductor layer, the gate insulating film, and the gate electrode are sequentially formed on the substrate,
A method of manufacturing a thin film transistor. Board;
A thin film transistor disposed on the substrate; And
And a first electrode connected to the thin film transistor,
The thin-
A gate electrode disposed on the substrate;
An oxide semiconductor layer which is insulated from the gate electrode and overlaps at least part of the gate electrode;
A gate insulating film disposed between the gate electrode and the oxide semiconductor layer;
A source electrode connected to the oxide semiconductor layer; And
And a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer,
Wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)
In the oxide semiconductor layer, the content of indium (In) is greater than the content of gallium (Ga)
The content of indium (In) and zinc (Zn) is substantially the same,
Wherein a ratio (Sn / In) of the tin (Sn) to the indium (In) is 0.1 to 0.25,
Display device.

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