KR20190041640A - Method of manufacturing a printed circuit board - Google Patents

Method of manufacturing a printed circuit board Download PDF

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KR20190041640A
KR20190041640A KR1020170133109A KR20170133109A KR20190041640A KR 20190041640 A KR20190041640 A KR 20190041640A KR 1020170133109 A KR1020170133109 A KR 1020170133109A KR 20170133109 A KR20170133109 A KR 20170133109A KR 20190041640 A KR20190041640 A KR 20190041640A
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South Korea
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filling
via hole
hole
present
dfsr
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KR1020170133109A
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Korean (ko)
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한병훈
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대덕전자 주식회사
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An objective of the present invention is to provide a new process of improving work efficiency in filling a via hole of a circuit wiring board with a filling material. To this end, the present invention provides a method for using a dry film type solder resist (DFSR) as a filling material for filling a via hole on a circuit wiring board, and for pushing the DFSR into a hole by performing a process of pressing at high temperatures and high pressure through vacuum lamination.

Description

회로배선판 제조방법{METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD}[0001] METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD [0002]

본 발명은 회로배선판 또는 인쇄회로기판을 제조하는 방법에 관한 것으로서, 특히 비아홀(via hole)을 충진 물질로 충진하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board or a printed circuit board, and more particularly, to a method of filling a via hole with a filling material.

회로기판의 다층화 함에 따라 각층에 제작된 동박 회로를 층간 회로접속을 위한 비아 홀(via hole)을 신뢰성 있게 제작하는 중요하다. 층간 회로 접속을 위한 비아 홀로서, 기판을 상하로 완전히 관통하는 관통홀(PTH; punch through hole; 도1a 참조), 특정 층까지만을 층간 접속하는 뎁스 홀(depth hole; 반관통홀; 도1b 참조), 국부적으로 연결하는 레이저 드릴 홀(laser drill hole; 도1c 참조) 등이 필요하다.It is important to reliably manufacture a via hole for interlayer circuit connection of the copper foil circuit fabricated in each layer according to the multilayering of the circuit board. A through hole (PTH) completely penetrating the substrate up and down (see FIG. 1A); a depth hole (a half through hole; see FIG. ), A laser drill hole (see FIG. 1C) that connects locally, and the like are required.

층간 회로접속을 위한 비아홀을 제작하는 종래기술은 다음과 같다. 기판에 층간접속이 필요한 부위에 대해 드릴 공정을 실시해서 홀을 제작한 후, 동도금을 실시해서 표면에 동(Cu)을 피복하는 캡(cap) 도금 공정을 진행한다. A conventional technique for fabricating a via hole for interlayer circuit connection is as follows. A hole is formed by performing a drilling process on a portion of the substrate where interlayer connection is required, and then a copper plating process is performed to coat copper on the surface by performing copper plating.

기판 전면에 테이프를 밀착하고 잉크 충진이 필요한 부위에 대해서만 레이저 드릴을 진행해서 테이프를 선택적으로 개구(open)한다. 이어서, 진공 홀 프러깅(hole plugging) 공정을 진행함으로써 동으로 내벽이 도금된 비아홀의 내부 공간을 잉크로 충진한다. 최종적으로 베이킹 과정을 통해 초기에 액상상태에 있던 유동성 잉크를 경화시키고, 표면에 돌출된 부분을 연마하여 평탄화 한다. The tape is tightly adhered to the entire surface of the substrate, and the tape is selectively opened by advancing the laser drill only to the portion where ink filling is required. Subsequently, a hole plugging process is performed to fill the inner space of the copper-plated inner wall with ink. Finally, the liquid ink that has been initially in the liquid state is cured by the baking process, and the projected portion is polished and planarized.

그러나 위 비아 홀 충진을 위한 잉크 인쇄 공정(당업계에서는 통상 '진공 아나우메' 공정이라 칭한다)에 있어서, 특히 뎁스 홀 또는 레이저 비아와 같이 양단이 모두 개구되지 않은 홀의 경우에는 홀 속에 에어(기포)가 발생하게 되어 진공이 잘 잡히지 않으므로, 스크린 인쇄 시에 충진성이 저하되어 작업시간 오래 걸리는 문제가 발생한다. However, in the ink printing process for filling a wi-ba hole (generally referred to as a vacuum anuma process in the related art), in the case of a hole in which both ends are not all opened, such as a depth hole or a laser via, And thus the vacuum is not easily caught. Therefore, the filling property is reduced during the screen printing, which causes a problem that the operation takes a long time.

그 결과 잉크를 충진하는 작업시간이 길어져서 생산성이 떨어지는(리드타임 4 ~ 5배 이상 증가) 문제가 발생하며, 결국 기술적으로는 홀 내부에 잔존하는 공기/기포 등의 영향으로 페이스트가 완전히 충진되지 못해 보이드(void) 불량이 발생하는 기술적 문제가 있다. As a result, there is a problem that the time for filling the ink is prolonged and the productivity is decreased (lead time is increased by 4 to 5 times or more). As a result, technically, the paste is not completely filled due to the air / There is a technical problem that void defects can occur.

1. 대한민국 특허공개 제10-2005-0112364호.1. Korean Patent Publication No. 10-2005-0112364. 2. 대한민국 특허공개 제10-2007-0076871호.2. Korean Patent Publication No. 10-2007-0076871. 3. 대한민국 특허공개 제10-2015-0052496호.3. Korean Patent Publication No. 10-2015-0052496.

본 발명의 제1 목적은 회로배선판의 비아 홀을 충진 물질로 충진하는데 있어서 작업효율을 개선하는 새로운 공법을 제공하는 데 있다.SUMMARY OF THE INVENTION A first object of the present invention is to provide a new method of improving work efficiency in filling a via hole of a circuit board with a filling material.

본 발명의 제2 목적은 회로배선판의 비아 홀을 충진 물질로 충진하는데 있어서 기포로 인하여 보이드가 형성되는 기술적 한계를 극복한 새로운 공법을 제공하는 데 있다.A second object of the present invention is to provide a new method overcoming the technical limitations of forming voids due to bubbles in filling a via hole of a circuit board with a filling material.

상기 목적을 달성하기 위하여, 본 발명은 충진 물질로서 DFSR(dry film type solder resist)을 사용하고, 진공 라미네이션(vacuum lamination)을 통해 고온 고압으로 프레스(press)하는 공정을 진행해서 홀 속으로 DFSR을 밀어 넣는 방식을 제안한다. 여기서 DFSR은 필름 형태로 만든 솔더레지스트(SR; solder resist)이다.In order to accomplish the above object, the present invention provides a method of forming a DFSR (DFSR) film using a dry film type solder resist (DFSR) as a filling material and pressing the film at a high temperature and a high pressure through vacuum lamination We suggest a push method. Here, DFSR is a solder resist (SR) made in film form.

본 발명은 회로배선판의 비아홀을 충진 물질로 충진하는 방법에 있어서, (a) 비아홀을 드릴하는 단계; (b) 캡도금을 진행해서 비아홀 내벽을 동(Cu)으로 피복하는 단계; (c) 테이프를 밀착하고 충진이 필요한 부위를 레이저로 드릴하여 개구하는 단계; (d) 상기 충진 물질로서 DFSR을 진공 밀착하는 단계; (e) 프레스 공정을 진행해서 상기 단계 (c)에서 개구한 개구부 속으로 상기 DFSR을 밀어 넣어 비아홀을 충진하는 단계; 및 (f) 상기 테이프를 제거하고 베이킹 및 연마를 진행하는 단계를 포함하는 회로배선판 제조방법을 제공한다. A method of filling a via hole of a circuit board with a filling material, the method comprising the steps of: (a) drilling a via hole; (b) coating the inner wall of the via hole with copper by proceeding with cap plating; (c) opening the tape by tightly pressing the portion where the filling is required with a laser; (d) vacuum-adhering the DFSR as the filling material; (e) pressing the DFSR into the opening portion opened in the step (c) through the pressing step to fill the via hole; And (f) removing the tape and advancing baking and polishing.

본 발명은 반 관통홀(depth hole) 또는 레이저 비아홀과 일반 PTH 관통홀이 혼합된 제품의 경우에도 홀 내부의 기포를 진공으로 제거하는데 시간이 소요하지 않으므로 작업시간을 4 ~ 5 배 이상 현저하게 줄일 수 있어 생산성이 탁월하다. In the case of a product in which a depth hole or a laser via hole and a general PTH through hole are mixed, it is not necessary to vacuum the bubbles in the hole, so that the working time is significantly reduced by 4 to 5 times or more The productivity is excellent.

또한, 본 발명은 액상의 잉크를 진공 플러깅하는 프로세스를 대신해서 드라이필름 타입의 솔더레지스트를 고온 고압으로 프레스하는 공정이므로 비아 홀 내부에 보이드가 발생하는 것을 방지할 수 있다. Further, the present invention is a process for pressing a dry film type solder resist at a high temperature and a high pressure in place of the process of vacuum plugging a liquid ink, so voids can be prevented from being generated in the via hole.

도1a 내지 도1c는 각각 일반 관통홀, 뎁스 홀, 레이저 비아 홀을 나타낸 도면.
도2는 본 발명에 따른 비아홀 충진 프로세스를 나타낸 일처리 흐름도.
도3은 종래기술과 본 발명을 양산에 적용한 경우 작업효율을 비교하여 나타낸 도표.
1A to 1C are diagrams showing a general through hole, a depth hole, and a laser via hole, respectively.
FIG. 2 is a work process flowchart showing a via hole filling process according to the present invention. FIG.
Fig. 3 is a diagram showing a comparison between the prior art and the working efficiency when the present invention is applied to mass production. Fig.

본 발명은 비아 홀 충진 물질로서 종래에 사용하던 잉크 대신에 드라이필름 타입의 솔더 레지스트, 즉 DFSR을 사용하는 것을 특징으로 한다. 본 발명은 액상의 잉크 대신에 상온에서 고체상태인 DFSR을 충진물질로 사용하기 위해서, 충진을 할 부위를 개구한 후 DFSR을 밀착해서 고온 고압 프레스 방식으로 진공 라미네이션을 진행함을 특징으로 한다. The present invention is characterized in that a dry film type solder resist, that is, a DFSR is used instead of the ink used conventionally as a via hole filling material. In order to use the DFSR as a filling material in a solid state at room temperature instead of the liquid ink, the DFSR is closely contacted after opening the region to be filled, and vacuum laminating is performed by a high-temperature high-pressure pressing method.

이하, 첨부도면 도2를 참조하여 본 발명에 따른 비아홀 충진 방법을 상세히 설명한다.Hereinafter, a method for filling a via hole according to the present invention will be described in detail with reference to FIG.

도2를 참조하면, 우선 비아홀을 제작할 부위를 드릴 한다(단계 S100). 본 발명의 양호한 실시예로서, 일반 관통홀(PTH), 반 관통홀(depth hole), 레이저 비아 홀 등을 모두 동시에 드릴 작업을 통해 제작하는 것이 바람직하다. Referring to FIG. 2, first, a portion to be a via hole is drilled (Step S100). As a preferred embodiment of the present invention, it is preferable that the general through hole (PTH), the depth hole, the laser via hole, and the like are all simultaneously formed by drilling.

이어서 캡 도금을 실시한다(단계 S110). 본 발명의 양호한 실시예로서, 동(Cu) 도금을 실시함으로써 홀 내벽 및 표면에 동(Cu)으로 캡을 형성한다. 이어서 기판 전면에 걸쳐 테이프를 밀착한다(단계 S120). 본 발명의 양호한 실시예로서, 테이프는 PET 필름이 사용될 수 있다. Followed by cap plating (step S110). As a preferred embodiment of the present invention, copper (Cu) plating is performed to form a cap on the inner wall and the surface of the hole with copper (Cu). Subsequently, the tape is closely contacted over the entire surface of the substrate (step S120). As a preferred embodiment of the present invention, a PET film may be used as the tape.

그리고 나면, 충진을 위한 캡 드릴만을 개구(open) 한다(단계 S130). 본 발명의 양호한 실시예로서, 레이저 드릴 공법을 적용하여 개구할 수 있다. 즉, 아나우메가 필요한 홀만을 레이저로 오프닝한다.Then, only the cap drill for filling is opened (step S130). As a preferred embodiment of the present invention, it is possible to open by applying a laser drilling method. That is, only the holes required for the anema are opened by the laser.

테이프가 부착된 상태로 DFSR을 기판 표면에 밀착하고 진공 라미네이션(vacuum lamination)을 진행한다(단계 S140). 본 발명의 양호한 실시예로서, 70℃ 에서 0.45 MPa의 압력으로 약30초 동안 진공 라미네이션을 진행할 수 있다.The DFSR is brought into close contact with the substrate surface with the tape attached thereto, and vacuum lamination is performed (step S140). As a preferred embodiment of the present invention, vacuum lamination can be carried out at 70 DEG C and a pressure of 0.45 MPa for about 30 seconds.

이어서 고온 고압으로 프레스(press) 공정을 진행해서 DFSR을 개구부를 통해 홀 속으로 밀어 넣는다(단계 S150). 본 발명의 양호한 실시예로서, 70℃ 에서 8 Kgf의 압력으로 약30초 동안 프레스 공정을 진행할 수 있다. 이어서 테이프를 제거한 후, 본 발명은 추가의 클리닝 작업 없이 베이킹, 연마 등 후속 공정을 진행한다(단계 S160). Then, a press process is performed at a high temperature and a high pressure to push the DFSR into the hole through the opening (step S150). As a preferred embodiment of the present invention, the pressing process can be carried out at a pressure of 8 Kgf at 70 DEG C for about 30 seconds. Subsequently, after removing the tape, the present invention carries out a subsequent process such as baking and polishing without further cleaning (step S160).

전술한 내용은 후술할 발명의 특허청구범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허청구범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. The inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

도3은 종래기술과 본 발명을 양산에 적용한 경우 작업효율을 비교하여 나타낸 도표이다. 도3을 참조하면, 종래기술이 4대의 진공 인쇄 설비가 필요한 반면에, 본 발명은 1대의 진공 열가압 설비로 족하다. 또한, 택트 타임이 약 4배 이상 빨라지므로 월생산량을 비교할 때에 생산성이 비약적으로 개선된다. FIG. 3 is a chart showing a comparison of the work efficiency when the prior art and the present invention are applied to mass production. Referring to FIG. 3, while the prior art requires four vacuum printing facilities, the present invention suffices as a single vacuum heat press facility. In addition, since the tact time is about four times faster, the productivity is remarkably improved when the monthly production amount is compared.

Claims (1)

회로배선판의 비아홀을 충진 물질로 충진하는 방법에 있어서,
(a) 비아홀을 드릴하는 단계;
(b) 캡도금을 진행해서 비아홀 내벽을 동(Cu)으로 피복하는 단계;
(c) 테이프를 밀착하고 충진이 필요한 부위를 레이저로 드릴하여 개구하는 단계;
(d) 상기 충진 물질로서 DFSR을 진공 밀착하는 단계;
(e) 프레스 공정을 진행해서 상기 단계 (c)에서 개구한 개구부 속으로 상기 DFSR을 밀어 넣어 비아홀을 충진하는 단계; 및
(f) 상기 테이프를 제거하고 베이킹 및 연마를 진행하는 단계
를 포함하는 회로배선판 제조방법.
A method for filling a via hole of a circuit board with a filling material,
(a) drilling a via hole;
(b) coating the inner wall of the via hole with copper by proceeding with cap plating;
(c) opening the tape by tightly pressing the portion where the filling is required with a laser;
(d) vacuum-adhering the DFSR as the filling material;
(e) pressing the DFSR into the opening portion opened in the step (c) through the pressing step to fill the via hole; And
(f) removing the tape and proceeding to baking and polishing
Wherein the method comprises the steps of:
KR1020170133109A 2017-10-13 2017-10-13 Method of manufacturing a printed circuit board KR20190041640A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117395884A (en) * 2023-10-18 2024-01-12 江苏博敏电子有限公司 Manufacturing process for improving flatness of solder mask layer of carrier plate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050112364A (en) 2004-05-25 2005-11-30 대덕전자 주식회사 Manufacturing a build-up printed circuit board
KR20070076871A (en) 2006-01-20 2007-07-25 삼성전기주식회사 Plugging method of via hole in pcb
KR20150052496A (en) 2013-11-06 2015-05-14 대덕지디에스 주식회사 Method for forming via fill of circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050112364A (en) 2004-05-25 2005-11-30 대덕전자 주식회사 Manufacturing a build-up printed circuit board
KR20070076871A (en) 2006-01-20 2007-07-25 삼성전기주식회사 Plugging method of via hole in pcb
KR20150052496A (en) 2013-11-06 2015-05-14 대덕지디에스 주식회사 Method for forming via fill of circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117395884A (en) * 2023-10-18 2024-01-12 江苏博敏电子有限公司 Manufacturing process for improving flatness of solder mask layer of carrier plate

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