KR20190018302A - Communication method and display device using the same - Google Patents

Abstract

The present invention relates to a communication method capable of minimizing a time delay in a manufacturing process due to a communication error by varying a frequency of a clock according to a communication environment, and a display device using the same. According to one embodiment of the present invention, the display device comprises: an interface board including a first LVDS transmission/reception module; a control board including a second LVDS transmission/reception module; and a cable connected to a connector of the interface board and a connector of the control board. The first LVDS transmission/reception module establishes a window by performing link-training the clock with the second LVDS transmission/reception module, increases a frequency of the clock when a timing margin of the clock is larger than a first threshold based on the window, and transmits data to the second LVDS transmission/reception module according to the frequency of the clock.

Description

TECHNICAL FIELD [0001] The present invention relates to a communication method and a display device using the same,

The present invention relates to a communication method and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used. Of these, the organic light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed.

The organic light emitting display includes a display panel including pixels formed at intersections of data lines, scan lines, data lines and scan lines, a scan driver for supplying scan signals to the scan lines, A timing controller for controlling the operation timings of the scan driver and the data driver, and a power supplier for supplying driving voltages to the pixels, the scan driver, the data driver, and the timing controller. Each of the pixels includes an organic light emitting diode, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, A scan transistor for supplying a voltage to the gate electrode of the driving transistor, and a storage capacitor for holding the voltage of the gate electrode of the driving transistor for a predetermined period.

The threshold voltage of the driving transistor may vary from pixel to pixel due to a process variation during manufacture of the organic light emitting display device or deterioration of the driving transistor due to long term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode should be the same. However, even if the same data voltage is applied to the pixels due to the difference in threshold voltage of the driving transistor between the pixels, The current supplied may vary from pixel to pixel. Also, the organic light emitting diode may be deteriorated due to long-term driving. In this case, the brightness of the organic light emitting diode may vary from pixel to pixel. Accordingly, even if the same data voltage is applied to the pixels, the luminance at which the organic light emitting diode emits light may vary from pixel to pixel. In order to solve this problem, a compensation method for compensating a threshold voltage and an electron mobility of a driving transistor has been proposed.

The threshold voltage and electron mobility of the driving transistor can be compensated by the external compensation method. In the external compensation method, a predetermined data voltage is supplied to a pixel, a source voltage of the driving transistor is sensed through a predetermined sensing line according to a predetermined data voltage, and a sensed voltage is detected using an analog digital converter Converts the digital data into digital data insensitive data, calculates compensation data based on the sensing data, and compensates digital image data to be supplied to the pixel according to the compensation data.

In the case of compensating the threshold voltage and the electron mobility of the driving transistor by an external compensation method, the compensation data is calculated by controlling the timing controller of the organic light emitting display device using a computer before shipment of the product, . Specifically, the organic light emitting diode display and the computer are connected through the interface board. Then, a timing controller of the organic light emitting display is controlled using a computer to transmit the sensing data of the organic light emitting display to the computer. Then, the compensation data calculated from the computer is transmitted to the OLED display and stored in the memory of the control board. The control board is a circuit board on which the timing controller and memory are mounted.

The interface board and the control board communicate with a low voltage differential signal interface (hereinafter referred to as "LVDS ") interface. In this case, the interface board and the control board communicate using a clock having a fixed frequency.

The interface board and the control board set the skew range through link training before sending and receiving data. However, even if the skew range is set through link training, the communication environment between the interface board and the control board may vary depending on various factors, so that data may be out of the skew range, resulting in a communication error. If a communication error occurs, it will try again from the link training, which may lead to a delay in the manufacturing process.

Disclosure of Invention Technical Problem [6] The present invention provides a communication method capable of minimizing a time delay in a manufacturing process due to a communication error by varying the frequency of a clock according to a communication environment, and a display device using the same.

According to another aspect of the present invention, there is provided a communication method including linking a clock to set a window, determining whether a timing margin of the clock is greater than a first threshold based on a window, And increasing the frequency of the clock if it is greater than the value.

A display device according to an embodiment of the present invention includes an interface board including a first LVDS transceiver module, a control board including a second LVDS transceiver module, and a cable connected to a connector of the interface board and a connector of the control board . The first LVDS transceiving module establishes a window by link-training the clock with the second LVDS transceiving module and increases the frequency of the clock when the timing margin of the clock is larger than the first threshold based on the window, And transmits the data to the second LVDS transmitting / receiving module.

In an embodiment of the present invention, an interface board can be used to connect a control board of a display module to a computer. As a result, embodiments of the present invention can transmit the sensing data of the display module to the computer by controlling the timing controller of the display module by using a computer before shipment of the product, The compensation data for compensating the threshold voltage and the electron mobility of the transistor may be calculated and then the compensation data may be transferred to the display module and stored in the memory of the control board.

In the embodiment of the present invention, the first LVDS transceiver module exchanges data with the second LVDS transceiver module and performs link training to set a window corresponding to the skew range, and determines a timing margin of the clock based on the window Adjust the frequency of the clock, and transmit the data according to the frequency of the adjusted clock. As a result, since the frequency of the clock can be varied according to the communication environment, the embodiment of the present invention can minimize the time delay in the manufacturing process due to the communication error.

1 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.
2 is a detailed block diagram illustrating a first LVDS transceiver module of the interface board and a second LVDS transceiver module of the control board of FIG.
3 is a flowchart illustrating a communication method according to an embodiment of the present invention.
4A and 4B are waveform diagrams showing examples of clock and data transmission according to the communication method of FIG.
5 is a perspective view showing a display device according to an embodiment of the present invention.
6 is a block diagram schematically illustrating the display module of FIG.
7 is a circuit diagram of the pixel of Fig.

Like reference numerals throughout the specification denote substantially identical components. In the following description, detailed descriptions of configurations and functions known in the technical field of the present invention and those not related to the core configuration of the present invention can be omitted. The meaning of the terms described herein should be understood as follows.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display module 100 and an interface board 300.

In the embodiment of the present invention, the display module 100 is an organic light emitting display. The display module 100 may include a display panel 110, a display panel driver 120, and a control board 160.

The display panel 110 includes data lines, scan lines, and pixels formed in intersecting areas of the data lines and the scan lines. Each of the pixels receives the data voltage DV from the data line when the gate signal GS is applied from the scan line and emits light at a predetermined brightness according to the data voltage. Thus, the display panel 100 can display an image using pixels.

The display panel driver 120 receives data (DATA), a scan control signal (GCS), and a data control signal (DCS) from the timing controller (130). The display panel driving unit 120 generates driving signals for driving the display panel 100 according to the scan control signal GCS and the data control signal DCS and supplies driving signals to the display panel 100. [ That is, the display panel driver 120 generates the scan signals GS according to the scan control signal GCS and supplies the scan signals GS to the scan lines of the display panel 100, and supplies the data voltages DV And supplies the generated data to the data lines of the display panel 100.

In addition, the display panel driver 120 may sense the source voltages of the driving transistors of the pixels of the display panel 100, that is, the sensing voltages SV through the reference voltage line. The display panel driver 120 converts the sensing voltages SV into digital video data sensing data SD and transmits the sensing data SD to the timing controller 130.

The control board 160 includes a timing controller 130 and a second LVDS transceiver module 170. The timing controller 130 and the second LVDS transceiver module 170 may be implemented as an integrated circuit and mounted on the control board 160, respectively. Alternatively, the timing controller 130 and the second LVDS transceiving module 170 may be integrated into one integrated circuit and mounted on the control board 160.

The second LVDS transceiver module 170 communicates with the first LVDS transceiver module 310 of the interface board 300 through a low voltage differential signal (LVDS) interface. The second LVDS transceiver module 170 includes a second LVDS transmitter for transmitting sensing data SD as a low voltage differential signal to the first LVDS transceiver module 310 of the interface board 300 and a second LVDS transceiver for the first LVDS And a second LVDS receiving unit for receiving data (DATA) from the transmission / reception module 310 as a low voltage differential signal. The second LVDS transceiver module 170 can receive timing signals along with the data DATA from the first LVDS transceiver module 310 of the interface board 300. [ The second LVDS transmission / reception module 170 transmits data (DATA) and timing signals to the timing controller 130. The timing signals may include a vertical sync signal, a horizontal sync signal, and a data enable signal.

The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on the timing signals when the data DATA is video data and outputs the data DATA, And supplies the data control signal DCS to the display panel driver 120. [ The timing controller 130 stores the data DATA in an electrically erasable programmable read-only memory of the control board 160 if the data DATA is compensation data.

The interface board 300 includes a first LVDS transmission / reception module 310 and an Ethernet transmission / reception module 320. The first LVDS transceiver module 310 and the Ethernet transceiver module 320 may be implemented as an integrated circuit and mounted on the interface board 300, respectively. Alternatively, the first LVDS transmission / reception module 310 and the Ethernet transmission / reception module 320 may be integrated into one integrated circuit and mounted on the interface board 300.

The first LVDS transceiver module 310 communicates with the second LVDS transceiver module 170 of the control board 160 via the LVDS interface. The first LVDS transmission / reception module 310 includes a first LVDS transmission unit that transmits data (DATA) transmitted from the Ethernet transmission / reception module 320 as a low-voltage differential signal to the second LVDS transmission / reception module 170 of the control board 160, And a first LVDS receiver for receiving the sensing data SD from the second LVDS transceiver module 170 of the board 160 as a low voltage differential signal. The first LVDS transceiver module 310 may transmit timing signals along with the data DATA to the second LVDS transceiver module 170 of the control board 160. [

The interface board 300 can communicate with the computer via an ethernet interface. The Ethernet transmission / reception module 320 includes an Ethernet transmission unit for transmitting sensing data SD transmitted from the first LVDS transmission / reception module 310 to a computer via an Ethernet interface, and an Ethernet transmission unit for transmitting data (DATA) And an Ethernet receiving unit for transmitting the data to the transmission / reception module 310. [

The control board 160 and the interface board 300 may be connected through the first cable 400 as shown in FIG. 5, and the interface board 300 and the computer may be connected through the second cable. The interface board 310 and the control board 160 may be referred to as a first interface board and the control board 160 may be a display board And may be referred to as a second interface board.

1, the embodiment of the present invention can connect the control board 160 of the display module 100 and a computer using the interface board 300. [ As a result, the embodiment of the present invention can transmit the sensing data (SD) of the display module 100 to the computer by controlling the timing controller 130 of the display module 100 using a computer before shipping the product, The compensation data for compensating the threshold voltage and the electron mobility of the driving transistors of the pixels P of the display module 100 are calculated according to the sensing data SD and the compensation data is transmitted to the display module 100 May be stored in the memory of the control board 160. [

2 is a detailed block diagram illustrating a first LVDS transceiver module of the interface board and a second LVDS transceiver module of the control board of FIG.

2, the first LVDS transceiver module 310 includes an LVDS controller 311, a clock generator 312, a multiplexer 313, a first LVDS transceiver 314, a clock delay 315, And a first clock recovery unit 316.

The LVDS control unit 311 receives the recovery clock signal RC1 and the recovery data RD from the first LVDS transceiver unit 314 and receives the first threshold TH1 and the second threshold TH1 from the nonvolatile memory of the interface board 300, The threshold value TH2 can be input.

The LVDS controller 311 outputs the frequency control signal FCS to the clock generator 312 and controls the clock delay of the clock delay 315 to control the frequency of the clock generated by the clock generator 312 And outputs the delay signal DS to the clock delay unit 315 for control. The LVDS control unit 311 outputs the test data TD to the multiplexer 315 for link training and outputs the multiplex control signal MCS for controlling the output of the multiplexer 315 to the multiplexer 315 .

The clock generating unit 312 generates a reference clock signal RC according to the frequency control signal FCS of the LVDS controller 311 and outputs the generated reference clock signal to the first LVDS transceiver 314. The reference clock RC is a clock signal for synchronization of the serial data SD transmitted by the first LVDS transceiver 314.

The multiplexer 313 selects either the test data TD from the LVDS control unit 311 and the data DATA from the Ethernet transmission / reception module 320 in accordance with the mux control signal MCS from the LVDS control unit 311 And outputs it to the first LVDS transceiver 314.

The first LVDS transceiver 314 includes a transmitter TX1 for converting the parallel data input from the multiplexer 313 into serial data and outputting the serial data in synchronization with the reference clock RC from the clock generator 312 at a high speed, A receiver RX1 for converting the feedback serial data FD from the second LVDS transceiver 172 to the parallel data recovery data RD using the recovery clock RC1 from the one clock recovery unit 136 . The receiver RX1 of the first LVDS transceiver 314 outputs the recovery clock RC1 and the recovery data RD to the LVDS controller 311. [

The clock delay unit 315 delays the reference clock RC by a predetermined period according to the delay signal DS of the LVDS control unit 311 and outputs the delayed clock.

The first clock recovery unit 316 restores the feedback clock FC from the second LVDS transceiver unit 172 to the recovery clock RC1 and outputs it to the first LVDS transceiver unit 314. [ The first clock recovery unit 316 outputs the locked signal Locked to the first LVDS transceiver unit 313 when the feedback clock FC is not distorted, that is, when the frequency of the feedback clock FC is constant and the pulse width is constant. ).

A PLL (Phase Locked Loop) circuit may be used as the first clock recovery unit 316. In this case, the PLL circuit may include a phase detector, a voltage controlled oscillator (VCO), and a loop filter. Alternatively, a CDR (Clock Data Recovery) circuit may be used as the first clock recovery unit 316. In this case, the second LVDS transceiver unit 172 can transmit the serial data SD and the reference clock RC at one time through the embedded clock line.

The second LVDS transceiver module 170 may include a second clock recovery unit 171 and a second LVDS transceiver unit 172.

The second clock recovery unit 171 restores the reference clock RC from the clock delay unit 315 to the recovery clock RC2 and outputs it to the second LVDS transceiver unit 172. [ The second clock recovery unit 171 outputs the locked signal Locked to the second LVDS transceiver unit 172 when the reference clock signal RC is not distorted, that is, when the frequency of the reference clock signal RC is constant and the pulse width is constant. ).

As the second clock recovery unit 171, a PLL circuit may be used, in which case the PLL circuit may include a phase detector, a voltage controlled oscillator, and a loop filter. In this case, the first LVDS transceiver unit 314 transmits the serial data SD and the reference clock RC at one time through the embedded clock line. Alternatively, the first LVDS transceiver unit 314 may transmit the serial data SD and the reference clock RC can do.

The second LVDS transceiver unit 172 includes a receiving unit for converting the serial data SD from the first LVDS transceiver unit 314 into parallel data using the recovery clock RC2 from the second clock recovery unit 171 And a transmission unit TX2 that converts the parallel data from the receiving unit RX2 and the receiving unit RX2 into the feedback serial data FD and outputs the same at a high speed in synchronization with the feedback clock FC corresponding to the recovery clock RC2 .

3 is a flowchart illustrating a method of communicating a first LVDS transceiver module and a second LVDS transceiver module according to an embodiment of the present invention.

Hereinafter, a communication method of the first LVDS transmitting / receiving module 310 and the second LVDS transmitting / receiving module 170 according to an embodiment of the present invention will be described in detail with reference to FIG. 2 and FIG.

First, the first LVDS transceiver module 310 transmits and receives data to and from the second LVDS transceiver module 170 and performs link training to set a window corresponding to a skew range. The first LVDS transceiving module 310 sequentially delays the clock and performs link training to set the window.

The LVDS controller 311 outputs a frequency control signal FCS to the clock generator 312 so as to generate a clock at a predetermined frequency during link training.

The LVDS control section 311 outputs the mux control signal MCS so that the multiplexer 313 outputs the test data TD during the link training. For example, when the multiplexer 313 outputs the test data TD when the mux control signal MCS of the first logic voltage is input and the mux control signal MCS of the second logic voltage is input, And can output the data (DATA) from the unit (320). In this case, the LVDS control section 311 may output the mux control signal MCS of the first logic voltage during link training.

The LVDS control unit 311 determines whether the test data TD and the recovery data RD match during link training. The LVDS control unit 311 outputs the delay signal DS so that the clock delay unit 315 further delays the reference clock RC when the test data TD and the recovery data RD coincide with each other. That is, the LVDS control unit 311 increases the delay signal value of the delay signal DS until the test data TD and the recovery data RD do not coincide with each other during the link training, thereby delaying the clock.

For example, when the delay signal DS is a 5-bit signal, it may have a delay signal value corresponding to 0 to 31. In this case, the clock delay unit 315 may delay the clock in 32 steps according to the delay signal DS, and the higher the delay signal value, the further delay the reference clock RC. That is, if the test data TD and the recovery data RD coincide with each other when the delay signal DS having the delay signal value corresponding to 4 is output, the LVDS control unit 311 has the delay signal value corresponding to 5 And outputs the delay signal DS to the clock delay unit 315.

If the test data TD and the recovery data RD do not match during the link training, the LVDS control unit 311 sets the previous delay signal value to the window. For example, when the test data (TD) and the recovery data (RD) do not coincide with each other when the delay signal (DS) having the delay signal value corresponding to 5 is outputted, the LVDS control section (311) The value 4 can be set. (S101 in Fig. 3)

Second, the LVDS controller 311 determines whether the timing margin of the clock is equal to or greater than the first threshold value TH1 based on the window.

The LVDS control unit 311 calculates the delay signal value from the recovery clock RC. The LVDS control unit 311 determines whether the difference between the delay signal value of the recovery clock signal RC and the window is equal to or greater than the first threshold TH1. The difference between the delay signal value of the recovery clock RC and the window can be defined as the timing margin of the clock. (S102 in Fig. 3)

Third, the LVDS controller 311 determines whether the frequency of the current clock is the A frequency when the timing margin of the clock is greater than the first threshold TH1. The A frequency may be the maximum value of the frequency of the clock, and may be, for example, 100 MHz.

The LVDS controller 311 can determine that the timing margin of the clock is large when the difference between the delay signal value of the recovery clock signal RC and the window is larger than the first threshold value TH1, The communication error does not occur. However, if the frequency of the current clock is the maximum value, the LVDS controller 311 can not increase the frequency of the clock. Accordingly, the LVDS controller 311 determines whether the frequency of the current clock is the maximum value by determining whether the frequency of the current clock is the A frequency.

If the difference between the delay signal value of the recovery clock signal RC and the window is larger than the first threshold TH1 and the frequency of the current clock is not the A frequency, the LVDS controller 311 sets the frequency of the clock to a predetermined value, It can be increased by 10 MHz as shown in FIG. 4A. In FIG. 4A, the frequency of the current clock is 80 MHz and the frequency of the adjusted clock is 90 MHz.

If the timing margin of the clock is greater than the first threshold TH1, the LVDS controller 311 maintains the current clock frequency as it is if the frequency of the current clock is correct. (S103 and S104 in Fig. 3)

Fourth, the LVDS control unit 311 determines whether the timing margin of the clock is less than the second threshold value TH2 when the timing margin is less than or equal to the first threshold value TH1. (S105 in Fig. 3)

Fifth, when the timing margin of the clock is smaller than the second threshold value TH2, the LVDS controller 311 determines whether the frequency of the current clock is the B frequency. The B frequency may be the minimum value of the frequency of the clock and may be, for example, 40 MHz.

The LVDS controller 311 can determine that the timing margin of the clock is small when the difference between the delay signal value of the recovery clock signal RC and the window is smaller than the second threshold value TH2, The communication error can be minimized. However, if the frequency of the current clock is the minimum value, the LVDS controller 311 can not lower the frequency of the clock. Therefore, the LVDS controller 311 determines whether the frequency of the current clock is the minimum value by determining whether the frequency of the current clock is the B frequency.

If the difference between the delay signal value of the recovery clock signal RC and the window is smaller than the second threshold TH2 and the frequency of the current clock is not the B frequency, the LVDS controller 311 sets the frequency of the clock to a predetermined value, And can be lowered by 10 MHz as shown in FIG. 4B. In FIG. 4B, the frequency of the current clock is 80 MHz and the frequency of the adjusted clock is 70 MHz.

Further, if the timing margin of the clock is smaller than the second threshold value TH2, the LVDS control unit 311 maintains the current clock frequency as it is if the frequency of the current clock is correct. Further, when the timing margin of the clock is equal to or greater than the second threshold value TH2, the LVDS control unit 311 maintains the frequency of the current clock as it is. (S106 and S107 in Fig. 3)

Sixth, the first LVDS transmitting / receiving module 310 transmits data (DATA) to the second LVDS transmitting / receiving module 320 according to the frequency of the predetermined clock.

The LVDS controller 311 generates a frequency control signal FCS so that the clock generator 312 generates a clock according to a predetermined clock frequency and outputs the frequency control signal FCS to the clock generator 312. The LVDS control unit 311 generates a delay signal DS so that the reference clock RC from the first LVDS transceiver unit 314 is not delayed and outputs the delayed signal DS to the clock delay unit 315. The LVDS control unit 311 also outputs the mux control signal MCS so that the multiplexer 313 outputs the data DATA from the Ethernet transceiver 320. [ For example, the LVDS control unit 311 may output the mux control signal MCS of the second logic voltage.

2 and 3, according to an exemplary embodiment of the present invention, the first LVDS transceiver module 310 transmits and receives clocks and data to and from the second LVDS transceiver module 170 and performs link training to generate a skew ), Determines the timing margin of the clock based on the window, adjusts the frequency of the clock, and transmits the data according to the frequency of the adjusted clock. As a result, since the frequency of the clock can be varied according to the communication environment, the embodiment of the present invention can minimize the time delay in the manufacturing process due to the communication error.

5 is a perspective view showing a display device according to an embodiment of the present invention.

Referring to FIG. 5, a display device according to an exemplary embodiment of the present invention includes a display module 100, an interface board 300, a first cable 200, and a second cable 210.

5, the display module 100 includes a display panel 110, source driver ICs 121 corresponding to the display panel driver 120, flexible films 122, a timing controller 130, a source circuit board 140, a flexible cable 150, and a control board 160.

The display panel 110 may include a lower substrate 111 and an upper substrate 112. The lower substrate 111 may be formed of glass or plastic, and the upper substrate 112 may be formed of a plastic film, a sealing film, or a barrier film.

The display panel driver 120 may include a gate driver and source driver ICs 121 corresponding to the data driver. Each of the source drive ICs 121 may be bonded to the flexible film 122. Each of the flexible films 122 may be attached to the lower substrate 111 of the display panel 110 and the source circuit board 140.

The source circuit boards 140 may be connected to the control board 160 via a flexible cable 150. Connectors 151 may be provided on each of the source circuit boards 140 and the control board 160 to be connected through the flexible cable 150.

The control board 160 may be provided with a timing controller 130, connectors 151, a first connector 161, a second connector 162, a second LVDS transceiver module 170, and a power supply unit. The timing controller 130, the second LVDS transceiver module 170, and the power supply unit may be implemented as an integrated circuit, respectively. Alternatively, the timing controller 130 and the second LVDS transceiving module 170 may be integrated into one integrated circuit and mounted on the control board 160. The power supply unit generates driving voltages for driving the timing controller 130 and the source drive ICs 121 and generates high and low potential voltages for driving the organic light emitting diodes of the pixels of the display panel 110 .

The third connector 301, the fourth connector 302, the first LVDS transceiver module 310, and the Ethernet transceiver module 320 may be mounted on the interface board 300. The first LVDS transceiver module 310 and the Ethernet transceiver module 320 may be implemented as an integrated circuit and mounted on the interface board 300, respectively. Alternatively, the first LVDS transmission / reception module 310 and the Ethernet transmission / reception module 320 may be integrated into one integrated circuit and mounted on the interface board 300.

Each of the first LVDS transmission / reception module 310 and the second LVDS transmission / reception module 170 may be referred to as a Serdes IC. A serializer / deserializer is a communication that converts parallel data into serial data and transmits it to a fixed lane. Specifically, a serializer is used to convert parallel data to serial data, and a deserializer is used to convert serial data to parallel data. A deserializer is a term that refers to both a serializer and a serializer .

The first cable 200 connects the first connector 161 of the control board 160 and the third connector 301 of the interface board 300. One end of the second cable 210 is connected to the second connector 162 of the control board 160 and the other end is connected to an external graphic source device such as a set top box, And the like. The fourth connector 302 of the interface board 300 may be connected to the computer via a cable.

6 is a block diagram schematically illustrating the display module of FIG.

Hereinafter, the configurations of the display module will be described in detail with reference to FIG. In the embodiment of the present invention, the display module 100 is an organic light emitting display.

Referring to FIG. 6, the display panel 110 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area where pixels P are formed to display an image. In the display panel 110, the data lines D1 to Dm, m are positive integers of 2 or more, reference voltage lines R1 to Rp, p is a positive integer of 2 or more, scan lines S1 to Sn, n Is a positive integer of 2 or more), and the sensing signal lines SE1 to SEn are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may intersect the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the pixels P includes one of the data lines D1 to Dm, one of the reference voltage lines R1 to Rp, one of the scan lines S1 to Sn, and one of the sensing signal lines SE1 to SEn, respectively. Each of the pixels P of the display panel 110 may include an organic light emitting diode (OLED) as shown in FIG. 7 and a plurality of transistors for supplying current to the organic light emitting diode OLED. A detailed description of each of the pixels P in the display area will be described later with reference to FIG.

The display panel driving unit 120 may include a gate driving unit 170 and a data driving unit 121D as shown in FIG.

The data driver 121D may include a plurality of source drive ICs 121 as shown in FIG. Each of the source drive ICs 121 may include a data voltage supply unit and a sensing unit.

A data voltage supply is connected to the data lines to supply the data voltages. The data voltage supply unit receives the digital video data (DATA) and the data control signal (DCS) from the timing controller 130. The data voltage supply unit converts the digital video data (DATA) into data voltages according to the data control signal (DCS) and supplies the data voltages to the data lines.

The sensing unit supplies a reference voltage to the reference voltage lines R1 to Rz, senses the source voltages of the driving transistors of the pixels P through the reference voltage lines R1 to Rz, And outputs the sensing data to the timing controller 130.

The scan driver 180 includes a scan signal output unit 181 and a sensing signal output unit 182.

The scan signal output unit 181 supplies scan signals to the scan lines S1 to Sn in accordance with a scan control signal GCS input from the timing controller 130. [ The sensing signal output unit 182 supplies sensing signals to the sensing signal lines SE1 to SEn according to a scan control signal GCS input from the timing controller 130. [

The scan signal output unit 181 and the sensing signal output unit 182 may include a plurality of transistors and may be formed directly in the non-display area NDA of the display panel 110 using a gate driver in panel (GIP) method. Alternatively, the scan signal output unit 181 and the sensing signal output unit 182 may be mounted on a flexible film (not shown) formed in the form of a driving chip and connected to the display panel 110.

The timing controller 130 receives video data (DATA) and timing signals from the interface board 300. The timing controller 130 generates a scan control signal GCS and a data control signal DCS based on the timing signals when the data DATA is video data and outputs the data DATA, And supplies the data control signal DCS to the display panel driver 120. [ The timing controller 130 stores the data DATA in the nonvolatile memory of the control board 160 if the data DATA is compensation data.

7 is a circuit diagram of the pixel of Fig.

Referring to FIG. 7, the pixel P may include an organic light emitting diode OLED, a driving transistor DT, first and second switching transistors ST1 and ST2, and a storage capacitor Cst.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT and the cathode electrode may be connected to a second power supply line VSL to which a second power supply lower than the first power supply is supplied.

The driving transistor DT adjusts the current flowing from the first power supply line EVL to the organic light emitting diode OLED in accordance with the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first switching transistor ST1. The source electrode of the driving transistor DT is connected to the anode electrode of the organic light emitting diode OLED. The drain electrode of the driving transistor DT is connected to the first power line EVL. Lt; / RTI >

The first switching transistor ST1 is turned on by the kth scan signal of the kth scan line Sk to connect the jth data line Dj to the gate electrode of the driving transistor DT. The first electrode of the first switching transistor T1 is connected to the kth scan line Sk and the first electrode of the first switching transistor T1 is connected to the gate electrode of the first driving transistor DT1. .

The second switching transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SEk to connect the u th reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST3 is connected to the kth sensing signal line SEk and the first electrode thereof is connected to the u th reference voltage line Ru and the second electrode is connected to the source of the driving transistor DT Can be connected to the electrode.

It should be noted that the first electrode of each of the first and second switching transistors ST1 and ST2 may be a source electrode and the second electrode may be a drain electrode. That is, the first electrode of each of the first and second switching transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a thin film transistor. Although the driving transistor DT and the first and second switching transistors ST1 and ST2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in FIG. 7, shall. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a P-type MOSFET.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

100: display module 110: display panel
120: Display panel drive unit 121D:
121: Source drive IC 122: Flexible film
130: timing controller 140: source circuit board
150: flexible cable 160: control board
170: first LVDS transceiver module 180: scan driver
181: scan signal output unit 182: sensing signal output unit
200: first cable 210: second cable
300: interface board 310: second LVDS transmitting / receiving module
320: Ethernet transmit / receive module

Claims (11)

Link training a clock to set a window;
Determining whether a timing margin of the clock is greater than a first threshold based on the window; And
And increasing the frequency of the clock if the timing margin of the clock is greater than the first threshold value. The method according to claim 1,
The step of increasing the frequency of the clock includes:
Increasing the frequency of the clock if the frequency of the clock is not the A frequency; And
And maintaining the frequency of the clock as it is when the frequency of the clock is the A frequency. The method according to claim 1,
Determining whether a timing margin of the clock is less than a second threshold value when the timing margin of the clock is less than or equal to the first threshold value; And
And if the timing margin of the clock is equal to or greater than the second threshold value, maintaining the frequency of the clock as it is. The method of claim 3,
And lowering the frequency of the clock when the timing margin of the clock is less than the second threshold. 5. The method of claim 4,
The step of lowering the frequency of the clock comprises:
Lowering the frequency of the clock if the frequency of the clock is not a lower frequency than the A frequency; And
And maintaining the frequency of the clock as it is when the frequency of the clock is the B frequency. 6. The method according to claim 2 or 5,
And transmitting data according to the frequency of the clock. An interface board including a first LVDS transceiver module;
A control board including a second LVDS transceiver module; And
And a cable connected to the connector of the interface board and the connector of the control board,
Wherein the first LVDS transceiver module links and clocks the second LVDS transceiver module with a window to set a window and increases the frequency of the clock when the timing margin of the clock is greater than a first threshold based on the window, And transmits the data to the second LVDS transceiving module according to the frequency of the clock. 8. The method of claim 7,
Wherein the first LVDS transceiving module comprises:
Wherein the controller increases the frequency of the clock when the frequency of the clock is not the A frequency and maintains the frequency of the clock when the frequency of the clock is the A frequency. 8. The method of claim 7,
Wherein the first LVDS transceiving module comprises:
And maintains the frequency of the clock when the timing margin of the clock is equal to or lower than the first threshold value and equal to or higher than the second threshold value. 10. The method of claim 9,
Wherein the first LVDS transceiving module comprises:
And decreases the frequency of the clock when the timing margin of the clock is smaller than the second threshold value. 11. The method of claim 10,
Wherein the first LVDS transceiving module comprises:
Wherein the control unit lowers the frequency of the clock when the frequency of the clock is not lower than the B frequency lower than the A frequency and maintains the frequency of the clock when the frequency of the clock is the B frequency.

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