KR20190005721A - Method for evaluating wafer and method for manufacturing epitaxial wafer - Google Patents

Abstract

Provided is a method for evaluating whether the unevenness of a back surface of a wafer, which is caused by an epitaxial reaction or an etching reaction on a wafer surface, is attributable to a deposition reaction or an etching reaction. The method comprises: a step (S1) of preparing an SOI wafer; a step (S2) of measuring the thickness of an SOI layer of the SOI wafer; steps (S3, S4) of vertically inverting the SOI wafer so that the SOI layer faces a susceptor side, placing the wafer on the susceptor, and performing an epitaxial reaction or an etching reaction; steps (S5, S6) of vertically inverting the SOI wafer after the reaction so that the SOI layer faces upward, and measuring the thickness of the SOI layer; and a step (S7) of obtaining an in-plane distribution of the deposition reaction and the etching reaction on the back surface of the wafer by obtaining the difference in the thickness of the SOI layer before and after the reaction. In addition, process conditions for epitaxial growth that make the in-plane distribution uniform are obtained based on the obtained in-plane distribution, and the epitaxial growth is performed on a product substrate based on the process conditions.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer evaluation method and an epitaxial wafer manufacturing method,

The present invention relates to a method for evaluating a reaction on the back surface of a wafer caused by a deposition reaction (deposition of a deposition) on a wafer surface placed on a susceptor or an etching reaction, and a method for producing an epitaxial wafer .

With the high integration of semiconductor devices, the quality required for a wafer to be a raw material is further increased. In the case of epitaxial wafers, in addition to the planarization of the film thickness distribution of the epitaxial layer vapor-grown on the surface, the smoothness of the irregularities of the back surface (wafer surface opposite to the side on which the epitaxial layer is formed) It is one.

Since a large amount of raw material is not normally supplied to the back surface of the wafer, a large reaction such as that occurring on the surface does not occur, but the depressurization reaction and the etching reaction coexist slightly, and irregularities correlated with the design of the susceptor are generated. The degree of this irregularity changes depending on the conditions of the reaction or the design of the susceptor. As a method of evaluating the unevenness, it is possible to visually and numerically confirm the nano topology analysis function of the flatness tester such as WaferSight2 (KLA-Tencor).

In addition, Patent Document 1 below discloses a method for evaluating a change in shape of a wafer end portion before and after epitaxial growth.

Japanese Patent Laid-Open Publication No. 2015-126010

However, since the information obtained from the nanotopology of WaferSight2 corresponds to the amount of displacement of height, there is a problem that it is not distinguished whether it is caused by the deposition reaction or the etching reaction even if irregularities exist.

SUMMARY OF THE INVENTION The present invention has been made in view of the problems described above, and it is an object of the present invention to provide a method and apparatus for evaluating whether a back surface of a wafer (surface on a susceptor side of a wafer) caused by an epitaxial reaction or an etching reaction is caused by a deposition reaction and an etching reaction And an object of the present invention is to provide a wafer evaluation method and a manufacturing method of an epitaxial wafer wherein the back surface of the wafer is planarized.

In order to achieve the above object, in a wafer evaluation method of the present invention,

A preparation step of preparing a wafer having a known thickness on the surface thereof in advance and having a plurality of layers stacked thereon including the known thickness,

A reaction step of depositing a film on the surface of the wafer opposite to the base layer in a state in which the wafer is placed on the susceptor so that the thickness of the base layer faces the susceptor,

A measuring step of measuring the thickness of the thicknessed layer after the reaction step;

An evaluation step of evaluating a change in the thickness of the layer of the known thickness before and after the reaction step

And FIG.

According to the present invention, it is possible to know whether or not the thickness of the known layer after the reaction step becomes larger or smaller than the thickness of the known layer after the reaction step, and the unevenness of the back surface of the wafer, And the etching reaction can be evaluated.

Also, in the comparison step, the thickness of the thicknessed layer is compared before and after the reaction process over the entire surface of the thicknessed layer. As a result, it is possible to evaluate how the deposition portion and the etching portion are distributed on the entire surface of the back surface of the wafer. Further, in the present invention, the base substrate in a wafer on which another layer is formed on the base substrate is also included in the concept of " layer ".

Further, the wafer is an SOI (Silicon On Insulator) wafer in which an oxide film and a silicon layer are formed in this order on a silicon substrate, and the thickness of the base layer is the silicon layer.

The method for producing an epitaxial wafer according to the present invention is a method for producing an epitaxial wafer which is obtained by the wafer evaluation method of the present invention and which has an in-plane distribution of the thickness variation amount of the thickness of the known layer before and after the reaction step, And epitaxial growth is performed on the product substrate based on the process conditions.

This makes it possible to obtain an epitaxial wafer in which the in-plane distribution of the amount of the deposition or the amount of etching in the back surface of the wafer is made uniform, that is, the epitaxial wafer in which the back surface of the wafer is planarized.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a view showing a schematic configuration of an epitaxial growth apparatus. FIG.
Fig. 2 is a flowchart showing a procedure for obtaining the in-plane distribution of the substrate reaction and the etching reaction on the back surface of the wafer.
3 is a view showing the state of the SOI wafer in each step in the measurement of the in-plane distribution of the etching reaction and the desorption reaction on the back surface of the wafer.
Fig. 4 is a diagram showing the in-plane distribution of the reaction of the wafer back surface and the etching reaction when the power ratio of the vertical ramp is changed. Fig.
Fig. 5 is a diagram showing the in-plane distribution of the substrate reaction on the back surface of the wafer when the etching reaction is performed on the surface of the SOI wafer.
Fig. 6 is a view showing the in-plane distribution of the etching reaction on the back surface of the wafer in the same wafer as Fig.

(Mode for carrying out the invention)

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the epitaxial growth apparatus will be described with reference to FIG. The epitaxial growth apparatus 1 shown in Fig. 1 is a device for vapor-growing a silicon epitaxial layer on the surface of one wafer W.

The epitaxial growth apparatus 1 includes a reaction furnace 2 composed of a transparent quartz member or the like. In the reaction furnace 2, a susceptor 3 for placing a wafer W to be epitaxially grown thereon is disposed. The susceptor 3 is made of, for example, SiC or a SiC coating is applied to the graphite substrate. The susceptor 3 is formed in a disc shape, and the upper surface and the lower surface are horizontally arranged. A concave portion 31 is formed on the upper surface of the susceptor 3 and the wafer W is placed on the concave portion 31. Further, as shown in Fig. 3 (c), the bottom surface of the concave portion 31 is formed in a deeper shape in the central portion than in the outer peripheral portion. The outer peripheral portion of the wafer W is supported on the outer peripheral portion of the bottom surface of the concave portion 31 and the central portion of the wafer W is not in contact with the bottom surface of the recess 31. [ That is, a space is formed between the wafer W and the bottom surface of the concave portion 31. The shape of the recess 31 is not limited to the shape shown in Fig. 3 (c), and the recess 31 may be formed so that the entire surface of the back surface of the wafer W comes into contact with the bottom surface of the recess 31 You can.

A hole (not shown) penetrating to the back surface of the susceptor 3 may be formed on the bottom surface of the concave portion 31 in some cases. This through hole is an insertion hole of a lift pin for supporting the back surface of the wafer W at the front end to raise and lower the wafer W when the wafer W is put in and taken out from the recess 31, for example.

The back surface of the susceptor 3 is supported by a support shaft 8. The support shaft 8 is installed such that its axial line L1 crosses the center of the susceptor 3. The support shaft (8) is connected to a driving unit (not shown) for rotating the support shaft (8). The susceptor 3 and the wafer W mounted on the susceptor 3 rotate about the axis L1 of the support shaft 8 by the rotation of the support shaft 8 by the driving unit.

Lamps 6 and 7 for heating the wafer W to an epitaxial growth temperature (for example, 900 to 1200 占 폚) at the time of epitaxial growth are disposed above and below the reaction furnace 2. The powers of the upper lamp 6 and the lower lamp 7 are individually controllable. In other words, the power ratio between the upper lamp 6 and the lower lamp 7 can be changed.

A gas supply port 4 is provided at one end in the horizontal direction of the reaction furnace 2 and a gas discharge port 5 is provided at a side opposite to the side where the gas supply port 4 is installed. The gas supply port (4) is formed above the susceptor (3). From the gas supply port 4, a silicon source gas (specifically, a silicon-based gas such as trichlorosilane (TCS)) to be a raw material of the silicon single crystal thin film (silicon epitaxial layer) A reaction gas containing a carrier gas (for example, hydrogen) and a dopant gas (for example, boron or phosphorus-containing gas) for adjusting the conductivity type and conductivity of the epitaxial layer is introduced. The reaction gas supplied from the gas supply port 4 flows along the surface of the wafer W which is kept substantially horizontally rotated in the inner space of the reaction furnace 2. [ Thereafter, the reaction gas is discharged from the gas outlet 5. That is, the reaction gas flows from the gas supply port 4 toward the gas discharge port 5 substantially horizontally and one way.

This completes the construction of the epitaxial growth apparatus 1. Here, when performing the deposition reaction (epitaxial reaction) or the etching reaction based on the reaction gas on the wafer W, the reaction gas is supplied to the gap between the wafer W and the recess 31 or the gap between the wafer W and the recess 31 Through the through hole formed in the bottom surface, to the back surface of the wafer W, and the back surface of the wafer W is also slightly subjected to a deposition reaction or an etching reaction. These deformation reactions and etching reactions cause irregularities on the back surface of the wafer that are correlated with the reaction conditions and the design of the susceptor 3. It is considered that knowing whether the irregularities are attributable to the depression reaction or the etching reaction is an important factor for optimizing the reaction conditions and clues to the optimization of the design of the susceptor 3.

Thus, in the present embodiment, it is evaluated according to the procedure of Figs. 2 and 3 whether the unevenness of the back surface of the wafer is due to the deposition reaction or the etching reaction. Hereinafter, the procedure of Figs. 2 and 3 will be described.

First, an SOI wafer is prepared (S1). Fig. 3 (a) shows a cross-sectional view of the SOI wafer 10 prepared in S1. The SOI wafer 10 has a structure in which a silicon oxide film 12 is formed on a base substrate 11 (hereinafter referred to as a silicon substrate) constituted as a layer of silicon single crystal and a silicon single crystal layer And the SOI layer 13 is formed. The thickness of the SOI layer 13 is preferably set to a value larger than the etching amount performed on the SOI layer 13 in the step of S4 described later and is set to be, for example, 40 nm or more .

The SOI wafer 10 is obtained by forming an oxide film on one side of two silicon single crystal substrates, joining the silicon single crystal substrate with the formed oxide film interposed therebetween, and then thinning one silicon single crystal substrate to obtain an SOI layer Loses.

Next, the thickness of the SOI layer 13 is measured (S2). This thickness can be measured by any method. For example, the thickness of the SOI layer 13 may be measured by an optical interferometer measuring the thickness of the thin film of the object to be measured and interference from surface reflected light and back surface reflected light, . The thickness may be measured over the entire surface of the SOI layer 13. If the thickness distribution of the SOI layer 13 is uniform, the thickness is measured only for a part of the thickness, and the thickness of the entirety of the SOI layer 13 . The steps S1 and S2 correspond to the preparing step of the present invention. Further, the SOI layer 13 corresponds to the thickness base layer of the present invention.

Next, as shown in Fig. 3 (b), the SOI wafer 10 is turned upside down (S3) so that the SOI layer 13 faces downward and the silicon substrate 11 faces upward.

The SOI wafer 10 is placed in the reaction furnace 2 shown in Fig. 1 and placed on the susceptor 3 and the SOI wafer 10 is subjected to a predetermined epitaxial reaction recipe or an etching reaction recipe A reaction (a depo reaction or an etching reaction) is performed (S4). 3 (c), the SOI wafer 10 is mounted on the susceptor 3 so that the SOI layer 13 is opposed to the bottom surface of the concave portion 31 of the susceptor 3 do. Then, the surface of the silicon substrate 11 is heated to a predetermined temperature by the upper and lower lamps 6 and 7, and a gas is supplied to the surface of the silicon substrate 11 so as to perform a desorption reaction or an etching reaction. Concretely, in the case of performing the depo reaction, a silicon source gas such as trichlorosilane or dichlorosilane is supplied to the surface of the silicon substrate 11, for example. On the other hand, when the etching reaction is performed, hydrogen chloride (HCl) gas is supplied to the surface of the silicon substrate 11, for example.

At this time, a part of the gas supplied to the surface of the silicon substrate 11 flows to the surface side of the SOI layer 13 to cause a slight depression reaction or an etching reaction to the surface of the SOI layer 13. For example, when trichlorosilane (SiHCl ₃ ) is supplied to the surface of the silicon substrate 11 together with the carrier gas H ₂ , Si and HCl generated by the reaction of SiHCl ₃ + H ₂ → Si + The SOI layer 13 is caused to coexist with both the deposition reaction and the etching reaction. The distribution of the sites where the depression reaction or the etching reaction occurs in the SOI layer 13 depends on the reaction conditions (gas type, flow rate, temperature, etc.) and the design of the susceptor 3 (depth of the recess 31) Respectively. Since the oxide film 12 and the silicon substrate 11 are laminated on the surface of the SOI layer 13 on the side opposite to the surface on the susceptor 3 side, a deposition reaction or an etching reaction I never do that. The steps S3 and S4 correspond to the reaction step of the present invention.

3 (d), the SOI wafer 10 after the reaction is vertically inverted (S5) such that the SOI layer 13 faces upward and the silicon substrate 11 faces downward.

Next, as shown in Fig. 3 (e), the thickness of the SOI layer 13 in the SOI wafer 10 after the reaction is measured (S6). This thickness may be measured by any method. For example, the thickness of the SOI layer 13 is measured by an optical interference meter. The range of the surface of the SOI layer 13 over which the thickness is to be measured is determined depending on the range of the surface of the SOI layer 13 and the distribution of the desorption reaction and the etching reaction. For example, when it is desired to obtain the distribution of the deposition reaction and the etching reaction over the entire surface of the SOI layer 13, the thickness is measured over the entire surface of the SOI layer 13. The steps S5 and S6 correspond to the measuring step of the present invention.

Next, the difference between the pre-reaction thickness (T1) obtained in the step S2 and the post-reaction thickness (T2) obtained in the step S6 is calculated, so that the deformation reaction in the surface of the SOI layer 13, The distribution of the etching reaction is obtained (S7). At this time, the difference between the pre-reaction thickness T1 and the post-reaction thickness T2 in the same coordinates in the plane of the SOI layer 13 is calculated. The step of S7 corresponds to the comparative step of the present invention.

As a result, the portion 14 (see Fig. 3 (e)) where the value obtained by subtracting the thickness T1 from the thickness T2 after the reaction (= T2-T1) The portion 15 having a negative value can be evaluated to have undergone the etching reaction. In other words, in the epitaxial reaction or the etching reaction, It is possible to evaluate which of the reaction and the etching reaction is caused.

Further, by knowing the distribution of the site 14 (deposition portion) where the deposit reaction occurred on the back surface of the wafer and the site 15 (etching portion) where the etching reaction occurred, optimization of the reaction conditions and optimization of the susceptor design You will be able to catch clues. Specifically, for example, a process for epitaxial growth that uniformizes the in-plane distribution based on the in-plane distribution of the amount of deposition or the amount of etching in the back surface of the wafer (SOI layer 13) obtained in the step S7 And a silicon single crystal layer is formed on the silicon single crystal substrate to be a product substrate by epitaxial growth based on the process conditions. More specifically, for example, as in Embodiment 1 described later, the power optimum ratio which is the ratio of the power of the upper lamp 6 and the power of the lower lamp 7, in which the in-plane distribution becomes uniform, The epitaxial growth is performed on the product substrate. For example, as in Embodiment 2 described later, a plurality of dimples (small cavities) are formed on the bottom surface of the concave portion of the susceptor, and the optimum dimple depth, which is the dimple depth at which the in-plane distribution becomes uniform, Epitaxial growth is performed on the product substrate using a susceptor having an optimum dimple depth.

As described above, according to the present embodiment, it is possible to evaluate the in-plane distribution of the deposition reaction and the etching reaction on the back surface of the wafer. In this evaluation, an SOI wafer is used, and both surfaces of the SOI wafer are the same surface of the silicon layer as both surfaces of the product substrate. Therefore, the surface reaction of the back surface of the wafer and the in- This high in-plane distribution can be obtained. Further, since the SOI layer of the SOI wafer is formed on the oxide film which is different from the silicon layer, the thickness of the SOI layer can be easily and accurately measured.

(Example)

Hereinafter, the present invention will be described in detail with reference to examples, but they should not be construed as limiting the present invention.

(Example 1)

Using the same epitaxial growth apparatus as in Fig. 1, the in-plane distribution of the amount of deposition or the amount of etching in the back surface (SOI layer) of the wafer was obtained according to the procedure of Fig. At this time, in the step S4, the silicon source gas supplied to the SOI wafer is used as the DCS (dichlorosilane) gas, and the surface of the silicon substrate of the SOI wafer is mainly subjected to the desorption reaction (epitaxial reaction). Further, the procedure of Fig. 2 is performed one by one for a plurality of SOI wafers, and at this time, power ratios of the upper lamp and the lower lamp in the step S4 are made different between the plurality of SOI wafers.

Fig. 4 shows the in-plane distribution of the amount of deposition or the amount of etching of the back surface (SOI layer) in each SOI wafer. (Lwr 47), 51% (Lwr 51), 55% (Lwr 55), and 59% (Lwr 59) from the left to the total power of the upper lamp and the lower lamp, And the in-plane distribution is shown.

4, the in-plane distribution is changed by changing the power ratio of the vertical ramp. Specifically, in the in-plane distribution in which the power ratio of the lower side lamp is 47%, 51%, 55% The etching amount of the outer peripheral portion of the wafer is increased in all of 47%, 51%, and 55%. However, the etching reaction of the outer peripheral portion of the wafer is promoted at lower power ratios.

On the other hand, in the in-plane distribution in which the power ratio of the lower side lamp is 59%, the deposition reaction dominates (strictly speaking, the deposition amount is represented by a positive value and the etching amount by a negative value, Plane distribution in the range of -20 nm to +20 nm).

In addition, as the power ratio of the lower lamp increases, the distribution becomes uniform. From this point, it is understood that it is preferable to increase the power ratio of the lower side lamp in order to uniform the in-plane distribution of the amount of deposition or the amount of etching on the back side of the wafer.

(Example 2)

Using the same epitaxial growth apparatus as in Fig. 1, the in-plane distribution of the amount of deposition and the amount of etching in the back surface (SOI layer) of the wafer was obtained in accordance with the procedure of Fig. At this time, in step S4, HCl gas is supplied to the surface of the SOI wafer, and the etching reaction is mainly performed on the surface of the silicon substrate of the SOI wafer. The reaction conditions (such as the flow rate of HCl gas) were set so that the etching amount on the surface of the silicon substrate was 0.5 mu m. Further, a susceptor having many dimples formed on the bottom surface of the susceptor recess was prepared. Using this susceptor, HCl gas was supplied to the surface of the SOI wafer and reacted.

Figs. 5 and 6 show the in-plane distribution of the amount of deposition and the amount of etching in the back surface (SOI layer) of the SOI wafer when HCl gas is supplied to the surface of the SOI wafer. The in-plane distributions of FIGS. 5 and 6 show in-plane distributions in the same SOI wafer. Specifically, FIG. 5 shows the in-plane distribution shown from the viewpoint of the desorption reaction, the colored portion shows the portion where the depression reaction occurred, and the white portion shows the portion where the etching reaction occurred. In the colored portion of FIG. 5, the difference in amount of deposition is shown according to the density of the color (see the scale in FIG. 5). Fig. 6 shows the in-plane distribution shown from the viewpoint of the etching reaction, the colored portion shows the portion where the etching reaction occurred, and the white portion shows the portion where the depo reaction occurs. In the colored portion in Fig. 6, the difference in the amount of etching is shown according to the density of the color (see the scale in Fig. 6).

As shown in Fig. 5, even when the etching reaction was performed on the front surface side, it can be seen that a depo reaction also occurred on the back surface side. In addition, when the dimple depth of the susceptor was changed, the in-plane distribution of Figs. 5 and 6 was changed. Specifically, in-plane distribution in which the etching reaction predominated more than that of Figs. 5 and 6 was obtained. Thus, by changing the dimple depth, the balance of the deposition reaction and the etching reaction on the back surface of the wafer can be changed.

The present invention is not limited to the above-described embodiments. It is to be understood that the above-described embodiments are illustrative and that any element that has substantially the same structure as the technical idea described in the claims of the present invention and can obtain the same operational effects is included in the technical scope of the present invention.

In the above embodiment, an example in which the SOI wafer is used to evaluate the in-plane distribution of the wafer reaction and the etching reaction on the back surface of the wafer has been described. However, evaluation may be performed using a wafer in which a plurality of layers other than the SOI wafer are stacked. In this case, it is preferable that the layer disposed on the susceptor side in the step S4 is a layer formed of the same material as the product substrate, that is, a silicon layer. As a result, under the same conditions as the back surface of the wafer on the product substrate, it is possible to perform a depo reaction or an etching reaction on the back surface of the wafer.

As the wafer other than the SOI wafer, for example, an epitaxial wafer having a silicon epitaxial layer formed on a silicon substrate may be used. In this case, since the silicon substrate has a thickness of about 700 mu m and it is difficult to measure the thickness, the epitaxial layer is made to have a thickness as a base layer, and in the step of S4 in Fig. 2, the epitaxial layer is formed so as to face the susceptor, To the susceptor. In order to make it possible to measure the thickness of the epitaxial layer made of the same material as the substrate, an epitaxial wafer having a resistivity different from that of the epitaxial layer is used.

1 epitaxial growth apparatus
2 reaction furnace
3 Susceptor
6 Top lamp
7 Lower lamp

Claims (4)

A preparation step of preparing a wafer having a known thickness on the surface thereof in advance and having a plurality of layers stacked thereon including the known thickness,
A reaction step of depositing a film on the surface of the wafer opposite to the base layer in a state in which the wafer is placed on the susceptor so that the thickness of the base layer faces the susceptor,
A measuring step of measuring the thickness of the thicknessed layer after the reaction step;
A comparison step of comparing the thickness of the layer of the known thickness before and after the reaction step
Wherein the wafer is a wafer. The method according to claim 1,
Wherein the comparison step compares the thickness of the layer of known thickness before and after the reaction step over the entire surface of the layer of the known thickness. 3. The method according to claim 1 or 2,
The wafer is an SOI wafer in which an oxide film and a silicon layer are formed in this order on a silicon substrate,
Wherein the thickness of the known layer is the silicon layer. The process conditions for the epitaxial growth for obtaining the uniformity of the in-plane distribution are obtained on the basis of the in-plane distribution of the thickness variation of the thickness layer before and after the reaction step obtained by the wafer evaluation method described in claim 1, And epitaxial growth is performed on the product substrate based on the conditions.

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