CN109216222A - The manufacturing method of chip evaluation method and epitaxial wafer - Google Patents
The manufacturing method of chip evaluation method and epitaxial wafer Download PDFInfo
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- CN109216222A CN109216222A CN201810663483.1A CN201810663483A CN109216222A CN 109216222 A CN109216222 A CN 109216222A CN 201810663483 A CN201810663483 A CN 201810663483A CN 109216222 A CN109216222 A CN 109216222A
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- 238000011156 evaluation Methods 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000006243 chemical reaction Methods 0.000 claims abstract description 128
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 35
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000009826 distribution Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 52
- 238000005530 etching Methods 0.000 abstract description 45
- 235000012431 wafers Nutrition 0.000 description 56
- 238000000151 deposition Methods 0.000 description 50
- 239000007789 gas Substances 0.000 description 27
- 239000010408 film Substances 0.000 description 13
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 5
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 5
- 238000005457 optimization Methods 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910003822 SiHCl3 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000005046 Chlorosilane Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
Abstract
A kind of method is provided, can evaluate the bump of chip inner surface generated by the extension reaction or etching reaction with respect to wafer outer surface is generated because of which person in deposition reaction and etching reaction.Prepare SOI wafer (S1), measures the thickness (S2) of the soi layer of SOI wafer.In such a way that soi layer is towards base side, SOI wafer is spun upside down and is placed on pedestal, carries out extension reaction or etching reaction (S3, S4).SOI wafer after reaction is spun upside down into the state of soi layer upward, measures the thickness (S5, S6) of soi layer.By finding out the difference of the thickness of the soi layer of reaction front and back, (S7) is distributed to obtain in the deposition reaction of chip inner surface and the face of etching reaction.In addition, finding out the process conditions for making the epitaxial growth of distribution uniformity in the face according to being distributed in acquired face, according to the process conditions, epitaxial growth is carried out on product substrate.
Description
Technical field
The present invention relates to the manufacturing methods of the method and epitaxial wafer of evaluating the reaction occurred on chip inner surface, this is anti-
Should be along with the deposition reaction (reaction of accumulative deposit (film)) for the wafer outer surface being placed on pedestal or etching reaction and
It generates.
Background technique
With the highly integrated of semiconductor devices, the requirement to the chip quality for constituting its raw material is further improved.It is right
In epitaxial wafer, other than the planarization of the film thickness distribution of the epitaxial layer of vapor phase growth on the outer surface, inner surface is (with formation
The wafer surface of the side opposite side of epitaxial layer) bump smoothing also as flatness quality improving project it
One.
Due to usually will not initiatively provide reaction raw materials on the inner surface of chip, therefore will not on the inner surface of chip
The huge reaction as occurred on the outer surface occurs, but only slight deposition reaction and etching reaction coexists, and causes to generate
Bump related with the design of pedestal.The concave-convex degree of the bump is varied because of the condition of reaction, the design of pedestal.
As the evaluation method of bump, can be laid out by the nanometer of the testing flatness of Wafer Sight2 (KA-Tencor company)
Technology (nanotopology) analytic function, with sense of vision, the mode of numerical value and confirm.
In addition, following patent documents 1 discloses the method for the chip end shape variation before and after evaluation epitaxial growth.
Existing technical literature
Patent document
Patent document 1:JP 2015-No. 126010 bulletins of special open
Summary of the invention
Technical problems to be solved by the inivention
But the information obtained due to the nanometer topology (nanotopology) according to Wafer Sight2 is related to
The displacement of height, therefore even if being still faced with and it cannot be distinguished is generated because of deposition reaction with bump,
Or it is led to the problem of because of etching reaction.
It is proposed the present invention be directed to described problem, the purpose of the present invention is to provide evaluable because extension is reacted or is lost
Carve reaction and generate, the bump of chip inner surface (the pedestal side surface of chip) is because in deposition reaction and etching reaction
Any person and the chip evaluation method generated, and the manufacturing method of the epitaxial wafer that planarizes chip inner surface.
A technical solution to solve project
In order to realize the purpose, chip evaluation method of the invention be characterized in that this method comprises:
Preparatory process prepares chip, has the thickness known layer for knowing thickness in advance on the outer surface of the chip,
The multiple layers being stacked on the chip including the thickness known layer；
Reaction process, it is described being placed in the chip according to the thickness known layer and the opposed facing mode of pedestal
In the state of on pedestal, in the chip and on the outer surface of the thickness known layer opposite side, the anti-of accumulating film is carried out
It answers or etching reaction；
Mensuration operation measures the thickness of the thickness known layer after the reaction process；
Process is evaluated, thickness change of the thickness known layer before and after the reaction process is evaluated.
According to the present invention, by the relatively process, the thickness of the thickness known layer after understand that reaction process is big
In the thickness being also less than before reaction process can be according to the comparison result of the relatively process, to evaluate chip inner surface
Bump be because of caused by any person in deposition reaction and etching reaction.
In addition, in the range of the entire surface of the thickness known layer, the thickness is in the relatively process
Know thickness of the layer before and after the reaction process.Thereby, it is possible to evaluate deposition portion and etching in the entire surface of chip inner surface
How portion is distributed.In addition, in the present invention, being formed in the chip of other layers on substrate (base), substrate
(base) it is also included in the concept of " layer ".
In addition, the chip is SOI (the Silicon On sequentially formed to form oxidation film and silicon fiml on a silicon substrate
Insulator) chip, the thickness known layer can be the silicon layer.
In addition, the manufacturing method of epitaxial wafer of the invention is characterized in that chip evaluation method according to the present invention and obtains
, it is distributed in the face of the amounts of thickness variation of the thickness known layer of the front and back of the reaction process, finding out makes in the face
The process conditions of the epitaxial growth of distribution uniformity carry out epitaxial growth according to the process conditions on product substrate.
By the above method, the extension being evenly distributed in the face of the deposition or etch quantity that make chip inner surface can be obtained
Chip, that is, the epitaxial wafer that chip inner surface can be made flat.
Detailed description of the invention
Fig. 1 is the appearance assumption diagram for indicating epitaxial growth device；
Fig. 2 is to obtain the process flow chart being distributed in the deposition reaction of chip inner surface and the face of etching reaction；
SOI in each process when Fig. 3 is the distribution in the face for measuring deposition reaction and etching reaction that chip inner surface occurs
The state diagram of chip；
Fig. 4 is distribution map in the deposition reaction of chip inner surface and the face of etching reaction when changing the power ratio of lamp up and down；
Fig. 5 is distributed in the face of the deposition reaction of chip inner surface when carrying out etching reaction on the outer surface of SOI wafer
Figure；
Fig. 6 be with distribution map in the face of the etching reaction on the inner surface of the same chip of Fig. 5.
Symbol description
1 epitaxial growth device；
2 reacting furnaces；
3 pedestals；
Side lamp on 6；
7 lower side lamps.
Specific embodiment
Below with reference to accompanying drawings, description of specific embodiments of the present invention.Firstly, referring to Fig.1, to epitaxial growth
The structure of device is illustrated.The epitaxial growth device 1 of Fig. 1 is a kind of to make silicon epitaxy layer on the outer surface of 1 wafer W with gas
The device that phase mode is grown.
Epitaxial growth device 1 includes the reacting furnace 2 being made of suprasil portion material etc..In the inside of reacting furnace 2, it is provided with
For placing the pedestal 3 of the wafer W of epitaxial growth.Pedestal 3 can be made of SiC, be also possible to coat SiC in graphite substrate
Coating forms.Pedestal 3 is in the form of annular discs, and top and bottom are arranged in a manner of horizontal.Recess portion is formed on the top surface of pedestal 3
31, wafer W is placed on the recess portion 31.In addition, as shown in Fig. 3 (c), the bottom surface of recess portion 31 be in compared with its peripheral part,
The deeper shape of middle part.In addition, the peripheral part of wafer W is supported on the peripheral part of 31 bottom surface of recess portion, the middle part of wafer W is not
It is contacted with the bottom surface of recess portion 31.That is, being formed with space between wafer W and the bottom surface of recess portion 31.In addition, the shape of recess portion 31 is not
It is limited to the shape of Fig. 3 (c), recess portion 31 can also be constituted in such a way that the entire inner surface of wafer W is contacted with the bottom surface of recess portion 31.
In addition, forming the hole (not shown) for penetrating into 3 back side of pedestal on the bottom surface of recess portion 31.For example, the through-hole
It is the insertion hole of lifter pin, i.e., when wafer W passes in and out recess portion 31, above-mentioned lifter pin supports the inner surface of wafer W by its front end,
Go up and down wafer W.
The inner surface of pedestal 3 is supported by support shaft 8.Support shaft 8 is according to the central crossbar of its axis L1 and pedestal 3
Mode is arranged.The driving portion (not shown) for rotating it is connected in support shaft 8.In epitaxial growth, pass through driving
Portion rotates support shaft 8, and the wafer W for thus making pedestal 3 and being placed on pedestal 3 surrounds the axis L1 of support shaft 8 and rotates.
The upper side and lower side of reacting furnace 2 is provided with lamp 6,7.In epitaxial growth, which is heated to wafer W outer
Prolong growth temperature (for example, 900~1200 DEG C).Power of side lamp 6 and lower side lamp 7 can control respectively on this.In other words, upper side lamp
6 and the power ratio of lower side lamp 7 be variable.
The one end of the horizontal direction of reacting furnace 2 is provided with gas supply port 4, be provided with the gas supply port 4
The opposite side of side is provided with gas discharge outlet 5.Gas supply port 4 is formed in the upside of pedestal 3.It is led from gas supply port 4
Enter reaction gas, which includes: that the silicon source gas for constituting monocrystalline silicon thin film (silicon epitaxy layer) raw material (specifically has three
The silane-based gas such as chlorosilane (TCS))；For diluting the carrying gas (such as: hydrogen) of silicon source gas；And for adjusting extension
The impurity gas (such as: including the gas of boron, phosphorus) of the electric conductivity of layer, conductivity.The reaction gas entered from gas supply port 4
Body flows in the inner space of reacting furnace 2 along the outer surface for the wafer W for keeping approximate horizontal rotation, then arranges from gas
It exports 5 and is discharged.That is, reaction gas from gas supply port 4 towards gas discharge outlet 5, substantially horizontally and in one direction flows
It is dynamic.
The above are the structures of epitaxial growth device 1.Herein, the deposition reaction based on reaction gas is carried out (outside in wafer W
Prolong reaction) or when etching reaction, reaction gas is via the gap between wafer W and recess portion 31 or is formed in the bottom surface of recess portion 31
On through-hole, unroll to the inner surface of wafer W, so that slight deposition reaction or etching reaction can occur in this interior surface.
Due to the deposition reaction, etching reaction, bump can be generated on the inner surface of chip, with reaction condition or pedestal 3
It designs related.Understand that the bump is as caused by deposition reaction, or as caused by etching reaction, it is considered to be for reality
Existing Optimization of reaction condition realizes the design optimization of pedestal 3 and can most catch the main points of main threads.Then, in this embodiment party
In formula, according to the sequence of Fig. 2, Fig. 3, the cause to the bump of the inner surface of chip is that deposition reaction or etching reaction carry out
Evaluation.The process of Fig. 2, Fig. 3 will be illustrated below.
Firstly, preparing SOI wafer (S1).Fig. 3 (a) indicates the cross-sectional view of the SOI wafer 10 prepared in S1.SOI wafer
10 have following structures: on basic (base) substrate 11 (hereinafter referred to as silicon substrate) being made of monocrystalline silicon layer, forming oxygen
SiClx film 12 forms the soi layer 13 being made of monocrystalline silicon layer on the silicon oxide film 12.The thickness of soi layer 13 is preferably set to
Greater than the value of the etch quantity carried out in aftermentioned S4 process to soi layer 13, specifically, for example it is set in 40nm or more.
The production method of SOI wafer 10 is as follows: firstly, forming oxidation film on one in 2 monocrystalline substrates, then
It clamps the established oxidation film and engages another monocrystalline substrate, then, to a progress film in 2 monocrystalline substrates
Change processing to form soi layer.
Then, the thickness (S2) of soi layer 13 is measured.The thickness can be measured by arbitrary method, for example, to measurement
The film light projector of object, by the optical interference formula for measuring film thickness according to the interference of outer surface reflected light and inner surface reflected light
Measuring instrument, to measure the thickness of soi layer 13.In addition, both can measure the thickness of the entire outer surface of soi layer 13, if soi layer 13
Thickness distribution is uniform, then can also only measure the thickness of a part, the thickness whole as soi layer 13 using the thickness of the part.
In addition, the process work of S1, S2 are equivalent to preparatory process of the invention.In addition, in the present invention, soi layer 13 is equivalent to this hair
Thickness known layer in bright.
Then, as shown in Fig. 3 (b), SOI wafer 10 is spun upside down so that soi layer 13 downward, 11 direction of silicon substrate
Top (S3).
Later, SOI wafer 10 is put into the state of overturning in the reacting furnace 2 of Fig. 1, and be placed on pedestal 3, led to
Defined extension reaction formula or etching reaction formula are crossed, SOI wafer 10 is made to be reacted (deposition reaction or etching reaction)
(S4).That is, as shown in Fig. 3 (c), according to the opposed facing mode in bottom surface of soi layer 13 and the recess portion 31 of pedestal 3, by SOI wafer
10 are placed on pedestal 3.Then, the temperature of the outer surface of silicon substrate 11 is made to rise to predetermined temperature by the lamp of upper and lower sides 6,7,
And the gas for making it carry out deposition reaction or etching reaction is provided to its outer surface.Specifically, it is made to carry out deposition reaction
When, the silane-based gas such as trichlorosilane is provided to the outer surface of silicon substrate 11.On the other hand, it is etched it instead
At once, such as hydrogen chloride (HCl) gas is provided to the outer surface of silicon substrate 11.
At this point, providing, to the gas on the outer surface of silicon substrate 11, some unrolls to the outer surface side of soi layer 13, therefore
Slight deposition reaction or etching reaction occur on the outer surface of soi layer 13.For example, by trichlorosilane (SiHCl3) and carry
Gas H2When provided on the outer surface of silicon substrate 11 together, pass through SiHCl3+H2The Si and HCl that → Si+3HCl is reacted and generated are returned
Around 13 side of soi layer, deposition reaction and etching reaction occurs simultaneously on soi layer 13.Soi layer 13 occur deposition reaction or
The distribution at the position of etching reaction, according to reaction condition (type, flow, temperature of gas etc.) or the design (recess portion of pedestal 3
31 depth etc.) and change.In addition, on the face of the outer surface opposite side of the soi layer 13 with 3 side of pedestal, due to stacked
There are oxidation film 12 and silicon substrate 11, therefore on the surface of the opposite side, deposition reaction or etching reaction do not occur.In addition, S3, S4
Process be equivalent to reaction process of the invention.
Then, as shown in Fig. 3 (d), the soi wafer 10 after reaction is spun upside down so that soi layer 13 upward, silicon lining
Bottom 11 is downward (S5).
Then, as shown in Fig. 3 (e), the thickness (S6) of soi layer 13 in the SOI wafer 10 after measurement reaction.The thickness can also
To be measured by arbitrary method, for example, measuring the thickness of soi layer 13 by optical interference formula measuring instrument.In addition,
For measuring the thickness this point of which range of 13 outer surface of soi layer, it is determined by following: wanting to obtain deposition reaction
With that range of 13 outer surface of soi layer of etching reaction distribution.For example, intending the entire outer surface of acquisition soi layer 13
When deposition reaction and etching reaction are distributed, then the thickness of the entire outer surface of soi layer 13 is measured.In addition, the process of S5, S6 are suitable
In mensuration operation of the invention.Later, by calculate obtained in thickness T1, with S6 process before the reaction that obtains in S2 process it is anti-
The difference between rear thickness T2 is answered, the deposition reaction in face, etching reaction to obtain the soi layer 13 occurred with S4 process
It is distributed (S7).At this point, calculate 13 face of soi layer in same coordinate reaction before thickness T1 with react after thickness T2 difference.In addition, S7
Process be equivalent to comparison process of the invention.
Position (the reference that the value (=T2-T1) before reacting after thickness T1 is positive is subtracted accordingly, for thickness T2 after reaction
Fig. 3 (e)), it can be evaluated as deposition reaction has occurred, for the position 15 (referring to Fig. 3 (e)) of negative value, can be evaluated to be etched
Reaction.That is, can be in extension reaction or etching reaction, the bump generated on chip inner surface is by deposition reaction and erosion
The case where carving which of reaction and generating is evaluated.
In addition, position 14 (deposition portion) and the generation etching reaction of deposition reaction occurs on chip inner surface by understanding
The distribution at position 15 (etched part) can grasp the optimization of reaction condition and the optimization of pedestal design.Specifically,
For example, being distributed according in the deposition of chip inner surface (soi layer 13) or the face of etch quantity obtained in S7 process, finding out makes
The process conditions of the epitaxial growth of distribution uniformity in the face, according to the process conditions, in the monocrystalline silicon for constituting product substrate
On substrate, by being epitaxially-formed monocrystalline silicon layer.More specifically, for example, described in embodiment as follows 1, finding out can make
The power ratio of the power of the upper side lamp 6 of distribution uniformity and lower side lamp 7 in face is stated, i.e. power most preferably compares, most according to the power
Good ratio, carries out epitaxial growth on product substrate.In addition, for example, described in embodiment as follows 2, on the bottom surface of base recess,
Multiple scrobiculas (small lower concave part) is formed, the best dimple depth that can make distribution uniformity in above-mentioned face is found out, it should using having
The pedestal of best dimple depth, carries out epitaxial growth on product substrate.
As described above, in the embodiment, can be evaluated in the deposition reaction on chip inner surface and the face of etching reaction
Distribution.In the evaluation, using SOI wafer, two surfaces of the SOI wafer are silicon identical with two surfaces of product substrate
The surface of layer, thereby, it is possible to obtain the deposition reaction occurred on chip inner surface corresponding with product substrate and etching reaction
Face in distribution in the high face of distribution correlation.In addition, since the soi layer of SOI wafer is formed in as the layer for being different from silicon layer
Oxidation film on, therefore can be easy and correctly measure the thickness of soi layer.
Embodiment
The present invention is specifically described below by embodiment is enumerated, but they are not constituted to limit of the invention
It is fixed.
(embodiment 1)
The deposition of chip inner surface (soi layer) is found out according to the process of Fig. 2 using epitaxial growth device identical with Fig. 1
The distribution of the inner surface of amount or etch quantity.At this point, the silicon source gas provided to SOI wafer is DCS (dichloro silicon in the process of S4
Alkane) gas, make on the outer surface of the silicon substrate of SOI wafer, is substantially carried out deposition reaction (extension reaction).In addition, multiple
In SOI wafer, the process that 1 ground carries out Fig. 2 every time, at this point, for different SOI wafers, make upper side lamp in the process of S4 with
The power ratio of upper side lamp is different.
It is distributed in the deposition of inner surface (soi layer) of each SOI wafer or the face of etch quantity as shown in Figure 4.Fig. 4 is indicated
Be side lamp instantly power opposite upper lamp and lower side lamp general power ratio be followed successively by from left side 47% (Lwr47),
It is distributed in each face when 51% (Lwr51), 55% (Lwr55), 59% (Lwr59).
As shown in figure 4, making distribution in face change, specifically, in lower side lamp by the power ratio for changing lamp up and down
Power ratio be 47%, 51%, 55% face in be distributed in, etching reaction is more dominant than deposition reaction, in particular, 47%,
51%, the etch quantity of any one chip peripheral part in 55% is all big, and power ratio is lower, can more promote chip peripheral part
Etching reaction.
On the other hand, in the face that the power ratio of lower side lamp is 59% in distribution, deposition reaction is dominant (strictly speaking,
When positive value indicates deposition, and negative value indicates etch quantity, deposition or etch quantity are distributed as in -20nm~+20nm model in face
In enclosing).
In addition, the power ratio of lower side lamp is bigger, it is distributed in face more uniform.It follows that the power ratio for increasing lower side lamp can
So that distribution becomes uniform in the deposition of chip inner surface or the face of etch quantity.
(embodiment 2)
The deposition of chip inner surface (soi layer) is found out according to the process of Fig. 2 using epitaxial growth device identical with Fig. 1
It is distributed in the face of amount or etch quantity.At this point, providing HCl gas to the outer surface of SOI wafer in the process of S4, make in SOI crystalline substance
On the outer surface of the silicon substrate of piece, it is substantially carried out etching reaction.It sets reaction condition (flow etc. of HCl gas), makes silicon substrate
Outer surface etch quantity be 0.5 μm.In addition, preparing the pedestal on the bottom surface of base recess with multiple scrobiculas.Then, it adopts
With the pedestal, HCl gas is provided to the outer surface of SOI wafer, brings it about reaction.
When providing HCl gas to the outer surface of SOI wafer, the deposition of the inner surface (soi layer) of SOI wafer or etching
It is distributed in the face of amount as shown in Figure 5, Figure 6.In addition, being distributed as being distributed in the face of same SOI wafer in Fig. 5, face shown in fig. 6.
Specifically, Fig. 5 is the angle with deposition reaction and is distributed in the face that indicates that coloured part indicates that the portion of deposition reaction occurs
Point, white portion indicates that the part of etching reaction occurs.In the coloured part of Fig. 5, indicate to deposit by the depth of color
The difference of amount (referring to the scale in Fig. 5).Fig. 6 is the angle with etching reaction and is distributed in the face that indicates that coloured part indicates
The part of etching reaction is generated, white part indicates to generate the part of deposition reaction.In the coloured part of Fig. 6, pass through color
The depth indicate the difference of etch quantity (referring to the scale in Fig. 6).
As shown in Figure 5 it is found that even if still can also be sent out in the case where outer surface side is etched reaction in inner surface side
Raw deposition reaction.In addition, distribution can also change in the face of Fig. 5, Fig. 6 if the dimple depth of pedestal changes, it is specific next
It says, will obtain and be distributed in the more dominant face of etching reaction when comparing with the example of Fig. 5, Fig. 6.It like this, can be by changing
Become dimple depth to change the deposition reaction of chip inner surface and the balance of etching reaction.
In addition, the present invention is not limited to the above embodiments.Above embodiment is particularization, still, and in the present invention
Claims in the technical concept recorded there is substantially the same structure, realize the scheme of identical function and effect, nothing
By be why the type of sample, be included in technical scope of the invention.
In addition, in the above-described embodiment, giving using SOI wafer and evaluating the deposition reaction and erosion of chip inner surface
The example being distributed in the face of reaction is carved, however, it is possible to comment using the chip for being stacked with the multilayer in addition to SOI wafer to carry out this
Valence.In this case, when carrying out S4 process, preferably the layer choosing that base side is arranged in is selected as by identical with product substrate
Substance and the layer formed, that is, silicon layer.Thereby, it is possible under the same conditions, make in chip with the chip inner surface of product substrate
Deposition reaction or etching reaction occur on surface.
As the chip other than SOI wafer, can also be used for example, forming the epitaxial wafer of silicon epitaxy layer on a silicon substrate.
In this case, since silicon substrate has 700 μm of thickness, thickness measurement is difficult, therefore by epitaxial layer as thickness known layer,
In the S4 process of Fig. 2, in such a way that epitaxial layer and pedestal are opposed facing, epitaxial wafer is placed on pedestal.In addition, in order to
The thickness that the epitaxial layer formed by raw material identical with substrate can be measured, using the resistivity of substrate and the resistivity of epitaxial layer
Different epitaxial wafers.
Claims (4)
1. a kind of chip evaluation method, which is characterized in that this method comprises:
Preparatory process prepares chip, has the thickness known layer for knowing thickness in advance on the outer surface of the chip, described
The multiple layers being stacked on chip including the thickness known layer；
The chip is placed on the pedestal by reaction process according to the thickness known layer and the opposed facing mode of pedestal
In the state of, in the chip and on the outer surface of the thickness known layer opposite side, carry out the reaction or erosion of accumulating film
Carve reaction；
Mensuration operation measures the thickness of the thickness known layer after the reaction process；
Compare process, thickness of the thickness known layer before and after the reaction process.
2. chip evaluation method according to claim 1, it is characterised in that:
In the relatively process, in the range of the entire surface of the thickness known layer, the thickness known layer is in institute
State the thickness before and after reaction process.
3. chip evaluation method according to claim 1 or 2, it is characterised in that:
The chip is according to the SOI wafer sequentially formed for forming oxidation film and silicon fiml on a silicon substrate；
The thickness known layer is the silicon layer.
4. a kind of manufacturing method of epitaxial wafer, it is characterised in that:
Chip evaluation method according to claim 1 and obtain, known to the thickness of the front and back of the reaction process
It is distributed in the face of the amounts of thickness variation of layer, finds out the process conditions for making the epitaxial growth of distribution uniformity in the face, according to
The process conditions carry out epitaxial growth on product substrate.
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| JP2004349493A (en) * | 2003-05-22 | 2004-12-09 | Canon Inc | Device for controlling film thickness and method of manufacturing soi substrate |
| JP2009302133A (en) * | 2008-06-10 | 2009-12-24 | Sumco Corp | Film thickness measurement method, epitaxial wafer manufacturing method, and epitaxial wafer |
| JP2011009246A (en) * | 2009-06-23 | 2011-01-13 | Sumco Corp | Method of manufacturing epitaxial silicon wafer |
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| JP4899445B2 (en) * | 2005-11-22 | 2012-03-21 | 信越半導体株式会社 | Epitaxial wafer manufacturing method and epitaxial wafer |
| JP5445508B2 (en) * | 2011-04-22 | 2014-03-19 | 信越半導体株式会社 | Eccentricity evaluation method and epitaxial wafer manufacturing method |
| JP6127748B2 (en) * | 2013-06-10 | 2017-05-17 | 株式会社Sumco | Epitaxial wafer manufacturing method |
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