JP2019016713A - Method for evaluating wafer and method for manufacturing epitaxial wafer - Google Patents

Abstract

To provide a method by evaluation can be performed about which of deposition and etching reactions wafer backside asperities formed by an epitaxial or etching reaction on a wafer surface come from.SOLUTION: The method comprises the steps of: preparing an SOI wafer (S1); measuring a thickness of an SOI layer of the SOI wafer(S2); inverting the SOI wafer upside down so that the SOI layer faces a susceptor side, putting the wafer on a susceptor, and performing an epitaxial or etching reaction (S3, S4); inverting the SOI wafer after the reaction upside down so that the SOI layer faces up, and measuring the thickness of the SOI layer (S5, S6); determining a difference in the SOI layer thicknesses before and after the reaction, thereby obtaining an in-plane distribution of deposition and etching reactions on a wafer backside (S7); and determining a process condition for an epitaxial growth to uniformize the in-plane distribution based on the in-plane distribution thus obtained and performing an epitaxial growth on an article substrate based on the process condition.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for evaluating a reaction on the back surface of a wafer, which is caused by a deposition reaction (a reaction for depositing a deposition (film)) or an etching reaction on a wafer surface placed on a susceptor, and a method for manufacturing an epitaxial wafer. .

  With the high integration of semiconductor devices, the quality required for wafers as raw materials is further increasing. In the case of an epitaxial wafer, in addition to flattening the film thickness distribution of the epitaxial layer that is vapor-grown on the surface, smoothing the unevenness on the back surface (the wafer surface opposite to the side where the epitaxial layer is formed) improves flatness quality. It is one of the items.

  Since the active material supply is not normally performed on the backside of the wafer, a large reaction that occurs on the front surface does not occur, but the deposition reaction and the etching reaction coexist slightly, resulting in unevenness that correlates with the susceptor design. Resulting in. The degree of unevenness varies depending on reaction conditions and susceptor design. As an unevenness evaluation method, it can be visually and numerically confirmed by a nanotopology analysis function of a flatness tester such as WaferSight 2 (KLA-Tencor).

  Patent Document 1 below discloses a method for evaluating a change in the shape of the wafer end before and after epitaxial growth.

JP2015-125010A

  However, since the information obtained from the nanostructure of WaferSight2 corresponds to the amount of displacement in height, there is a problem that even if there are irregularities, it cannot be distinguished whether it is generated by a deposition reaction or an etching reaction. It was.

  The present invention has been made in view of the above problems, and evaluates whether the unevenness of the wafer back surface (the surface on the susceptor side of the wafer) caused by an epitaxial reaction or an etching reaction is caused by a deposition reaction or an etching reaction. An object of the present invention is to provide a wafer evaluation method that can be used, and a method for manufacturing an epitaxial wafer with the wafer back surface planarized.

In order to achieve the above object, the wafer evaluation method of the present invention comprises:
A preparatory step of preparing a wafer having a thickness known layer having a known thickness on the surface and a plurality of layers including the thickness known layer being laminated;
With the wafer placed on the susceptor so that the known thickness layer faces the susceptor, a reaction or etching reaction is performed to deposit a film on the surface of the wafer opposite to the known thickness layer. Reaction steps to be performed;
After the reaction step, a measurement step of measuring the thickness of the known thickness layer,
An evaluation step for evaluating a change in thickness of the known thickness layer before and after the reaction step;
It is characterized by providing.

  According to the present invention, it is possible to know whether the thickness of the known layer after the reaction step is larger or smaller than that before the reaction step by the comparison step. Based on the result, it can be evaluated whether the unevenness on the back surface of the wafer is caused by a deposition reaction or an etching reaction.

  In the comparison step, the thickness of the known thickness layer before and after the reaction step is compared over the entire surface of the known thickness layer. Thereby, it is possible to evaluate how the deposition part and the etching part are distributed over the entire back surface of the wafer. In the present invention, a base substrate in a wafer in which another layer is formed on the base substrate is also included in the concept of “layer”.

  The wafer may be an SOI (Silicon On Insulator) wafer in which an oxide film and a silicon layer are formed in this order on a silicon substrate, and the known thickness layer may be the silicon layer. .

  The epitaxial wafer manufacturing method of the present invention is based on the in-plane distribution of the thickness variation of the known thickness layer before and after the reaction step obtained by the wafer evaluation method of the present invention. A process condition for epitaxial growth that makes the distribution uniform is obtained, and epitaxial growth is performed on a product substrate based on the process condition.

  According to this, an epitaxial wafer in which the in-plane distribution of the deposition amount or etching amount on the wafer back surface is made uniform, that is, an epitaxial wafer in which the wafer back surface is flattened can be obtained.

It is the figure which showed schematic structure of the epitaxial growth apparatus. It is the flowchart which showed the procedure which acquires the in-plane distribution of the deposition reaction and etching reaction of a wafer back surface. It is the figure which showed the mode of the SOI wafer in each process in the measurement of the in-plane distribution of the deposition reaction and etching reaction of a wafer back surface. It is the figure which showed the in-plane distribution of the deposition reaction and etching reaction of a wafer back surface when the power ratio of an up-and-down lamp was changed. It is the figure which showed the in-plane distribution of the deposition reaction of the wafer back surface at the time of performing etching reaction on the surface of an SOI wafer. It is the figure which showed the in-plane distribution of the etching reaction of the wafer back surface in the same wafer as FIG.

  Next, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the epitaxial growth apparatus will be described with reference to FIG. The epitaxial growth apparatus 1 of FIG. 1 is an apparatus for vapor-phase growing a silicon epitaxial layer on the surface of one wafer W.

  The epitaxial growth apparatus 1 includes a reaction furnace 2 composed of a transparent quartz member or the like. A susceptor 3 for placing a wafer W to be epitaxially grown is disposed in the reaction furnace 2. The susceptor 3 may be made of, for example, SiC, or a graphite base coated with SiC. The susceptor 3 is formed in a disc shape, and is arranged so that the upper surface and the lower surface are horizontal. A recess 31 is formed on the upper surface of the susceptor 3, and the wafer W is placed in the recess 31. In addition, as shown in FIG.3 (c), the bottom face of the recessed part 31 is formed in the shape where the center part is deeper than the outer peripheral part. The outer peripheral portion of the wafer W is supported by the outer peripheral portion of the bottom surface of the concave portion 31, and the central portion of the wafer W is not in contact with the bottom surface of the concave portion 31. That is, a space is formed between the wafer W and the bottom surface of the recess 31. The shape of the recess 31 is not limited to the shape shown in FIG. 3C, and the recess 31 may be configured so that the entire back surface of the wafer W and the bottom surface of the recess 31 are in contact with each other.

  Further, a hole (not shown) penetrating to the back surface of the susceptor 3 may be formed on the bottom surface of the recess 31. This through hole is, for example, a lift pin insertion hole for raising and lowering the wafer W while supporting the back surface of the wafer W at the tip when the wafer W is taken in and out of the recess 31.

  The back surface of the susceptor 3 is supported by a support shaft 8. The support shaft 8 is provided such that its axis L1 intersects the center of the susceptor 3. A drive unit (not shown) for rotating the support shaft 8 is connected to the support shaft 8. During the epitaxial growth, the support shaft 8 is rotated by the driving unit, so that the susceptor 3 and the wafer W placed thereon rotate around the axis L1 of the support shaft 8.

  Lamps 6 and 7 for heating the wafer W to an epitaxial growth temperature (for example, 900 to 1200 ° C.) at the time of epitaxial growth are arranged above and below the reaction furnace 2. The power of the upper lamp 6 and the lower lamp 7 can be individually controlled. In other words, the power ratio between the upper lamp 6 and the lower lamp 7 can be changed.

  A gas supply port 4 is provided on one end side in the horizontal direction of the reaction furnace 2, and a gas discharge port 5 is provided on the side opposite to the side where the gas supply port 4 is provided. The gas supply port 4 is formed above the susceptor 3. From the gas supply port 4, a silicon source gas (specifically, a silane-based gas such as trichlorosilane (TCS)) as a raw material for a silicon single crystal thin film (silicon epitaxial layer), a carrier gas for diluting the silicon source gas A reaction gas containing (for example, hydrogen) and a dopant gas (for example, a gas containing boron or phosphorus) for adjusting the conductivity type or conductivity of the epitaxial layer is introduced. The reaction gas supplied from the gas supply port 4 flows along the surface of the wafer W that is rotated and held substantially horizontally in the internal space of the reaction furnace 2. Thereafter, the reaction gas is discharged from the gas discharge port 5. That is, the reaction gas flows in a substantially horizontal direction from the gas supply port 4 toward the gas discharge port 5.

  The above is the configuration of the epitaxial growth apparatus 1. Here, when the deposition reaction (epitaxial reaction) or etching reaction based on the reaction gas is performed on the wafer W, the reaction gas passes through the gap between the wafer W and the recess 31 or through the through-hole formed in the bottom surface of the recess 31. As a result, the wafer W goes around the back surface of the wafer W, and the deposition reaction or the etching reaction is slightly performed on the back surface. Due to these deposition reactions and etching reactions, irregularities correlated with the reaction conditions and the design of the susceptor 3 are generated on the back surface of the wafer. Knowing whether the unevenness is caused by the deposition reaction or the etching reaction is considered to be an important factor for grasping the clues for optimizing the reaction conditions and optimizing the design of the susceptor 3.

  Therefore, in the present embodiment, it is evaluated whether the unevenness on the back surface of the wafer is caused by the deposition reaction or the etching reaction according to the procedures of FIGS. Hereinafter, the procedure of FIGS. 2 and 3 will be described.

  First, an SOI wafer is prepared (S1). FIG. 3A shows a cross-sectional view of the SOI wafer 10 prepared in S1. The SOI wafer 10 includes a silicon oxide film 12 formed on a base substrate 11 (hereinafter referred to as a silicon substrate) configured as a silicon single crystal layer, and is configured as a silicon single crystal layer on the silicon oxide film 12. It has a structure in which an SOI layer 13 is formed. The thickness of the SOI layer 13 is preferably set to a value larger than the etching amount performed on the SOI layer 13 in the later-described step S4, specifically, for example, set to 40 nm or more.

  In the SOI wafer 10, an oxide film is formed on one of two silicon single crystal substrates, the silicon single crystal substrate is bonded with the formed oxide film interposed therebetween, and then one silicon single crystal substrate is thinned to form an SOI layer. Is obtained.

  Next, the thickness of the SOI layer 13 is measured (S2). This thickness may be measured by any method. For example, the thickness of the thin film to be measured is projected by an optical interference measuring instrument that measures the film thickness from the interference of the front surface reflected light and the back surface reflected light. The thickness of layer 13 is measured. Further, the thickness may be measured over the entire surface of the SOI layer 13, or if the thickness distribution of the SOI layer 13 is uniform, only a part of the thickness is measured, and the SOI layer 13 having the part of the thickness is measured. It may be the total thickness. In addition, the process of S1 and S2 is equivalent to the preparatory process of this invention. The SOI layer 13 corresponds to a known thickness layer of the present invention.

  Next, as shown in FIG. 3B, the SOI wafer 10 is turned upside down so that the SOI layer 13 faces downward and the silicon substrate 11 faces upward (S3).

  Next, in an inverted state, the SOI wafer 10 is put into the reaction furnace 2 of FIG. 1 and placed on the susceptor 3, and the SOI wafer 10 reacts with a predetermined epitaxial reaction recipe or etching reaction recipe (depot reaction or etching). Reaction) is performed (S4). That is, as shown in FIG. 3C, the SOI wafer 10 is mounted on the susceptor 3 so that the SOI layer 13 faces the bottom surface of the recess 31 of the susceptor 3. Then, the surface of the silicon substrate 11 is heated to a predetermined temperature by the upper and lower lamps 6 and 7, and a gas for performing a deposition reaction or an etching reaction is supplied to the surface. Specifically, when the deposition reaction is performed, a silicon source gas such as trichlorosilane or dichlorosilane is supplied to the surface of the silicon substrate 11. On the other hand, when an etching reaction is performed, for example, hydrogen chloride (HCl) gas is supplied to the surface of the silicon substrate 11.

At this time, part of the gas supplied to the surface of the silicon substrate 11 goes around to the surface side of the SOI layer 13 and slightly causes a deposition reaction or etching reaction to the surface of the SOI layer 13. For example, when trichlorosilane (SiHCl ₃ ) is supplied to the surface of the silicon substrate 11 together with the carrier gas H ₂ , Si and HCl generated by the reaction of SiHCl ₃ + H ₂ → Si + 3HCl circulate to the SOI layer 13 side, so that the SOI layer In FIG. 13, both the deposition reaction and the etching reaction occur together. The distribution of the site where the deposition reaction or etching reaction occurs in the SOI layer 13 varies depending on the reaction conditions (gas type, flow rate, temperature, etc.) and the design of the susceptor 3 (depth of the recess 31). Since the oxide film 12 and the silicon substrate 11 are laminated on the surface of the SOI layer 13 opposite to the surface on the susceptor 3 side, no deposition reaction or etching reaction occurs on the opposite surface. . In addition, the process of S3 and S4 corresponds to the reaction process of this invention.

  Next, as shown in FIG. 3D, the reacted SOI wafer 10 is turned upside down so that the SOI layer 13 faces upward and the silicon substrate 11 faces downward (S5).

  Next, as shown in FIG. 3E, the thickness of the SOI layer 13 in the SOI wafer 10 after the reaction is measured (S6). This thickness may be measured by any method. For example, the thickness of the SOI layer 13 is measured by an optical interference measuring device. The range over which the thickness is measured on the surface of the SOI layer 13 depends on the range over which the surface of the SOI layer 13 is desired to obtain the distribution of deposition reaction and etching reaction. For example, when it is desired to obtain the distribution of deposition reaction and etching reaction over the entire surface of the SOI layer 13, the thickness is measured over the entire surface of the SOI layer 13. In addition, the process of S5 and S6 corresponds to the measurement process of this invention.

Next, by calculating the difference between the pre-reaction thickness Thk _bef obtained in the step S2 and the post-reaction thickness Thk _aft obtained in the step S6, the SOI layer 13 generated in the step S4 is calculated. A distribution of deposition reaction and etching reaction is obtained in the plane (S7). At this time, the difference between the pre-reaction thickness Thk _bef and the post-reaction thickness Thk _{aft at} the same coordinates in the plane of the SOI layer 13 is calculated. In addition, the process of S7 corresponds to the comparison process of this invention.

As a result, the depot reaction occurred at the site 14 (see FIG. 3E) in which the value obtained by subtracting the thickness Thk _bef before reaction from the thickness Thk _aft after reaction (= Thk _aft −Thk _bef ) is a positive value. It can be evaluated that the negative portion 15 (see FIG. 3E) can be evaluated as an etching reaction, that is, the unevenness generated on the back surface of the wafer in the epitaxial reaction or the etching reaction is caused by the deposition reaction or the etching reaction. It can be evaluated whether it is caused.

  In addition, by knowing the distribution of the part 14 (deposition part) where the deposition reaction has occurred on the back surface of the wafer and the part 15 (etching part) where the etching reaction has occurred, it is possible to optimize the reaction conditions and the susceptor design. You can get a clue. Specifically, for example, based on the in-plane distribution of the deposition amount or the etching amount on the wafer back surface (SOI layer 13) obtained in the step S7, the process conditions for epitaxial growth for making the in-plane distribution uniform are obtained. A silicon single crystal layer is formed by epitaxial growth on a silicon single crystal substrate to be a product substrate based on the process conditions. More specifically, for example, as in Example 1 described later, a power optimum ratio, which is a ratio of the power of the upper lamp 6 and the power of the lower lamp 7 where the in-plane distribution is uniform, is obtained, and the power optimum ratio is obtained. Based on the above, epitaxial growth is performed on the product substrate. Further, for example, as in Example 2 described later, a large number of dimples (small depressions) are formed on the bottom surface of the concave portion of the susceptor, and the optimum dimple depth that is the dimple depth at which the in-plane distribution becomes uniform is obtained. Then, epitaxial growth is performed on the product substrate using a susceptor having the optimum dimple depth.

  Thus, according to this embodiment, the in-plane distribution of the deposition reaction and the etching reaction on the wafer back surface can be evaluated. In this evaluation, an SOI wafer is used, and both surfaces of the SOI wafer are the same silicon layer surface as both surfaces of the product substrate. An in-plane distribution having a high correlation with the distribution can be obtained. Further, since the SOI layer of the SOI wafer is formed on an oxide film which is a layer different from the silicon layer, the thickness of the SOI layer can be easily and accurately measured.

  EXAMPLES Hereinafter, the present invention will be specifically described with reference to examples, but these do not limit the present invention.

Example 1
Using the same epitaxial growth apparatus as in FIG. 1, the in-plane distribution of the deposition amount or etching amount on the wafer back surface (SOI layer) was determined according to the procedure of FIG. At this time, the silicon source gas supplied to the SOI wafer in the step S4 is used as DCS (dichlorosilane) gas so that the deposition reaction (epitaxial reaction) is mainly performed on the surface of the silicon substrate of the SOI wafer. Further, the procedure of FIG. 2 was performed for each of the plurality of SOI wafers, and at this time, the power ratio of the upper lamp and the lower lamp in the step S4 was varied among the plurality of SOI wafers.

  FIG. 4 shows the in-plane distribution of the deposition amount or etching amount on the back surface (SOI layer) in each SOI wafer. In FIG. 4, the ratio of the lower lamp power to the total power of the upper lamp and the lower lamp is 47% (Lwr47), 51% (Lwr51), 55% (Lwr55), and 59% (Lwr59) from the left side. Each in-plane distribution is shown.

  As shown in FIG. 4, the in-plane distribution is changed by changing the power ratio of the upper and lower lamps. Specifically, in the in-plane distribution where the power ratio of the lower lamp is 47%, 51%, and 55%, The etching reaction is dominant compared to the deposition reaction, and in particular, the etching amount of the wafer outer peripheral portion is larger in all of 47%, 51%, and 55%. Has been promoted.

  On the other hand, in the in-plane distribution in which the power ratio of the lower lamp is 59%, the deposition reaction is dominant (strictly, the deposition amount is expressed as a positive value and the etching amount is expressed as a negative value). Alternatively, the in-plane distribution includes an etching amount in the range of −20 nm to +20 nm).

  Further, the in-plane distribution becomes more uniform as the power ratio of the lower lamp increases. This shows that it is desirable to increase the power ratio of the lower lamp in order to make the in-plane distribution of the deposition amount or etching amount on the back surface of the wafer uniform.

(Example 2)
Using the same epitaxial growth apparatus as in FIG. 1, the in-plane distribution of the deposition amount and the etching amount on the wafer back surface (SOI layer) was obtained according to the procedure of FIG. 2. At this time, HCl gas was supplied to the surface of the SOI wafer in the step of S4 so that the etching reaction was mainly performed on the surface of the silicon substrate of the SOI wafer. Reaction conditions (HCl gas flow rate, etc.) were set so that the etching amount on the surface of the silicon substrate was 0.5 μm. In addition, a susceptor having a large number of dimples formed on the bottom surface of the susceptor recess was prepared. Then, using this susceptor, HCl gas was supplied to the surface of the SOI wafer for reaction.

  5 and 6 show the in-plane distribution of the deposition amount and the etching amount on the back surface (SOI layer) of the SOI wafer when HCl gas is supplied to the surface of the SOI wafer. Note that the in-plane distributions in FIGS. 5 and 6 indicate the in-plane distribution in the same SOI wafer. Specifically, FIG. 5 shows the in-plane distribution from the viewpoint of the deposition reaction, the colored portion indicates the portion where the deposition reaction has occurred, and the white portion indicates the portion where the etching reaction has occurred. . In the colored portion of FIG. 5, the difference in deposition amount is represented by the shade of color (see the scale in FIG. 5). FIG. 6 shows the in-plane distribution expressed from the viewpoint of the etching reaction, the colored portion indicates the portion where the etching reaction has occurred, and the white portion indicates the portion where the deposition reaction has occurred. In the colored portion of FIG. 6, the difference in etching amount is represented by the shade of color (see the scale in FIG. 6).

  As shown in FIG. 5, even if the etching reaction is performed on the front surface side, it can be seen that the deposition reaction also occurs on the back surface side. Further, when the dimple depth of the susceptor is changed, the in-plane distribution of FIGS. 5 and 6 changes, and specifically, the in-plane in which the etching reaction is more dominant than the examples of FIGS. A distribution was obtained. Thus, by changing the dimple depth, the balance between the deposition reaction and the etching reaction on the back surface of the wafer can be changed.

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and has the same configuration as the technical idea described in the claims of the present invention, and can produce any similar effects. It is included in the technical scope of the present invention.

  In the above embodiment, an example is shown in which the in-plane distribution of the deposition reaction and etching reaction on the back surface of the wafer is evaluated using an SOI wafer. However, the evaluation is performed using a wafer in which a plurality of layers other than the SOI wafer are stacked. May be. In this case, the layer disposed on the susceptor side in the step of S4 is preferably a layer formed of the same material as the product substrate, that is, a silicon layer. Thereby, the deposition reaction or the etching reaction can be performed on the wafer back surface under the same conditions as the wafer back surface of the product substrate.

  As a wafer other than the SOI wafer, for example, an epitaxial wafer in which a silicon epitaxial layer is formed on a silicon substrate may be used. In this case, since the silicon substrate has a thickness of about 700 μm and it is difficult to measure the thickness, the epitaxial wafer is formed so that the epitaxial layer faces the susceptor in the step S4 of FIG. Is placed on the susceptor. Further, in order to make it possible to measure the thickness of the epitaxial layer formed of the same raw material as that of the substrate, an epitaxial wafer in which the resistivity of the substrate and the resistivity of the epitaxial layer are different is used.

1 Epitaxial Growth Equipment 2 Reactor 3 Susceptor 6 Upper Lamp 7 Lower Lamp

Claims (4)

A preparatory step of preparing a wafer having a thickness known layer having a known thickness on the surface and a plurality of layers including the thickness known layer being laminated;
With the wafer placed on the susceptor so that the known thickness layer faces the susceptor, a reaction or etching reaction is performed to deposit a film on the surface of the wafer opposite to the known thickness layer. Reaction steps to be performed;
After the reaction step, a measurement step of measuring the thickness of the known thickness layer,
A comparison step for comparing the thickness of the known thickness layer before and after the reaction step;
A wafer evaluation method comprising:   2. The wafer evaluation method according to claim 1, wherein in the comparison step, the thickness of the known thickness layer is compared before and after the reaction step over the entire surface of the known thickness layer. The wafer is an SOI wafer in which an oxide film and a silicon layer are formed in this order on a silicon substrate,
The wafer evaluation method according to claim 1, wherein the known thickness layer is the silicon layer.   The in-plane distribution is obtained based on the in-plane distribution of the thickness change amount of the known thickness layer before and after the reaction step obtained by the wafer evaluation method according to claim 1. A process for producing an epitaxial wafer, characterized by obtaining process conditions for uniform epitaxial growth and performing epitaxial growth on a product substrate based on the process conditions.