KR20180127144A - Antenna substrate and semiconductor combined module - Google Patents

Abstract

The present disclosure relates to an antenna substrate and a semiconductor package combined module capable of improving antenna reception sensitivity. A fan-out semiconductor package comprises: a semiconductor chip; an encapsulant sealing at least a part of the semiconductor chip; and a connection member including a rewiring layer electrically connected to a connection pad. The antenna substrate includes an antenna member including an antenna pattern, a ground pattern, and a feeding line and a wiring member including a wiring layer disposed under the antenna member and including a feeding pattern electrically connected to the feeding line.

Description

TECHNICAL FIELD [0001] The present invention relates to an antenna substrate and a semiconductor package composite module,

The present disclosure relates to a composite module in which an antenna substrate and a semiconductor package are combined.

Applications using 10GHz or higher mm-Wave are not only for mobile 5G communication and 60GHz communication, but also motion sensor products that detect motion and increase user's I / F convenience, security motion monitoring sensor Products, 24GHz, 77GHz radar systems for near-field and far-field detection for automobiles. In the case of a product using such an mm-wave, when transmitting signals from an RFIC (Radio Frequency Integrated Circuit) to an antenna, or from an antenna to an RFIC, it is necessary to transmit signals in such a manner that loss of the signal is minimized. In the past, the distance between the RFIC and the antenna was coaxially connected to minimize the signal attenuation. However, this is inefficient in terms of space and cost.

Recently, a 60GHz antenna has been designed with materials such as LTCC (Low Temperature Co-fired Ceramic) in 60GHz communication system and then applied to the RFIC to minimize the distance between components. In the automotive radar system, the RFIC is mounted on the main PCB (Printed Circuit Board) board, and the antenna is formed by connecting the antennas in a pattern on the PCB board or mounting a separate antenna module on the main PCB . However, it is also difficult to sufficiently prevent occurrence of line-to-line loss between the components.

Recently, a package technology has been developed and a method of forming an antenna in a package of an RFIC has been developed. In some cases, a method of forming an antenna pattern in a package's RDL (Re-Distribution Layer) There are some design constraints or there is a possibility of a performance error. Therefore, there is a need for a stable RFIC and antenna integrated package design technology that can flexibly design design freedom and minimize design errors.

One of the objects of the present disclosure is to provide a new type of composite module capable of designing the shortest signal path between the antenna and the semiconductor chip, securing the omnidirectional coverage characteristics, and improving the antenna reception sensitivity.

One of the various solutions proposed through the present disclosure is to composite the module substrate including the semiconductor chip and the antenna substrate including the antenna.

For example, an antenna substrate and a semiconductor package composite module according to an example proposed in the present disclosure may include a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, Out semiconductor package including a seal member for sealing the semiconductor chip and a connection member including a re-wiring layer disposed on the semiconductor chip and electrically connected to the connection pad, and an insulation layer disposed on the insulation layer, A second pattern layer disposed on a lower surface of the insulating layer and including a ground pattern, and a via including a via hole extending through the insulating layer and electrically connected to the antenna pattern, And a wiring pattern disposed at a lower portion of the antenna member and including a feeding pattern electrically connected to the feeding line, Comprising: an antenna board, including a wiring member including the fan-out of a semiconductor package and the antenna substrate on which the connection member and the wiring member may be coupled to each other.

Alternatively, the antenna substrate and the semiconductor package composite module according to an example proposed in the present disclosure may include a core member having a through hole, an active surface disposed in the through hole and having a connection pad disposed thereon, and an inactive surface And a connecting member disposed on the semiconductor chip, wherein the core member and the connecting member are respectively connected to the core wiring layer and the core wiring layer electrically connected to the connection pad, A semiconductor device comprising: a fan-out semiconductor package including a re-wiring layer; and a first pattern layer including an antenna pattern on an upper surface thereof and a second pattern layer including a ground pattern on an upper surface thereof, An antenna member having a via formed therein and including a feeding line electrically connected to the antenna pattern through the insulating layer, And an antenna substrate disposed at a lower portion of the substrate and including a wiring layer including a wiring layer including a feeding pattern electrically connected to the feeding line, wherein the antenna substrate is stacked on the fan-out semiconductor package, The antenna substrate and the fan-out semiconductor package may be connected to each other through the electrical connection structure.

As one of the effects of the present disclosure, it is possible to provide a new type of composite module capable of designing the shortest signal path between the antenna and the semiconductor chip, securing the omnidirectional coverage characteristics, and improving the antenna reception sensitivity have.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of an antenna substrate and a semiconductor package composite module.
FIG. 10 schematically shows a sectional plan view of the antenna substrate and the semiconductor package composite module of FIG. 9 taken along line I-I '.
11 schematically shows various examples of the antenna substrate of the antenna substrate and the semiconductor package composite module of Fig.
FIG. 12 schematically shows an application example of a patch antenna of an antenna substrate and a composite package module of the semiconductor package of FIG. 9; FIG.
13 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
14 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
15 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
16 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
17 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
18 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.
19 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
20 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.
21 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.
22 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.
23 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other electronic components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, An analog-to-digital converter, and a logic chip such as an application-specific IC (ASIC), but the present invention is not limited thereto and other types of chip-related electronic components may be included. It goes without saying that these electronic components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 can be combined with the chip-related electronic component 1020 with each other.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. Of course, other components 1040 may be combined with chip-related electronic components 1020 and / or network-related electronic components 1030 with each other.

Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the mainboard 1010. Examples of other electronic components include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown) (Not shown), a CD (compact disk) (not shown), and a mass storage device (not shown), an accelerometer (not shown), a gyroscope And a digital versatile disk (DVD) (not shown). However, the present invention is not limited thereto, and other electronic components used for various purposes may be included depending on the type of the electronic device 1000 .

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A radio frequency integrated circuit (RF IC) may be applied to the smartphone 1100 in the form of a semiconductor package, and an antenna may be applied in the form of a substrate or a module. The radio frequency integrated circuit and the antenna are electrically connected in the smartphone 1100, so that radiation (R) of the antenna signal in various directions is possible. A semiconductor package including a radio frequency integrated circuit and a substrate or a module including an antenna can be applied to electronic devices such as smart phones in various forms.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the sizes of the connection pads and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic devices, the size of the electronic component mounting pads and the intervals of the electronic component mounting pads It is much bigger. Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connecting member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connecting pad 2122 and the re-wiring layer 2142 .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Antenna substrate and semiconductor package composite module

9 is a cross-sectional view schematically showing an example of an antenna substrate and a semiconductor package composite module.

FIG. 10 schematically shows a sectional plan view of the antenna substrate and the semiconductor package composite module of FIG. 9 taken along line I-I '.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300A according to an exemplary embodiment are formed by combining a fan-out semiconductor package 100A and an antenna substrate 200A. More specifically, the fan-out semiconductor package 100A and the antenna substrate 200A are integrated.

The fan-out semiconductor package 100A includes a core member 110 having a through hole 110H, an active surface disposed in the through hole 110H and having an active surface on which the connection pad 120P is disposed, A passive component 125 disposed in parallel with the semiconductor chip 120 in the through hole 110H and at least a portion of the core member 110 and the semiconductor chip 120 and the passive component 125. [ A connecting member 140 disposed on the active surface of the semiconductor chip 120, an inactive surface of the semiconductor chip 120, and a backside wiring layer 132 disposed on the core member 110, A passivation layer 150 disposed under the sealing material 130, an under bump metal layer 160 connected to the backside wiring layer 132, and an electrical connection structure 170 connected to the under bump metal layer. The core member 110 and the connecting member 140 include core wiring layers 112a and 112b and a redistribution layer 142 electrically connected to the connection pad 120P. The semiconductor chip 120 is face-up disposed toward the antenna substrate 200A.

The antenna substrate 200A includes a first pattern layer 212a including an antenna pattern 212aA on the upper surface thereof and a second pattern layer 212b including a ground pattern 212bG on the lower surface thereof, An antenna member 210 having an insulating layer 211 and a via 213 formed through the insulating layer 211 and including a feeding line 213F electrically connected to the antenna pattern 212aA, A wiring member 220 disposed on a lower portion of the antenna member 210 and including a wiring layer 222 including a feeding pattern 222F electrically connected to a feeding line 213F, And a passivation layer 230 covering the wiring layer 212a. The antenna member 210 is thicker than the wiring member 220.

The wiring member 220 of the antenna substrate 200A and the connecting member 140 of the fan-out semiconductor package 100A come into contact with each other without any separate electrical connection structure or the like. On the other hand, the term "combination" refers to a case where two components are integrated so as to be in contact with each other and a case where two components are stacked by using an intermediary.

Meanwhile, when an antenna is formed as a single composite module together with an RFIC, it is necessary to consider how to implement an antenna, a ground plane, a dielectric material, and a feeding line to determine the resonance frequency and bandwidth of the antenna. For example, the distance between the antenna and the ground plane, which affects the antenna characteristics sensitively, that is, the thickness of the air layer or the thickness of the dielectric material, must be constantly maintained and managed to secure stable radiation characteristics of the antenna.

On the other hand, in the conventional case, an antenna is formed on the rewiring layer of the semiconductor package, and a ground surface is formed on the main board. In this case, the thickness or the distance between the antenna and the ground surface must be secured to the height of the solder ball of the package. Therefore, when the package is mounted on the main board, thickness difference may occur depending on the height of the solder ball. In this case, since the air layer is used as a dielectric material, the size of the antenna is increased. Also, in this case, flux or foreign matter may be inserted into the space between the antenna and the ground plane, and as a result, the characteristics of the antenna may be greatly affected. Further, in this case, when heat is generated in the RFIC, it is difficult to secure a sufficient heat radiation path, and therefore, it is limited to a product using a lot of electric power.

On the other hand, in the case of the antenna substrate and the semiconductor package composite module 300A according to the example, the fan-out semiconductor package 100A in which the semiconductor chip 120 such as an RFIC is packaged in a face-up form is referred to as a dipole antenna, And the antenna substrate 200A including the antenna pattern 212aA of FIG. At this time, the antenna substrate 210A introduces the antenna member 210. The antenna member 210 forms the antenna pattern 212aA and the ground pattern 212bG on both sides with respect to the insulating layer 211, And through the vias 213 penetrating the layer 211 and the like. Therefore, it is possible to maintain the radiation characteristics of the antenna by stably maintaining the distance between the antenna and the ground plane in a single composite module regardless of external environment change. Nevertheless, by minimizing the signal path between the antenna and the semiconductor chip, .

It is also possible to miniaturize the size of the antenna by appropriately using the dielectric constant Dk of the insulating layer 211 of the antenna member 210 and the dielectric constant Dk of the insulating layer 211 of the core member 110, It is possible to reduce the cost while improving the spatial efficiency. It is also possible to prevent deterioration of antenna performance due to the influence of foreign matter on the antenna and the ground plane space. In addition, the rigidity of the module 300A can be added by introducing the core member 110, and the electrical connection structure 170 for connecting the core member 110 to the main board or the like by providing an electrical connection path, It is possible to effectively provide a signal path in the module up to the time of the present invention. In addition, since passive components 125 are embedded in the fan-out semiconductor package 100A together with the semiconductor chip 120, it is also possible to minimize the loss of signals and power.

Hereinafter, components of the antenna substrate and the semiconductor package composite module 300A according to an example will be described in more detail with reference to the drawings.

First, the fan-out semiconductor package 100A includes a core member 110 having a through hole 110H, an active surface disposed on the through hole 110H and having an active surface on which the connection pad 120P is disposed, A passive component 125 disposed in parallel with the semiconductor chip 120 in the through hole 110H, a core member 110 and a semiconductor chip 120, and a passive component A connecting member 140 disposed on the active surface of the semiconductor chip 120, a non-active surface of the semiconductor chip 120, and a sealing member 130 disposed on the core member 110. The seal member 130 seals at least a part of the semiconductor chip 120, A passivation layer 150 disposed under the sealing material 130, an under bump metal layer 160 connected to the backside wiring layer 132, and an electrical connection structure 170 connected to the under bump metal layer. do. The core member 110 and the connecting member 140 include core wiring layers 112a and 112b and a redistribution layer 142 electrically connected to the connection pad 120P.

The core member 110 can reduce the number of the bar connecting members 140 including the core wiring layers 112a and 112b. The rigidity of the package 100A can be further improved according to the specific material, and the function of securing the thickness uniformity of the sealing material 130 can be performed. An electrical path may be provided in the module 300A by the core wiring layers 112a and 112b and the core vias 113 of the core member 110. [ The core member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 and the passive components 125 are arranged in parallel so as to be spaced apart from the core member 110 by a predetermined distance. The periphery of the side surfaces of the semiconductor chip 120 and the passive component 125 may be surrounded by the core member 110. However, it is to be understood that the present invention is not limited thereto and various modifications may be made in other forms, and other functions may be performed according to the forms.

The core member 110 includes a dielectric layer 111, a first core wiring layer 112a disposed on the upper surface of the dielectric layer 111, a second core wiring layer 112b disposed on the lower surface of the dielectric layer 111, And core vias 113 connecting the first and second core wiring layers 112a and 112b. The first and second core wiring layers 112a and 112b of the core member 110 may be thicker than the re-wiring layer 142 of the connecting member 140. [ The core member 110 may have a thickness similar to or greater than that of the semiconductor chip 120 and the first and second core wiring layers 112a and 112b may be formed to have a larger size through the substrate process . On the other hand, the redistribution layer 142 of the connection member 140 can be formed in a smaller size through a semiconductor process for thinning.

The material of the dielectric layer 111 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a glass fiber, a glass cloth, or a glass fabric together with an inorganic filler, Such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (bismaleimide triazine), etc., can be used. If desired, a photosensitive insulator (PID) resin may be used. For example, low Df & Low Dk general copper clad laminate (CCL) or low Df & High Dk glass or ceramic type insulating material can be applied as the material of the dielectric layer 111, depending on the required material properties.

The core wiring layers 112a and 112b can perform the role of rewiring the connection pads 120P of the semiconductor chip 120. [ It can also be used as a connection pattern when electrically connecting the fan-out semiconductor package 100A with other components at the top and bottom. The core wiring layers 112a and 112b may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium ), Or alloys of these materials may be used. The core wiring layers 112a and 112b can perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad or the like may be included.

The core vias 113 electrically connect the core wiring layers 112a and 112b formed in the different layers, thereby forming an electrical path in the core member 110. [ The core vias 113 may also be formed of copper, aluminum, silver, tin, gold, nickel, lead, titanium, Or an alloy thereof may be used. The core via 113 may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. Further, any known shape such as an hourglass shape or a cylindrical shape can be applied. Core vias 113 may also include vias for signals, vias for ground, and the like.

The metal layer 115 may be further disposed on the wall surface of the through hole 110H of the core member 110 as needed. The metal layer 115 may be formed on the wall surface of the through hole 110H to surround the semiconductor chip 120. [ As a result, the heat dissipation characteristics can be improved, and the electromagnetic wave shielding effect can be obtained. The metal layer 115 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The metal layer 115 may be electrically connected to the ground pattern of the first core wiring layer 112a and / or the second core wiring layer 112b to be used as a ground plane.

Semiconductor chip 120 may be a bare state integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit (IC) may be, for example, a Radio-Frequency Integrated Circuit (RFIC). That is, the antenna substrate and the semiconductor package composite module 300A according to an example may be a package in which the RFIC and the mmWave / 5G antenna are integrated. The semiconductor chip 120 may include a body having various circuits, and a connection pad 120P may be formed on the active surface of the body. The body may be formed based on, for example, an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs) or the like may be used as the base material. The connection pad 120P is for electrically connecting the semiconductor chip 120 to other components. The connection pad 120P may be formed of a conductive material, preferably aluminum (Al), but is not limited thereto. In the semiconductor chip 120, the surface on which the connection pad 120P is disposed becomes the active surface and the surface on the opposite side becomes the inactive surface. A passivation film (not shown) composed of an oxide film and / or a nitride film having an opening for exposing at least a part of the connection pad 120P may be formed on the active surface of the semiconductor chip 120, though not shown in the figure. The semiconductor chip 120 is disposed in a face-up fashion and thus can have a minimum signal path to the antenna.

The passive component 125 is disposed in parallel with the semiconductor chip 120 in the through hole 110H. The passive component 125 may be a known passive component such as a capacitor, an inductor, or the like. As a non-limiting example, the passive component 125 may be a capacitor. The passive component 125 may be electrically connected to the semiconductor chip 120 through the connection member 140. [ Also, it can be electrically connected to the antenna substrate 200A through the connecting member 140. [ The number of passive components 125 is not particularly limited.

The sealing member 130 is a structure for protecting the semiconductor chip 120, the passive components 125, and the like and providing an insulating region. The sealing shape is not particularly limited and may be a shape that covers at least a part of the semiconductor chip 120 and the passive component 125. For example, the sealing member 130 may cover the lower surface of the core member 110, cover the side surface and the inactive surface of the semiconductor chip 120, and may cover the side surface and the lower surface of the passive component 125 . In addition, the space in the through hole 110H can be filled. The material of the sealing material 130 is not particularly limited. For example, PIE (Photo Imageable Encapsulant) can be used. Other, fill, therefore, an insulating material such as ABF may be used.

The backside wiring layer 132 may serve as a wiring for rewiring the connection pads 120P of the semiconductor chip 120. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn) , Gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The backside wiring layer 132 may perform various functions according to the design design of the layer. For example, a ground pattern, a signal pattern, and the like. It may also include via pads, electrical connection structure pads, and the like.

The backside via 133 electrically connects the backside wiring layer 132 and the second core wiring layer 112b formed in different layers. In addition, if necessary, the backside via 133 may be connected to the metal layer 122 formed on the inactive surface of the semiconductor chip 120 and utilized as a heat radiation via. The backside via 133 may also be formed of copper, aluminum, silver, tin, gold, nickel, lead, titanium, Or an alloy thereof may be used. The backside via 133 may also be completely filled with a conductive material, or the conductive material may be formed only along the walls of the via. Further, any known shape such as a taper shape, a cylindrical shape, or the like can be applied.

The connection member 140 may rewire the connection pad 120P of the semiconductor chip 120. [ The connection pads 120P of several hundreds of semiconductor chips 120 having various functions can be rewired through the connecting member 140, respectively. The connection member 140 provides a connection path so that the bar-out semiconductor package 100A connected to the wiring member 220 and the antenna substrate 200A can be integrated. The connecting member 140 includes an insulating layer 141, a redistribution layer 142 disposed on the insulating layer 141, and a via 143 connected to the redistribution layer 142 through the insulating layer 141 . The connecting member 140 may be composed of a single layer or may be designed in a plurality of layers in the figure.

As the material of the insulating layer 141, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitivity, the insulating layer 141 can be made thinner and the pitch of the via 143 can be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 has multiple layers, these materials may be the same as each other and may be different from each other as needed. If the insulating layers 141 are multilayered, they may be unified according to the process, and the boundaries may be unclear.

The re-distribution layer 142 may serve to rewire the connection pad 120P. The re-distribution layer 142 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The re-distribution layer 142 may perform various functions according to the design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include via pads, connection terminal pads, and the like. The redistribution layer 142 may include a feeding pattern electrically connected to the feeding line 223F.

The vias 143 electrically connect the re-wiring layer 142, the connection pads 120P, and the like formed in the different layers, thereby forming an electrical path in the package 100A. The via 143 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The vias 153 may be completely filled with a conductive material, or a conductive material may be formed along the walls of the vias. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied. The via 143 includes a feeding line that is electrically connected to the feeding line 223F.

The passivation layer 150 can protect the backside wiring layer 132 from external physical chemical damage or the like. The passivation layer 150 includes an insulating resin and an inorganic filler, but may not include glass fibers. For example, the passivation layer 150 may be ABF, but is not limited thereto, and may be a PID, a solder resist, or the like.

The under bump metal layer 160 improves the connection reliability of the electrical connection structure 170, thereby improving the board level reliability of the package 100A. The underbump metal layer 160 is connected to various pads for the electrical connection structure of the backside interconnect layer 132 exposed through the openings of the sealant 130 and / or the passivation layer 150. The under bump metal layer 160 may be formed on the opening of the sealing material 130 by a known metallization method using a known conductive material, that is, metal, but is not limited thereto.

The electrical connection structure 170 is an additional structure for physically and / or electrically connecting the semiconductor package 100A with the outside. For example, the semiconductor integrated package 100A with an antenna can be mounted on the main board of the electronic device through the electrical connection structure 170. The electrical connection structure 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The electrical connection structure 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. . The number, spacing, arrangement type, etc. of the electrical connection structures 170 are not particularly limited and can be sufficiently modified according to design specifications for a typical engineer. For example, the number of electrical connection structures 170 may be several tens to several thousands depending on the number of connection pads 120P, and may have a number greater than or less than the number.

At least one of the electrical connection structures 170 is disposed in the fan-out area. The fan-out area means an area outside the area where the semiconductor chip 120 is disposed. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. Compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to make package thickness thinner and excellent price competitiveness.

The antenna substrate 200A includes a first pattern layer 212a including an antenna pattern 212aA on the upper surface thereof and a second pattern 212b including a ground pattern 212bG on the lower surface thereof, An antenna member 210 in which a layer 212b is disposed and the via 213 including the insulating layer 211 and the feeding line 213F electrically connected to the antenna pattern 212aA is formed in the insulating layer 211, A wiring member 220 disposed on the lower portion of the antenna member 210 and including a wiring layer 222 including a feeding pattern 222F electrically connected to the feeding line 213F, And a passivation layer 230 covering the first wiring layer 212a. The antenna member 210 is thicker than the wiring member 220. The wiring member 220 and the connecting member 140 are in contact with each other without a separate electrical connection structure or the like. The antenna substrate 200A has an asymmetric structure with respect to the antenna member 210.

The antenna member 210 is an area capable of realizing an mmWave / 5G antenna and includes an insulating layer 211, a first pattern layer 212a formed on the upper surface of the insulating layer, a second pattern layer 212b formed on the lower surface of the insulating layer 211, And a via 213 for electrically connecting the first and second pattern layers 212a and 212b through the insulating layer 211. [ The antenna member 210 is formed such that the first pattern layer 212a includes the antenna pattern 212aA and the second pattern layer 212b includes the ground pattern 212bG and the insulating layer 211 is disposed therebetween Therefore, the distance between the antenna and the ground plane can be stably secured within a single composite module regardless of changes in the external environment, thereby maintaining the radiation characteristic of the antenna. Also, by appropriately using the dielectric constant Dk of the insulating layer 211, the size of the antenna can be miniaturized to reduce the structure of the entire module, thereby improving the spatial efficiency and reducing the cost. For example, the dielectric constant Dk of the insulating layer 211 of the antenna member 210 may be higher than the dielectric constant Dk of the dielectric layer 111 of the core member 110. The dielectric constant Dk of the insulating layer 211 of the antenna member 210 may be higher than that of other insulating layers or dielectric layers in the module 300A.

As the material of the insulating layer 211, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a glass fiber, a glass cloth, a glass fabric For example, prepregs, Ajinomoto Build-up Film (ABF), FR-4, BT (Bismaleimide Triazine) and the like may be used. For example, as the material of the insulating layer 211, a general copper-clad laminate (CCL) of Low Df & Low Dk or a glass or ceramic-based insulating material of Low Df & High Dk can be applied according to required material properties. It is possible to form an antenna capable of downsizing as compared with the case of using the high Dk & Low Df material such as glass or ceramic as the material of the insulating layer 211. The thickness of the insulating layer 211 can be freely changed in accordance with the impedance matching characteristic.

The first wiring layer 212a includes an antenna pattern 212aA that realizes an mmWave / 5G antenna or the like, and may include other ground patterns 212aG and the like. The antenna pattern 212aA may be a dipole antenna, a patch antenna, or the like. The periphery of the antenna pattern 212aA may be surrounded by a ground pattern, but is not limited thereto. The first wiring layer 212a may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Or an alloy thereof can be used.

The second wiring layer 212b includes a ground pattern 212bG for the antenna pattern 212aA, and may include other signal patterns and the like. The ground pattern 212bG may be in the form of a ground plane. The second wiring layer 212b may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Or an alloy thereof can be used.

The vias 213 electrically connect the first and second pattern layers 212a and 212b formed in the different layers and thus provide an electrical path within the antenna member 210. Vias 213 include a feed line 213F, and may include other ground vias 213G and the like. The feeding line 213F is electrically connected to the antenna pattern 212aA. The ground vias 213G can tightly surround the feeding line 213F. Examples of the material for forming the vias 213 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The via 213 may be completely filled with the conductive material, or unlike the drawing, the conductive material may be formed along the wall surface of the via hole. Any known vertical cross-sectional shape such as a cylindrical shape, an hourglass shape, or a taper shape may be applied.

The wiring member 220 electrically connects the wiring layer 222 formed on the different layers through the insulating layer 221 and the wiring layer 222 formed on the insulating layer 221 and the insulating layer 221, 222 electrically connected to the pattern layer or the rewiring layer of the other member. The wiring member 220 may have a larger number of wiring layers, or may have only one wiring layer.

As the material of the insulating layer 221, an insulating material may be used. As the insulating material, Ajinomoto Build-up Film (ABF), Photo Image Binary Dielectric (PID), or the like may be used. When there are a plurality of insulating layers 221, the boundaries of the respective layers may be unclear, but the present invention is not limited thereto.

The wiring layer 222 includes a feeding pattern 222F electrically connected to the feeding line 213F and may include other ground patterns 222G and the like. The wiring layer 222 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used.

The vias 223 electrically connect the wiring layers 222 formed on different layers or electrically connect the wiring layers 222 with pattern layers or rewiring layers of other members to provide an electrical path. The via 223 includes a feeding line 223F that is electrically connected to the feeding pattern 222F. As the material for forming the via 223, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used.

The passivation layer 230 may protect the antenna member 210 from external physical chemical damage or the like. The passivation layer 230 includes an insulating resin and an inorganic filler, but may not include glass fibers. For example, the passivation layer 150 may be ABF, but is not limited thereto, and may be a PID, a solder resist, or the like.

11 schematically shows various examples of the antenna substrate of the antenna substrate and the semiconductor package composite module of Fig.

Referring to the drawings, the antenna substrate 200A may be configured to include a plurality of dipole antennas 210DA and a plurality of patch antennas 210PA. Alternatively, it may be a form including a larger number of patch antennas 210PA. That is, the antenna substrate 200A may include various types of antennas depending on the design.

FIG. 12 schematically shows an application example of a patch antenna of an antenna substrate and a composite package module of the semiconductor package of FIG. 9; FIG.

Referring to the drawing, the patch antenna 210PA may have a shape surrounded by a ground via 213G in which an antenna pattern 212bA and a feeding line 213F are closely formed. An insulating material such as the passivation layer 230 may be disposed between the antenna pattern 212bA and the ground vias 213G. The feeding line 213F may be electrically connected to the feeding pattern 222F and, as a result, may be electrically connected to the connection pad 120P.

13 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300B according to another example have a form in which an antenna substrate 200B and a semiconductor package 100B are integrated. The semiconductor package 100B includes a first dielectric layer 111a in contact with the connection member 140 and a first core core wiring layer in contact with the connection member 140 and embedded in the first dielectric layer 111a, A second core core wiring layer 112b disposed on the opposite side of the first dielectric layer 111a on the side where the first core core wiring layer 112a is buried, a second core core wiring layer 112b disposed on the first dielectric layer 111a, A second dielectric layer 111b covering the core wiring layer 112b and a third core core wiring layer 112c disposed on the second dielectric layer 111b. The first to third core core wiring layers 112a, 112b and 112c are electrically connected to the connection pad 120P. The first and second core core wiring layers 112a and 112b and the second and third core core wiring layers 112b and 112c are formed of first and second core layers 112a and 111b penetrating through the first and second dielectric layers 111a and 111b, And are electrically connected through vias 113a and 113b. At least one of the first to third core wiring layers 112a, 112b and 112c may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, The insulating material of the core member 110 may be a material having a low dielectric constant for minimizing the filter loss, but the present invention is not limited thereto.

The step generated by the thickness of the first core core wiring layer 112a is minimized when the first core core wiring layer 112a is buried in the first dielectric layer 111a, It becomes. That is, the distance from the first rewiring layer 142a of the connecting member 140 to the lower surface of the first dielectric layer 111a and the distance from the first rewiring layer 142a of the connecting member 140 to the connection of the semiconductor chip 120 The difference in distance to the pad 120P may be smaller than the thickness of the first core core wiring layer 112a. Therefore, high-density wiring design of the connecting member 140 can be facilitated.

The distance between the re-wiring layer 142 of the connecting member 140 and the first core core wiring layer 112a of the core member 110 is larger than the distance between the re-wiring layer 142 of the connecting member 140 and the connection pad 120P. ≪ / RTI > This is because the first core core wiring layer 112a can be recessed into the first dielectric layer 111a. When the first core core wiring layer 112a is recessed into the first dielectric layer 111a and the upper surface of the first dielectric layer 111a and the upper surface of the first core core wiring layer 112a have a step, It is possible to prevent the first core core wiring layer 112a from being contaminated by bleeding of the first core core wiring layer 112a. The second core core wiring layer 112b of the core member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The second core core wiring layer 112b formed in the core member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120, And may be disposed at a level between the inactive surfaces.

The thickness of the core core wiring layers 112a, 112b and 112c of the core member 110 may be thicker than the thickness of the re-wiring layer 142 of the connecting member 140. [ The core member 110 may have a thickness greater than that of the semiconductor chip 120 and the core core wiring layers 112a, 112b, and 112c may be formed to have a larger size in accordance with the scale. On the other hand, the redistribution layer 142 of the connection member 140 may be formed in a relatively smaller size than the core core wiring layers 112a, 112b, and 112c for thinning.

The material of the dielectric layers 111a and 111b is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler, or a glass fiber Such as a prepreg, an Ajinomoto Build-up Film (ABF), a bismaleimide triazine (BT), or the like, may be used. If desired, a photosensitive insulator (PID) resin may be used.

The core core wiring layers 112a, 112b and 112c may serve to re-wire the connection pads 120P of the semiconductor chip 120. [ The core core wiring layers 112a, 112b and 112c are formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni) Titanium (Ti), or an alloy thereof may be used. The core core wiring layers 112a, 112b and 112c can perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include signal via pads, ground via pads, and the like.

The core core vias 113a and 113b electrically connect the core core wiring layers 112a, 112b, and 112c formed in different layers, thereby forming an electrical path in the core member 110. [ The core core vias 113a and 113b may also be formed of a conductive material. The core core vias 113a and 113b may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. In addition, not only tapered but also all known shapes such as a cylindrical shape can be applied. A part of the pads of the first core core wiring layer 112a may serve as a stopper when the holes for the first core core vias 113a are formed. It is advantageous in terms of the process that the width is larger than the width of the upper surface. In this case, the first core core via 113a can be integrated with the pad pattern of the second core core wiring layer 112b. In addition, when forming a hole for the second core core via 113b, some pads of the second core core wiring layer 112b can serve as stoppers, and the second core core via 113b It is advantageous in terms of the process that the width of the lower surface is larger than the width of the upper surface. In this case, the second core core via 113b can be integrated with the pad pattern of the third core core wiring layer 112c.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example.

14 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300C according to another example have a form in which an antenna substrate 200C and a semiconductor package 100C are integrated. At this time, in the semiconductor package 100C, the core member 110 includes a first dielectric layer 111a, a first core wiring layer 112a and a second core wiring layer 112b disposed on both surfaces of the first dielectric layer 111a, A second dielectric layer 111b disposed on the insulating layer 112a and covering the first core wiring layer 112a, a third redistribution layer 111c disposed on the second dielectric layer 111b, A third dielectric layer 111c disposed on the third dielectric layer 111c and covering the second core wiring layer 112b and a fourth core wiring layer 112d disposed on the third dielectric layer 111c. The first to fourth core wiring layers 112a, 112b, 112c, and 112d are electrically connected to the connection pad 120P. Since the core member 110 includes a larger number of core wiring layers 112a, 112b, 112c and 112d, the connecting member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the connecting member 140. The first through fourth core wiring layers 112a 112b 112c and 112d have first through third core vias 113a 113b and 113c passing through the first through third dielectric layers 111a 111b and 111c, As shown in FIG. At least one of the first to fourth core wiring layers 112a, 112b, 112c, and 112d may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, 210 may be made of a high dielectric constant material for miniaturization of the antenna and a low dielectric constant material may be used for the insulation material of the core member 110 to minimize filter loss.

The first dielectric layer 111a may be thicker than the second dielectric layer 111b and the third dielectric layer 111c. The first dielectric layer 111a may be relatively thick for maintaining stiffness and the second dielectric layer 111b and the third dielectric layer 111c may be formed to have a larger number of core wiring layers 112c and 112d Lt; / RTI > The first dielectric layer 111a may include an insulating material different from the second dielectric layer 111b and the third dielectric layer 111c. For example, the first dielectric layer 111a may be a prepreg, for example, comprising a core material, a filler, and an insulating resin, and the second dielectric layer 111c and the third dielectric layer 111c may include fillers and insulating resin But is not limited to, an ABF film or a PID film. The first core via 113a passing through the first dielectric layer 111a has a diameter greater than that of the second and third core vias 113b and 113c passing through the second and third dielectric layers 111b and 111c It can be big.

The distance between the redistribution layer 142 of the connection member 140 and the third core wiring layer 112c of the core member 110 is set to be shorter than the distance between the redistribution layer 142 of the connection member 140 and the connection pads 120P As shown in FIG. The third core wiring layer 112c may be disposed on the second dielectric layer 111b so as to be in contact with the connection member 140. [ The first core wiring layer 112a and the second core wiring layer 112b of the core member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first core wiring layer 112a and the second core wiring layer 112b formed in the core member 110 may be formed to correspond to the thickness of the semiconductor chip 120, ) Between the active surface and the inactive surface.

The thickness of the core wiring layers 112a, 112b, 112c and 112d of the core member 110 may be thicker than the thickness of the re-wiring layer 142 of the connecting member 140. [ The core member 110 may have a thickness greater than that of the semiconductor chip 120 and the core wiring layers 112a, 112b, 112c, and 112d may also be formed in a larger size. On the other hand, the redistribution layer 142 of the connection member 140 can be formed in a relatively smaller size for thinning.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example.

15 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, the antenna substrate and the semiconductor package composite module 300D according to another example have a form in which the antenna substrate 200D and the semiconductor package 100D are integrated. At this time, in the antenna substrate 200D, the wiring layer 222 of the wiring member 220 includes the filter pattern 222R. The filter pattern 222R is electrically connected to the feeding line 213F, the feeding pattern 222F, and the like. The filter pattern 222R may be, but is not limited to, a microstrip line or a stripline. The filter pattern 222R may be appropriately formed in various layers of the wiring member 220. [ As the insulating material of the antenna member 210, a material having a high dielectric constant (Er1) characteristic may be used to reduce the antenna size. As the insulating material of the wiring member 220, a low dielectric constant (Er12) Can be used. The ground pattern 212bG of the antenna member 210 and / or the ground pattern 222G of the wiring member 220 may provide a ground plane for the filter pattern 222R.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example. It goes without saying that the antenna substrate and the semiconductor package composite module 300D according to other examples may be applied to the antenna substrate and the semiconductor package modules 300B and 300C according to other examples.

16 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300E according to another example have a form in which an antenna substrate 200E and a semiconductor package 100E are integrated. At this time, the semiconductor package 100E is formed such that the third wiring layer 112c and the third wiring layer 112c, in which the core member 110 is buried in the dielectric layer 111, are electrically and electrically connected to the first and second wiring layers 112a and 112b, And second and third core vias 113b and 113c connecting the first and second core vias 113a and 113b. The third wiring layer 112c includes a filter pattern 112cR. The filter pattern 112cR is electrically connected to the feeding line 213F, the feeding pattern 222F, and the like. The filter pattern 112cR may be, but is not limited to, a microstrip line or strip line. The ground pattern of the first and second wiring layers 112a and 112b of the core member 110 may provide a ground plane for the filter pattern 112cR. The semiconductor chip 120 is disposed in a face-down fashion. When the semiconductor chip 120 is disposed in a face-down configuration, the active surface is closer to the main board, so that it can have a high heat radiation effect to the main board. The metal layer 122 formed on the inactive surface of the semiconductor chip 120 may be replaced with a die attach film as occasion demands.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example. It goes without saying that the antenna substrate and the semiconductor package composite module 300E according to other examples may be applied to the antenna substrate and the semiconductor package modules 300B and 300C according to other examples. In this case, the wiring layer of the core member disposed therein may be in a form including the filter pattern.

17 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300F according to another example have a form in which an antenna substrate 200F and a semiconductor package 100F are integrated. The antenna substrate 200F according to another exemplary embodiment may be formed by first forming the antenna substrate 200F and bonding the semiconductor chip 120 on the wiring member 220 of the antenna substrate 200F with a bump And the semiconductor package 100F is formed by forming a backside wiring layer 132 and a backside via 133 in addition to the semiconductor package 100F. That is, the composite module 300F integrated with the so-called chip-last method is manufactured. Therefore, the connecting member 140 of the semiconductor package 100F is integrated into the wiring member 220 of the antenna substrate 200F. That is, as shown in the drawing, a part of the wiring member 220 serves as the connecting member 140. That is, the wiring member 220 includes the connecting member 140. In this case, the semiconductor package 100F may not include the core member 110, and the upper and lower electrical connection paths may be provided through the through vias 117 passing through the sealing material 130. [

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example.

18 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.

Referring to the drawings, an antenna substrate and a semiconductor package composite module 300G according to another example have a form in which an antenna substrate 200G and a semiconductor package 100G are integrated. Meanwhile, the antenna substrate and the semiconductor package composite module 300G according to another example are arranged such that the semiconductor chip 120 of the semiconductor package 100G is disposed in face-down fashion, 200G via the die attach film 128. The die attach film 128 is attached to the wiring members 220 of the semiconductor devices 200A, 200G. When the semiconductor chip 120 is disposed in a face-down configuration, the active surface is closer to the main board, so that it can have a high heat radiation effect to the main board. Also in this case, the connecting member 140 of the semiconductor package 100G is integrated into the wiring member 220 of the antenna substrate 200G. That is, as shown in the drawing, a part of the wiring member 220 serves as the connecting member 140. That is, the wiring member 220 includes the connecting member 140. In this case, the semiconductor package 100G may not include the core member 110, and the upper and lower electrical connection paths may be provided through the through vias 117 passing through the sealing material 130.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example.

19 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, in an antenna substrate and a semiconductor package composite module 300H according to another example, an antenna substrate 200H and a semiconductor package 100H are coupled in a package-on-package (PoP) form. The antenna substrate 200H further includes a second wiring member 240 including an insulating layer 241 and a wiring layer 242 and a via 243 under the first wiring member 220. [ Passivation layers 190 and 250 are disposed on the connection member 140 and the second wiring member 240, respectively. The connection member 140 of the semiconductor package 100H and the second wiring member 240 of the antenna substrate 200H are electrically connected through the electrical connection structure 180 such as a solder ball.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example.

20 is a cross-sectional view schematically showing another example of an antenna substrate and a semiconductor package composite module.

Referring to the drawings, the antenna substrate and the semiconductor package composite module 300I according to another exemplary embodiment, like the antenna substrate and the semiconductor package composite module 300B according to another example described above, includes a core member 110, A first dielectric layer 111a in contact with the connection member 140, a first core core wiring layer 112a in contact with the connection member 140 and embedded in the first dielectric layer 111a, a first core core layer 112b of the first dielectric layer 111a, A second dielectric layer 111b disposed on the first dielectric layer 111a and covering the second core core wiring layer 112b, and a second dielectric layer 111b covering the second core core wiring layer 112b. The second core core wiring layer 112b is disposed on the opposite side of the side where the wiring layer 112a is embedded. And a third core core wiring layer 112c disposed on the second dielectric layer 111b. The first to third core core wiring layers 112a, 112b and 112c are electrically connected to the connection pad 120P. The first and second core core wiring layers 112a and 112b and the second and third core core wiring layers 112b and 112c are formed of first and second core layers 112a and 111b penetrating through the first and second dielectric layers 111a and 111b, And are electrically connected through vias 113a and 113b. At least one of the first to third core wiring layers 112a, 112b and 112c may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, The insulating material of the core member 110 may be a material having a low dielectric constant for minimizing the filter loss, but the present invention is not limited thereto.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example, and the antenna substrate and semiconductor package composite modules 300B and 300H according to another example.

21 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.

Referring to the drawings, the antenna substrate and the semiconductor package composite module 300J according to another exemplary embodiment, like the antenna substrate and the semiconductor package composite module 300C according to another example described above, include the core member 110, A first core wiring layer 112a and a second core wiring layer 112b disposed on both sides of the first dielectric layer 111a and a first core wiring layer 112b disposed on the first insulation layer 112a, A third re-distribution layer 111c disposed on the second dielectric layer 111b; a third re-distribution layer 111b disposed on the first dielectric layer 111a to cover the second core wiring layer 112b; A dielectric layer 111c, and a fourth core wiring layer 112d disposed on the third dielectric layer 111c. The first to fourth core wiring layers 112a, 112b, 112c, and 112d are electrically connected to the connection pad 120P. Since the core member 110 includes a larger number of core wiring layers 112a, 112b, 112c and 112d, the connecting member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the connecting member 140. The first through fourth core wiring layers 112a 112b 112c and 112d have first through third core vias 113a 113b and 113c passing through the first through third dielectric layers 111a 111b and 111c, As shown in FIG. At least one of the first to fourth core wiring layers 112a, 112b, 112c, and 112d may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, 210 may be made of a high dielectric constant material for miniaturization of the antenna and a low dielectric constant material may be used for the insulation material of the core member 110 to minimize filter loss.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package complex module 300A according to the above-described example, and the antenna substrate and semiconductor package complex modules 300C and 300H according to another example.

22 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.

The antenna substrate 200 and the semiconductor package composite module 300K according to another exemplary embodiment are similar to the antenna substrate and the semiconductor package composite module 300D according to another example described above, The wiring layer 222 includes a filter pattern 222R. The filter pattern 222R is electrically connected to the feeding line 213F, the feeding pattern 222F, and the like. The filter pattern 222R may be, but is not limited to, a microstrip line or a stripline. The ground pattern 212bG of the antenna member 210 and / or the ground pattern 222G of the wiring member 220 may provide a ground plane for the filter pattern 222R.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described exemplary embodiment and the antenna substrate and semiconductor package composite module 300D according to another example. It goes without saying that the antenna substrate and the semiconductor package composite module 300K according to other embodiments may be applied to the antenna substrate and the semiconductor package composite module 300K according to another example of the shape of the core member 110 described in the antenna substrate and the semiconductor package modules 300I and 300J.

23 is a cross-sectional view schematically showing another example of the antenna substrate and the semiconductor package composite module.

Referring to the drawings, the antenna substrate and the semiconductor package composite module 300L according to another example are arranged in a face-down fashion. When the semiconductor chip 120 is disposed in a face-down configuration, the active surface is closer to the main board, so that it can have a high heat radiation effect to the main board. A connecting member 140 is disposed on the active surface of the semiconductor chip 120 and a backside wiring 132 and a backside via 133 are disposed on the inactive surface. The metal layer 122 formed on the inactive surface of the semiconductor chip 120 may be replaced with a die attach film as occasion demands.

Other configurations are substantially the same as those described in the antenna substrate and semiconductor package composite module 300A according to the above-described example, and the antenna substrate and the semiconductor package composite module 300H according to another example. It is needless to say that the antenna substrate and the semiconductor package composite module 300L according to another example may be applied to the antenna substrate and the semiconductor package modules 300I and 300J according to another example.

The expression " bond " used in the present disclosure is a concept including two cases where the two elements are integrated so as to be in contact with each other and a case where the two elements are laminated using the medium.

The expression " exemplary " used in this disclosure does not mean the same embodiment but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude that they are implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

In the present disclosure, the meaning of being connected is not a direct connection but a concept including an indirect connection. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. For example, a case where a signal is not physically connected but is connected to a signal. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

In the present disclosure, upper, lower, upper, lower, upper, lower, and the like are determined based on the attached drawings. For example, the first connecting member is located above the re-wiring layer. However, the claims are not limited thereto. In addition, the vertical direction means the above-mentioned upper and lower direction, and the horizontal direction means the direction perpendicular thereto. In this case, the vertical cross-section means a case of cutting into a plane in the vertical direction, and the cross-sectional view shown in the figure is an example. In addition, the horizontal cross-section means a case where the horizontal cross-section is cut into a plane in the horizontal direction, for example, the plan view shown in the drawing.

Claims (22)

A semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a seal member for sealing at least a part of the semiconductor chip, and a sealing member disposed on the semiconductor chip, A connecting member including a re-wiring layer connected thereto; And
A first pattern layer disposed on the insulating layer and on the insulating layer, the first pattern layer including an antenna pattern; a second pattern layer disposed on a lower surface of the insulating layer and including a ground pattern; An antenna member including a via including a feeding line connected to the antenna member, and a wiring member including a wiring layer disposed below the antenna member and including a feeding pattern electrically connected to the feeding line; / RTI >
Wherein the fan-out semiconductor package and the antenna substrate are connected to each other with the connecting member and the wiring member facing each other,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the semiconductor chip comprises a radio frequency integrated circuit (RFIC)
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the antenna pattern comprises at least one of a dipole antenna and a patch antenna.
Antenna Substrate and Semiconductor Package Composite Module.
The method of claim 3,
Wherein the patch antenna and the feeding line connected to the patch antenna are surrounded by ground vias passing through an insulating layer of the antenna member,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the semiconductor chip is face-up arranged such that the active surface faces the wiring member,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein a wiring layer of the wiring member includes a filter pattern electrically connected to the feeding line,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the antenna substrate is integrated with the fan-out semiconductor package,
Antenna Substrate and Semiconductor Package Composite Module.
8. The method of claim 7,
Wherein the connecting member and the wiring member are integrated with each other,
Antenna Substrate and Semiconductor Package Composite Module.
9. The method of claim 8,
The rewiring layer of the connecting member and the wiring layer of the wiring member are electrically connected to each other through vias of the wiring member,
Antenna Substrate and Semiconductor Package Composite Module.
8. The method of claim 7,
Wherein the connecting member is integrated with the wiring member,
Antenna Substrate and Semiconductor Package Composite Module.
11. The method of claim 10,
Wherein the fan-out semiconductor package further comprises through vias through the sealing material and electrically connected to the wiring layer of the wiring member,
Antenna Substrate and Semiconductor Package Composite Module.
11. The method of claim 10,
Wherein the semiconductor chip is mounted on the wiring member through a bump,
Antenna Substrate and Semiconductor Package Composite Module.
11. The method of claim 10,
Wherein the semiconductor chip is face-down disposed such that the inactive surface faces the wiring member,
Wherein the inactive surface of the semiconductor chip is attached to the wiring member via a die attach film,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the antenna substrate is laminated on the fan-out semiconductor package,
Wherein the antenna substrate and the fan-out semiconductor package are connected to each other through an electrical connection structure,
Antenna Substrate and Semiconductor Package Composite Module.
The method according to claim 1,
Wherein the fan-out semiconductor package further comprises a core member having a through-hole,
Wherein the semiconductor chip is disposed on the core member,
Wherein the core member comprises at least one core wiring layer electrically connected to the connection pad,
Antenna Substrate and Semiconductor Package Composite Module.
16. The method of claim 15,
Wherein the fan-out semiconductor package further comprises a passive component that is disposed in parallel with the semiconductor chip in the through-hole and is electrically connected to the connection pad through a re-wiring layer of the connection member.
Antenna Substrate and Semiconductor Package Composite Module.
16. The method of claim 15,
Wherein the core wiring layer of the core member includes a filter pattern electrically connected to the feeding line,
Antenna Substrate and Semiconductor Package Composite Module.
16. The method of claim 15,
The core member includes a first dielectric layer in contact with the connecting member, a first core wiring layer in contact with the connecting member and embedded in the first dielectric layer, and a second core wiring layer disposed on the opposite side of the first dielectric layer, And a first core via electrically connecting the first and second core wiring layers through the first dielectric layer,
Wherein the first and second core wiring layers are electrically connected to the connection pad,
Antenna Substrate and Semiconductor Package Composite Module.
19. The method of claim 18,
The core member includes a second dielectric layer disposed on the first dielectric layer and covering the second core wiring layer, a third core wiring layer disposed on the opposite side of the second dielectric layer on the side where the second core wiring layer is disposed, And a second core via penetrating the second dielectric layer and electrically connecting the second and third core wiring layers,
Wherein the third core wiring layer is electrically connected to the connection pad,
Antenna Substrate and Semiconductor Package Composite Module.
16. The method of claim 15,
Wherein the core member comprises a first dielectric layer, a first core wiring layer and a second core wiring layer respectively disposed on both surfaces of the first dielectric layer, and a second core wiring layer which penetrates the first dielectric layer and electrically connects the first and second core wiring layers 1 core vias,
Wherein the first and second core wiring layers are electrically connected to the connection pad,
Antenna Substrate and Semiconductor Package Composite Module.
21. The method of claim 20,
Wherein the core member comprises a second dielectric layer disposed on the first dielectric layer and covering the first core wiring layer, a third dielectric layer disposed on the second dielectric layer, a second dielectric layer disposed on the first dielectric layer, A second dielectric layer, a third dielectric layer, a fourth dielectric layer disposed on the third dielectric layer, a first core via electrically connecting the first and second core wiring layers through the first dielectric layer, 1 and a third core wiring layer and a third core via electrically connecting the second and fourth core wiring layers through the third dielectric layer,
Wherein the third and fourth core wiring layers are electrically connected to the connection pad,
Antenna Substrate and Semiconductor Package Composite Module.
A semiconductor chip having an active surface disposed on the through hole and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, a sealing material for sealing at least a part of the semiconductor chip, And a connecting member disposed on an upper portion of the semiconductor chip, wherein the core member and the connecting member each include a core wiring layer and a re-wiring layer electrically connected to the connection pads, respectively; And
A first pattern layer including an antenna pattern is disposed on an upper portion of the insulating layer and a second pattern layer including a ground pattern is disposed on an upper portion of the first pattern layer, and the insulating layer is electrically connected to the antenna pattern An antenna substrate comprising: an antenna member having a via formed therein including a feeding line; and a wiring member disposed at a lower portion of the antenna member and including a wiring layer including a feeding pattern electrically connected to the feeding line; / RTI >
Wherein the antenna substrate is laminated on the fan-out semiconductor package,
Wherein the antenna substrate and the fan-out semiconductor package are connected to each other through an electrical connection structure,
Antenna Substrate and Semiconductor Package Composite Module.

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