KR20170121671A - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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Publication number
KR20170121671A
KR20170121671A KR1020160166951A KR20160166951A KR20170121671A KR 20170121671 A KR20170121671 A KR 20170121671A KR 1020160166951 A KR1020160166951 A KR 1020160166951A KR 20160166951 A KR20160166951 A KR 20160166951A KR 20170121671 A KR20170121671 A KR 20170121671A
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South Korea
Prior art keywords
layer
fan
semiconductor package
semiconductor chip
out semiconductor
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Application number
KR1020160166951A
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Korean (ko)
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KR102016492B1 (en
Inventor
이문희
정주환
정율교
Original Assignee
삼성전기주식회사
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Priority to KR20160049830 priority Critical
Priority to KR1020160049830 priority
Priority to KR1020160117321A priority patent/KR20170121666A/en
Priority to KR1020160117321 priority
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority claimed from TW107116224A external-priority patent/TWI655726B/en
Priority claimed from US15/413,713 external-priority patent/US9875970B2/en
Publication of KR20170121671A publication Critical patent/KR20170121671A/en
Application granted granted Critical
Publication of KR102016492B1 publication Critical patent/KR102016492B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02379Fan-out arrangement
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

The present invention provides a fan-out semiconductor package capable of efficiently emitting heat generated from a semiconductor chip with a simple process. The fan-out semiconductor package comprises: a first connection member having a through hole; the semiconductor chip disposed on the through hole of the first connection member, and having an active surface in which a contact pad is disposed and a non-active surface which is disposed on an opposite side of the active surface; an encapsulant encapsulating at least a part of the first connection member and the non-active surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least a part of the non-active surface of the semiconductor chip; a via penetrating the encapsulant and connecting the pattern layer to the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, and including a re-wire layer electrically connected to the contact pad of the semiconductor chip.

Description

[0001] FAN-OUT SEMICONDUCTOR PACKAGE [0002]

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package capable of extending a connection terminal to an area outside the area where the semiconductor chip is disposed.

One of the main trends of technology development related to semiconductor chips in recent years is to reduce the size of components. Accordingly, in the field of packages, it is required to implement a large number of pins with a small size in response to a surge in demand of small semiconductor chips and the like .

One of the proposed package technologies to meet this is the fan-out package. The fan-out package rewires the connection terminal to the area outside the area where the semiconductor chip is disposed, thereby enabling a small number of pins to be realized while having a small size.

One of the objects of the present disclosure is to provide a fan-out semiconductor package that can effectively dissipate heat generated in a semiconductor chip by a simple process.

One of the solutions proposed through this disclosure is to form a pattern layer on a seal material to seal the semiconductor chip and to connect the pattern layer to the inactive surface of the semiconductor chip using vias passing through the seal material.

For example, a fan-out semiconductor package according to an example proposed in the present disclosure may include a first connecting member having a through hole, a second connecting member disposed in the through hole of the first connecting member, A sealing member which seals at least a part of the inactive surface of the semiconductor chip, a pattern layer which is disposed on the sealing member and covers at least a part of the inactive side of the semiconductor chip, And a second connection member including a first connection member and a rewiring layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad of the semiconductor chip, May include.

It is possible to provide a fan-out semiconductor package which can effectively dissipate heat generated in a semiconductor chip by a simple process as one of the effects of the present disclosure.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
Figure 10 is a schematic diagram of the fan-out semiconductor package of Figure 9; Fig.
11 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
Figure 12 is a schematic diagram of the fan-out semiconductor package of Figure 11; Fig.
13 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
Figure 14 is a schematic diagram of the fan-out semiconductor package of Figure 13; Fig.
15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
Figure 16 is a schematic cross-sectional view of the fan-out semiconductor package of Figure 15; Fig.
17 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
Figure 18 is a schematic diagram of the fan-out semiconductor package of Figure 17; Fig.
19 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
20 is a schematic VI-VI 'cutting plan view of the fan-out semiconductor package of FIG. 19;
21 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
22 is a schematic sectional view VII-VII 'of the fan-out semiconductor package of FIG.
23 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
24 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
25 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
26 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, Analog-to-digital converters, and logic chips such as application-specific integrated circuits (ICs), and the like, but it is needless to say that other types of chip-related components may be included. It goes without saying that these components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 may be combined with the chip-related component 1020, as well.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. It is also understood that other components 1040 may be combined with each other with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. Other components include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (Not shown), a CD (compact disk) (not shown), and a DVD (not shown), an accelerometer (not shown), a gyroscope a digital versatile disk (not shown), and the like. However, the present invention is not limited thereto, and other components used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, a semiconductor package is applied to various electronic apparatuses as described above for various purposes. For example, a main board 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. In addition, other components, such as the camera 1130, that are physically and / or electrically connected to the main board 1010 or not may be contained within the body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. It is needless to say that the electronic device is not necessarily limited to the smartphone 1100, but may be another electronic device as described above.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic equipment, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2202 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2202. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connecting pad 2122 and the re-wiring layer 2142 .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Hereinafter, a fan-out semiconductor package capable of effectively dissipating heat generated in a semiconductor chip will be described with reference to the drawings.

9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

Figure 10 is a schematic diagram of the fan-out semiconductor package of Figure 9; Fig.

Referring to FIG. 1, a fan-out semiconductor package 100A according to an exemplary embodiment includes a first connection member 110 having a through hole 110H, a through hole 110H of the first connection member 110, The first connecting member 110 and the semiconductor chip 120 having the active surface on which the semiconductor chip 120 is disposed and the inactive surface disposed on the opposite side of the active surface, A second connection member 140 disposed on the active surface of the first connection member 110 and the semiconductor chip 120, a passivation layer 150 disposed on the second connection member 140, An under bump metal layer 160 formed on the opening 151 of the layer 150 and a connection terminal 170 formed on the under bump metal layer 160. [ A pattern layer 132 covering at least a part of the non-active surface side of the semiconductor chip 120 is disposed on the sealing material 130. The pattern layer 132 is electrically connected to the semiconductor chip 120 via a via 133 passing through the sealing material 130. [ And is connected to the inactive surface of the chip 120. Heat (arrows) generated in the semiconductor chip 120 can be easily discharged to the outside through the vias 133 and the pattern layer 132. [

In general, in the case of a fan-out semiconductor package, a structure in which a semiconductor chip is simply surrounded by a sealing material such as an epoxy molding compound (EMC) or the like is adopted. In this case, , And the heat of the sealing material having a low thermal conductivity is transmitted only to a very small amount of heat.

On the other hand, when the pattern layer 132 and the via 133 connected to the inactive surface of the semiconductor chip 120 are introduced into the inactive surface of the semiconductor chip 120 like the fan-out semiconductor package 100A according to the example, Heat (arrows) generated from the semiconductor chip 120 can be easily released, and heat radiation characteristics can be improved. In addition, the pattern layer 132 may also improve Electro Magnetic Interference (EMI).

Since the fan-out semiconductor package 100A according to the exemplary embodiment connects the inactive surface of the semiconductor chip 120 to the pattern layer 132 via the via 133, the fan-out semiconductor package 100A includes the plurality of semiconductor chips 120 The via 133 can be selectively connected to only the specific semiconductor chip 120 having a large heat generation and the via 133 can be formed concentrically only at the point where the semiconductor chip 120 generates heat significantly. Since the vias 133 and the pattern layer 132 can be formed simultaneously with the same material and can be integrated without special boundaries, the process is simple and the connection reliability between the vias 133 and the pattern layer 132 is excellent can do.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to the example will be described in more detail.

The rigidity of the package 100A can be maintained according to the specific material of the first connection member 110 and the uniformity of the thickness of the sealing material 130 can be secured. The first connecting member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the first connection member 110 by a predetermined distance. The periphery of the side surface of the semiconductor chip 120 may be surrounded by the first connection member 110. However, it is to be understood that the present invention is not limited thereto and various modifications may be made in other forms, and other functions may be performed according to the forms.

The first connecting member 110 includes an insulating layer 111. The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a core material such as a glass cloth (glass cloth) For example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (bismaleimide triazine), or the like can be used.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may, for example, be but is not limited to an application processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, .

The semiconductor chip 120 may be formed on the basis of an active wafer. Silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 121. The body 121 may have various circuits. The connection pad 122 electrically connects the semiconductor chip 120 to other components. As the forming material, a conductive material such as aluminum (Al) may be used without any particular limitation. A passivation film 123 exposing the connection pad 122 may be formed on the body 121. The passivation film 123 may be an oxide film or a nitride film or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 122 may have a step with the lower surface of the sealing material 130 through the passivation film 123, thereby improving the bleeding of the sealing material 130. An insulating film (not shown) or the like may be further disposed at a necessary position.

The sealing member 130 may protect the first connection member 110 and / or the semiconductor chip 120. [ The sealing shape is not particularly limited and may be a shape that covers at least a part of the first connection member 110 and / or the semiconductor chip 120. For example, the sealing member 130 may cover the inactive surfaces of the first connecting member 110 and the semiconductor chip 120, and may be formed to have a space between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120 Can be filled. The sealing member 130 may fill at least a part of the space between the passivation film 123 of the semiconductor chip 120 and the second connecting member 140. [ On the other hand, by filling the through hole 110H with the sealing material 130, it can act as an adhesive according to a specific material and reduce buckling.

The specific material of the sealing material 130 is not particularly limited. For example, an insulating material may be used. As the insulating material, a material including an inorganic filler and an insulating resin such as a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a reinforcement such as an inorganic filler The included resins, ABF, FR-4, BT, EMC, etc., may be used. If necessary, a thermosetting resin or a thermoplastic resin may be used, which is impregnated with a core material such as glass fiber together with an inorganic filler. If necessary, a photosensitive insulating material (Photo Imagable Dielectric: PID) may be used.

The pattern layer 132 may be formed on the surface of the sealing material 130. The pattern layer 132 may be a metal layer containing a known conductive material. For example, the pattern layer 132 may be formed of a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium Alloys thereof, and the like. The pattern layer 132 may be formed by a known plating method together with the via 133. The pattern layer 132 may be a pattern electrically insulated from the connection pad 122 of the semiconductor chip 120, that is, a heat radiation pattern. However, the pattern layer 132 is not limited to this, And may be electrically connected to the connection pad 122 of the semiconductor chip 120.

The via 133 is formed in a via hole formed in the sealing material 130. The via hole penetrates from one surface of the sealing material 130 to the inactive surface of the semiconductor chip 120. Thus, the via 133 can be in contact with the inactive surface of the semiconductor chip 120. The via hole may be a laser via hole or a via via hole depending on the material of the sealing material 130. For example, when the sealing material 130 is ABF or the like including an inorganic filler and an insulating resin, it may be a laser via hole formed by a known laser drill. When the sealing material 130 includes a photosensitive insulating material, It may be a photovoltaic hole formed by the method. The via 133 is formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) Or an alloy thereof, and may be formed by a plating method together with the pattern layer 132. [

If the pattern layer 132 and the vias 133 are formed together by a plating method, they may be integrated, and the boundary may not exist. It may also comprise the same conductive material, for example copper (Cu). That is, no separate adhesive material is required between them. Therefore, the heat dissipating member 135 can be realized in a simple and thinner process. When the pattern layer 132 and the vias 133 are directly contacted with each other without being bounded, the heat emitted through the inactive surface of the semiconductor chip 120 can be more effectively discharged to the outside.

The second connection member 140 is a structure for rewiring the connection pad 122 of the semiconductor chip 120. Hundreds of hundreds of connection pads 122 having various functions can be rewired through the second connection member 140 and physically and / or electrically connected to the outside through the connection terminal 170 to be described later . The second connection member 140 includes an insulating layer 141, a re-wiring layer 142 disposed on the insulating layer 141, and a via 143 connecting the re-wiring layer 142 through the insulating layer 141. [ . In the fan-out semiconductor package 100A according to the exemplary embodiment, the second connection member 140 is formed as a single layer, but may be a plurality of layers.

As the material of the insulating layer 141, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitivity, the insulating layer 141 can be made thinner and the pitch of the via 143 can be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 has multiple layers, these materials may be the same as each other and may be different from each other as needed. If the insulating layers 141 are multilayered, they may be unified according to the process, and the boundaries may be unclear.

The rewiring layer 142 substantially rewires the connection pad 122 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) , Nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The re-distribution layer 142 may perform various functions according to the design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include via pads, connection terminal pads, and the like.

A surface treatment layer (not shown) may be formed on the surface of the exposed rewiring layer 142 as needed. The surface treatment layer (not shown) may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / replacement gold plating, DIG plating, HASL, But is not limited thereto.

The via 143 electrically connects the re-wiring layer 142, the connection pad 122, and the like formed in the different layers, thereby forming an electrical path in the package 100A. The via 143 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The vias 143 can be fully filled with a conductive material, or a conductive material can be formed along the walls of the vias. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied.

The passivation layer 150 is an additional structure for protecting the second connection member 140 from external physical chemical damage or the like. The passivation layer 150 may have an opening 151 that exposes at least a portion of the redistribution layer 142 of the second connection member 140. As the material of the passivation layer 150, a material having a larger elastic modulus than the insulating layer 141 of the second connection member 140 is used. For example, ABF or the like including an inorganic filler and an insulating resin may be used although it does not include glass fibers. The weight percentage of the inorganic filler included in the passivation layer 150 is larger than the weight percentage of the inorganic filler included in the insulating layer 141 of the second connection member 140 have.

The underbump metal layer 160 has an additional configuration, which improves the connection reliability of the connection terminals 170 and, as a result, improves the board level reliability of the package 100A. The under bump metal layer 160 is connected to the redistribution layer 142 of the second connection member 140 exposed through the opening 151 of the passivation layer 150. The under bump metal layer 160 may be formed on the opening 151 of the passivation layer 150 using a known conductive material, that is, a metal, by a known metallization method, but the present invention is not limited thereto.

The connection terminal 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device via the connection terminal 170. [ The connection terminal 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed as a multilayer or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. .

The number, spacing, arrangement type, etc. of the connection terminals 170 are not particularly limited and can be sufficiently modified according to the design specifications of the ordinary artisan. For example, the number of the connection terminals 170 may be several tens to several thousands depending on the number of the connection pads 122 of the semiconductor chip 120, and may have more or less numbers. When the connection terminal 170 is a solder ball, it can cover the side surface of the under bump metal layer 160 that extends on one side of the passivation layer 150, and the connection reliability can be further improved.

At least one of the connection terminals 170 is disposed in the fan-out area. The fan-out area means an area outside the area where the semiconductor chip 120 is disposed. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. Compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to make package thickness thinner and excellent price competitiveness.

11 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Figure 12 is a schematic diagram of the fan-out semiconductor package of Figure 11; Fig.

Referring to the drawings, a fan-out semiconductor package 100B according to another embodiment extends to a region where the pattern layer 132 covers the first connecting member 110 of the sealing material 130. [ For example, the pattern layer 132 may cover the entire surface of the sealing material 130. Other details are substantially the same as those described above, and a detailed description thereof will be omitted.

13 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Figure 14 is a schematic diagram of the fan-out semiconductor package of Figure 13; Fig.

Referring to the drawings, a fan-out semiconductor package 100C according to another example further includes a metal layer 115 in which a first connecting member 110 is disposed on a wall surface of a through hole 110H. The metal layer 115 may extend to the upper side and the lower side of the insulating layer 111, but is not limited thereto. Heat (arrows) generated in the semiconductor chip 120 through the metal layer 115 may be discharged to the upper side and the lower side of the first connection member 110 after moving to the first connection member 110 side. In addition, electromagnetic waves can be blocked more effectively. The metal layer 115 may be formed by a known plating method, or may include a known conductive material. Other details are substantially the same as those described above, and a detailed description thereof will be omitted.

15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Figure 16 is a schematic cross-sectional view of the fan-out semiconductor package of Figure 15; Fig.

Referring to the drawings, a fan-out semiconductor package 100D according to another embodiment includes a metal layer 128 disposed on an inactive surface of a semiconductor chip 120, and a via 133 connected to a metal layer 128. The pattern layers 132a and 132b may include a heat dissipation pattern 132a covering at least a part of the inactive surface side of the semiconductor chip 120 and may be formed by rewiring the connection pad 122, The wiring pattern 132b may be formed. At this time, the heat radiation pattern 132a and the wiring pattern 132b may be disconnected from each other on the sealing material 130. [ The first connection member 110 may include redistribution layers 112a and 112b disposed above and below the insulation layer 111 and separated from the metal layer 115. The redistribution layers 112a and 112b May be electrically connected through a via 113 passing through the insulating layer 111. A passivation layer 180 covering at least a part of the pattern layers 132a and 132b may be disposed on the sealant 130 and a heat dissipating member 190 may be attached on the passivation layer 180. [ On the other hand, the heat radiation member 190 may be directly attached to the passivation layer 180, but it may be attached through the connection member 195 for improved reliability.

The metal layer 128 is formed on the inactive surface of the semiconductor chip 120 to more effectively perform heat dissipation or electromagnetic wave shielding of the semiconductor chip 120. The metal layer 128 may be in the form of a plate and cover all of the inactive surfaces of the semiconductor chip 120, but the present invention is not limited thereto. The metal layer 128 may be formed by a known plating method or may include a conductive material such as copper (Cu). The via 133 may be connected to the inactive surface of the semiconductor chip 120 in such a way as to connect with the metal layer 128.

The heat radiation pattern 132a can cover an area where the wiring pattern 132b on the sealant 130 is not disposed. The heat radiation pattern 132a may be in a plate shape, but is not limited thereto. The heat dissipation pattern 132a may be connected to the metal layer 115 formed on the first connection member 110 via the via 133. The heat dissipation pattern 132a and the metal layer 115 may function as a ground GND if necessary. In this case, the ground pattern of the rewiring layer formed on the first connection member 110 and the second connection member 140, And may be electrically connected to the ground connection pad among the connection pads 122 of the semiconductor chip 120 through a pattern or via. That is, the pattern layers 132a and 132b may include a ground pattern.

The wiring patterns 132b may be various kinds of wiring patterns for rewiring the connection pads 122 of the semiconductor chip 120. [ The wiring pattern 132b may include a power pattern and a signal pattern except for the case where the heat radiation pattern 132a performs a ground function. That is, the pattern layers 132a and 132b may include a power pattern and a signal pattern. The wiring patterns 132b may be electrically connected to the rewiring layers 112a and 112b and the vias 113 of the first connection member 110 through the vias 133. [ The second connection member 140 may be electrically connected to the re-wiring layer 142 and the via 143 through the first connection member 110. And may be electrically connected to the connection pad 122 of the semiconductor chip 120 through this path. The wiring pattern 132b may also include various types of pad patterns.

The rewiring layers 112a and 112b can perform rewiring of the connection pad 122. When the first connection member 110 also includes the rewiring layers 112a and 112b, 140 can be reduced, so that the degree of freedom in designing can be increased and the thickness can be reduced. The redistribution layers 112a and 112b can perform various functions according to the design design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include via pads, connection terminal pads, and the like.

The vias 113 electrically connect the redistribution layers 112a and 112b formed in the different layers. The vias 113 may be fully filled with a conductive material, or a conductive material may be formed along the walls of the vias. In addition, any shape known in the art, such as a cylindrical shape or an hourglass shape, may be applied.

The passivation layer 180 may comprise the same or similar material as the passivation layer 150 described above. In this case, the warpage of the package 100D can be improved through the symmetry effect of the passivation layer 180 disposed on both sides. However, the present invention is not limited thereto, and other materials may be used. For example, as the material of the passivation layer 180, a prepreg including a core material such as glass fiber or the like may be used. On the other hand, in terms of improving the warpage, the weight percentage of the inorganic filler included in the passivation layer 180 may be larger than the weight percentage of the inorganic filler included in the sealing material 130. The passivation layer 180 may be adhered to the sealing material 130 before curing, and in this case, a dimple may be formed toward the through hole 110H by movement of the inorganic filler by curing.

The heat dissipating member 190 may be a known heat sink. The heat radiating member 190 can easily discharge the heat radiated through the heat radiating pattern 132a of the pattern layers 132a and 132b to the outside of the package 100A. The heat radiating member 190 may have a plurality of trenches on its upper surface for easy heat dissipation. In this case, the surface area increases and the heat can be easily released. The heat dissipating member 190 is not particularly limited as long as it is a material having excellent thermal conductivity. For example, a metal material. The connecting member 195 can easily attach the heat dissipating member 190 to the passivation layer 180 and, if necessary, prevent electrical shorting and efficiently perform heat transfer. The material of the connecting member 195 may be appropriately selected depending on the material of the heat radiation member 190.

The other contents are substantially the same as those described above, and a detailed description will be omitted.

17 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Figure 18 is a schematic diagram of the fan-out semiconductor package of Figure 17; Fig.

Referring to the drawings, a fan-out semiconductor package 100E according to another example includes a plurality of through holes 110Ha, 110Hb, and 110Hc, and a plurality of through holes 110Ha, 110Hb, The semiconductor chips 120, 125a, and 125b. The further disposed semiconductor chips 125a and 125b may be the same or different integrated circuits including bodies 123a and 123b and connection pads 124a (not shown), respectively. The connection pads 124a (not shown) of the semiconductor chips 125a and 125b may also be electrically connected to the second connection member 140. [ If necessary, the via 133 may be selectively connected only to a specific semiconductor chip having a large heat generation, and the via 133 may be formed concentrically only at a point where a specific heat of the specific semiconductor chip seriously feels. Other details are substantially the same as those described above, and a detailed description thereof will be omitted.

19 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

20 is a schematic VI-VI 'cutting plan view of the fan-out semiconductor package of FIG. 19;

Referring to the drawings, a fan-out semiconductor package 100F according to another example includes a plurality of through holes 110Ha, 110Hb, and 110Hc, and a plurality of through holes 110Ha, 110Hb, and 110Hc, (120) and passive components (191, 192). The passive components 191 and 192 may be, for example, the same or different capacitors, inductors, and the like, but are not limited thereto. Meanwhile, the vias 133 may be selectively formed to be connected only to the semiconductor chip 120. Optionally, a surface mount passive component 193 may be further disposed on the passivation layer 180, which may also be a capacitor, an inductor, or the like, but is not limited thereto. In some cases, the passive components 191, 192, and 193 may all be capacitors and may be connected to the same power wiring line. Other details are substantially the same as those described above, and a detailed description thereof will be omitted.

21 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

22 is a schematic sectional view VII-VII 'of the fan-out semiconductor package of FIG.

Referring to FIG. 1, a fan-out semiconductor package 100G according to another embodiment includes a plurality of through holes 110Ha, 110Hb, and 110Hc, and semiconductor chips 120, 125a, 125b. Metal layers 128 and 128a (not shown) may be respectively disposed on the inactive surfaces of the semiconductor chips 120, 125a and 125b, and vias 133 may be connected to the metal layers 128, 128a and 128b. The pattern layers 132a and 132b may include a heat dissipation pattern 132a covering at least a portion of the inactive surface side of each of the semiconductor chips 120 and 125a and 125b, And a wiring pattern 132b for rewiring the connection pads 122 and 124a (not shown) and the like. The first connection member 110 may include redistribution layers 112a and 112b disposed above and below the insulation layer 111 and separated from the metal layer 115. The redistribution layers 112a and 112b May be electrically connected through a via 113 passing through the insulating layer 111. A passivation layer 180 covering at least a part of the pattern layers 132a and 132b may be disposed on the sealant 130 and a heat dissipating member 190 may be attached on the passivation layer 180. [ On the other hand, the heat radiation member 190 may be directly attached to the passivation layer 180, but it may be attached through the connection member 195 for improved reliability. Other details are substantially the same as those described above, and a detailed description thereof will be omitted.

23 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100H according to another exemplary embodiment includes a first insulating layer 111a, a second connecting member 140, and a second connecting member 140. The first insulating layer 111a contacts the second connecting member 140, A first rewiring layer 112a in contact with the first insulation layer 111a and a second rewiring layer 112a disposed on the opposite side of the first rewiring layer 112a of the first insulation layer 111a, A second insulating layer 111b disposed on the first insulating layer 111a and covering the second redistribution layer 112b and a third redistribution layer 112c disposed on the second insulating layer 111b, . The first to third rewiring layers 112a, 112b, and 112c are electrically connected to the connection pad 122. The first and second redistribution layers 112a and 112b and the second and third redistribution layers 112b and 112c are connected to the first and second via layers 111a and 111b through the first and second insulating layers 111a and 111b, (113a, 113b).

Since the first rewiring layer 112a is buried, the insulation distance of the insulating layer 141a of the second connection member 140 can be substantially constant as described above. The first connection member 110 includes a large number of rewiring layers 112a, 112b, and 112c, thereby simplifying the second connection member 140. [ Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140. The first rewiring layer 112a may be recessed into the first insulation layer so that the lower surface of the first insulation layer 111a and the lower surface of the first rewiring layer 112a may have a step. As a result, it is possible to prevent the material for forming the sealant 130 from being contaminated by contamination of the first rewiring layer 112a when the sealant 130 is formed.

The lower surface of the first redistribution layer 112a of the first connection member 110 may be located above the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142 of the second connection member 140 and the redistribution layer 112a of the first connection member 110 is larger than the distance between the redistribution layer 142 of the second connection member 140 and the semiconductor chip 120 Of the connection pads 122 of the semiconductor device. This is because the first rewiring layer 112a can be recessed into the insulating layer 111. [ The second rewiring layer 112b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connection member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120 so that the second rewiring layer 112b formed in the first connection member 110 is electrically connected to the semiconductor chip 120 May be disposed at a level between the active surface and the inactive surface.

The thickness of the redistribution layers 112a, 112b and 112c of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120 and the rewiring layers 112a, 112b, and 112c may be formed to have a larger size in accordance with the scale. On the other hand, the redistribution layer 142 of the second connection member 140 can be formed in a relatively small size for thinning.

Other details are substantially the same as those described above, and a detailed description thereof will be omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G according to another example described above may be applied to the fan-out semiconductor package 100H according to another example.

24 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100I according to another example extends to at least a part of a region where the pattern layer 132 covers the first connecting member 110 of the sealing material 130. The pattern layer 132 is connected to the first connection member 110 through the via member 133 passing through the sealing member 130 and connected to the first connection member 110. For example, to the third redistribution layer 112c of the first connection member 110. [ The rewiring layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be discharged to the lower portion through the first connecting member 110, so that the heat radiation effect can be more excellent. Although only the first and third redistribution layers 112a and 112c of the first connection member 110 have a ground pattern electrically connected to the pattern layer 132 in the figure, 112b may also have a ground pattern electrically connected to the pattern layer 132 through the first vias 113a. In some cases, only the third redistribution layer 112c may have a ground pattern electrically connected to the pattern layer 132.

Other details are substantially the same as those described above, and a detailed description thereof will be omitted. The description of the fan-out semiconductor packages 100B to 100G according to another example described above may be applied to the other example of the fan-out semiconductor package 100I.

25 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100J according to another example, a first connecting member 110 includes a first insulating layer 111a, a first rewiring layer 111B disposed on both surfaces of the first insulating layer 111a, A second insulating layer 111b disposed on the first insulating layer 112a and covering the first redistribution layer 112a and a second insulating layer 111b disposed on the second insulating layer 111b, A third insulating layer 111c disposed on the first insulating layer 111a and covering the second redistribution layer 112b and a third insulating layer 111c disposed on the third insulating layer 111c, 4 redistribution layer 112d. The first to fourth rewiring layers 112a, 112b, 112c, and 112d are electrically connected to the connection pad 122. The first connecting member 110 includes a greater number of redistribution layers 112a, 112b, 112c and 112d, so that the second connecting member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140. The first to fourth rewiring layers 112a, 112b, 112c and 112d have first to third vias 113a, 113b and 113c passing through the first to third insulation layers 111a, 111b and 111c. As shown in FIG.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity and the second insulating layer 111b and the third insulating layer 111c may form a larger number of redistribution layers 112c and 112d May be introduced. The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111c and the third insulating layer 111c may be, And an insulating resin, but the present invention is not limited thereto.

The lower surface of the third redistribution layer 112c of the first connection member 110 may be located below the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 is larger than the distance between the redistribution layer 142 of the second connection member 140 and the semiconductor chip 1. [ May be less than the distance between the connection pads (122) of the first substrate (120). This is because the third rewiring layer 112c can be disposed on the second insulating layer 111b so as to be in contact with the second connection member 140. [ The first redistribution layer 112a and the second redistribution layer 112b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connecting member 110 may have a thickness corresponding to the thickness of the semiconductor chip 120 and may include a first rewiring layer 112a and a second rewiring layer 112b formed in the first connecting member 110, May be disposed at a level between the active surface and the inactive surface of the semiconductor chip 120.

The thickness of the redistribution layers 112a, 112b, 112c and 112d of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120 and the rewiring layers 112a, 112b, 112c and 112d may be formed in a larger size. On the other hand, the redistribution layer 142 of the second connection member 140 can be formed in a relatively small size for thinning.

Other details are substantially the same as those described above, and a detailed description thereof will be omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G according to another example described above may be applied to the fan-out semiconductor package 100J according to another example.

26 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100K according to another example extends to at least a partial region where the pattern layer 132 covers the first connecting member 110 of the sealing material 130. [ The pattern layer 132 is connected to the first connection member 110 through the via member 133 passing through the sealing member 130 and connected to the first connection member 110. For example, it may be connected to the fourth redistribution layer 112d of the first connection member 110. The rewiring layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be discharged to the lower portion through the first connecting member 110, so that the heat radiation effect can be more excellent. Although only the second and fourth redistribution layers 112b and 112c of the first connection member 110 are shown as having a ground pattern electrically connected to the pattern layer 132 in the figure, 3 redistribution layers 112a and 112c may also have a ground pattern electrically connected to the pattern layer 132 through the first and / or second vias 113a and 113b. In some cases, only the fourth redistribution layer 112d may have a ground pattern electrically connected to the pattern layer 132.

Other details are substantially the same as those described above, and a detailed description thereof will be omitted. The description of the fan-out semiconductor packages 100B to 100G according to another example described above may be applied to the other example of the fan-out semiconductor package 100K.

Other details are substantially the same as those described above, and a detailed description thereof will be omitted. The description of the fan-out semiconductor packages 100B to 100I according to another example described above may also be applied to the fan-out semiconductor package 100J according to another example.

In the present disclosure, the lower side, the lower side, the lower side and the like refer to the direction toward the mounting surface of the fan-out semiconductor package with reference to the cross section of the drawing for convenience, and the upper side, the upper side and the upper side are used in the opposite direction. It should be noted, however, that this is a definition of a direction for the sake of convenience of explanation, and it is needless to say that the scope of rights of the claims is not particularly limited by description of such direction.

The meaning of being connected in this disclosure includes not only a direct connection but also an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

The expression " exemplary " used in this disclosure does not mean the same embodiment but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude that they are implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

The terms used in this disclosure are used only to illustrate an example and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

1000: electronic device 1010: main board
1020: Chip related parts 1030: Network related parts
1040: Other parts 1050: Camera
1060: antenna 1070: display
1080: Battery 1090: Signal line
1100: Smartphone 1101: Smartphone body
1110: Smartphone mainboard 1111: mainboard insulation layer
1112: main board wiring 1120: parts
1130: Smartphone camera 2200: Fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: re-wiring layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: Interposer substrate 2302: Interposer substrate
2100: Fan-out semiconductor package 2120: Semiconductor chip
2121: Body 2122: Connection pad
2140: connecting member 2141: insulating layer
2142: re-wiring layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A to 100K: Fan-out semiconductor package
110: first connecting member 111, 112a, 112b, 112c: insulating layer
112a, 112b, 112c, 112d: re-wiring layers 113, 113a, 113b, 113c: vias
120, 125a, 125b: semiconductor chips 121, 123a, 123b: body
122, 124a: connection pad 123: passivation film
128, 128a, 128b: metal layer
130: sealing material 131: opening
132: pattern layer 133: via
132a: heat radiation pattern 132b: wiring pattern
140: second connecting member 141: insulating layer
142: re-wiring layer 143: via
150: passivation layer 160: under bump metal layer
170: connection terminal 180: passivation layer
191, 192: Passive component 193: Surface mount component
190: heat radiating member 195: connecting member

Claims (18)

  1. A first connecting member having a through hole;
    A semiconductor chip disposed in the through hole of the first connection member and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
    A sealing member for sealing at least a part of the inactive surfaces of the first connecting member and the semiconductor chip;
    A pattern layer disposed on the sealing material and covering at least a part of the non-active surface side of the semiconductor chip;
    A via penetrating the sealing material and connecting the pattern layer to an inactive surface of the semiconductor chip; And
    A second connecting member disposed on the active surface of the first connecting member and the semiconductor chip and including a re-wiring layer electrically connected to a connection pad of the semiconductor chip; / RTI >
    A fan-out semiconductor package.
  2. The method according to claim 1,
    Wherein the pattern layer and the via are integrated without boundaries,
    A fan-out semiconductor package.
  3. The method according to claim 1,
    A metal layer disposed on the inactive surface of the semiconductor chip; Further comprising:
    Wherein the via connects to the metal layer,
    A fan-out semiconductor package.
  4. The method according to claim 1,
    A passivation layer covering at least a part of the pattern layer; And
    A heat dissipating member attached on the passivation layer; ≪ / RTI >
    A fan-out semiconductor package.
  5. The method according to claim 1,
    Wherein the pattern layer comprises a pattern electrically insulated from a connection pad of the semiconductor chip,
    A fan-out semiconductor package.
  6. The method according to claim 1,
    Wherein the pattern layer comprises a ground pattern,
    A fan-out semiconductor package.
  7. The method according to claim 6,
    Wherein the pattern layer further comprises a signal pattern,
    A fan-out semiconductor package.
  8. 8. The method of claim 7,
    Wherein the first connecting member includes a ground pattern,
    Wherein the ground pattern of the pattern layer is electrically connected to the ground pattern of the first connection member via the via,
    A fan-out semiconductor package.
  9. The method according to claim 1,
    Wherein the first connecting member includes a rewiring layer at least partially exposed by an opening penetrating the sealing material,
    The re-wiring layer of the first connection member is electrically connected to the connection pad,
    A fan-out semiconductor package.
  10. The method according to claim 1,
    A metal layer disposed on a wall surface of the through hole; ≪ / RTI >
    A fan-out semiconductor package.
  11. 11. The method of claim 10,
    Wherein the metal layer extends upward and downward from the first connection member,
    A fan-out semiconductor package.
  12. The method according to claim 1,
    Wherein the first connecting member includes first and second through holes through the through hole,
    The semiconductor chip is disposed in the first through hole,
    A passive component is disposed in the second through hole,
    Wherein the via is selectively connected to an inactive surface of the semiconductor chip,
    A fan-out semiconductor package.
  13. The method according to claim 1,
    Wherein the first connecting member comprises a first insulating layer, a first rewiring layer in contact with the second connecting member and embedded in the first insulating layer, and a second rewiring layer on the opposite side of the first rewiring layer, And a second rewiring layer disposed on the first rewiring layer,
    Wherein the first and second rewiring layers are electrically connected to the connection pad,
    A fan-out semiconductor package.
  14. 14. The method of claim 13,
    The first connecting member further includes a second insulating layer disposed on the first insulating layer and covering the second rewiring layer and a third rewiring layer disposed on the second insulating layer,
    Wherein the third re-wiring layer is electrically connected to the connection pad,
    A fan-out semiconductor package.
  15. 14. The method of claim 13,
    Wherein the lower surface of the first rewiring layer has a stepped surface with the lower surface of the first insulating layer,
    A fan-out semiconductor package.
  16. The method according to claim 1,
    The first connecting member includes a first insulating layer, a first rewiring layer and a second rewiring layer disposed on both surfaces of the first insulating layer, a second rewiring layer disposed on the first insulating layer, An insulating layer, and a third rewiring layer disposed on the second insulating layer,
    Wherein the first to third rewiring layers are electrically connected to the connection pad,
    A fan-out semiconductor package.
  17. 17. The method of claim 16,
    The first connecting member further includes a third insulating layer disposed on the first insulating layer and covering the second rewiring layer and a fourth rewiring layer disposed on the third insulating layer,
    Wherein the fourth redistribution layer is electrically connected to the connection pad,
    A fan-out semiconductor package.
  18. 17. The method of claim 16,
    Wherein the first insulating layer is thicker than the second insulating layer,
    A fan-out semiconductor package.
KR1020160166951A 2016-04-25 2016-12-08 Fan-out semiconductor package KR102016492B1 (en)

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KR1020160049830 2016-04-25
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KR1020160117321 2016-09-12

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TW107116224A TWI655726B (en) 2016-04-25 2017-01-24 Fan-out semiconductor package
US15/413,713 US9875970B2 (en) 2016-04-25 2017-01-24 Fan-out semiconductor package
TW106102511A TWI630690B (en) 2016-04-25 2017-01-24 Fan-out semiconductor package
US15/799,624 US10199329B2 (en) 2016-04-25 2017-10-31 Fan-out semiconductor package

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