KR20180114958A - FERAM-DRAM Hybrid Memory - Google Patents

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of the first memory cell array or a second memory cell of the second memory cell array, wherein the first digit line coupled to the first memory cell is sensed And is coupled to a paging buffer register that includes an amplifier. The method further comprises operating the transfer gate based at least in part upon having determined to read a second memory cell of the second memory cell array, wherein the transfer gate is configured to couple the second digit line coupled to the second memory cell to the first And to selectively couple to the paging buffer register through the digit line.

Description

FERAM-DRAM Hybrid Memory

Cross-references

This application for patent is filed on March 16, 2016, entitled " FERAM-DRAM Hybrid Memory ", assigned to the assignee hereof by Kajigaya. Patent application number 15 / 071,961.

The following relates generally to memory devices, and more particularly to a hybrid memory including a ferroelectric random access memory (FeRAM) array and a dynamic random access memory (DRAM) array.

Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. The information is stored by programming the different states of the memory device. For example, binary devices have two states, often indicated by a logic "1" or a logic "0 ". In other systems, more than one state may be stored. To access the stored information, the electronic device can read or sense the stored state in the memory device. To store information, the electronic device may record or program the status in the memory device.

Including, but not limited to, random access memory (RAM), read only memory (ROM), DRAM, synchronous dynamic random access memory (SDRAM), FeRAM, MRAM, resistive, Memory devices exist. The memory devices may be volatile or non-volatile. A non-volatile memory flash memory can store data for extended periods of time even in the absence of external power. Volatile memory devices, such as DRAMs, may lose their stored data over time if they are not periodically refreshed by an external power source. A binary memory device may include, for example, charged or discharged capacitors. The charged capacitor can be discharged over time through the leakage currents, resulting in the loss of stored information. Certain aspects of volatile memory may provide performance advantages, such as faster read or write speeds, while non-volatile aspects, such as the ability to store data without periodic refreshing, may be advantageous.

In some cases, the FeRAM can operate at similar non-volatility characteristics and speeds to the operation of the DRAM. However, in these cases, the ferroelectric capacitors used in the memory cells of the FeRAM can experience repeated polarization and reversal fatigue of the ferroelectric materials in the ferroelectric capacitors, resulting in a reduction in the remanent polarization . Also, when the write operations are performed continuously in the same polarization direction, a shift in the hysteresis characteristic of the memory cell, referred to as "in-print " causes subsequent degradation of the rewrite characteristics of the memory cell . Thus, compared to DRAM, FeRAM can support fewer read and write operations over its lifetime.

On the other hand, the ferroelectric capacitor of the FeRAM has a ferroelectric characteristic due to the remanent polarization component and a paraelectric property due to the normal capacitor component, and by using only the phase dielectric property, the FeRAM does not perform polarization inversion, Can be operated similarly.

Embodiments of the present disclosure are described with reference to the following drawings:
Figure 1 illustrates an exemplary memory device, in accordance with various embodiments;
Figure 2 illustrates an exemplary memory device, in accordance with various embodiments;
Figure 3 shows a block diagram of a memory device, in accordance with various embodiments;
Figure 4 illustrates a first example of an apparatus comprising a hybrid memory, according to various embodiments;
5 illustrates a second example of a device comprising a hybrid memory, according to various embodiments;
Figure 6 illustrates a first example of a sense amplifier according to various embodiments;
7 is a block diagram of a second memory cell array according to various embodiments when the second memory cell array is configured for FeRAM operation and the first sense amplifier is configured as described with reference to Figure 6, Illustrate exemplary waveforms for use in read and rewrite operations in a cell array;
FIG. 8 illustrates examples of analysis of read and rewrite operations in the second memory cell array described with reference to FIG. 5 when the second memory cell array is configured for FeRAM operation, according to various embodiments, and hysteresis characteristics Lt; / RTI >
FIG. 9 is a block diagram of a first memory cell array (or a third memory cell array) when a first memory cell array is configured for DRAM operation and a first sense amplifier is configured as described with reference to FIG. 6, Array) for use in read and rewrite operations;
FIG. 10 illustrates examples of analysis of read and rewrite operations in the first memory cell array described with reference to FIG. 5 when the first memory cell array is configured for DRAM operation, according to various embodiments, and hysteresis characteristics Lt; / RTI >
11 illustrates a third example of an apparatus 1100 including a hybrid memory according to various embodiments;
12 illustrates a second example of a sense amplifier according to various embodiments;
13 is a block diagram of a second memory cell array according to various embodiments. When the second memory cell array is configured for FeRAM operation and the first sense amplifier is configured as described with reference to FIG. 12, Illustrate exemplary waveforms for use in read and rewrite operations in a memory cell array;
FIG. 14 illustrates examples of analysis of read and rewrite operations in the second memory cell array described with reference to FIG. 11 when the second memory cell array is configured for FeRAM operation, according to various embodiments, and hysteresis characteristics Lt; / RTI >
FIG. 15 illustrates examples of analysis of read and rewrite operations in the first memory cell array described with reference to FIG. 5 when the first memory cell array is configured for DRAM operation, according to various embodiments, and hysteresis characteristics Lt; / RTI >
Figure 16 illustrates a fourth example of an apparatus comprising a hybrid memory, according to various embodiments;
Figure 17 illustrates a fifth example of an apparatus comprising a hybrid memory, according to various embodiments;
Figure 18 shows a diagram of a system including a hybrid main memory according to various embodiments;
19 shows a flowchart illustrating a method 1900 of an operational memory device according to various embodiments; And
FIG. 20 shows a flowchart illustrating a method 2000 of operating a memory device, according to various embodiments.

The disclosed techniques relate to memory devices having a plurality of memory cells (e.g., ferroelectric memory cells (hybrid RAM (HRAM) cells). Ferroelectric memory cells have an information storage capacitor with a ferroelectric film. In one embodiment, In a hybrid memory array, a first memory cell array (e.g., a first HRAM array) may be configured to operate in a volatile mode (e.g., as a DRAM array) and a second memory cell array The memory cells of the DRAM array and the FeRAM array may have the same cell structure; however, the memory cells of the HRAM memory cells (not shown) in the DRAM array may be configured to operate in non-volatile mode (e.g., as a FeRAM array) The cell plate voltages of the ferroelectric capacitors of the read / write capacitors can be set to VSS (or ground) The operations can be performed without reversing the polarization of the ferroelectric films of the ferroelectric capacitors in the DRAM array. The digit lines of the DRAM array can be coupled to the sense amplifiers in the paging buffer. through the sense amplifiers in the paging buffer register by the transfer gates and the digit lines of the DRAM array so that the memory cells of the FeRAM array are selectively coupled to (or decoupled from) the sense amplifiers, In this manner, the sense amplifiers of the paging buffer register may be shared by the memory arrays of the DRAM array and the FeRAM array, but the memory cells of the FeRAM array may be selectively coupled to the sense amplifiers.

Aspects of the present disclosure introduced above are further described below in connection with memory devices. Specific examples of hybrid memory are then described. These and other aspects of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts related to the configuration, operation, and use of the hybrid memory.

FIG. 1 illustrates a block diagram of an exemplary memory device 100, in accordance with various embodiments. The memory device 100 may include programmable memory cells 105 to store different states. Each memory cell 105 may be programmable to store two states, denoted as logic zero and logic one. In some cases, the memory cell 105 may be configured to store three or more logic states. The memory cell 105 may include a capacitor for storing a charge indicative of a programmable state; For example, the charging and non-charging capacitors may represent two logic states. DRAM architectures can typically use this design, and the capacitors employed may include dielectric materials having linear electro-polarization properties. In contrast, a ferroelectric memory cell may include a capacitor having a rigid dielectric as a dielectric material. Ferroelectric materials have non-linear polarization properties.

Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the appropriate access line 110 and digit line 115. Activating or selecting the access line 110 or the digit line 115 may include applying a voltage potential to a separate line. In some cases, the access line 110 may be referred to as a word line, or the digit line 115 may be referred to as a bit line. The word line 110 and the digit line 115 may be made of a conductive material. In some examples, the word line 110 and the digit line 115 may be made of a metal (e.g., copper, aluminum, gold, tungsten, etc.). Each row of memory cells 105 may be coupled to a single word line 110 and each column of memory cells 105 may be coupled to a single digit line 115. [ By activating one word line 110 and one digit line 115, a single memory cell 105 can be accessed in their intersection. The intersection of the access line 110 and the digit line 115 may be referred to as the address of the memory cell.

In some architectures, the logic storage device of the cell, e.g., the capacitor, can be electrically isolated from the digit line by the selection device. The word line 110 may be coupled to the selection device and may control the selection device. For example, the select device may be a transistor and the word line 110 may be connected to the gate of a transistor. Activating the word line 110 results in an electrical connection between the capacitor of the memory cell 105 and the corresponding digit line 115. The digit line may then be accessed to read or write the memory cell 105. [

Access to the memory cell 105 may be controlled through the row decoder 120 and the column decoder 130. [ For example, the row decoder 120 may receive the row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives the column address from the memory controller 140 and activates the appropriate digit line 115. Thus, by activating the access line 110 and the digit line 115, the memory cell 105 can be accessed.

Upon access, the memory cell 105 may be read or sensed by the sensing component 125. For example, the sensing component 125 may compare a signal, e.g., a voltage, of the associated digit line 115 with a reference signal (not shown) to determine the stored state of the memory cell 105. For example, if the digit line 115 has a voltage higher than the reference voltage, the sensing component 125 may determine whether the stored state of the memory cell 105 is logic 1 or vice versa. The sensing component 125 may include various transistors or amplifiers to detect and amplify the difference in signal that may be referred to as latching. The sensed logic state of the memory cell 105 may then be output through the column decoder 130 as an output 135.

The memory cell 105 may be set or written by similarly activating the associated word line 110 and digit line 115. As discussed above, activating the access line 110 electrically connects the corresponding rows of the memory cells 105 to their respective digit lines 115. By controlling the associated digit line 115 while the word line 110 is active, the memory cell 105 can be written - that is, the logic value can be stored in the memory cell 105. The column decoder 130 may receive data to be written to the memory cell 105, for example, In the case of a ferroelectric capacitor, the memory cell 105 can be written by applying a voltage across the ferroelectric capacitor.

In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state and rewrite or refresh operations may be performed to return the original logic state to the memory cell 105 . For example, in a DRAM, a capacitor may be partially or completely discharged during a sensing operation, which may compromise the stored logic state. Thus, the stored logic state can be rewritten after the sensing operation. Additionally, activating a single word line 110 may result in a discharge of all memory cells in the row; Thus, all memory cells 105 in a row may need to be rewritten.

Some memory architectures, including DRAM architectures, can lose their stored state over time unless they are periodically refreshed by external power. For example, a charged capacitor can discharge over time through leakage currents, resulting in loss of stored information. The refresh rate of this so-called volatile memory device can be relatively high, such as several dozen refresh operations per second for a DRAM, resulting in significant power consumption. As the memory array grows larger, the placement or operation of memory arrays (e.g., power supplies, heat generation, material limitations, etc.) for mobile devices where increased power consumption is specifically dependent on a limited power source such as a battery . ≪ / RTI > The ferroelectric memory cell, which will be described below, may have advantageous properties that can result in improved performance compared to other memory architectures.

The memory controller 140 controls the operation (reading, writing, refreshing, etc.) of the memory cell 105 through various components such as a row decoder 120, a column decoder 130 and a sensing component 125 can do. The memory controller 140 may generate row and column address signals to activate the desired word line 110 and digit line 115. The memory controller 140 may also generate and control various voltage potentials used during operation of the memory device 100. In general, the amplitude, shape or duration of the applied voltage discussed in this application may be adjusted or varied and may be different for the various operations discussed in operating the memory device 100. Moreover, one, many, or all of the memory cells 105 in the memory device 100 may be accessed simultaneously. For example, many or all of the cells of memory device 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

In some examples of memory device 100, memory cell 105 may be laid out into banks and arrays. For example, memory cells 105 may be laid out in an 8-bank configuration, with each bank being selectable by a bank address. The row decoders may be arranged in two rows in the longitudinal direction at the central portion of each bank, and the column decoder may be arranged in the lateral direction in the central portion. Arrays 0 to 3 can be arranged in four areas divided by a row decoder and a column decoder. Each array may be divided into blocks (e.g., 16 blocks). Block 0 of the array can be divided into two parts, one part being disposed at each end of the array. In some examples, each block may be selected by a block address configured by six bits of the row address.

The array control circuit can receive the row address and transmit the row address to the block selected by the block address. In addition, the array control circuit may transmit an area control signal TG to each block. A row of sense amplifiers (of sense component 125), each sensing and amplifying a signal read from a memory cell onto a digit line, may be placed between adjacent blocks. In the sense amplification circuit, a control signal for controlling the sense amplifier in the corresponding row may be input. Exemplary configurations of the blocks are described with reference to Figures 4, 5, 11, 16 and 17.

The column address may be input to the column decoder 130 such that the column select line YS is selected. For example, if eight YS lines are selected, 64 sense amplifiers in the sense amplifiers selected by the active command and 64 pairs of IO pair lines can be selectively connected to each other. The read data and write data of the 64-bit memory cell 105 to be accessed may be transferred to the sensing component 125 via the IO pair lines and received from the sensing component. A parallel / serial conversion circuit may be installed between the sensing component 125 and the data input / output buffer 135 and may be implemented in a process of converting from 64 bits of parallel data to serial data having 8 burst widths of 8 burst lengths May be performed according to a column address (e.g., 3 bits).

FIG. 2 illustrates an exemplary memory device 200, in accordance with various embodiments. The memory device 200 may include a ferroelectric memory cell 105-a, an access line 110-a, a digit line 115-a, and a sensing component 125-a, May be examples of memory cells 105, word lines 110, digit lines 115, and sensing components 125 that are individually described for reference. The memory device 200 includes a logic storage component, e.g., a capacitor 205, including two conductive terminals, a cell plate (CP) 210, and a cell bottom (CB) . These terminals can be separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging the capacitor 205.

The stored state of the capacitor 205 may be read or sensed by operating the various elements represented in the memory device 200. Capacitor 205 may be in electronic communication with digit line 115-a. Thus, when the selection component 220 is deactivated, the capacitor 205 can be isolated from the digit line 115-a and the capacitor 205 can be isolated from the selection component 220 when the selection component 220 is activated 220 to the digit line 115-a. In some cases, the selection component 220 can be a transistor (e.g., an nMOS transistor) and its operation can be controlled by applying a voltage to the transistor gate, where the voltage magnitude is the critical magnitude of the magnitude transistor . The word line 110-a may activate the selection component 220; For example, the voltage applied to the word line 110-a may be applied to the transistor gate, thereby connecting the capacitor 205 to the digit line 115-a.

In the example shown in Fig. 2, the capacitor 205 is a ferroelectric capacitor. Due to the ferroelectric material between the plates of the capacitor 205, the capacitor 205 may not be discharged when connected to the digit line 115-a. Instead, the cell plate 210 may be biased by an external voltage to cause a change in the stored charge on the capacitor 205. The change in the stored charge depends on the initial state of the capacitor 205, i.e., whether the initial stored state is logic 1 or logic zero. The change in stored charge may be compared to a reference (e.g., a reference voltage) by sensing component 125-a to determine the logic state stored in memory cell 105-a.

Certain sensing techniques or processes can take many forms. In one example, the digit line 115-a may have a unique capacitance and generate a non-zero voltage when the capacitor 205 is charged or discharged in response to a voltage applied to the cell plate 210. The intrinsic electrostatic capacitance may depend on the physical characteristics including the dimensions of the digit line 115-a. The digit line 115-a may be connected to a plurality of memory cells 105, so that the digit line 115-a may have a length that results in negligible capacitance (e.g., the size of pF). The subsequent voltage of the digit line 115-a may depend on the initial logic state of the capacitor 205 and the sensing component 125-a may compare this voltage to the reference voltage.

To write the memory cell 105-a, a voltage potential may be applied across the capacitor 205. [ Various methods can be used. In one example, the selection component 220 may be activated through the word line 110-a to electrically connect the capacitor 205 to the digit line 115-a. The voltage may be applied across the capacitor 205 by controlling the voltage on the cell plate 210 and the cell bottom 215 through the digit line 115-a. To write logic 1, the cell plate 210 can be driven high, i.e. a positive voltage can be applied, and the cell bottom 215 can be driven low, i. E., Connected to ground, It may be in fact grounded, or a negative voltage may be applied. The inverse can be performed to record a logic zero, the cell plate 210 can be driven low, and the cell bottom 215 can be driven high.

FIG. 3 illustrates a block diagram 300 of a memory device 100-a, in accordance with various embodiments. A memory device 100-a includes memory controller 140-a and memory cell 105-b, which may be examples of memory controller 140 and memory cell 105 described with reference to Figures 1 and 2, . The memory controller 140-a may include a bias component 310 and a timing component 315 and may operate the memory device 100-a described in one or more of Figures 1 and 2 have. The memory controller 140-a may be in electronic communication with the access line 110-b, the digit line 115-b, the sensing component 125-b, and the cell plate 210-a, The digit line 115, the sensing component 125, and the cell plate 210 described with reference to Figures 1 and 2, respectively. The memory device 100-a may also include a reference component 320 and a latch 325. The components of memory device 100-a may be in electronic communication with one another and may perform the functions described with reference to one or more of Figures 1 and 2. In some cases, the reference component 320, the sensing component 125-b, and the latch 325 may be components of the memory controller 140-a.

The memory controller 140-a may be configured to activate the word line 110-b, the cell plate 210-a, or the digit line 115-b by applying a voltage to these various nodes. For example, bias component 310 may be used to operate (e.g., read or write memory cell 105-b) to operate memory cell 105-b described with reference to Figures 1 and 2 For example). ≪ / RTI > In some cases, memory controller 140-a may include the row decoder, column decoder, or both described with reference to FIG. This may enable memory controller 140-a to access one or more memory cells 105-b. The bias component 310 may also provide a voltage potential to the reference component 320 to generate a reference signal for the sensing component 125-b. In addition, the bias component 310 may provide a voltage potential for operation of the sensing component 125-b.

In some cases, memory controller 140-a may use timing component 315 to perform its operations. For example, the timing component 315 may provide various word line selections or timing of the cell plate bias, including timing to switch the switching function and the voltage application to perform memory functions such as reading and writing described in this application Can be controlled. In some cases, the timing component 315 may control the operation of the bias component 310.

The reference component 320 may include various components for generating a reference signal for the sensing component 125-b. The reference component 320 may comprise circuitry specifically configured to generate a reference signal. In some cases, the reference component 320 may include other ferroelectric memory cells. In some instances, the reference component 320 may be configured to output a voltage having a value between two sense voltages, or the reference component 320 may be designed to output a virtual ground voltage.

The sensing component 125-b may compare the signal from the memory cell 105-b (received via the digit line 115-b) with the reference signal from the reference component 320. When determining the logic state, the sensing component 125-b may store the logic state in the latch 325 that may be used in accordance with operations of the electronic device using the device in which the memory device 100-a is part .

4 illustrates a first example of an apparatus 400 including a hybrid memory according to various embodiments. Apparatus 400 may include a first memory cell array 405-a and a second memory cell array 405-b. In some instances, the device 400 may be an example of the aspects of one block of the memory device 100 described with reference to Figures 1 and 3.

The first memory cell array 405-a may include a plurality of memory cells including a first plurality of memory cells 410 coupled to a first digit line (e.g., a digit line BLDk). The first memory cell array 405-a may also include other memory cells 415 coupled to other digit lines (e.g., digit lines BLD1, BLD2, BLDk-1, etc.). The second memory cell array 405-b may also include a plurality of memory cells including a second plurality of memory cells 420 coupled to a second digit line (e.g., digit line BLFk). The second memory cell array 405-b may also include other memory cells 425 coupled to other digit lines (e.g., digit lines BLF1, BLF2, BLFk-1, etc.). In some instances, some or all of the memory cells 410, 415, 420, and / or 425 included in the first memory cell array 405-a or the second memory cell array 405- 2, < / RTI > and < RTI ID = 0.0 > 3, < / RTI >

Each digit line of the first memory cell array 405-a may be coupled to a respective sense amplifier in the paging buffer register 430. [ Each digit line of the second memory cell array 405-b may be selectively coupled to a respective sense amplifier in the paging buffer register 430 through the digit line of the first memory cell array 405-a. For example, the first transfer gate 435 (e.g., an nMOS transistor) may have source and drain terminals coupled to a first digit line BLDk and a second digit line BLFk, respectively. The area control signal TG applied to the gate terminal of the first transfer gate 435 activates the first transfer gate 435 to open the first transfer gate 435 to disconnect the second digit line from the first digit line Or couples the second digit line to the first digit line by closing the first transmission gate 435. When the first transfer gate 435 is closed, the data is read from or written to the second plurality of memory cells 420, or the first plurality of memory cells 410 and the memory cells 420 of the second plurality of memory cells 420 The data can be transmitted between them. Other transfer gates 440 may be used to selectively couple the other digit lines of the second memory cell array 405-b to the digit lines of the first memory cell array 405-a.

Each of the sense amplifiers in the paging buffer register 430 may be shared by the first memory cell array 405-a and the second memory cell array 405-b. For example, the first digit line BLDk may be coupled to the first sense amplifier, and when the first transfer gate 435 is closed, the second digit line BLFk is coupled to the first sense amplifier < RTI ID = 0.0 >Lt; / RTI >

In some instances, the first memory cell array 405-a may include fewer memory cells than the second memory cell array 405-b, and the first plurality of memory cells 410 may include a second plurality And may include fewer memory cells than memory cells 420. In the same or different examples, the first memory cell array 405-a may comprise a first plurality of ferroelectric memory cells and the second memory cell array 405-b may comprise a second plurality of ferroelectric memory cells . In some instances, the first plurality of ferroelectric memory cells may be configured to operate in a volatile mode (e.g., the first plurality of ferroelectric memory cells or first memory cell array 405-a may be configured to operate as a DRAM . When the first memory cell array 405-a operates as a DRAM, the cell plates of the memory cells 410 and 415 included in the first memory cell array 405-a are connected to the first common voltage rail and to a rail. In some examples, the second plurality of ferroelectric memory cells may be operated in non-volatile mode (e.g., a second plurality of ferroelectric memory cells or second memory cell array 405-b may be configured to operate as FeRAM) . When the second memory cell array 405-b operates as FeRAM, the cell plates of the memory cells 420 and 425 included in the second memory cell array 405-b are turned to the voltage HVDD (or VDD / 2) And may be connected to the second common voltage rail.

The memory cells in the first memory cell array 405-a or the second memory cell array 405-b are connected to one or more digit lines via the column decoder 130-a and to the row decoder 120- (Or accessed) by applying an appropriate voltage to one or more word lines via word line 120-b.

In some examples, the first memory cell array 405-a and the second memory cell array 405-b may be provided on the same conductor chip.

FIG. 5 illustrates a second example of an apparatus 500 including a hybrid memory according to various embodiments. The apparatus 500 may include a first memory cell array 505-a, a second memory cell array 505-b, and a third memory cell array 505-c. The second memory cell array 505-b may be located between the first memory cell array 505-a and the third memory cell array 505-c. In some instances, the device 500 may be an example of one aspect of one block of the memory device described with reference to FIG.

The first memory cell array 505-a may include a plurality of memory cells including a first plurality of memory cells 510 coupled to a first digit line (e.g., a digit line BLDk). The first memory cell array 505-a may also include other memory cells 515 coupled to other digit lines (e.g., digit lines BLD2, etc.). The second memory cell array 505-b also includes a second plurality of memory cells 520 connected to a second digit line (e.g., a digit line BLFk), a third digit line (e.g., a digit line BLFk- 1). ≪ / RTI > The second memory cell array 505-b may also include other memory cells 530 connected to other digit lines (e.g., digit lines BLF1, BLF2, etc.). The third memory cell array 505-c may include a plurality of memory cells including a fourth plurality of memory cells 535 coupled to a fourth digit line (e.g., a digit line BLDk-1) have. The third memory cell array 505-c may also include other memory cells 540 coupled to other digit lines (e.g., digit lines BLD2, etc.). In some instances, the memory cells 510, 515, 520, 525, 525 included in the first memory cell array 505-a, the second memory cell array 505-b or the third memory cell array 505- 530, 535, and / or 540) may be an example of the sides of the memory cell 105 described with reference to Figures 1, 2, and 3.

The first memory cell array 505-a may include k / 2 digit lines identified by even digit lines BLD2 through BLDk. The third memory cell array 505-c may include a second set of k / 2 digit lines identified by odd digit lines BLD1 through BLDk-1. Each digit line of the first memory cell array 505-a and the third memory cell array 505-c may be coupled to a respective sense amplifier in a paging buffer register (e.g., a first sense amplifier SAk (545-a), the second sense amplifier SAk-1 or 545-b, the third sense amplifier SA2 or 545-c), and the fourth sense amplifier SA1 or 545- ) To the input terminal of one of the plurality of sense amplifiers.

Each digit line of the first memory cell array 505-a and the third memory cell array 505-c may be connected to the input terminal of the respective sense amplifier in a folded back arrangement. For example, a first plurality of memory cells may be coupled to a first subset of memory cells 550 coupled to a first digit line (BLDk-1) and to a second subset of memory cells 555 coupled to a first digit line A first digit line may be coupled to an input terminal of a first sense amplifier 545-a between a first subset of memory cells 550 and a second subset of memory cells 555 . Similarly, a fourth plurality of memory cells include a first subset of memory cells 560 coupled to a fourth digit line (BLDk) and a second subset of memory cells 565 coupled to a fourth digit line And a fourth digit line may be coupled to the input terminal of the second sense amplifier 545-b between the first subset of memory cells 560 and the second subset of memory cells 565. [

Each digit line of the second memory cell array 505-b is connected to the respective sense amplifiers in the paging buffer register via the digit line of the first memory cell array 505-a or the third memory cell array 505- And may be selectively coupled to the input terminal. For example, the first transmission gate 570 (e.g., an nMOS transistor) may have source and drain terminals coupled to a first digit line BLDk and a second digit line BLFk, respectively. The area control signal TG applied to the gate terminal of the first transfer gate 570 activates the first transfer gate 570 to open the first transfer gate 570 to transfer the second digit line from the first digit line Or the gate 570 is closed to couple the second digit line to the first digit line. When the first transfer gate 570 is closed, the data is read from or written to a second plurality of memory cells 520, or the first plurality of memory cells 510 and the memory cells 520 of the second plurality of memory cells 520, The data can be transmitted between them. The second transmission gate 575 (e.g., an nMOS transistor) may have source and drain terminals individually coupled to the third digit line BLFk-1 and the fourth digit line BLDk-1. The area control signal TG applied to the gate terminal of the second transfer gate 575 activates the second transfer gate 575 to open the second transfer gate 575 to transfer the third digit line from the fourth digit line And couples the third digit line to the fourth digit line by disassociating or closing the second transmission gate 575. [ When the second transfer gate 575 is closed, the data is read from or written to the third plurality of memory cells 525, or written to the memory of the third plurality of memory cells 525 and the fourth plurality of memory cells 535 Lt; / RTI > may be transmitted between cells. Other transfer gates 580 may be used to selectively connect the other digit lines of the second memory cell array 505-b to the first memory cell array 505-a or the third memory cell array 505- Lt; / RTI >

In some examples, each digit line (e.g., each even BLD digit line) of the first memory cell array 505-a is coupled to two digit lines by its source and drain terminals, (For example, a BLF digit line) of the second memory cell array 505-b by an isolation transistor 585 (for example, an nMOS transistor) connected to the ground . For example, the first isolation transistor 585 is coupled between the first digit line BLDk and the third digit line BLFk-1. Similarly, each digit line (e.g., each odd-numbered BLD digit line) of the third memory cell array 505-c is coupled to two digit lines by its source and drain terminals, (E.g., a BLF digit line) of the second memory cell array 505-b by an isolation transistor 585 (e.g., an nMOS transistor) connected to ground. For example, the second isolation transistor 585 is coupled between the fourth digit line BLDk-1 and the second digit line BLFk.

The sense amplifiers in the paging buffer register are controlled by the first memory cell array 505-a and the second memory cell array 505-b or the second memory cell array 505-b and the third memory cell array 505- -c). < / RTI >

In some examples, each of the first memory cell array 505-a and the third memory cell array 505-c may include fewer memory cells than the second memory cell array 505-b, Each of the plurality of memory cells 510 and the fourth plurality of memory cells 535 includes less memory cells than each of the second plurality of memory cells 520 and the third plurality of memory cells 525 . In the same or different examples, each of the first memory cell array 505-a and the third memory cell array 505-c may include a first plurality of ferroelectric memory cells and the second memory cell array 505- 505-b may include a second plurality of ferroelectric memory cells. In some instances, a first plurality of ferroelectric memory cells may be configured to operate in a volatile mode (e.g., a first plurality of ferroelectric memory cells or first and third memory cell arrays 505-a, 505- c) may be configured to operate as a kxm DRAM). When the first and third memory cell arrays 505-a and 505-c operate as DRAMs, the memory cells 510 and 515 included in the first and third memory cell arrays 505-a and 505- , 535, and 540 may be coupled to a first common voltage rail set to voltage VSS. In some examples, the second plurality of ferroelectric memory cells may be arranged in a non-volatile mode (e.g., a second plurality of ferroelectric memory cells or a second memory cell array 505-b may be configured to operate as kxn FeRAMs ) Lt; / RTI > The cell plates of the memory cells 520, 525 and 530 included in the second memory cell array 505-b are connected to the voltage HVDD (or VDD / 2 ) To the second common voltage rail.

The memory cells in the first memory cell array 505-a, the second memory cell array 505-b, or the third memory cell array 505-c receive appropriate voltages from one or more digit lines (e.g., (E. G., Using a row decoder) and one or more word lines (e. G., Using a row decoder). 5 illustrates a first plurality of word lines (WLD1, WLDm, etc.) and a second memory cell array 505-b for addressing the first and third memory cell arrays 505-a and 505-c, (E.g., WLF1, WLFn, etc.) for addressing a plurality of word lines. When the first memory cell array 505-a and the third memory cell array 505-c operate as DRAMs, each word line of the first plurality of word lines is connected to a first subset ( Representing the first bit of the kxm DRAM array) in a second subset within the memory cells 555, a third memory cell in a first subset within the memory cells 560 and a second memory cell May be coupled to a fourth memory cell in a second subset within memory cells 565 and to other memory cells in a first memory cell array 505-a and a third memory cell array 505-c. In some examples, each of the word lines in a first plurality of word lines (e.g., WLD1, WLDm, etc.) may be a word line on a logic representing a pair of physical word lines - for example, Line WLD1 may include a first physical word line for addressing the first memory cell array 505-a, and a second physical word line for addressing the third memory cell array 505-c. In some examples, the number of word lines in the first set of word lines and the number of word lines in the second set of word lines may be optimized for the amount of read signal or optimized for the application.

In operation, the set of memory cells in the first memory cell array 505-a or the third memory cell array 505-c can be accessed by driving the region control signal TG low, The digit lines of the first memory cell array 505-a and the third memory cell array 505-c are connected to the digit lines of the second memory cell array 505-b, Lt; / RTI > One of the word lines WLD may then be asserted to select a set of memory cells in the first memory cell array 505-a and / or the third memory cell array 505-c. have. As a result, a sufficient read signal voltage is obtained even in the DRAM operation in which the signal charge amount is small, and the operation margin is improved. In addition, in this embodiment, during DRAM operation, two memory cells are connected to the digit line in parallel to each other. Consequently, although there is no significant increase in the read signal voltage, by connecting the two memory cells in parallel to each other, there is a low probability that leakage will occur simultaneously in both capacitors against leakage of charge of the capacitors, which is a problem in DRAM operation under; Therefore, the margin for leakage is improved.

The memory cells of the second memory cell array 505-b can be accessed by driving the region control signal TG high and the transfer gates 570, 575 and 580 are closed to form the second memory cell array 505-b ) To the digit lines of the first memory cell array 505-a and the third memory cell array 505-c. One of the word lines WLF may then be asserted to select a set of memory cells of the second memory cell array 505-b. 1) during a second memory cell array 505-b (e.g., during FeRAM operation) or first or third memory cell arrays 505-a, 505-c 2) the second memory cell array 505-b (e.g. during FeRAM operation) or the first or third memory cell arrays 505-a (for example, during FeRAM operation) The first or third memory cell arrays 505-a, 505-a, 505-a, 505-a, 505- no problem occurs when the digit line capacitance is increased by transferring data to / from the memory cell of the second memory cell array 505-b through the digit line of the second memory cell array 505-b. Thus, the capacitance of the digit lines of the first and third memory cell arrays 505-a and 505-c can be optimized for DRAM operation and the capacitance of the digit line of the second memory cell array 505- Capacity can be optimized for FeRAM operation.

In some examples, the first memory cell array 505-a, the second memory cell array 505-b, and the third memory cell array 505-c may be provided on the same conductor chip.

6 shows a first example of a sense amplifier 600 according to various embodiments. In some instances, sense amplifier 600 may be an example of one of the sides of one of the sense amplifiers 545 described with reference to FIG. In some examples, sense amplifier 600 may include a sense circuit that compares signals on digit lines (BL and / BL), where / BL is a complementary digit line to BL. By way of example, the sensing circuit may comprise four transistor sets including two pMOS transistors 605-a and 605-b and two nMOS transistors 610-a and 610-b. The sense amplifier 600 may also include a pair of transistors (e.g., nMOS transistors 615-a and 615-b) for individually coupling BL or / BL to the I / O registers IO have. Transistors 615-a and 615-b may have gate terminals driven by a column decoder select signal YS.

The sense amplifier 600 may be configured to read BL from a first voltage cell array (e. G., A DRAM array configured similar to the memory cell array 505-a described with reference to Figure 5) (E. G., HVDD). ≪ / RTI > The first circuit has a gate terminal driven by a precharge (PC) signal, and is coupled by a source and a drain terminal between a voltage source HVDD (for example, 1/2 of VDD) and BL (or / BL) Gt; a < / RTI > pair of transistors 620-a, 620-b. The third transistor 625 coupled by the source and drain terminals between BL and its / BL may also have a gate terminal that is driven by a PC signal.

The sense amplifier 600 biases BL to the second voltage before reading from the second memory cell array (e.g., a FeRAM array configured similarly to the memory cell array 505-b described with reference to Figure 5) And a second circuit operable to cause the second circuit to operate. The second circuit may include a transistor 630-a coupled by a source and a drain terminal between BL and VSS (or ground). The gate terminal of the gate transistor 630-a may be driven by the selection signal, FER. The FER signal may also drive transistor 635-a that biases / BL to voltage Vref when BL is biased to VSS. Similarly, a pair of transistors 630-b and 635-b having a gate terminal driven by the selection signal FEL are biased to / from VSS and BL to VREF before reading from the memory cell array connected to / BL can do.

Figure 7 illustrates that when a second memory cell array 505-b is configured for FeRAM operation and a first sense amplifier 545-a is configured as described with reference to Figure 6, according to various embodiments, Illustrate exemplary waveforms 700 for use in read and rewrite operations in the second memory cell array 505-b described with reference to FIG.

At the end of precharge period 705, the PC signal may be switched from a high level (e.g., VDD) to a low level (e.g., VSS), and then the FER signal may be switched to a low level To a high level. If the PC signal is low level and the FER signal is high level, BL can be switched from HVDD to VSS while / BL can be switched from HVDD to Vref.

During the cell selection period 710 subsequent to the precharge period 705, the access line (e.g., WLF1) of the second memory cell array 505-b is at a low level (e.g., VKK) (E.g., VPP), and the high level signal voltage may be switched from the memory cell 520 associated with the second digit line, BLFk, and word line WLFl to the second digit line BLFk of Figure 5 Of BL).

During the sense amplification period 715 subsequent to the cell selection period 710, the CSN signal (shown in FIG. 6 but not shown in FIG. 7) may be switched from a high level to a low level, , But not shown in FIG. 7) is switched from low level to high level, thereby activating the first sense amplifier 545-a so that signals on BL and / BL are sensed and amplified. If this state is maintained through the rewrite period 720 subsequent to the sense amplification period 715, the high level information rewrite is performed on the memory cell at the time of the high level information read, and the low level information rewrite is performed on the low level read Lt; RTI ID = 0.0 > memory cell.

During the start of the precharge period 725 following the rewrite period 720, the first sense amplifier 545-a may be deactivated and the PC signal may be switched from a low level to a high level. This state precharges BL and / BL to HVDD. The word line WLF1 can then be switched from a high voltage to a low voltage and the sequence of read and rewrite operations in the second memory cell array 505-b can be completed.

FIG. 8 is a block diagram illustrating the read and write operations in the second memory cell array 505-b described with reference to FIG. 5 when the second memory cell array 505-b is configured for FeRAM operation, according to various embodiments. Examples of analysis of rewrite operations and hysteresis characteristics are illustrated. In these examples, the amount of residual polarization charge at the high level information holding time (indicated by black dots labeled "H HOLD") can be about 10 fC (femto-coulomb), and the low level information holding time , The digitally-line capacitance may be 60 fF, so that when the access line of the second memory cell array 505-b is switched from a low level to a high level, The positions are shifted in the left down direction and in the intersection with the load straight line (not shown in FIG. 8), the digit line voltage can be VsigH or VsigL. The difference between one of these voltages VsigH or VsigL and Vref forms the read signal voltage so that the digit line voltage at the time of the high level read operation can be amplified to VDD = 0.0 > VSS < / RTI > = 0V. If this state is maintained for a predetermined time period, the rewrite operation can be completed; When the precharge state is started, the sequence can return to the original information holding position ("H hold" or "L hold").

9 is a block diagram of a memory cell array 500 when a first memory cell array 505-a is configured for DRAM operation and a first sense amplifier 545-a is configured as described with reference to FIG. 6, Illustrate exemplary waveforms 900 for use in read and rewrite operations in the first memory cell array 505-a (or the third memory cell array 505-c).

At the end of precharge period 905, the PC signal may be switched from a high level (e.g., VDD) to a low level (e.g., VSS). During the cell selection period 910 following the precharge period 905, the access line (e.g., WLD1) of the first memory cell array 505-a is switched from a low level (e.g., VKK) (E.g., VPP), and the high level signal voltage may be switched from the memory cell 510 associated with the first digit line BLDk and the word line WLDl to the first digit line 6, < / RTI > BL).

During the sense amplification period 915 subsequent to the cell selection period 910, the CSN signal (shown in FIG. 6 but not shown in FIG. 9) can be switched from a high level to a low level and the CSP signal , But not shown in FIG. 9) is switched from a low level to a high level, thereby activating the first sense amplifier 545-a so that signals on BL and / BL are sensed and amplified. If this state is maintained through the rewrite period 920 subsequent to the sense amplification period 915, the high level information rewrite is performed on the memory cell at the time of the high level information readout, and the low level information rewrite is performed on the low level readout Lt; RTI ID = 0.0 > memory cell.

During the start of the precharge period 925 following the rewrite period 920, the word line WLD1 may be switched from a high voltage to a low voltage. Then, the first sense amplifier 545-a may be deactivated and the PC signal may be switched from a low level to a high level. This state precharges BL and / BL to HVDD, and the sequence of read and rewrite operations in the first memory cell array 505-a can be completed.

Figure 10 is a block diagram illustrating the read and write operations of the first memory cell array 505-a described with reference to Figure 5 when the first memory cell array 505-a is configured for DRAM operation, Examples of analysis of rewrite operations and hysteresis characteristics are illustrated. When operating in the DRAM mode of operation, only the phase-dielectric component of the ferroelectric capacitor of the memory cell is used. Thus, read and rewrite operations are performed within the linear region of the hysteresis characteristic. The capacitance of the dielectric component of the ferroelectric capacitor may be set to about 7.5 fF. In these examples, the position indicated by the black point labeled "H hold" may correspond to the high level information hold time, and the position indicated by the white point indicated by "L hold" may correspond to the low level information hold time . In addition, the digit line capacitance may be set to 20 fF, and when the word line is switched from low level to high level in the intersection with the load line (not shown in Fig. 10), the digit line voltage is charged Because of sharing, it can be VsigH or VsigL. The difference between this voltage and HVDD = 1V, which corresponds to the digit line precharge voltage, can form the read signal voltage, so that the digit line voltage can be amplified to VDD = 2V at the time of the high level read operation, Level at the time of the read operation. If this state is maintained for a predetermined time period, the rewrite operation can be completed; When the precharge state is started, the sequence can return to the original information holding position ("H hold" or "L hold").

11 shows a third example of an apparatus 1100 that includes a hybrid memory according to various embodiments. The device 1100 may be configured similar to the device 500 described with reference to Figure 5 and includes a first memory cell array 505-a, a second memory cell array 505-b, Cell array 505-c. The second memory cell array 505-b may be located between the first memory cell array 505-a and the third memory cell array 505-c. In some instances, the device 1100 may be an example of the aspects of one block of the memory device 100 described with reference to Figures 1 and 3.

The device 500 described with reference to FIG. 5 may be used to perform FeRAM operations in the second memory cell array 505-b at a relatively high power-supply voltage (e.g., VDD = 2V). On the other hand, the device 1100 may be used to perform FeRAM operations in the second memory cell array 505-b at a relatively low power-supply voltage (e.g., VDD = 1V). Apparatus 1100 may be configured such that each cell plate of a second plurality of memory cells (e.g., each cell plate of a memory cell connected to a second digit line BLFk) is connected to a different voltage potential line (E.g., different ones of the plate lines PL1, PLn). Similarly, each cell plate in a third plurality of memory cells (e.g., each cell plate of a memory cell connected to the third digit line BLFk-1) may be connected to a different voltage potential line. The memory cells in the same column connected to the same word line may be connected to the same voltage potential line. Each of the plurality of voltage potential lines may be independently controllable.

12 illustrates a second example of a sense amplifier 1200 in accordance with various embodiments. The sense amplifier may be configured similar to the sense amplifier 600 described with reference to FIG. In some instances, the sense amplifier 1200 may be an example of one of the sides of one of the sense amplifiers 545 shown in FIG.

The sense amplifier 1200 is further provided with a first pull-down transistor 1205-a (e.g., a first nMOS transistor) to pull the digit line BL to VSS, The sense amplifier 600 described with reference to FIG. 6 in that a pull-down transistor 1205-b (e.g., a second nMOS transistor) is added to pull the complementary digit line / BL to VSS different. The gate terminals of the first and second pull-down transistors 1205-a and 1205-b may be driven by a reset (RES) signal to reset the digit line and the complementary digit line to VSS in parallel.

Figure 13 is a schematic diagram of a memory cell array 505-b when a second memory cell array 505-b is configured for FeRAM operation and a first sense amplifier 545-a is configured as described with reference to Figure 12, Illustrate exemplary waveforms 1300 for use in read and rewrite operations in the second memory cell array 505-b described with reference to FIG.

At the end of precharge period 1305, the PC signal may be switched from a high level (e.g., VDD) to a low level (e.g., VSS), and then the FER signal is applied to a low level To a high level. If the PC signal is low level, BL can be switched from HVDD to VSS, while / BL can be switched from HVDD to Vref.

The access line (e.g., WLF1) of the second memory cell array 505-b is at a low level (e.g., VKK) during a cell selection period 1310 subsequent to the precharge period 1305, (E.g., VPP), and the voltage potential line PL1 may be switched from a low level to a high level, and the high level signal voltage may be switched to a second digit line, BLFk, and a word line, (BLFk in Fig. 11 or BL in Fig. 12) from the first digit line 520 (Fig.

During the sense amplification period 1315 subsequent to the cell selection period 1310, the CSN signal (shown in FIG. 12 but not shown in FIG. 13) may be switched from a high level to a low level, , But not shown in Fig. 13) is switched from a low level to a high level, thereby activating the first sense amplifier 545-a so that signals on BL and / BL are sensed and amplified. If this state is maintained through the rewrite period 1320 subsequent to the sense amplification period 1315, the low level information rewrite is performed on the memory cell at the time of low level information read. When the voltage potential line PL1 is switched from the high level to the low level, high level information rewriting is performed on the memory cell at the time of the high level reading.

During the start of precharge period 1325 following rewrite period 1320, first sense amplifier 545-a may be deactivated and then the RES signal may be deactivated at a low level (e.g., VSS) to a high level (e.g., VDD) so that BL and / BL can be reset to VSS. Subsequently, WLF1 is controlled to VKK, and finally, PC is controlled to a high level to precharge BL and / BL to HVDD, completing the sequence of read and rewrite operations.

Figure 14 illustrates the read and write operations in the second memory cell array 505-b described with reference to Figure 11 when the second memory cell array 505-b is configured for FeRAM operation, according to various embodiments. Examples of analysis of rewrite operations and hysteresis characteristics are illustrated. In these examples, the amount of residual polarization charge at the high level information holding time (indicated by the black dot labeled "H HOLD") may be about 10 fC and the low level information holding time (indicated by the white dot labeled & The digitally-line capacitance may be about 60 fF, so that when the voltage potential line (plate line) of the second memory cell array 505-b is switched from the low level to the high level, The individual positions are moved in the left down direction and in the intersection with the load straight line (not shown in Fig. 14), the digit line voltage becomes VsigH or VsigL. The difference between one of these voltages (VsigH or VsigL) and Vref forms the read signal voltage, so that the digit line voltage at the time of the high level read operation can be amplified to VDD = 1V or the low level read operation Lt; RTI ID = 0.0 > VSS = 0V. ≪ / RTI > During a low level read operation, this state forms a rewrite state; However, in the high-level read operation, since the cell plate voltage and the digit line voltage are both 1 V, the black point is located in the vicinity of the L-hold position. When the cell plate voltage is driven to VSS to rewrite high level information, the black point on the hysteresis curve can be returned to the upper right, and the white point can be returned to the L-hold state. When BL is successively reset to VSS, the black dot is returned to the H-HOLD state to complete the rewrite process. When the precharge state is started, the potential of BL is precharged to HVDD = 0.5V.

Figure 15 illustrates a block diagram of a first memory cell array 505-a, which is described with reference to Figure 11, when reading from and writing to a first memory cell array 505-a, Examples of analysis of rewrite operations and hysteresis characteristics are illustrated. When operating in the DRAM mode of operation, only the phase-dielectric component of the ferroelectric capacitor of the memory cell is used. Thus, read and rewrite operations are performed within the linear region of the hysteresis characteristic. The capacitance of the dielectric component of the ferroelectric capacitor may be set to about 7.5 fF. In these examples, the position indicated by the black point labeled "H hold" may correspond to the high level information hold time, and the position indicated by the white point indicated by "L hold" may correspond to the low level information hold time . In addition, the digit line capacitance may be set to 20 fF, and when the word line is switched from low level to high level in the intersection with the load line (not shown in Figure 15), the digit line voltage is charged Because of sharing, it can be VsigH or VsigL. The difference between this voltage and HVDD = 0.5V corresponding to the digit line pre-charge voltage can form the read signal voltage, so that the digit line voltage can be amplified to VDD = 1V at the time of the high level read operation, or And is amplified to VSS = 0V at the time of a low level read operation. If this state is maintained for a predetermined time period, the rewrite operation can be completed; When the precharge state is started, the sequence can return to the original information holding position ("H hold" or "L hold").

16 illustrates a fourth example of an apparatus 1600 including a hybrid memory according to various embodiments. The device 1600 may be configured similar to the device 500 described with reference to Figure 5 and includes a first memory cell array 505-a, a second memory cell array 505-b, Cell array 505-c. The second memory cell array 505-b may be located between the first memory cell array 505-a and the third memory cell array 505-c. In some examples, device 1600 may be an example of one side of one block of memory device 100 described with reference to FIGS.

(E.g., BLD1, BLD2) of the first and third memory cell arrays 505-a and 505-c in the device 1600, as opposed to the device 500 described with reference to Fig. 5 , BLDk-1, BLDk, etc.) are not folded back. For example, a second subset of memory cells 555 coupled to a first digit line (BLDk) and a portion of a first digit line coupled to a second subset of memory cells 555 are coupled to a first sense amplifier 545- a < / RTI > Alternatively, device 1600 may be configured without a portion of the first digit line to which a second subset of memory cells 555 and a second subset of memory cells 555 are coupled. This reduces the parasitic capacitance of the first digit line by about half and enables a greater number of memory cells to be connected to the second digit line BLFk of the second memory cell array 505-b. A similar change can be made to each digit line of the first and third memory cell arrays 505-a and 505-c and a larger number of memory cells can be stored in each digit of the second memory cell array 505- Lines. ≪ / RTI > When the second memory cell array 505-b is configured as FeRAM, the techniques described with reference to Fig. 16 may be configured to have a larger FeRAM than can be supported by the device 500 described with reference to Fig. 5 .

FIG. 17 shows a fifth example of an apparatus 1700 including hybrid memory according to various embodiments. The device 1700 may be configured similar to the device 500 described with reference to Figure 5 and includes a first memory cell array 505-a, a second memory cell array 505-b, Cell array 505-c. The second memory cell array 505-b may be located between the first memory cell array 505-a and the third memory cell array 505-c. In some instances, the device 1700 may be an example of one side of one block of the memory device 100 described with reference to FIGS.

In contrast to the device 500 described with reference to FIG. 5, the first and third memory cell arrays 505-a and 505-c may be provided with a dummy word line. For example, the first memory cell array 505-a may be provided with a first dummy word line DWLR and the third memory cell array 505-c may be provided with a second dummy word line DWLL. have. Only one memory cell of the pair of DRAM memory cells coupled to each dummy word line DWLR or DWLL can be designed to function efficiently (e.g., the cell plate of the memory cells 510-a and 540-a) (E.g., memory cells 515-a and 535-a) coupled to a dummy word line may provide a reference signal voltage level on an individual digit line Can function as a dummy (or reference) memory cell. The reference signal voltage level may be used by a corresponding sense amplifier during a sensing (or reading) operation. As a result, the digit lines of the first and third memory cell arrays 505-a and 505-c can be precharged to VSS during DRAM operation and FeRAM operation of the device 1700 and the sense amplifiers The amplifiers 545-a, the second sense amplifiers 545-b, the third sense amplifiers 545-c, and the fourth sense amplifiers 545-d need not include the HVDD precharge control The transistors 620-a, 620-b, and 625 described with reference to FIG. 6).

In some examples, the dummy word lines and non-functional memory cells described with reference to FIG. 17 may be integrated into device 1700 described with reference to FIG. 11, and the sense amplifiers of device 1100 may be integrated into HVDD- It is not necessary to include charge control.

18 shows a diagram of a system 1800 including hybrid main memory in accordance with various embodiments. The system 1800 may include a device 1805, which may be or include a printed circuit board to connect or physically support the various components.

The device 1805 may include a main memory subsystem 1810, which may be an example of the memory devices 100 described in Figures 1 and 3. The main memory subsystem 1810 may include a memory controller 140-b and a plurality of memory cells 105-c, which may include memory controllers 140 and memory controllers 140- May be examples of the Mori cells 105, 410, 415, 420, 425, 510, 515, 520, 525, 530, 535 or 540 described with reference to Figs. 1-5, 11, 16 and 17. In some examples, main memory subsystem 1810 includes memory cell 105-c and paging buffer registers (including sense amplifiers) configured as described with reference to Figures 4, 5, 11, 16, can do.

The device 1805 may also include a processor 1815, a direct memory access controller (DMAC) 1820, a BIOS component 1825, a peripheral component (s) 1830 and an input / output controller 1835 have. The components of device 1805 may be in electronic communication with one another via bus 1840. Processor 1815 may be configured to operate main memory subsystem 1810 via memory controller 140-b. In some cases, the memory controller 140-b may perform the functions of the memory controller 140 described with reference to FIG. 1 or FIG. In other cases, the memory controller 140-b may be integrated into the processor 1815. The processor 1815 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, Or a combination of components of these types. In some instances, processor 1815 may be a multicore processor. The processor 1815 may perform the various functions described in the present application. Processor 1815 may be configured to execute computer-readable instructions stored in memory system 105-c, for example, to cause device 1805 to perform various functions or tasks.

The DMAC 1820 may enable the processor 1815 to perform direct memory accesses within the main memory subsystem 1810.

The BIOS component 1825 may be a software component that includes a basic input / output system (BIOS) that is operated as a firmware that can initialize and drive various hardware components of the system 1800. The BIOS component 1825 may also manage the flow of data between the processor 1815 and various components such as the peripheral component (s) 1830, the input / output controller 1835, and so on. The BIOS component 1825 may include programs or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component (s) 1830 may be any input or output device, or an interface for such devices, integrated into device 1805. Examples of peripheral devices include peripheral cards such as disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, USB controllers, serial or parallel ports, or Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) Slots.

The input / output controller 1835 includes a processor 1815 and peripheral component (s) 1830, input device (s) 1845, output device (s) 1850, and / ) Can be managed. Input / output controller 1835 may also manage peripherals that are not integrated into device 1805. In some cases, the input / output controller 1835 may represent a physical connection or port to an external peripheral.

Input device (s) 1845 may represent a signal or device external to device 1805 that provides input to device 1805 or its components. This may include a user interface or an interface with or between other devices. In some instances, input device (s) 1845 may be a peripheral that interfaces with device 1805 via peripheral component (s) 1830 or may be managed by input / output controller 1835 .

Output device (s) 1850 may represent a signal or device external to device 1805 configured to receive output from device 1805 or its components. Examples of output device 1850 may include a display, audio speakers, a printing device, another processor, or a printed circuit board. Output device (s) 1850 may be a peripheral that interfaces with device 1805 via one of peripheral component (s) 1830, or may be managed by input / output controller 1835 .

The components of device 1805, including memory controller 140-b and memory cell 105-c, may include circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described in this application, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements .

In some examples of device 1805, memory cells 105-c of main memory subsystem 1810 may be allocated between DRAM array 1860 and FeRAM array 1865, The cells and digit lines are selectively coupled to the sense amplifiers of the main memory subsystem 1810 via the digit line of the DRAM array 1860 (e.g., to the transfer gate operated by the memory controller 140-b) due to). In some instances, the processor 1815 may be configured such that the memory controller 140-b closes the transfer gate to couple the digit lines of the FeRAM array 1865 to the digit lines of the DRAM array 1860, At least one of a read command to cause the memory controller 140-b to transfer data to the array 1860 or a write command to cause the memory controller 140-b to close the transfer gates to transfer data from the DRAM array 1860 to the FeRAM array 1865 can do. The processor 1815 may also issue instructions that cause the memory controller 140-b to be transferred between the main memory subsystem 1810 and the processor 1815. [

In some of these examples, the DRAM array 1860 may be operated as cache memory for the FeRAM array 1865 by the memory controller 140-b. For example, the memory management unit (MMU) 1860 of the processor 1815 uses the two translation-lookaside buffers (e.g., TLB1 and TLB2) to determine the page address of the main memory subsystem 1810 Can be managed. The MMU 1870 can manage a memory system including three layers, such as a DRAM array 1860, a FeRAM array 1865, and a sub memory device 1855. In some instances, the memory controller 140-b may issue a store instruction in a direction opposite to the direction of transfer of page data from the FeRAM array 1865 to the DRAM array 1860. [ Data can be easily transferred and stored between the DRAM array 1860 and the FeRAM array 1865 because the DRAM array 1860 and the FeRAM array 1865 share digit lines and sense amplifiers.

In some examples of device 1805, memory controller 140-b may be configured to place page data having different attributes according to the individual characteristics of DRAM array 1860, FeRAM array 1865 or sub-memory device 1855 It is possible to control the memory cell 105-c. For example, the processor 1815 may be able to cause the memory controller 140-b to operate to couple the transfer gate to the digit line of the FeRAM array 1865 to the digit line of the DRAM array 1860, Type data into the DRAM array 1860 and writes the second type of data to the FeRAM array 1865. [

19 shows a flowchart illustrating a method 1900 of operating a memory device, according to various embodiments. The operations of method 1900 may be performed on or within a memory array, such as memory cell arrays 405 and 505, described with reference to Figures 4, 5, 11, 16, and 17. In some instances, the operation of method 1900 may be performed by control of, or under the control of, a memory controller, such as memory controller 140, described with reference to Figures 1, 3, and 18. In some instances, the memory controller may execute a set of codes for controlling the functional elements of the memory array to perform the functions described below. Additionally or alternatively, the memory controller may perform aspects of the functions described below using special purpose hardware.

At block 1905, the method may include determining whether to access a first memory cell of the first memory cell array or a second memory cell of the second memory cell array. The first digit line connected to the first memory cell may be coupled to a paging buffer register containing the sense amplifiers described with reference to Figures 4, 5, 11, 16 and 17. In some examples, the first memory cell may comprise a first ferroelectric memory cell and the second memory cell may comprise a second ferroelectric memory cell. In some examples, the first ferroelectric memory cell may be configured to operate in a volatile mode (e.g., a DRAM mode) and the second ferroelectric memory cell may be configured to operate in a non-volatile mode (e.g., FeRAM mode) . In some instances, the operation (s) in block 1905 may be performed using the memory controller 140 described with reference to Figs. 1, 3, and 18.

At block 1910, the method may include operating the transfer gate based at least in part upon determining to read a second memory cell of the second memory cell array. The transfer gate may be configured to selectively couple a second digit line coupled to the second memory cell described with reference to Figures 4, 5, 11, 16, and 17 to the paging buffer register via a first digit line . In some instances, the operation (s) in block 1910 may be performed using the memory controller 140 described with reference to Figs. 1, 3, and 18.

In some examples of method 1900, a first digit line may be coupled to a first plurality of memory cells including a first memory cell, and a second digit line may be coupled to a second plurality of memory cells including a second memory cell Lt; / RTI > cell. In some of these examples, the first plurality of memory cells may comprise fewer memory cells than the second plurality of memory cells.

In some examples of method 1900, the method may include preventing inversion of the ferroelectric film of the capacitor of the first memory cell by biasing the cell plate of the first memory cell. In some examples, the method may include biasing each cell plate of each memory cell of the second memory cell array to a common voltage. In some instances, the method may include independently biasing the voltage of each cell plate of each memory cell in the second memory cell array.

In some examples of method 1900, the method may include operating the first memory cell array as an embedded cache for the second memory cell array.

FIG. 20 shows a flowchart illustrating a method 2000 of operating a memory device, according to various embodiments. The operations of method 2000 may be performed on or within a memory array, such as memory cell arrays 405 and 505, described with reference to Figures 4, 5, 11, 16 and 17. In some instances, the operation of method 2000 may be performed by or under the control of a memory controller, such as memory controller 140, described with reference to Figures 1, 3, and 18. In some instances, the memory controller may execute a set of codes for controlling the functional elements of the memory array to perform the functions described below. Additionally or alternatively, the memory controller may perform aspects of the functions described below using special purpose hardware.

In block 2005, the method may include determining whether to access a first memory cell of the first memory cell array or a second memory cell of the second memory cell array. The first digit line coupled to the first memory cell may be coupled to a paging buffer register that includes the sense amplifiers described with reference to Figures 4, 5, 11, 16, and 17. In some examples, the first memory cell may comprise a first ferroelectric memory cell and the second memory cell may comprise a second ferroelectric memory cell. In some examples, the first ferroelectric memory cell may be configured to operate in a volatile mode (e.g., a DRAM mode) and the second ferroelectric memory cell may be configured to operate in a non-volatile mode (e.g., FeRAM mode) . When it is determined to access the second memory cell, the method may continue at block 2010. When it is determined not to access the second memory cell, the method may continue at block 2020. [ In some instances, the operation (s) in block 2005 may be performed using the memory controller 140 described with reference to Figs. 1, 3, and 18.

In block 2010 or 2020, the method may include operating the transfer gate based at least in part upon determining to read a second memory cell of the second memory cell array. The transfer gate may be configured to selectively couple a second digit line coupled to the second memory cell described with reference to Figures 4, 5, 11, 16, and 17 to the paging buffer register via a first digit line . At block 2010, the method may include closing the transfer gate to couple the second digit line through the first digit line to the paging buffer register. At block 2020, the method includes opening the transfer gate to decouple the second digit line from the paging buffer register. In some instances, the operation (s) in block 2010 or 2020 may be performed using the memory controller 140 described with reference to Figs. 1, 3 and 18.

At block 2015, after closing the transfer gate, the method may include transferring data bits between the second memory cell and the processor, or between the second memory cell and the first memory cell. In some instances, the operation (s) in block 2015 may be performed using the memory controller 140 described with reference to Figs. 1, 3, and 18.

At block 2025, after opening the transfer gate, the method may include transferring data bits between the first memory cell and the processor. In some instances, the operation (s) in block 2025 may be performed using the memory controller 140 described with reference to Figs. 1, 3, and 18.

It should be noted that the methods 1900 and 2000 illustrate possible implementations, and that the operations and steps of the methods 1900 and 2000 may be rearranged or otherwise modified to enable other implementations. In some instances, aspects of methods 1900 and 2000 may be combined.

The description in this application provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Variations may be made in the arrangement and function of the elements discussed without departing from the scope of the present disclosure. Various examples may be omitted, replaced, or added with various procedures or components, as appropriate. In addition, the features described for some examples may be combined in other examples.

In connection with the accompanying drawings, the description set forth in this application is intended to illustrate and be able to illustrate the exemplary arrangements, or not all of the examples falling within the scope of the claims. As used in this application, the terms "exemplary" and "exemplary" mean "serving as an example, instance, or illustration " rather than as being preferred or advantageous over other examples. The detailed description includes specific details for the purpose of providing an understanding of the techniques described. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type can be distinguished by reference labels by dashes and by following a second label that identifies similar components. When a first reference label is used in the specification, the description is applicable to any of the similar components having the same first reference label regardless of the second reference label.

The information and signals described in this application may be represented using any of a variety of different techniques and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may refer to voltages, currents, electromagnetic waves, magnetic fields or particles, Optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; It will be appreciated by those skilled in the art that the signal may represent a bus of signals, and that the bus in this application may have various bit widths.

As used in this application, the term "virtual ground" refers to a node of an electrical circuit that is maintained at a voltage of approximately zero volts (0 V) but is not directly connected to ground. Therefore, the voltage of the virtual ground temporarily changes and can return to about 0 V in the steady state. Virtual ground can be implemented using a variety of electronic circuit elements, such as a voltage divider composed of an operational amplifier and resistors. Other implementations are also possible.

The term "electronic communication" refers to the relationship between components that support electronic flow between components. This may include a direct connection between the components or may include intermediate components. The components in an electronic communication may not actively exchange electrons or signals (e.g., in an active circuit) or actively swap electrons or signals (e.g., in a deactivated circuit) May be configured and operable to exchange electrons or signals when activated. By way of example, two components physically connected through a switch (e.g., transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

Devices described in this application including memory device 100 may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate . The conductivity of the substrate, or the sub-regions of the substrate, can be controlled through doping using a variety of chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

The transistor discussed in this application may include a three terminal device that may represent a field effect transistor (FET) and include a source, a drain, and a gate. The terminals may be connected to other electronic devices through conductive materials, e.g., metals. The source and drain may be conductive and may include highly doped, for example, degenerated semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., many carriers are electrons), then the FET can be referred to as an n-type FET. Likewise, if the channel is p-type (i.e., majority carriers are holes), then the FET can be referred to as a p-type FET. The channel may be capped by an insulated gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage individually to an n-type FET or a p-type FET may result in the channel becoming conductive. The transistor may be "on" or " activated "when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "off" or "deactivated ".

The various illustrative blocks, components, and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described in this application, Or may be implemented or performed with transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described in this application may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored or transmitted thereon as one or more instructions or codes on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by the processor, hardware, firmware, hardwiring, or any combination thereof. Features that implement functions may also be physically located at various locations, including that portions of the functions are distributed such that they are implemented at different physical locations. Also used in the present application, including in claims, is a list of items (e.g., "at least one of" or "at least one of & Represents a comprehensive list such that, for example, the list of at least one of A, B, or C refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

Computer-readable media includes both communication media and non-transitory computer storage media, including any medium that enables the transfer of computer programs from one place to another. Non-temporary storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can be embodied in a variety of forms, including RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, Or other magnetic storage devices, or instructions or data structures that may be used to carry or store desired program code means and which may be accessed by a general purpose or special-purpose computer, or by a general purpose or special purpose processor Or any other non-transient medium.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a web site, server, or other remote source using wireless technologies such as coaxial cable, fiber optic cable, twisted pair cable, digital subscriber line (DSL), or infrared, radio, and microwave, Wireless technologies such as coaxial cable, fiber optic cable, twisted pair cable, digital subscriber line (DSL), or infrared, radio, and microwave are included in the definition of the medium. As used herein, discs and discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy discs and Blu-ray discs in which discs usually reproduce data magnetically, Discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description in the present application is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Accordingly, this disclosure is not limited to the examples and designs described in this application, and will be accorded the broadest scope consistent with the principles and novel features disclosed in this application.

Claims (25)

A method of operating a memory device,
Determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, wherein the first digit line coupled to the first memory cell is a sense amplifier, The paging buffer register being coupled to the paging buffer register; And
Operating a transfer gate based at least in part upon determining to read the second memory cell of the second memory cell array, the transfer gate having a second digit line coupled to a second digit line coupled to the second memory cell, To the paging buffer register via the first digit line. ≪ Desc / Clms Page number 22 > 3. The method of claim 1, wherein the first memory cell comprises a first ferroelectric memory cell and the second memory cell comprises a second ferroelectric memory cell. 3. The method of claim 2, wherein the first ferroelectric memory cell is configured to operate in a volatile mode and the second ferroelectric memory cell is configured to operate in a non-volatile mode. The memory cell of claim 1, wherein the first digit line is coupled to a first plurality of memory cells comprising the first memory cell and the second digit line is coupled to a second plurality of memory cells including a second memory cell. And wherein the first plurality of memory cells comprises less memory cells than the second plurality of memory cells. The method of claim 1, wherein operating the transfer gate comprises:
And closing the transfer gate when it is determined to access the second memory cell and coupling the second digit line to the paging buffer register via the first digit line. The method of claim 5,
Transferring the data bits in at least one of the second memory cell and the processor, or between the second memory cell and the first memory cell after closing the transfer gate. The method of claim 1, wherein operating the transfer gate comprises:
And opening the transfer gate when it is determined not to access the second memory cell. The method according to claim 1,
And operating the first memory cell array as an embedded cache for the second memory cell array. The method according to claim 1,
Further comprising preventing inversion of a ferroelectric film of a capacitor of the first memory cell by biasing a cell plate of the first memory cell. The method of claim 9,
Further comprising biasing each cell plate of each memory cell of the second memory cell array with a common voltage. The method of claim 9,
Further comprising independently biasing the voltage of each cell plate of each memory cell of the second memory cell array. In the apparatus,
A first memory cell array including a first digit line connected to a first plurality of memory cells;
A second memory cell array including a second digit line coupled to a second plurality of memory cells;
A paging buffer register including a first sense amplifier shared by the first memory cell array and the second memory cell array, the first digit line coupled to the first sense amplifier; And
And a first transfer gate operable to selectively couple the second digit line to the first sense amplifier via the first digit line. 13. The apparatus of claim 12, wherein the first plurality of memory cells comprises fewer memory cells than the second plurality of memory cells. 13. The memory array of claim 12, wherein the second memory cell array further comprises a third digit line connected to a third plurality of memory cells, the paging buffer register further comprising a second sense amplifier,
A third memory cell array including a fourth digit line connected to a fourth plurality of memory cells, wherein the second sense amplifier is shared by the third plurality of memory cells and the fourth plurality of memory cells, A fourth digit line coupled to the second sense amplifier, the third memory cell array; And
And a second transfer gate operable to selectively couple the third digit line to the second sense amplifier via the fourth digit line. 13. The memory cell of claim 12 wherein the first plurality of memory cells comprises a first subset of memory cells coupled to the first digit line and a second subset of memory cells coupled to the first digit line, The one digit line is coupled to the first sense amplifier between a first subset of memory cells and a second subset of memory cells. 16. The memory array of claim 15, wherein each of the plurality of access lines is coupled to a first memory cell in the first subset of memory cells and to a second memory cell in the second subset of memory cells, Wherein a first one of the plurality of memory cells is coupled to a functioning memory cell in the first subset of the memory cells and to a non-functioning memory cell in the second subset of memory cells. 13. The integrated circuit of claim 12, wherein the first sense amplifier comprises:
A first circuit operable to bias the first digit line to a first voltage before reading from the first memory cell array; And
And a second circuit operable to bias the first digit line and the second digit line to a second voltage before reading from the second memory cell array. 18. The sense amplifier of claim 17, wherein the first sense amplifier comprises:
And a third circuit operable to bias the first digit line and the second digit line in parallel to the second voltage. 13. The apparatus of claim 12, wherein the cell plate of each memory cell of the second plurality of memory cells is coupled to a common voltage rail. 13. The apparatus of claim 12, wherein the first memory cell array comprises a first plurality of ferroelectric memory cells and the second memory cell array comprises a second plurality of ferroelectric memory cells. 20. The apparatus of claim 20, wherein the first plurality of dielectric memory cells are configured to operate in a volatile mode and the second plurality of dielectric memory cells are configured to operate in a non-volatile mode. A data processing system comprising:
A processor;
Main memory; And
And a memory controller configured to transfer data between the main memory and the processor, the main memory comprising:
A first memory cell array including a first digit line connected to a first plurality of memory cells;
A second memory cell array including a second digit line coupled to a second plurality of memory cells;
A paging buffer register including a first sense amplifier shared by the first memory cell array and the second memory cell array, the first digit line coupled to the first sense amplifier; And
And a first transfer gate operable to selectively couple the second digit line to the first sense amplifier via the first digit line. 23. The system of claim 22, wherein the first memory cell array is used by the processor as a cache for the second memory cell array. 24. The memory system of claim 23, wherein the processor is further configured to: cause the memory controller to close the transfer gate and send a read command to transfer data from the second memory cell array to the first memory cell array, And to transmit data from the first memory cell array to the second memory cell array. 23. The memory system of claim 22, wherein the processor is configured to cause the memory controller to operate the transfer gate and to write a first type of data to the first memory cell array or to write a second type of data to the second memory cell array Data processing system.

Images