JPH10112191A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the high speed property of flip-flop circuits at the time of a normal operation by separating ferroelectric capacitors for retaining nonvolatility with a switching circuit. SOLUTION: A cache memory array S-MA is constituted of a word line WSO or the like, a bit line pair BLi/BLi or the like and a cache memory cell matrix arranged at intersections of word lines and bit line parts. An amplifier part SA-B detects and amplifies information of cache memory cells to output them to output lines Doi. A ferroelectric substance memory array F-MA is constituted of a work line WFO or the like, a bit line pair BLi/BLi or the like and a ferroelectric substance cell matrix arranged at intersections of word lines and bit line pairs and is arranged at a side opposite to the amplifier part SA-B with respect to the cache memory array S-MA via a switching circuit SWF. When the switching circuit SWF is turned on, the high speed property as a cache memory is not hindered by electrically separating the ferroelectric substance memory array F-MA from the cache memory array S-MA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a device for holding a state of a flip-flop circuit operating at high speed in a nonvolatile manner as a polarization direction of a ferroelectric capacitor.

[0002]

2. Description of the Related Art A method for nonvolatilely storing volatile information of a flip-flop circuit as a polarization direction of a ferroelectric capacitor is disclosed in, for example, US Pat. No. 6,390,390. 6A and 6B show a circuit configuration and an operation method, respectively. A ferroelectric capacitor is connected to a complementary storage node of the flip-flop circuit via a switch. In order to transfer the volatile information to the non-volatile information or vice versa, to convert the non-volatile information back to the volatile information, as shown in detail in FIG. 6 (b) or US Pat. , A pulse is applied to CLK2.

[0003]

However, when the above-described circuit configuration and operation method are applied to, for example, a high-speed operation flip-flop circuit known as a cache memory, there is a problem that the speed is deteriorated. This is because the area of the memory cell increases due to the added ferroelectric capacitor and field effect transistor, and as a result, a large amount of parasitic capacitance occurs in the bit line pair BL, BB, the word line WL, or the diffusion layer region of the flip-flop circuit. Is added or the wiring resistance is increased.

[0004]

In a semiconductor device according to the present invention, a plurality of flip-flop circuits (BLi / BBi, etc.) intersect a plurality of word lines (WS0, etc.) and a plurality of bit line pairs (BLi / BBi, etc.). For example, a field-effect transistor and a ferroelectric substance are provided at an intersection of a region where cache memory cells are arranged in a matrix, a plurality of word lines (such as WF0) other than the above word line, and a plurality of bit lines intersecting the word line. And a region in which a plurality of ferroelectric memory cells constituted by capacitors are arranged in a matrix. The bit line of the flip-flop circuit and the bit line of the ferroelectric memory cell are connected via a switch. The word line of the flip-flop circuit and the word line of the ferroelectric memory cell correspond one-to-one with the same address, but both are simultaneously activated by different control lines (FiS and FiF). Alternatively, either one can be selected and activated. Further, in this configuration, an amplifier (such as SAi) is connected to the bit line of the flip-flop circuit, and the amplifier detects volatile information of the flip-flop circuit and non-volatile information of the ferroelectric memory cell. (Figure 1).

Further, in the semiconductor device of the present invention, in this configuration, in the area where the flip-flop circuits are arranged in a matrix, a part of the flip-flop circuits closer to the amplifier is provided with an instruction set used for the CPU. The register is a register to which an address is directly specified, and the remaining flip-flop circuits are cache memories to which an address is indirectly specified through information of a memory management unit (MMU). The bit line connected to the cache memory cell and the bit line connected to the register cell can be electrically separated by a switch circuit (FIG. 2).

In the semiconductor device of the present invention, when transferring nonvolatile information of a ferroelectric memory cell to volatile information of a cache memory cell or a register cell, first, the potential of a common plate of a ferroelectric capacitor is changed from a ground potential to a power supply voltage. Will be migrated. Thereafter, the nonvolatile information of the ferroelectric memory cell is transferred to the volatile information of the cache memory cell or register cell selected by the word line of the same address and connected to the same amplifier. At this time, the bit line precharge potential is set to the ground potential. When the transfer is completed for all the ferroelectric memory cells, the potential of the common plate is returned to the ground potential. When the potential of the common plate changes, the word lines of the ferroelectric memory cell are all inactivated (FIGS. 3 and 4).

In the semiconductor device of the present invention, when the volatile information of the cache memory cell or the register cell is saved as the nonvolatile information of the ferroelectric memory cell, the common plate is kept at the ground potential. The volatile information of the cache memory cell or the register cell is transferred to the nonvolatile information of the ferroelectric memory cell selected by the word line of the same address and connected to the same amplifier. In the save operation, after the volatile information of the cache memory cell or the register cell is latched on the bit line by the amplifier as the ground potential or the power supply potential, the word line of the ferroelectric memory cell storing the information is activated. (FIGS. 3 and 5).

[0008]

FIG. 1 shows a configuration of a flip-flop circuit (for example, a cache memory) of a high-speed operation capable of holding volatile information in a nonvolatile manner according to an embodiment of the present invention. This circuit includes a word line WS0 and a bit line pair BL, for example.
A cache memory array S-MA in which a plurality of cache memory cells are arranged in a matrix at the intersection of i / BBi
And a word line such as WF0 and a bit line pair such as BL
A ferroelectric memory array F-MA in which a plurality of ferroelectric memory cells are arranged in a matrix at the intersection of i / BBi.

The bit line pair, for example, BLi / BBi,
By the switch circuit SW, the cache memory array area and the ferroelectric memory array area can be electrically separated from each other, and the amplifier SAi for detecting and amplifying information of the cache memory cell and the ferroelectric memory cell can be provided. Connected. SAi is provided closer to the cache memory array than the ferroelectric memory array, and has an output line Doi.

A word line of a flip-flop circuit such as WS0 and a word line of a ferroelectric memory cell such as WF
0 indicates one-to-one correspondence with the same address, but both can be simultaneously activated by another control line (FiS and FiF), or one of them can be selected and activated. Can also. That is, the gate GT for activating the word line is supplied from the X decoder X-DEC to the X driver X.
-A signal that has passed DRV and a control line FiF or FiS are input signals.

According to this embodiment, the saving of volatile information of a cache memory cell as nonvolatile information to a ferroelectric memory cell and the recall of the volatile information in the opposite manner are performed through the same bit line and amplifier. It can be realized at high speed with a small area circuit configuration. During normal operation, the switch circuit SWF
Is turned off, the cache memory array becomes exactly the same as the conventional array, so that the addition of non-volatility does not impair the high-speed performance.

Further, since the storage addresses of the volatile information and the nonvolatile information correspond one-to-one, the control is simple.
Further, the ferroelectric memory portion is formed by a process specialized for high integration (for example, a self-alignment process using polycrystalline silicon wiring), and the cache memory portion is formed by a process specialized for high speed (for example, a low resistance wiring process). Therefore, a high-performance nonvolatile cache memory which is easy to manufacture and has high performance can be obtained. If the ferroelectric memory section is formed by a process similar to that of a dynamic random access memory (DRAM), the cell size can be reduced to nearly one-tenth of a cache memory cell.

FIG. 2 is an embodiment of the present invention showing a configuration in which a cache memory and a register file formed on a chip in a CPU are made non-volatile. Compared with the memory array configuration of FIG. 1, a switch circuit SWS for electrically separating register files RF and bit lines of RF between amplifier section SA-B and cache memory array S-MA is different from that of S-MA. Is provided. RF circuit configuration is S
Same as -MA, except that the address of the cache memory is transferred from the CPU to the memory management unit MMU,
Further, while the address of the register is specified via the cache tag C-TAG, the address of the register is directly specified by the data of the instruction set of the CPU. Normally, the SWS and the SWF are in the OFF state, and when the cache memory is selected, the SWS is in the ON state. When saving as nonvolatile information and recalling the volatile information in reverse, the SWS is switched off.
F is also turned on. According to the embodiment of the present invention, the same effect as that of FIG. 1 can be obtained.

FIG. 3 is an embodiment of the present invention showing a more specific configuration of the memory array of FIG. A ferroelectric memory cell such as MF (00) is composed of two ferroelectric capacitors and two field effect transistors. The plate VPL of the ferroelectric capacitor is common in the ferroelectric memory array. A precharge circuit PF0 for precharging a bit line to a ground potential is used when detecting information of a ferroelectric memory cell. PF0 is the precharge signal line PCS when the recall signal bar is at the low level.
When the recall signal bar is at a high level, it is inactive.

The ferroelectric memory section is separated from the cache memory section when the signal line SHR is at a high level. A cache memory cell, for example, MS (00) is formed of a flip-flop circuit. A precharge circuit PS0 for precharging a bit line to a power supply potential is used when detecting information of a cache memory cell. PS0 is the precharge signal line PC when the recall signal bar is at a high level.
Controlled by S, when the recall signal bar is at a low level, it becomes inactive. YSB is a Y selection line for connecting the cache memory section to an amplifier, for example, SA0.

FIGS. 4 and 5 show operation waveforms for recalling (recalling) volatile information and saving (saving) volatile information in the circuit configuration shown in FIG. 3, respectively.

FIG. 4 is an embodiment of the present invention showing a recall operation waveform. When the standby state is released for the system including FIG. 1 or FIG. 2, the suspension of the supply of the power supply voltage in the standby state is released. That is, the internal power supply voltage of the system is reset to Vcc. VPL also becomes Vcc. At this time, Wi must be at the low level and the word line must be inactive. Amplifier signal line SAP,
SAN is set to Vcc and 0, respectively, to keep the amplifier inactive. The recall signal bar is at a low level indicating that the mode is the recall mode. During the recall operation, the bit line is precharged to 0 V, and SHR, YS
B is at a low level, and all the bit line connection switches are on. FiF is held at a high level and X-
The word line of the ferroelectric memory section is immediately activated by a signal from the DRV. After the standby state is released, the recall / store counter is counted up from 0000 to 0001 after a certain delay such that the internal power supply voltage is stabilized. Note that the counter need not always be 4 bits.

By counting up, the recall of the information selected by W0 from non-volatile to volatile starts. First,
PCS becomes high level, and the bit line becomes a floating state of 0V. Next, WF0 is activated by W0, and MF (00) is applied to a bit line pair, for example, BL0 / BB0.
Is generated as a potential difference. Next, SAP, S
When AN is set to a low level and a high level, respectively, BL0
/ BB0 information is amplified. Next, FiS is set to the high level to activate WS0, and information is written to the cache memory cell MS (00) corresponding to MF (00). This completes the recall of the information selected in W0, and WF0,
Return WS0 to the inactive state.

Finally, the amplifier is inactivated and the bit line is recharged to 0V. When the recall signal bar is at the low level during the re-precharge, the recall / store counter is counted up. As a result, recall of the information selected in W1 is started.

As described above, all the ferroelectric memory cells are recalled, and when the information selected by the last Wn is completed, the recall / store counter becomes 000.
It is reset to 0 to generate the most significant carry signal.
If the recall signal bar is at the low level when the carry signal is generated, the recall signal bar changes to the high level. This means transition to normal operation, VPL changes to the ground potential, and the SHR signal disconnects the ferroelectric memory from the cache memory. Also, FiF changes to low level and FIS changes to high level, and when Wi is selected, the cache memory is immediately selected.

FIG. 5 shows a store operation waveform according to an embodiment of the present invention. When the system enters a standby state, first, SHR goes low, and the ferroelectric memory unit is connected to the cache memory unit. Then, the recall / store counter is counted up from 0000 to 0001. When the recall signal bar is at the high level and the standby signal is at the high level, the counting operation starts the storing operation of the signal selected by W0. The bit line enters a floating state due to a change in PCS. At this time, since the recall signal bar is at a high level, the bit line is precharged to Vcc. Note that the bit line precharge potential during the store operation does not necessarily need to be Vcc.

Next, W0 corresponding to the counter 0001 is selected. Since FiS is at the high level and FiF is at the low level, WS0 is activated to select a cache memory cell. As a result, information of the cache memory cell MS (00) is generated as a potential difference on the bit line pair, for example, BL0 / BB0. Next, the amplifier is activated by SAP and SAN.
Then, the potential of the bit line pair is latched to 0 and Vcc according to the information of MS (00). At this point, FiF goes high and WF0 is activated.

Here, WF0 must not be activated before the bit line potential is amplified to 0 and Vcc. this is,
At the time of the recall, the polarization of the ferroelectric capacitor has been reset in one direction (the direction in which the plate side is at a high level), and only a part of the polarization is inverted at the time of storage in accordance with the information in the cache memory. That is,
When the bit line potential at the time of store is 0, the polarization to be written is the direction in which the plate side is at a high level, and is the polarization direction already set at the time of recall. If WF0 is activated when the bit line potential is amplified to 0 and Vcc, the voltage applied to the ferroelectric capacitor is almost 0, and the polarization direction set at the time of recall is not destroyed. On the other hand, when the bit line potential at the time of store is Vcc, a voltage at which the plate side becomes low level is applied to the ferroelectric capacitor by activating WF0, and the polarization direction is reversed in accordance with the information in the cache memory.

As described above, the saving of the information selected by W0 as the non-volatile information is completed, and the word line is deactivated. Finally, the amplifier is deactivated to recharge the bit line to Vcc. When the standby signal is at the high level at the time of re-precharge, the recall 1 / store counter is counted up.
As a result, the storage of the information selected by W1 is started. As described above, the storage as the nonvolatile information is performed for all the cache memory cells. When the information selected by the last Wn is completed, the recall / store counter is reset to 0000, and the most significant carry signal is generated. If the standby signal is at the high level when the carry signal is generated, the internal power supply is stepped down to the ground potential.

According to the embodiment of the present invention described with reference to FIGS. 3 to 5, (1) Since the plate of the ferroelectric capacitor can be shared in the memory array, the area of the ferroelectric memory array can be reduced. . (2) Among binary polarization directions,
According to this operation method, which is reset in one direction at the time of recall and writes only in the other direction at the time of storage, the potential of the common plate only needs to be changed once at the start and end of the recall, so that high speed and low noise generation Recall and store operations are possible. (3) The common plate potential is Vcc and the bit line precharge potential is 0 V during recall
When storing, the common plate potential is 0 V, and the bit line potential after detecting the cache memory cell information is 0 V or Vcc.
According to the present operation method, nonvolatile information can be written by applying a voltage of approximately Vcc to the ferroelectric capacitor, so that a system suitable for low-voltage operation fully utilizing the given voltage amplitude Vcc is provided. can get. (4) Since the common plate is already set to the ground voltage during normal operation, and it is not necessary to change the potential of the common plate after a store command is issued, the store operation can be performed immediately.

[0026]

According to the semiconductor device of the present invention, a flip-flop circuit which can operate at high speed and can maintain a nonvolatile state, particularly a cache memory or a register file, can be realized by an easy manufacturing process.

Further, according to the method for recalling (recalling) volatile information and saving (storing) volatile information according to the present invention, an increase in chip area due to the non-volatization of the flip-flop circuit can be suppressed, and high-speed operation can be achieved. , A highly reliable system can be obtained. Further, a system suitable for low-voltage operation is obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a cache memory according to the present invention.

FIG. 2 is an explanatory diagram of a data processing device according to the present invention.

FIG. 3 is a circuit diagram of a memory array according to the present invention.

FIG. 4 is a recall operation waveform diagram in the configuration of FIG. 3;

FIG. 5 is a store operation waveform diagram in the configuration of FIG. 3;

FIG. 6 is an explanatory diagram of an SRAM including a conventional ferroelectric capacitor.

[Explanation of symbols]

F-MA: ferroelectric memory array, S-MA: cache memory array, SA-B: amplifier section, SAi: amplifier, SWF: switch circuit, BLi / BBi: bit line pair, WF0, WS0: word line, GT ... Gate, X-DE
C: X decoder, X-DRV: X driver, FiF, Fi
S: control line.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Koji Yamada 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. Gochome No. 20, No. 1 Semiconductor Division, Hitachi, Ltd.

Claims (7)

[Claims] 1. A region in which a plurality of flip-flop circuits are arranged in a matrix at an intersection of a plurality of first word lines and a plurality of bit lines crossing the first word line, a plurality of second word lines and a plurality of crossing lines A plurality of ferroelectric memory cells each composed of a field effect transistor and a ferroelectric capacitor arranged in a matrix at an intersection with a bit line connected to the flip-flop circuit. And a bit line to which the ferroelectric memory cell is connected. The semiconductor device further comprises means for electrically connecting the bit line to the ferroelectric memory cell via a switch. A first operation mode for transferring non-volatile information as the state of the flip-flop circuit, and the switch in a non-connected state,
A second operation mode in which the state of the flip-flop circuit is detected or rewritten, and a third state in which the switch is connected and the state of the flip-flop circuit is transferred to nonvolatile information as a polarization direction of the ferroelectric capacitor. A semiconductor device having an operation mode, wherein the ferroelectric capacitor and the flip-flop circuit to which information is transferred in the first and third operation modes are determined one-to-one. . 2. An amplifier according to claim 1, wherein a bit line connected to said flip-flop circuit is used for detecting a state of said flip-flop circuit and nonvolatile information held in said ferroelectric capacitor. Semiconductor device to which is connected. 3. The semiconductor device according to claim 1, wherein said flip-flop circuit is used as a cache memory. 4. The CPU according to claim 1, wherein the CPU is mounted on the same chip.
Wherein at least a part of the plurality of flip-flop circuits is a register file directly addressed by data of an instruction set for controlling the CPU. 5. The ferroelectric capacitor according to claim 1, wherein a plate of the ferroelectric capacitor is used in common for memory cells connected to different ones of the first word lines, and in the first operation mode, the common plate is used. The plate is set to a first potential, the precharge potential of the bit line electrically connected by the switch is set to a second potential different from the first potential, and in the third operation mode, The common plate is set to a third potential, and the state of the flip-flop circuit is amplified to the bit line as a fourth potential different from the third potential or a fifth potential different from the fourth potential. After that, the ferroelectric memory cell is connected to the bit line, and the relationship between the second potential and the first potential is opposite to the relationship between the fourth potential and the third potential. Ah Semiconductor device. 6. The semiconductor device according to claim 5, wherein said fifth potential is substantially equal to said third potential. 7. The semiconductor device according to claim 6, wherein said second potential and said third potential are substantially equal to a power supply voltage, and said first potential and said fourth potential are substantially equal to a ground voltage.