CN115188403A

CN115188403A - Memory chip and control method of memory chip

Info

Publication number: CN115188403A
Application number: CN202210838725.2A
Authority: CN
Inventors: 拜福君; 段会福; 肖文武
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2022-07-15
Filing date: 2022-07-15
Publication date: 2022-10-14

Abstract

The application provides a memory chip and a control method of the memory chip, the memory chip comprises a plurality of memory modules, each memory module comprises a plurality of memory arrays, and each memory array comprises: the first storage array works in a first storage mode; the second storage array works in a second storage mode; the control circuit is connected with the first storage array and the second storage array and used for writing at least part of data in the second storage array into the first storage array so as to enable the external equipment to read and write data in the first storage array; and writing at least part of data in the first storage array into the second storage array for data backup. Specifically, the external device only reads and writes the first storage array, so that the storage chip of the application has the characteristics of high reading and writing speed and long service life, and the data in the first storage array can be backed up in the second storage array, so that the storage chip has the characteristic that the data cannot be lost after power failure.

Description

Memory chip and control method of memory chip

Technical Field

The present application relates to the field of chip technologies, and in particular, to a memory chip and a control method of the memory chip.

Background

Dynamic Random Access Memory (DRAM) stores information by how much charge is on a capacitor in a memory cell, and belongs to a volatile memory.

Disclosure of Invention

The invention provides a memory chip and a control method of the memory chip, wherein the memory chip has the characteristics of high read-write speed, long service life and no data loss after power failure.

In a first aspect, the present application provides a memory chip, comprising: a plurality of memory modules, each memory module comprising a plurality of memory arrays, each memory array comprising: the first storage array works in a first storage mode; the second storage array works in a second storage mode; the control circuit is connected with the first storage array and the second storage array and used for writing at least part of data in the second storage array into the first storage array so as to enable the external equipment to read and write data in the first storage array; and writing at least part of data in the first storage array into the second storage array for data backup.

Wherein the memory array comprises: the first sense amplifier is connected with the first storage array and used for reading and writing data of the first storage array; and the second sense amplifier is connected with the second storage array and used for reading and writing data of the second storage array.

Wherein the first storage array comprises: a plurality of first memory cells, each first memory cell comprising: the control end of the first transistor is connected with the first word line, and the first end of the first transistor is connected with the first bit line; a first end of the first capacitor is connected with a second end of the first transistor, and a second end of the first capacitor is connected with a first control line; the second storage array includes: a plurality of second memory cells, each second memory cell comprising: a control end of the second transistor is connected with a second word line, and a second end of the second transistor is connected with a second bit line; and the first end of the second capacitor is connected with the first end of the second transistor, and the second end of the second capacitor is connected with the second control line.

Wherein the memory array further comprises: the first switch circuit is connected with the first sense amplifier and the first storage array; the second switch circuit is connected with the second sense amplifier and the second storage array; the first switch circuit is conducted, and data are read from the first storage array; the second switch circuit is turned on, and at least a part of the data in the first memory array is written into the second memory array.

Wherein, the first switch circuit includes: the control end of the first switch is connected with the first driving wire, and the first end of the first switch and the second end of the first switch are connected with the first bit line; a control end of the second switch is connected with the first driving line, and a first end of the second switch and a second end of the second switch are connected with a second bit line; the second switching circuit includes: a control end of the third switch is connected with the second driving line, and a first end of the third switch and a second end of the third switch are connected with the first bit line; and a control end of the fourth switch is connected with the second driving line, and a first end of the fourth switch and a second end of the fourth switch are connected with the second bit line.

Wherein the first sense amplifier includes: the first amplifier is connected with the first bit line, the second bit line and the first enable line; a third switch circuit connected to the first bit line, the second bit line, the column selection line, the first data line, and the second data line; and the fourth switch circuit is connected with the first bit line, the second bit line and the first pre-charging line.

Wherein the second sense amplifier includes: the second amplifier is connected with the first bit line, the second bit line and the second enable line; the fifth switch circuit is connected with the first bit line, the second bit line, the column selection line, the third data line and the fourth data line; the sixth switching circuit is connected with the first bit line, the second bit line and the second pre-charging line; the first data line, the second data line, the third data line and the fourth data line are connected with the common data line.

Wherein, the storage module still includes: a column circuit connecting the column selection line and the common data line; and the row circuit is connected with the first word line and the second word line.

The row circuit further comprises a word line driving circuit, and the word line driving circuit is connected with the first word line and the second word line.

In a second aspect, the present application provides a method for controlling a memory chip, including: writing at least part of data in the second storage array into the first storage array so that the external equipment can read and write data in the first storage array; writing at least part of data in the first storage array into a second storage array to perform data backup; the first storage array works in a first storage mode, and the second storage array works in a second storage mode.

The beneficial effect of this application is different from prior art's condition, and every storage array includes in the memory chip of this application: the first storage array works in a first storage mode; the second storage array works in a second storage mode; the control circuit is connected with the first storage array and the second storage array and used for writing at least part of data in the second storage array into the first storage array so as to enable the external equipment to read and write data in the first storage array; and writing at least part of the data in the first storage array into the second storage array to perform data backup. Specifically, the external device only reads and writes the first storage array, so that the storage chip of the application has the characteristics of high reading and writing speed and long service life, and the data in the first storage array can be backed up in the second storage array, so that the external device has the characteristic that the data cannot be lost after power failure.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic structural diagram of a first embodiment of a memory chip of the present application;

fig. 2 is a schematic structural diagram of the memory block BANK in fig. 2;

FIG. 3 is a schematic diagram of a first embodiment of the memory array of FIG. 2;

FIG. 4 is a schematic diagram of a second embodiment of the memory array of FIG. 2;

FIG. 5 is a schematic diagram of the connection of first, second, third and fourth data lines with a common data line;

FIG. 6 is a schematic diagram of an embodiment of a wordline driver circuit;

FIG. 7 is a flowchart illustrating a first embodiment of a control method of a memory chip;

FIG. 8 is a timing diagram of signals for reading from and writing to a first memory array;

FIG. 9 is a timing diagram of step S71 in FIG. 7;

fig. 10 is a schematic diagram of timing signals of step S72 in fig. 7.

Detailed Description

In order to make the technical problems, the adopted technical solutions, and the achieved technical effects of the present application clearer, the technical solutions of the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory chip 1 according to a first embodiment of the present invention, specifically, the memory chip 1 includes a plurality of memory blocks BANK, and each of the memory blocks BANK is independent of each other. Referring to fig. 2, fig. 2 is a schematic structural diagram of memory blocks BANK, each of which includes a plurality of memory arrays 10. Referring to fig. 3, fig. 3 is a schematic structural diagram of memory arrays, each memory array 10 includes: a first memory array 11, a second memory array 12 and a control circuit 13. Wherein, the first storage array 11 works in a first storage mode; the second storage array 12 operates in a second storage mode. It will be appreciated that the first and second storage modes are different. The control circuit 13 is connected with the first storage array 11 and the second storage array 12, and the control circuit 13 is used for writing at least part of data in the second storage array 12 into the first storage array 11 so as to enable an external device to read and write data from and into the first storage array 11; and writing at least part of the data in the first storage array 11 into the second storage array 12 for data backup.

Specifically, referring to fig. 2, the control circuit is further connected to the column circuits COL and XDEC circuit, which control the word lines, the sense amplifiers and the data line switches through the XDEC circuit according to the row address, and control the transmission of signals and data of the column selection line CSL on the common data line MDQ through COL according to the column address. The XDEC circuit is a row decoder circuit.

The first memory array 11 is a DRAM memory array, and the second memory array 12 is a nonvolatile memory array. The DRAM stores information according to the amount of charges on the capacitor in the storage unit, belongs to a volatile memory, and has the advantages of high reading speed and almost infinite service life of the storage unit, but has the disadvantages that the storage unit needs to be refreshed continuously, and data can be lost after power failure. The DRAM storage array and the nonvolatile storage array are arranged on the storage chip at the same time, when external equipment reads and writes data, the DRAM storage array can be directly read and written so as to inherit the characteristic of high reading and writing speed of the DRAM, when power is off, at least part of data stored in the DRAM storage array is written into the nonvolatile storage array so as to backup the data, data loss is avoided, and after power is on, at least part of data backed up in the nonvolatile storage array is written into the DRAM storage array so as to inherit the characteristic that the data cannot be lost after the power is off of the nonvolatile storage array. Therefore, the memory chip has the advantages of being high in reading and writing speed, long in service life and free of data loss after power failure.

In the embodiment of the present application, the first memory array 11 and the second memory array 12 are provided in the same memory chip. Specifically, a plurality of memory chips are fabricated on the same wafer, each memory chip is divided into two parts, wherein part 1 is fabricated with the first memory array 11, and the other part is fabricated with the second memory array 12, that is, the first memory array 11 and the second memory array 12 are disposed on the same plane.

In an embodiment, the second memory array 12 may be a Ferroelectric random access memory (FeRAM), which stores information according to different polarization states of Ferroelectric capacitors in memory cells, and is a non-volatile memory that does not lose content when power is off, and has the advantages of high speed, high density, low power consumption, radiation resistance, and the like. The disadvantages are high read and write voltage, much slower read and write speed than DRAM, and limited memory cell life.

In the embodiment of the application, the DRAM and the FeRAM are integrated in the same chip, when external equipment reads and writes data, the data are directly read and written from the DRAM, the reading speed is high, when the power is off, the data in the DRAM are written into the FeRAM, the data cannot be lost, and after the power is on or when a user instruction is received, the data in the FeRAM are written into the DRAM so as to be convenient for reading and writing the data from the DRAM. It should be noted that, since the read/write speed of the FeRAM is much slower than that of the DRAM, in a preferred embodiment, the user may issue an instruction in advance to write the data of the FeRAM into the DRAM. Specifically, the command may be issued to write the data of the FeRAM into the DRAM during an idle time (the idle time refers to a time when the DRAM is not read or written). Compared with the method that the data of the FeRAM is written into the DRAM when the DRAM is read and written, the read-write time is greatly reduced, and the read-write speed is improved.

In another embodiment of the present application, the second memory array 12 may also be other capacitive nonvolatile memories, which is not limited herein.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a memory array of a second embodiment of the present application, and based on the first embodiment shown in fig. 3, the memory array 10 further includes a first sense amplifier 14 and a second sense amplifier 15. The first sense amplifier 14 is connected to the first memory array 11 and is used for reading and writing data of the first memory array 11; the second sense amplifier 15 is connected to the second memory array 12 for reading and writing data from and into the second memory array 12.

It should be noted that the memory array 10 includes a plurality of first memory arrays 11 and a plurality of second memory arrays 12, each first memory array 11 includes a plurality of first memory cells 111, and each second memory array 12 includes a plurality of second memory cells 121.

As shown in fig. 4, each of the first memory cells 111 includes: a first transistor Q1 and a first capacitor C1. The control end of the first transistor Q1 is connected to a first word line WLA, and the first end of the first transistor Q1 is connected to a first bit line BL. A first terminal of the first capacitor C1 is connected to the second terminal of the first transistor Q1, and a second terminal of the first capacitor C1 is connected to a first control line PLA. Each of the second memory cells 121 includes: and a second transistor Q2 and a second capacitor C2, wherein a control terminal of the second transistor Q2 is connected to the second word line WLB, and a second terminal of the second transistor Q2 is connected to the second bit line BLN. A first end of the second capacitor C2 is connected to the first end of the second transistor Q2, and a second end of the second capacitor C2 is connected to the second control line PLB.

With continued reference to FIG. 4, the first sense amplifier 14 includes: a first amplifier 141, a third switching circuit 142, and a fourth switching circuit 143. The first amplifier 141 is connected to the first bit line BL, the second bit line BLN, and the first enable line SEA. The third switch circuit 142 connects the first bit line BL, the second bit line BLN, the column selection line CSL, the first data line LA, and the second data line LAN.

The fourth switch circuit 143 is connected to the first bit line BL, the second bit line BLN, and the first precharge line EQL. Specifically, the third switch circuit 142 includes: the switch T1 and the switch T2, wherein a first end of the switch T1 is connected to the first bit line BL, a second end of the switch T1 is connected to the first data line LA, and a control end of the switch T1 is connected to the column selection line CSL. The fourth switching circuit 143 includes: the switch T3 and the switch T4, a first end of the switch T3 is connected to the first bit line BL, and a control end of the switch T3 is connected to the first pre-charge line EQL. The first end of the switch T4 is connected to the second end of the switch T3, the second end of the switch T4 is connected to the second bit line BLN, and the control end of the switch T4 is connected to the first precharge line EQL.

The second sense amplifier 15 includes: a second amplifier 151, a fifth switching circuit 152, and a sixth switching circuit 153. The second amplifier 151 is connected to the first bit line BL, the second bit line BLN, and the second enable line SEB. The fifth switch circuit 152 connects the first bit line BL, the second bit line BLN, the column selection line CSL, the third data line LB, and the fourth data line LBN. The sixth switching circuit 153 connects the first bit line BL, the second bit line BLN, and the second precharge line RST. Specifically, the fifth switch circuit 152 includes a switch T5 and a switch T6, a first terminal of the switch T5 is connected to the first bit line BN, a second terminal of the switch T5 is connected to the third data line LB, and a control terminal of the switch T5 is connected to the column selection line CSL. A first terminal of the switch T6 is connected to the fourth data line LBN, a second terminal of the switch T6 is connected to the second bit line BLN, and a control terminal of the switch T6 is connected to the column selection line CLS. The sixth switching circuit 153 includes: the first end of the switch T7 is connected with the first bit line BL, and the control end of the switch T7 is connected with the second pre-charge line RST. The first end of the switch T8 is connected to the second end of the switch T7, the second end of the switch T8 is connected to the second bit line BLN, and the control end of the switch T8 is connected to the second pre-charge line RST.

In an embodiment of the present application, the first data line LA, the second data line LAN, the third data line LB, and the fourth data line LBN connect the common data lines MDQ/MDQN. Referring specifically to fig. 5, fig. 5 shows a portion of the first sense amplifier 14 and the second sense amplifier 15. Specifically, the first data line LA is connected to the common data line MDQ through the switch N1, and the second data line LAN is connected to the common data line MDQN through the switch N2. The first end of the switch N1 is connected to the first data line LA, the second end of the switch N1 is connected to the common data line MDQN, and the control end of the switch N1 receives a signal MAS which is used for controlling the on/off of the switch N1. The first terminal of the switch N2 is connected to the second data line LAN, the second terminal of the switch N2 is connected to the common data line MDQN, and the control terminal of the switch N2 receives a signal MAS for controlling the on/off of the switch N2. That is, the switch N1 and the switch N2 are turned on and off at the same time. The third data line LB is connected to the common data line MDQ through a switch N3, and the fourth data line LBN is connected to the common data line MDQN through a switch N4. The first end of the switch N3 is connected to the third data line LB, the second end of the switch N3 is connected to the common data line MDQN, the control end of the switch N3 receives a signal MBS, and the signal MBS is used to control the switch N3 to be turned on and off. A first end of the switch N4 is connected to the fourth data line LBN, a second end of the switch N4 is connected to the common data line MDQN, a control end of the switch N4 receives the signal MBS, and the signal MBS is used to control the switch N4 to be turned on and off. I.e. switch N3 and switch N4 are turned on and off simultaneously.

With continued reference to fig. 4, the memory array 10 further includes a first switch circuit 16 and a second switch circuit 17. Wherein, the first switch circuit 16 is connected between the first sense amplifier 14 and the first memory array 11; second switch circuit 17 is connected between second sense amplifier 15 and second memory array 12. The first switch circuit 16 is turned on to read data from the first memory array 11; the second switch circuit 17 is turned on, and at least a part of the data in the first memory array 11 is written in the second memory array 12. Specifically, the first switch circuit 16 includes: a first switch M1 and a second switch M2, a control terminal of the first switch M1 is connected to the first driving line SAT, and a first terminal of the first switch M2 and a second terminal of the first switch M2 are connected to the first bit line BL. A control terminal of the second switch M2 is connected to the first driving line SAT, and a first terminal of the second switch M2 and a second terminal of the second switch M2 are connected to the second bit line BLN. The second switch circuit 17 includes: a third switch M3 and a fourth switch M4, a control end of the third switch M3 is connected to the second driving line SBC, and a first end of the third switch M3 and a second end of the third switch M3 are connected to the first bit line BL; a control terminal of the fourth switch M4 is connected to the second driving line SBC, and a first terminal of the fourth switch M4 and a second terminal of the fourth switch M4 are connected to the second bit line BLN.

In one embodiment, as shown in fig. 2, the memory array 10 further includes row circuitry and column circuitry 19, wherein the row circuitry connects the first word line WLA and the second word line WLB. The row circuit includes a wordline driver circuit 18 and an XDEC, and referring to fig. 6 in particular, fig. 6 is a schematic structural diagram of an embodiment of the wordline driver circuit, where the wordline driver circuit includes a switch A1, a switch A2, and a switch A3, a first end of the switch A1 receives a signal WLDV, a second end of the switch A1 is connected to a wordline WL, a first end of the switch A2 is connected to the wordline WL, a control end of the switch A2 and a control end of the switch A1 receive a global wordline signal MWLN, and a second end of the switch A2 is connected to a wordline low level. The first terminal of the switch A3 is connected to the word line WL, and the second terminal of the switch A3 is connected to the word line low level. The control terminal of switch A3 receives signal WLRST. When signal MWLN is active, WLDV is active and WLRST is inactive, wordline WL is active, otherwise WL is inactive and is low. It should be noted that the word line WL connects the first word line WLA and the second word line WLB. The word lines of the memory array 10, the first enable line of the first amplifier, and the second enable line of the second amplifier are connected to an XDEC circuit, which generates an enable signal, and transmits the enable signal to the first amplifier and the second amplifier using the first enable line and the second enable line. The XDEC circuit is connected to and controlled by the control circuit 13, and is a row decoder circuit. The column circuit 19 connects the column selection line CSL and the common data lines MDQ/MDQN.

The memory chip of the present application has two operation modes, i.e., a first memory array 11 and a second memory array 12. When the memory device operates in the first memory array 11, the signal output by the first driving line SAT is valid, the switch M1 and the switch M2 are turned on, the signal output by the second driving line SBC is invalid, and the switch M3 and the switch M4 are turned off. By connecting the first memory array 11 to the first bit line BL and the second bit line BLN at this time, the first memory cell 111 controlled by the first word line WLA can be read and written. Assuming that the first memory array 11 is a DRAM, in the active operation, the signal output by the first precharge line EQL is inactive, the first word line WLA is turned on, the potential of the first bit line BL varies according to the amount of charge stored in the first memory cell 111, and the second bit line BLN is kept constant as the reference potential. With the voltage difference between the first bit line BL and the second bit line BLN established and the output signal of the first enable line SEA asserted, the first amplifier 141 starts to work, amplify the voltage difference between the first bit line BL and the second bit line BLN and complete the write-back of the capacitor of the first memory cell 111.

When the memory cell operates in the second memory array 12, the signal output from the first driving line SAT is invalid, the switches M1 and M2 are turned off, the signal output from the second driving line SBC is valid, and the switches M3 and M4 are turned on. By connecting the second memory array 12 to the first bit line BL and the second bit line BLN at this time, a read/write operation can be performed on the second memory cell 121 controlled by the second word line WLB. Assuming that the second memory array 12 is an FeRAM, during a read operation, the signal output by the second precharge line RST is wireless, the second word line WLB is turned on, the signal output by the second control line PLB rises, the second memory cell 121 generates different amounts of polarization charges onto the second bit line BLN according to the polarization state of the ferroelectric capacitor, causing a change in its own potential, and the first bit line BL is a reference potential. As the voltage difference between the first bit line BL and the second bit line BLN is established and the signal output from the second enable line SEB is asserted, the second amplifier 151 starts to operate to amplify the voltage difference between the first bit line BL and the second bit line BLN.

Fig. 7 is a schematic flow chart of a control method of a memory chip according to a first embodiment of the present invention, which specifically includes:

step S71: and writing at least part of data in the second storage array into the first storage array so that the external equipment can read and write data from and into the first storage array.

Specifically, the first memory array operates in a first memory mode, and the second memory array operates in a second memory mode.

The control method further comprises reading and writing data to the first storage array. The first memory array may be a DRAM. Namely, the data reading and writing of the first storage array are the data reading and writing of the DRAM, and the method has the advantages of high reading and writing speed and long service life of the capacitor.

At this time, please refer to fig. 8, wherein fig. 8 is a timing diagram of the signals for reading and writing to the first memory array. The signal output by the first driving line SAT is effective, the switch M1 and the switch M2 are conducted, and the first storage array and the first sensitive amplifier are conducted; the signal output by the second driving line SBC is inactive, and the switch M3 and the switch M4 are turned off, disconnecting the second memory array from the second sense amplifier. Receiving a read-write instruction, and activating a selected page according to a row address in the read-write instruction, wherein the method specifically comprises the following steps:

in the T1 stage, the signal output by the first pre-charge line EQL is asserted, the switches T3 and T4 are turned on, and the first bit line BL and the second bit line BLN are connected to the reference potential.

In the stage t2, the signal output by the first precharge line EQL is inactive, the first word line WLA is turned on, the potential of the first bit line BL changes according to the amount of charges stored in the first memory cell, and the second bit line BLN remains unchanged as the reference potential.

During the period t3, as the voltage difference between the first bit line BL and the second bit line BLN is established, the signal output from the first enable line SEA is valid. The first amplifier starts to work, amplifies the voltage difference between the first bit line BL and the second bit line BLN, and completes the write back of the capacitor in the first memory cell, and at this time, the first amplifier is used as the data buffer of the selected page. Selecting a specific first amplifier according to a column address in a read-write command to read and write data, specifically comprising: the signal MSA is effective, the switch N1 and the switch N2 are conducted, the first data line LA and the second data line LAN of the first amplifier are connected to the common data line MDQ/MDQN through the switch N1 and the switch N2, the signal output by the column selection CSL is effective, the switch T1 and the switch T2 are conducted, the selected first amplifier is connected with the first data line LA and the second data line LAN through the switch T1 and the switch T2, and the row circuit accesses data in the first amplifier through the common data line MDQ/MDQN, the first data line LA and the second data line LAN.

In the stage t4, after the first amplifier completes the data transmission and write-back, the signal output by the first enable line SEA is disabled, the signal output by the first pre-charge line EQL is enabled, and the first amplifier, the first bit line BL, and the second bit line BLN are reset to the initial state.

When the power is on, or a user controls to write at least part of data in the second storage array into the first storage array, so that the external equipment can read and write the first storage array. Specifically, this step is performed by a read operation of the second memory array and a write operation of the first memory array. Referring to fig. 9, fig. 9 is a signal timing diagram of step S71. Firstly, reading the second storage array, wherein during the reading operation of the second storage array, a signal output by the first driving line SAT is invalid, the switch M1 and the switch M2 are cut off, and the first sense amplifier is disconnected with the first storage array end; the signal output by the second driving line SBC is invalid, and the switch M3 and the switch M4 are turned on, so as to connect the second sense amplifier to the second memory array. The method specifically comprises the following steps:

in the t1 phase, the signal output by the second pre-charge line RST is active, the first bit line BL and the second bit line BLN are reset to a low level, and then RST is inactive.

In the period t2, the second word line WLB is turned on, the signal output by the second control line PLB rises, the second memory cell generates different amounts of polarization charges to the second bit line BLN according to the polarization state of the ferroelectric capacitor, causing the change of its own potential, the first bit line BL is a reference potential, and the voltage difference between the first bit line BL and the second bit line BLN is established.

In a period t3, a signal output by the second enable line SEB is valid, and the second amplifier starts to operate to amplify a voltage difference between the first bit line BL and the second bit line BLN.

In the period t4, the signal output by the second control line PLB falls, and if the signal output by the first bit line BL is at a high level, the polarization direction of the ferroelectric capacitor in the second memory cell is rewritten and is marked as data "1"; if the signal output from the first bit line BL is low, the polarization direction of the ferroelectric capacitor in the second memory cell remains unchanged and remains as data "0".

During the period t5, the second word line WLB is turned off, and the second memory array write-back is finished, while the second amplifier is still turned on, and the first bit line level represents the corresponding data "0" and "1".

During the write operation of the first storage array, the method specifically includes:

in a stage t6, the first word line WLA is turned on, the first memory cell of the first memory array is connected to the first bit line BL, and the capacitor in the first memory cell is charged according to the level of the first bit line BL.

In the stage t7, the first word line WLA is turned off, the write-back of the first memory array is completed, then the signal output by the second enable line SEB is disabled, the second amplifier is turned off, the signal output by the second precharge line RST is enabled, and the second amplifier, the first bit line BL and the second bit line BLN are reset to the initial state.

Step S72: and writing at least part of the data in the first storage array into the second storage array for data backup.

And writing at least part of the data in the first storage array into the second storage array to perform data backup. Specifically, in an embodiment, after power is off, or a user controls to write at least a part of data in the first storage array into the second storage array, so as to perform data backup. Writing at least a portion of the data in the first storage array to the second storage array includes a read operation of the first storage array and a write operation of the second storage array.

In the read operation of the first memory array, data is read from the memory cells of the first memory array to the first amplifier, in the process, a signal output by the first driving line SAT is valid, the switch M1 and the switch M2 are conducted, and the first memory array and the first sense amplifier are conducted; the signal output by the second driving line SBC is inactive, and the switch M3 and the switch M4 are turned off, disconnecting the second memory array from the second sense amplifier. Specifically, referring to fig. 10, fig. 10 is a signal timing diagram of step S72, which specifically includes:

In the stage t2, the signal output by the first pre-charge line EQL is disabled, the row circuit activates the selected first word line WLA according to the row address, the potential of the first bit line BL varies according to the amount of charges stored in the first memory cell, and the potential of the second bit line BLN is kept unchanged as the reference voltage.

During the period t3, the signal output from the first enable line SEA is asserted as the voltage difference between the first bit line BL and the second bit line BLN is established. The first amplifier starts to operate, amplifies a voltage difference between the first bit line BL and the second bit line BLN and completes write-back of the capacitance of the first memory cell, and then the first word line WLA is turned off.

Then, the data is moved from the first amplifier to the second amplifier, in the process, the signal output by the first driving line SAT is invalid, the switch M1 and the switch M2 are turned off, and the first memory array is disconnected from the first sense amplifier; the signal output by the second driving line SBC is valid, and the switch M3 and the switch M4 are turned on, so that the second memory array and the second sense amplifier are turned on.

In the period t4, the signal output by the first enable line SEA is disabled, the first amplifier is turned off, and the first bit line BL and the second bit line BLN are disconnected from the first amplifier and connected to the second amplifier. At this time, the first bit line BL and the second bit line BLN still maintain the high level or the low level. The signal output by the second enable line SEB is valid, the second amplifier starts to work, the movement of data is realized, and the voltage difference between the first bit line BL and the second bit line BLN is further amplified to the high-low level required by the operation of the second memory array.

Finally, writing the data from the second amplifier into the second memory array specifically includes:

in the period t5, the second word line WLB is turned on, the signal output from the second control line PLB rises, and if the first bit line BL is at a low level, the polarization direction of the ferroelectric capacitor in the second memory cell is changed and is denoted as data "0".

In the period t6, the signal outputted from the second control line PLB falls, and if the first bit line BL is at high level, the polarization direction of the ferroelectric capacitor in the second memory cell is changed to another direction, which is marked as "1".

In the stage t7, the second word line WLB is turned off, the signal output by the second enable line SEB is inactive, the second amplifier is turned off, the signal output by the second precharge line RST is active, and the second amplifier, the first bit line BL, and the second bit line BLN are reset to the initial state.

According to the control method of the memory chip, the two memory arrays in different modes are combined together, on one hand, the control method has the characteristic of low power consumption, and particularly shows that refreshing is not needed after data are stored in the second memory array; on the other hand, the method has the characteristic of high reading and writing speed, and is particularly characterized in that the reading and writing speed of the first storage array is higher than that of the second storage array; on the other hand, the storage device has the characteristic of long service life, and is particularly characterized in that most data are completed in the working mode of the first storage array, the capacitor of the second storage array cannot be damaged, and the service life comparable to that of the first storage array is realized; on the other hand, the nonvolatile storage device has the characteristic of nonvolatile, and is characterized in that data in the first storage array can still be stored in the second storage array after power is off, and the data is restored to the first storage array after power is on. Further, the method has the advantages of low delay and high bandwidth. The low delay is embodied in that the operations of the first storage array and the second storage array are automatically and continuously completed in the storage chip, user intervention is not needed, and the delay is low. The high bandwidth is embodied in that data is shifted between the first amplifier of the first memory array and the second amplifier of the second memory array in units of pages, and all data shifting of a whole page can be completed only by one operation.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims

1. A memory chip, comprising: a plurality of memory modules, each memory module comprising a plurality of memory arrays, each said memory array comprising:

a first storage array operating in a first storage mode;

a second storage array operating in a second storage mode;

the control circuit is connected with the first storage array and the second storage array and used for writing at least part of data in the second storage array into the first storage array so as to enable external equipment to read and write data from and into the first storage array; and writing at least part of data in the first storage array into the second storage array to perform data backup.

2. The memory chip of claim 1, wherein the memory array comprises:

the first sense amplifier is connected with the first storage array and used for reading and writing data of the first storage array;

and the second sense amplifier is connected with the second storage array and used for reading and writing data of the second storage array.

3. The memory chip of claim 2,

the first storage array comprises: a plurality of first memory cells, each of the first memory cells comprising:

a control end of the first transistor is connected with a first word line, and a first end of the first transistor is connected with a first bit line;

a first end of the first capacitor is connected with a second end of the first transistor, and a second end of the first capacitor is connected with a first control line;

the second storage array comprises: a plurality of second memory cells, each of the second memory cells comprising:

a control end of the second transistor is connected with a second word line, and a second end of the second transistor is connected with a second bit line;

and a first end of the second capacitor is connected with the first end of the second transistor, and a second end of the second capacitor is connected with a second control line.

4. The memory chip of claim 3, wherein the memory array further comprises:

a first switch circuit connected between the first sense amplifier and the first memory array;

a second switch circuit connected between the second sense amplifier and the second memory array;

the first switch circuit is conducted, and data are read from the first storage array; and the second switch circuit is conducted, and at least part of data in the first storage array is written into the second storage array.

5. The memory chip of claim 4, wherein the first switching circuit comprises:

a first switch, a control end of the first switch is connected with a first driving line, and a first end of the first switch and a second end of the first switch are connected with the first bit line;

a second switch, a control end of the second switch is connected with a first driving line, and a first end of the second switch and a second end of the second switch are connected with the second bit line;

the second switching circuit includes:

a third switch, a control end of the third switch being connected to a second driving line, a first end of the third switch and a second end of the third switch being connected to the first bit line;

a fourth switch, a control end of the fourth switch is connected with a second driving line, and a first end of the fourth switch and a second end of the fourth switch are connected with the second bit line.

6. The memory chip of claim 5, wherein the first sense amplifier comprises:

a first amplifier connected to the first bit line, the second bit line, and a first enable line;

a third switch circuit connecting the first bit line, the second bit line, a column selection line, a first data line, and a second data line;

a fourth switch circuit connected to the first bit line, the second bit line, and the first pre-charge line.

7. The memory chip of claim 6, wherein the second sense amplifier comprises:

a second amplifier connected to the first bit line, the second bit line, and a second enable line;

a fifth switch circuit connected to the first bit line, the second bit line, the column selection line, a third data line, and a fourth data line;

a sixth switching circuit connected to the first bit line, the second bit line, and the second pre-charge line;

wherein the first data line, the second data line, the third data line and the fourth data line are connected to a common data line.

8. The memory chip according to claim 6 or 7, wherein the memory module further comprises:

a column circuit connecting the column selection line and the common data line;

a row circuit connecting the first word line and the second word line.

9. The memory chip of claim 8, wherein the row circuit further comprises a word line driver circuit, the word line driver circuit connecting the first word line and the second word line.

10. A method for controlling a memory chip, the method comprising:

writing at least part of data in the second storage array into the first storage array so that external equipment can read and write data in the first storage array;

writing at least part of data in the first storage array into the second storage array for data backup;

the first storage array works in a first storage mode, and the second storage array works in a second storage mode.