KR20180105400A - An oxide-based resistive switching memory device using a single nano-pore structure and method for fabricating the device - Google Patents

Abstract

Disclosed are an oxide-based resistive switching memory device using a single nano-pore structure and a manufacturing method thereof. The manufacturing method of the resistive switching memory device comprises a lower electrode layer forming step of forming a lower electrode layer on a substrate; a memory material layer forming step of forming a memory material layer on the lower electrode layer; a pore forming metal layer forming step of forming a metal layer for forming a pore in a predetermined region of the memory material layer; a pore forming step of forming the pore by removing the memory material layer at a lower portion of the pore forming metal layer; and an upper electrode forming step of forming an upper electrode at the formed pore. Therefore, the resistive switching memory device can manufacture a highly integrated device with a large area.

Description

TECHNICAL FIELD [0001] The present invention relates to an oxide-based resistance switching memory device using a single nano-pore structure, and a manufacturing method thereof. BACKGROUND ART < RTI ID = 0.0 >

The present invention relates to a memory device and a method of manufacturing the same, and more particularly, to an oxide-based resistance switching memory device and a method of manufacturing the same.

Recently, as the throughput of data explosively increases due to the development of artificial intelligence, autonomous driving vehicle, and Internet (IoT), demand for ultra-high speed, large capacity, and ultra low power memory devices is explosively increasing.

However, existing memory devices have difficulty satisfying such a demand sufficiently. For example, DRAMs operate at high speeds, but are nearing the physical limitations of integration, and FLASH memory is a problem with high power consumption and short life spans.

Therefore, ReRAM, which can realize nonvolatile, highly integrated, super high speed and ultra low power performance, is attracting attention as a next generation memory device. Unlike conventional DRAM or FLASH memory, which is a method of storing a charge, ReRAM utilizes a resistance switching phenomenon that exhibits nonvolatility among various characteristics of an oxide used as an insulator. More specifically, a characteristic that the resistance value is not constant using the current hysteresis curve of the oxide material is used, and the structure of the metal / insulator / metal structure is also relatively simple.

As a result, even if one voltage is applied, it can have two different resistance values. In a state where the resistance value changes once, the last resistance value is continuously maintained even when no external power is supplied until the next switching occurs.

However, despite the advantages that ReRAM has a simple structure and operation method, and that many oxide materials used as an insulator exhibit a common current hysteresis curve, a formal switching mechanism that explains this is not yet established.

In addition, a switching filament is required to be formed and controlled in an oxide material. However, a technology capable of controlling this in a large-area / highly integrated device using current semiconductor processing equipment has not yet been developed. In addition, there is a possibility that the switching filaments are formed non-uniformly in the oxide material in most cases, so that they do not have uniform performance per device.

KR 101570903 B1

SUMMARY OF THE INVENTION It is an object of the present invention to provide a resistance switching memory device capable of effectively controlling the formation and size of a switching filament and fabricating a large-area / highly integrated device using conventional semiconductor equipment, And a manufacturing method thereof.

In order to accomplish the above object, a method of fabricating a resistance switching memory device using a single pore structure according to the present invention includes: forming a lower electrode layer on a substrate; forming a memory material layer on the lower electrode layer; Forming a cavity-forming metal layer in a predetermined region of the memory material layer; forming a cavity by removing a memory material layer under the cavity-forming metal layer; and forming an upper electrode Forming an upper electrode, and forming a nanogap by electromigration by applying a voltage higher than a predetermined voltage to the electrode in the gap.

According to this structure, the formation and size control of the switching filaments are limited to the inside of the memory material layer, that is, the nano gap, not the edge of the memory material layer, thereby ensuring the uniformity and stability of switching of the resistive memory element .

In addition, since the cavity forming metal layer is formed and controlled on the surface of the memory material layer to form the cavity, the cavity can be uniformly and stably formed.

In addition, since each device can be formed with a single cavity and its size can be controlled, the device can be manufactured with uniform performance for each device.

At this time, the memory material layer may be a silicon oxide layer.

The method may further include forming a lower electrode by removing a predetermined region of the silicon oxide layer to expose the lower electrode layer.

The method may further include a switching region forming step of forming a separation region in the upper electrode by applying a voltage between the upper electrode and the lower electrode. With such a configuration, switching can be performed through the vertical gap in the memory material, thereby enabling low-power driving at a lower voltage.

Further, the metal of the metal layer for void formation may be at least one of gold, silver, platinum, and tungsten.

Further, the metal layer for forming voids may be patterned and then deposited using photolithography or electron beam lithography. According to such a configuration, a large-area device can be manufactured using conventional semiconductor equipment.

Also, the pores may have nanoscale pore size. According to this structure, one cell can be fabricated within 10 nm, making it possible to manufacture a highly integrated device.

In addition, a resistance switching memory device manufactured using the above method is also disclosed.

According to the present invention, the formation and size control of the switching filament are restricted to the inside of the memory material layer, not the edge of the memory material layer, thereby ensuring uniformity and stability of switching of the resistive memory device.

In addition, since the cavity forming metal layer is formed and controlled on the surface of the memory material layer to form the cavity, the cavity can be uniformly and stably formed.

In addition, since each device can be formed with a single cavity and its size can be controlled, the device can be manufactured with uniform performance for each device.

In addition, switching through the vertical gap in the memory material is possible, enabling low power driving at lower voltages.

In addition, a large-area device can be manufactured using conventional semiconductor equipment.

In addition, since one cell can be fabricated within 10 nm, highly integrated devices can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram illustrating a schematic fabrication process of a resistive memory switching device using a single pore structure according to an embodiment of the present invention; FIG.
2 shows an example of a SiO ₂ / Si substrate.
3 shows an example in which a lower electrode layer is formed on a substrate.
4 illustrates an example in which a memory material layer is formed on a lower electrode layer.
5 shows an example in which a metal layer for forming voids is formed on a memory material layer;
6 illustrates an example of forming voids in a layer of memory material;
Figures 7 and 8 are AFM measurement data and SEM image of a single nanopore formed.
9 illustrates an example of forming an upper electrode in a void in a layer of memory material;
SiO ₂ to expose the lower electrode 10 is Lt; RTI ID = 0.0 > etch < / RTI >
11 is a view showing an example of forming a switching region in a memory material layer by applying a voltage between an upper electrode and a lower electrode.
FIG. 12 is a graph showing an example of the current-voltage characteristics of a memory device manufactured according to the method of FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a fabrication process of a resistive memory switching device using a single pore structure according to an embodiment of the present invention. Referring to FIG. In FIG. 1, a lower electrode layer 120 is formed on a substrate 110. In this case, the substrate may be a SiOx / Si substrate, for example, a SiO ₂ / Si substrate may be used. 2 is a view showing an example of a SiO ₂ / Si substrate.

 Since the lower electrode layer 120 is deposited on the substrate 110, the thickness of the substrate 110 may be varied, but the area of the substrate must be greater than the area of the portion to be patterned by photolithography. For example, a substrate having a size of 1 cm to 1.5 cm may be used when the size of the patterning portion is 1 cm X 1 cm.

3, the lower electrode layer 120 is formed of Ta / Pt, but the lower electrode layer 120 is formed of Au, Pt, Cu, Al, ITO, graphene, TiN, heavily doped Si, Or a semiconductor material. 3 is a diagram showing an example in which a lower electrode layer is formed on a substrate. In FIG. 3, both Ta and Pt metals can be deposited by DC sputtering, wherein the thickness of the lower electrode layer 120 does not affect the switching performance of the memory.

A memory material layer 130 is then formed on the lower electrode layer 120. For example, a SiOx 130 may be deposited on a Pt / Ta electrode 120 deposited on a SiO ₂ / Si substrate 110, a 40 nm SiOx layer 130 may be deposited by PECVD, 130 may be deposited by electron beam evaporation.

The atomic ratio "x " between silicon and oxygen can be between 0.2 and 2 or the same range and can be deposited using any deposition system such as electron beam evaporation, sputtering, PECVD, and ALD.

4 is a view showing an example in which a memory material layer is formed on the lower electrode layer. FIG. 4 shows an example of SiO ₂ deposition using an electron beam evaporator (E-beam evaporator). The thickness of SiO _{2 to be} deposited is usually several tens nm, but in FIG. 4, the SiO ₂ thickness is 75 nm and the deposition rate is 0.1 nm / s or less.

Next, a metal layer 140 for forming a pore is formed in a predetermined area of the memory material layer 130. Next, A metal thin film is deposited on the surface of an oxide to be formed with a nanopore structure. 5 is a diagram showing an example in which a metal layer for forming voids is formed on the memory material layer.

5, an example is shown in which gold (Au) is deposited using an E-beam evaporator after patterning by a photolithography process. A circular gold pattern (Au pattern) has a diameter 1.5 μm or less, and 18 nm in height, and the deposition rate is 5.0 nm or less.

Next, the memory material layer 130 under the cavity formation metal layer 140 is removed to form a cavity. FIG. 6 is a diagram illustrating an example of forming voids in the memory material layer 130. FIG. FIG. 6 shows an example of forming a gap in the memory material layer 130 by annealing at normal pressure using an electric oven. At this time, the ramping up time is 1 hour, and the heating time is the time of deposition of the deposited SiO ₂ Depends on thickness.

As described above, when a metal thin film is deposited on the surface of an oxide to be formed with a nano-pore structure and heat is applied to a temperature near the melting point of the metal, the metal particles are evaporated, While forming a number of void structures.

Particularly, when the size of the metal particles deposited on the surface of the oxide is appropriately controlled, a single pore is formed from the single metal particles to be deposited. Alternatively, when an oxide is etched by an electrochemical method to form a void, the size and number of the voids are irregularly formed.

Thus, the present invention has great advantages in terms of uniformity and reproducibility of void formation. In addition, when the time and temperature of applying heat are simultaneously adjusted as the dependent variable, the depth and shape of the cavity can be controlled.

Figures 7 and 8 are AFM measurement data and SEM images of a single nanopore formed. FIG. 7 shows that the depth of the nano-void varies with the heat treatment time, and FIG. 8 shows an example in which the size of the lower portion of the void is adjusted to 10 nm or less.

Then, the upper electrode 140 is formed on the formed gap. Fig. 9 is a view showing an example of forming an upper electrode in a gap of a memory material layer. An upper electrode layer (Au or Pt) 150 may be deposited on a single nano-sized pore using, for example, a circular photomask or a circular shadow metal mask method, by depositing and filling the interior of the formed nanopore with a metal. FIG. 9 shows an example of patterning by photolithography and then depositing gold (Au) using an electron beam evaporator (E-beam evaporator) at a deposition rate of 5.0 nm or less.

Subsequently, a predetermined region of the memory material layer 130 is removed to form the lower electrode 120. For this, an etching process by reactive ion etching (RIE) may be performed to remove the uncovered SiOx layer. SiO ₂ to expose the lower electrode 10 is Lt; RTI ID = 0.0 > etched. ≪ / RTI > In this case, both reactive ion etching (RIE) and buffer oxide etch (BOE) etching can be used.

Subsequently, a voltage is applied between the upper electrode 150 and the lower electrode 120 to form an isolation region in the upper electrode 150. A voltage exceeding a certain level is applied to the electrode in the pore to form a nanogap by electromigration. 11 is a view illustrating an example of forming a switching region in a memory material layer by applying a voltage between an upper electrode and a lower electrode.

As shown in FIG. 11, when a bias is applied to a metal, physical defects are formed by electromigration of the metal. At this time, a nanogap is formed on the interface between the defect of the metal and the oxide surrounding the void, and switching phenomenon occurs in this nanogap.

Specifically, when a bias of about 5 V is applied to a metal having electromigration, the bond between silicon and oxygen atoms forming silicon oxide located in the nanogap region is broken. Then, recombination between the broken silicon atoms is formed to form a nano crystal structure, which serves as a conductive filament. It can be programmed to SET with low resistance state (LRS) or ON state of resistive memory.

Conversely, when a bias of about 15 V is applied in the ON state, the bond between the silicon atoms constituting the conductive Si nanocrystal filament is transformed into an amorphous silicon state by Joule heating. It is programmed to RESET with HRS (high resistance state) or OFF state. In addition, to determine the programmed state with SET or RESET, a read voltage pulse of 1V that does not affect the structure and state can be applied.

12 is a graph showing an example of the current-voltage characteristics of a memory element manufactured according to the method of FIG. In FIG. 12, it is confirmed that the read voltage is 3 V or less, the set voltage is 3 V to 7 V, and the reset voltage is 7 V or more.

According to the present invention, uniformity and stability of switching can be ensured by limiting the formation and size control of a switching filament only within a nano pore. In addition, a single filament can be formed through a single nano-pore, and since the formation size of a single nano-pore can be controlled, a single cell can be fabricated within 10 nm, thereby enabling high integration.

In addition, it is possible to improve the characteristics of the conventional silicon oxide memory with the controlled filament, and it is possible to manufacture a large-sized device by using the existing semiconductor equipment. Further, it is possible to secure the convenience of the crossbar array process, A switching device based on a structure can be developed.

In summary, the present invention relates to techniques for forming and controlling oxide (ex., SiOx) switching filaments using a single nanopore (sub-10 nm) structure made of metal particles. Particularly, the present invention is characterized in that a switching filament of a silicon oxide material capable of low-power driving can be uniformly manufactured / controlled by using a single nano-void structure of a sub-10 nm scale, and is characterized by a highly integrated memory device technology have.

Since the present invention has the advantages of DRAM and FLASH memory, which are the most representative memories at present, it is expected to be mainly applied to the field where the above two products are mounted in the case of mass production and commercialization.

The present invention can be applied not only to replace existing DRAM and FLASH memory products, but also to develop a new concept of next generation memory combined with performance and function of both products. In this case, when designing various mobile devices including a computer, it is expected to have technical advantages such as high integration, low power, and low energy.

It is expected that the present invention will be applied first to the PC and mobile electronic device market where existing memory devices are most loaded. In addition, it is expected to be used as a core technology for next-generation electronic devices beyond existing silicon-based electronic devices.

Furthermore, it can be applied to the server market, which requires high performance such as high-speed, large capacity, and low-power data in the future, and the automobile semiconductor market, which controls autonomous and unmanned automobiles in which product reliability can be directly linked to safety.

Although the present invention has been described in terms of some preferred embodiments, the scope of the present invention should not be limited thereby but should be modified and improved in accordance with the above-described embodiments.

100: Resistance switching memory element using single pore structure
110: substrate
120: lower electrode layer
130: memory material layer
140: metal layer for forming voids
150: upper electrode

Claims (14)

A lower electrode layer forming step of forming a lower electrode layer on a substrate;
Forming a memory material layer on the lower electrode layer;
Forming a void-forming metal layer in a predetermined area of the memory material layer;
A cavity forming step of forming a cavity by removing the memory material layer under the cavity forming metal layer; And
And forming an upper electrode on the gap formed between the upper electrode and the lower electrode.
The method according to claim 1,
Wherein the memory material layer is a silicon oxide layer.
The method of claim 2,
And forming a lower electrode by removing a predetermined region of the silicon oxide layer to expose the lower electrode layer.
The method of claim 3,
And forming a separation region in the upper electrode by applying a voltage between the upper electrode and the lower electrode.
The method of claim 4,
Wherein the metal of the cavity forming metal layer is at least one of gold, silver, platinum, and tungsten.
The method of claim 5,
Wherein the cavity forming metal layer is patterned using a photolithography process or an electron beam lithography process and then deposited.
The method of claim 6,
RTI ID = 0.0 > 1, < / RTI > wherein the pores have nanoscale pore size.
A lower electrode layer formed on a substrate;
A memory material layer formed on the lower electrode layer and having a single gap formed therein;
And an upper electrode formed on the single void,
Wherein the single void is formed by removing the memory material layer under the cavity formation metal layer formed in the predetermined area of the memory material layer.
The method of claim 8,
Wherein the memory material layer is a silicon oxide layer.
The method of claim 9,
And a lower electrode formed by removing a predetermined region of the silicon oxide layer.
The method of claim 10,
Wherein the upper electrode includes an isolation region formed by applying a voltage between the upper electrode and the lower electrode.
The method of claim 11,
Wherein the cavity-forming metal layer material is at least one of gold, silver, platinum, and tungsten.
The method of claim 12,
Wherein the metal layer for forming voids is patterned using a photolithography process or an electron beam lithography process and then deposited.
14. The method of claim 13,
Wherein the cavity has a nanoscale pore size.

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