WO2018169269A1

WO2018169269A1 - Oxide-based resistive switching memory element using single nanopore structure and manufacturing method therefor

Info

Publication number: WO2018169269A1
Application number: PCT/KR2018/002894
Authority: WO
Inventors: 왕건욱; 권순방
Original assignee: 고려대학교 산학협력단
Priority date: 2017-03-15
Filing date: 2018-03-12
Publication date: 2018-09-20
Also published as: KR101948638B1; KR20180105400A

Abstract

An oxide-based resistive switching memory element using a single nanopore structure and a manufacturing method therefor are disclosed. The resistive switching memory element manufacturing method comprises: a lower electrode layer forming step of forming a lower electrode layer on a substrate; a memory material layer forming step of forming a memory material layer on the lower electrode layer; a pore-forming metal layer forming step of forming a pore-forming metal layer in a preset region of the memory material layer; a pore forming step of forming a pore by removing the memory material layer at a lower part of the pore-forming metal layer; and an upper electrode forming step of forming an upper electrode on the formed pore.

Description

Oxide-based resistive switching memory device using single nanoporous structure and manufacturing method thereof

The present invention relates to a memory device and a method of manufacturing the same, and more particularly to an oxide-based resistance switching memory device and a method of manufacturing the same.

Recently, with the development of artificial intelligence, autonomous vehicles, and the Internet of Things (IoT), as data throughput explosively increases, the demand for ultra-fast, large-capacity, ultra-low-power memory devices is exploding.

However, existing memory devices have difficulty in sufficiently satisfying this demand. For example, DRAM operates at high speeds, but has reached the physical limits of density, while FLASH memory suffers from high power consumption and short lifetimes.

Accordingly, ReRAM capable of realizing non-volatile, high integration, ultra high speed, and ultra low power performance has attracted attention as a next generation memory device. Unlike conventional DRAM and FLASH memories that store charges, ReRAM uses a resistance switching phenomenon that exhibits non-volatile characteristics among oxides used as an insulator. More specifically, the current hysteresis curve of the oxide material is used to use a property in which the resistance value is not constant. As the metal / insulator / metal structure, the structure is also relatively simple.

As a result, even if one voltage is applied, two different resistance values can be obtained, and once the resistance value is changed, the last resistance value is continuously maintained even when no external power is supplied until the next switching occurs.

However, despite the advantages that ReRAM has a simple structure and operation method and many oxide materials used as insulators commonly exhibit a current hysteresis curve, a formal switching mechanism to explain this has not yet been established.

In addition, a switching filament must be formed and controlled in an oxide material, and a technology for controlling it in a large area / high density device using current semiconductor processing equipment has not been developed yet. In addition, there is a possibility that the switching filament is not uniformly formed in the oxide material in most cases and does not have uniform performance for each device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, which effectively controls the formation and size of a switching filament, and is capable of fabricating a large area / high density device using conventional semiconductor equipment, and It aims at providing the manufacturing method.

In order to achieve the above object, a resistance switching memory device manufacturing method using a single pore structure according to the present invention includes forming a lower electrode layer on a substrate, and forming a memory material layer on the lower electrode layer. Forming a pore forming metal layer in a predetermined region of the memory material layer; forming a pore by removing the memory material layer under the pore forming metal layer; and forming an air gap in the formed void. Forming an upper electrode, forming a nanogap by electromigration (electromigration) by applying a voltage or more to the electrode in the gap.

According to this configuration, it is possible to secure uniformity and stability of switching of the resistive memory device by limiting the formation and size control of the switching filament to the inside of the memory material layer, that is, the nanogap, not the edge of the memory material layer. .

In addition, since the voids are formed by forming and controlling the metal layer for forming the voids on the surface of the memory material layer, the voids can be formed uniformly and stably.

In addition, since each device can be formed into a single gap and the size can be controlled, it can be manufactured to have a uniform performance for each device.

In this case, the memory material layer may be a silicon oxide layer.

In addition, the method may further include forming a lower electrode exposing the lower electrode layer by removing a predetermined region of the silicon oxide layer.

The method may further include forming a switching region in which a separation region is formed in the upper electrode by applying a voltage between the upper electrode and the lower electrode. This configuration enables switching through the vertical gap inside the memory material, thus enabling low power operation at lower voltages.

In addition, the metal of the metal layer for forming voids may be at least one of gold, silver, platinum, tungsten.

In addition, the pore forming metal layer may be deposited after patterning using a photolithography or electron beam lithography process. According to such a structure, a large area element can be manufactured using conventional semiconductor equipment.

In addition, the pores may have nanoscale pore sizes. According to such a structure, since one cell can be manufactured within 10 nm, manufacture of a highly integrated element is attained.

In addition, a resistance switching memory device manufactured using the above method is disclosed.

According to the present invention, the uniformity and stability of the switching of the resistive memory device can be secured by limiting the formation and size control of the switching filament to the inside of the memory material layer rather than the edge of the memory material layer.

In addition, switching is possible through the vertical gap inside the memory material, enabling lower power operation at lower voltages.

In addition, it is possible to manufacture a large area device using conventional semiconductor equipment.

In addition, since one cell can be manufactured within 10 nm, a highly integrated device can be manufactured.

1 is a schematic manufacturing process conceptual diagram of a resistive memory switching device using a single pore structure in accordance with an embodiment of the present invention.

2 shows an example of a SiO ₂ / Si substrate.

3 illustrates an example in which a lower electrode layer is formed on a substrate.

4 illustrates an example in which a memory material layer is formed on a lower electrode layer.

5 illustrates an example in which a metal layer for forming voids is formed on a memory material layer;

6 shows an example of forming voids in a memory material layer.

7 and 8 are AFM measurement data and SEM images of the formed single nanopores.

9 illustrates an example of forming an upper electrode in a gap in a layer of memory material.

FIG. 10 illustrates a process where an SiO ₂ layer is etched to expose a bottom electrode.

FIG. 11 illustrates an example of forming a switching region in a memory material layer by applying a voltage between an upper electrode and a lower electrode.

12 is a graph showing an example of current voltage characteristics of a memory device manufactured according to the method of FIG.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic manufacturing process conceptual diagram of a resistive memory switching device using a single pore structure according to an embodiment of the present invention. In FIG. 1, first, a lower electrode layer 120 is formed on a substrate 110. In this case, a SiOx / Si substrate may be used as the substrate, for example, an SiO ₂ / Si substrate may be used. 2 shows an example of a SiO ₂ / Si substrate.

Since the lower electrode layer 120 is deposited on the substrate 110, the thickness of the substrate 110 may be variously selected, but the area of the substrate should be larger than the area of the portion patterned by photolithography. For example, when the size of the patterning portion is 1 cm × 1 cm, a substrate having a size of 1 cm to 1.5 cm may be used.

In FIG. 3, the lower electrode layer 120 is formed of Ta / Pt, but the lower electrode layer 120 is formed of Au, Pt, Cu, Al, ITO, graphene, TiN, heavily doped Si, or any other suitable metal, alloy. Or may be formed of a semiconductor material. 3 illustrates an example in which a lower electrode layer is formed on a substrate. In FIG. 3, both Ta and Pt metal may be deposited by DC sputtering, where the thickness of the lower electrode layer 120 does not affect the switching performance of the memory.

Next, the memory material layer 130 is formed on the lower electrode layer 120. For example, SiOx 130 is deposited on a Pt / Ta electrode 120 deposited on SiO ₂ / Si substrate 110, and a 40 nm SiO x layer 130 is deposited by PECVD, or a 100 nm SiO x layer ( 130 may be deposited by electron beam evaporation.

The atomic ratio "x" between silicon and oxygen can range between 0.2 and 2 or the same and can be deposited using any deposition system, such as electron beam evaporation, sputtering, PECVD, and ALD.

4 illustrates an example in which a memory material layer is formed on a lower electrode layer. 4 shows an example of SiO ₂ deposition using an E-beam evaporator. SiO ₂ thickness is usually several tens of nm, but in Fig. 4 SiO ₂ thickness is implemented as 75nm, the deposition rate is implemented to less than 0.1nm / s.

Next, a pore forming metal layer 140 is formed in a predetermined region of the memory material layer 130. It is to deposit a metal thin film on the surface of the oxide to form a nano-pore structure. 5 illustrates an example in which a metal layer for forming voids is formed on a memory material layer.

In FIG. 5, an example of depositing gold (Au) using an E-beam evaporator after patterning by a photolithography process is shown, and the circular gold pattern (Au pattern) has a diameter. Less than 1.5㎛, it is implemented to a height of 18nm, the deposition rate is implemented to 5.0nm or less.

Next, the gap is formed by removing the memory material layer 130 under the pore forming metal layer 140. 6 illustrates an example of forming a gap in the memory material layer 130. 6 shows an example of forming an air gap in the memory material layer 130 by annealing at atmospheric pressure using an electric oven. At this time, the ramping up time (Ramping up time) is 1 hour, the heating time (Heating time) of the deposited SiO ₂ Depends on the thickness.

As such, when the metal thin film is deposited on the surface of the oxide to form the nanopore structure and then heated to a temperature near the melting point of the metal, some of the metal particles evaporate and penetrate into the inside. As a result, numerous void structures are formed.

In particular, when the size of the metal particles deposited on the oxide surface is properly adjusted, a single pore is formed from the single metal particles to be deposited. In contrast, when the oxide is etched by the electrochemical method to form pores, the size and number of the pores are irregular.

Therefore, the present invention has a great advantage in terms of uniformity and reproducibility of pore formation. In addition, when adjusting the time and temperature of applying heat as a dependent variable at the same time, it is possible to control the depth and shape of the voids.

7 and 8 are AFM measurement data and SEM images of the formed single nanopores. FIG. 7 illustrates that the depth of the nanopores varies according to the heat treatment time, and FIG. 8 illustrates an example in which the size of the lower portion of the pores is adjusted to 10 nm or less.

Subsequently, the upper electrode 140 is formed in the formed gap. 9 illustrates an example of forming an upper electrode in a gap of a memory material layer. By filling the inside of the formed nano-pore by depositing with metal, the upper electrode layer (Au or Pt; 150) may be deposited on the nano single pore using, for example, a circular photo mask or a circular shadow metal mask method. 9 shows an example of depositing gold (Au) using an E-beam evaporator after patterning by a photolithography process, wherein the deposition rate is 5.0 nm or less.

Subsequently, the predetermined region of the memory material layer 130 is removed to form the lower electrode 120. To this end, an etching process by reactive ion etching (RIE) may be performed to remove the uncovered SiOx layer. FIG. 10 illustrates a process in which an SiO ₂ layer is etched to expose a lower electrode. In this case, both reactive ion etching (RIE) and buffer oxide etching (BOE) may be used as an etching method.

Subsequently, a voltage is applied between the upper electrode 150 and the lower electrode 120 to form a separation region in the upper electrode 150. The nanogap by electromigration is formed by applying a predetermined voltage to the electrode in the gap. FIG. 11 illustrates an example in which a switching region is formed in a memory material layer by applying a voltage between an upper electrode and a lower electrode.

As shown in FIG. 11, when a bias is applied to the metal, physical defects are formed by the electromigration phenomenon of the metal. At this time, a nanogap is formed at the junction between the metal defect and the oxide surrounding the void, and a switching phenomenon occurs at the nanogap.

Specifically, when a bias of about 5V is applied to a metal on which electromigration occurs, the bond between silicon and oxygen atoms forming silicon oxide in the nanogap region is broken. Subsequently, recombination between the broken silicon atoms is formed to form a nano single crystal structure, which serves as a conductive filament. This may be programmed as a SET by a low resistance state (LRS) or an ON state of the resistive memory.

On the contrary, when a bias of about 15V is applied in the ON state, the bond between the silicon atoms forming the conductive Si nanocrystal filament is changed to the amorphous silicon state by Joule heating. This is a high resistance state (HRS) or OFF state, programmed as RESET. In addition, to determine the state programmed with SET or RESET, a read voltage pulse of 1V can be applied that does not affect the structure and state.

12 is a graph illustrating an example of current voltage characteristics of a memory device manufactured according to the method of FIG. 1. In FIG. 12, the read voltage is 3V or less, the Set voltage is 3V to 7V, and the reset voltage is 7V or more.

According to the present invention, the uniformity and stability of the switching can be secured by limiting the formation and size control of the switching filament to only the nano pores. In addition, not only a single filament can be formed through a single nano-pore, but also the size of the single nano-pore can be controlled so that a single cell can be manufactured within 10 nm, and thus high integration is possible.

In addition, the controlled filament can improve the characteristics of the existing silicon oxide memory, and by using the existing semiconductor equipment, it is possible to manufacture a large-area device, and further, to secure the convenience of the crossbar array process, low cost, and conciseness. It will be possible to develop a switching device based on the structure.

In summary, the present invention relates to a technique for forming and controlling oxide material (ex. SiOx) switching filaments using a single nanoporous (sub-10 nm) structure made of metal particles. In particular, the present invention is characterized by a technology capable of uniformly manufacturing and controlling the switching filament of a silicon oxide material capable of driving low power using a single nano-pore structure of a sub-10 nm scale and a highly integrated memory device technology. have.

The present invention is expected to be mainly applied to the field in which the above two products are installed when mass production and commercialization are equipped with the advantages of the most representative memory DRAM and FLASH memory.

The present invention can be applied not only to the existing DRAM and FLASH memory mounted products, but also to the development of a new concept of the next-generation memory combining the performance and functions of the two products. In this case, when designing various mobile devices including computers, it is expected to have technical advantages such as high integration, low power, and low energy.

The present invention is expected to be applied first to the PC, mobile electronics market in which the existing memory devices are most installed. In addition, it is expected to be used as a core technology in the next generation electronic device area beyond the existing silicon-based electronic device.

Furthermore, it will be applied to the server market that requires high performance such as high speed, large capacity, and low power of data, and the automotive semiconductor market that controls autonomous and driverless cars, where product reliability can be directly linked to safety.

Although the present invention has been described in terms of some preferred embodiments, the scope of the present invention should not be limited thereby, but should be construed as modifications or improvements of the embodiments supported by the claims.

Claims

Forming a lower electrode layer on the substrate;

Forming a memory material layer on the lower electrode layer;

Forming a pore forming metal layer to form a pore forming metal layer in a predetermined region of the memory material layer;

Forming a pore by removing the memory material layer under the pore forming metal layer; And

And forming an upper electrode in the formed gap.
The method according to claim 1,

And the memory material layer is a silicon oxide layer.
The method according to claim 2,

And forming a lower electrode exposing the lower electrode layer by removing a predetermined region of the silicon oxide layer.
The method according to claim 3,

And a switching region forming step of forming a separation region in the upper electrode by applying a voltage between the upper electrode and the lower electrode.
The method according to claim 4,

The metal of the metal layer for forming a gap is at least one of gold, silver, platinum, tungsten manufacturing method of the resistance switching memory device.
The method according to claim 5,

The pore forming metal layer is patterned using a photolithography process or an electron beam lithography process is deposited after the resistive switching device, characterized in that the deposition method.
The method according to claim 6,

The voids have a nano-scale pore size, characterized in that the resistance switching memory device manufacturing method.
A lower electrode layer formed on the substrate;

A memory material layer formed on the lower electrode layer and having a single void formed therein;

An upper electrode formed in the single gap;

And wherein the single gap is formed by removing the memory material layer under the pore forming metal layer formed in a predetermined region of the memory material layer.
The method according to claim 8,

And the memory material layer is a silicon oxide layer.
The method according to claim 9,

And a lower electrode formed by removing a predetermined region of the silicon oxide layer.
The method according to claim 10,

And the upper electrode includes a separation region formed by applying a voltage between the upper electrode and the lower electrode.
The method according to claim 11,

The pore forming metal layer material is at least one of gold, silver, platinum, tungsten resistance switching memory device.
The method according to claim 12,

The pore forming metal layer is a resistive switching memory device, characterized in that deposited by patterning using a photolithography process or an electron beam lithography process.
The method according to claim 13,

And the pore has a nanoscale pore size.