KR20160043884A - Resistive random access memory device having nano-scale tip and nanowire, memory array using the same and fabrication method thereof - Google Patents

Abstract

The present invention relates to a resistive memory device having a nano-tip structure and a nano-wire, a memory array using the same, and a manufacturing method thereof. According to the present invention, a lower electrode has a protruding tip structure whose upper portion is sharper than a lower portion thereof by etching a semiconductor substrate, and an upper electrode is the nano-wire. The resistive memory device is formed in an area wherein the lower and upper electrodes are intersecting with each other. Accordingly, a size of each memory cell is minimized, and an electric field is focused on the lower electrode intersecting with the upper electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a resistive memory device having a nano-tip structure and a nanowire, and a memory array using the same and a method of fabricating the same. BACKGROUND ART < RTI ID = 0.0 >

The present invention relates to a resistive memory device (RRAM), and more particularly, to a resistive memory device having a nano-tip structure and a nanowire, a memory array using the same, and a manufacturing method thereof.

NAND flash memory technology, which is currently leading the mass storage information storage market, is currently dominating nonvolatile memory through continuous scaling down. In recent years, however, reliability problems have arisen as the device size is scaling down to 20 nm or less. Therefore, various next generation nonvolatile memories have been proposed to replace NAND flash memory technology, and studies are actively underway.

Among them, RRAM has a simple structure and it has a merit that reliability is improved when scaling down, which is a strong candidate as an alternative to the existing NAND flash memory technology. As shown in FIG. 1, the RRAM basically has an MIM structure composed of an upper electrode (metal), a resistance-variable layer (switch layer), and a lower electrode (metal).

The switching operation of the RRAM is divided into three steps. As shown in FIG. 2, a forming process that forms a conductive filament in an initial state to form a low resistance state, a reset operation that breaks the conductive filament and increases the resistance, and a reset operation in which a conductive filament is generated, Action.

In the general RRAM structure, the interface between the metal and the insulator is flat, so the electric field is evenly distributed when the voltage is applied at both ends. Therefore, the conductive filament generated in forming and set operation is formed at an arbitrary position and is difficult to control. As such, it is difficult to adjust the position where the conduction filament is generated to a desired level, which causes a problem of reliability of the RRAM, which remains the biggest obstacle to the commercialization of the RRAM.

The cause of such a reliability problem is that the filaments are formed in various shapes in the vertical direction depending on the condition between the grain boundaries of the material constituting the resistance variable layer (for example, transition metal oxide).

Accordingly, in Korean Patent No. 10-1113014, an attempt has been made to minimize the number of filaments involved in the transition by minimizing the area where the resistance variable layer is formed in the form of a spacer to meet with the upper electrode. -0048757 has attempted to form a groove along the grain boundary of the resistance variable layer and fill the groove so that the upper or lower electrode protrudes so as to form a reproducible conductive path by concentrating the electric field. Korean Patent No. 10-1263309 discloses a technique of concentrating an electric field in such a manner that one protrusion is directed to a lower electrode on an upper electrode per cell through a process of forming a side wall and a spacer.

Korean Patent No. 10-1113014, however, has a limitation in minimizing the number of filaments due to the formation of a resistance-variable layer in the form of a spacer, and Korean Patent Laid-Open No. 10-2008-0048757 discloses that a groove is formed on the surface by chemical etching (At the time of forming the upper electrode projection portion), the mixed liquid containing a plurality of metal particles is vaporized and vaporized to form protrusions with the remaining metal particles (at the time of forming the lower electrode projection portions), so that a plurality of protrusions are formed, There is a problem that it is difficult to commercialize it, and in the method disclosed in Korean Patent No. 10-1263309, a protrusion can not be formed on the lower electrode.

As shown in FIG. 3, the RRAM has a trade-off in which a high voltage is applied for a high-speed operation due to a voltage-time dilemma (inversely proportional to the operating voltage and switching time) And the operation current is increased.

In addition, as shown in FIG. 4, in order to configure the RRAM as an array, the upper electrode and the lower electrode must cross each other vertically and each constitute a word line and a bit line. The current technology defines pitch by photolithography, which is difficult to implement sub-10 nm memory devices because of lithography equipment limitations. To achieve higher memory densities, it is important to reduce the pitch of word lines and bit lines, and technology beyond the limits of lithography technology is required.

The present invention minimizes RRAM memory cells to a few nanometers and improves the dispersion of resistance values in high resistance / low resistance state by applying an easy electric field structure and improves the performance of switching speed, operating voltage and operating current And a nano-tip structure and a nanowire capable of improving integration, a memory array using the same, and a manufacturing method thereof.

In order to accomplish the above object, a resistive memory device according to the present invention comprises: a lower electrode formed in a first direction so as to have a tip structure protruding upward toward the top by etching a semiconductor substrate; A resistance-variable layer formed on the lower electrode; And an upper electrode formed on the resistance variable layer in a second direction, the nanowire crossing the lower electrode and passing over the tip structure.

The lower electrode is surrounded by an interlayer insulating film leaving only a part of an upper portion of the tip structure, and the resistance variable layer is formed on the upper part of the tip structure and on the interlayer insulating film as another feature of the resistive memory device according to the present invention.

The tip structure is a wedge-shaped cross section having a predetermined length in the first direction and cut in the second direction, and the nanowire is formed of a metal nanowire, a carbon nanotube , CNTs, and graphene nanoribbons. The resistive memory device according to the present invention is also characterized in that the resistive memory device according to the present invention is a resistive memory device.

The tip structure has another aspect of the resistive memory device according to the present invention in which the size of the upper end in the cross section cut in the second direction is 10 nm or less.

A memory array according to the present invention includes: a semiconductor substrate; A plurality of bit lines formed in the first direction on the semiconductor substrate; And a plurality of word lines crossing the bit lines with a resistance variable layer interposed therebetween and formed in a second direction on the plurality of bit lines, wherein each bit line has a tip And each of the word lines is formed of a nanowire passing over a tip structure formed on each of the plurality of bit lines.

Wherein each of the bit lines is integrally connected to the semiconductor substrate and has a tip structure protruding vertically as the semiconductor line is etched away electrically insulated from the neighboring semiconductor substrate by the isolation insulating film and doped with impurities to form a lower electrode line, An interlayer insulating film is formed between the bit lines and the resistance variable layer to leave only a part of the upper portion of the tip structure of each bit line on the plurality of bit lines, And the word line is formed as an upper electrode line passing over a tip structure formed on each of the plurality of bit lines, .

The tip structure is a wedge-shaped cross section having a predetermined length in the first direction and cut in the second direction, and the nanowire is formed of a metal nanowire, a carbon nanotube , CNTs, and graphene nanoribbons. The memory array according to the present invention is also characterized in that:

A method of manufacturing a memory array according to the present invention includes: a first step of etching a semiconductor substrate to protrude a plurality of semiconductor lines to be formed with a plurality of contacts and bit lines; A second step of depositing and etching a first insulating material on the semiconductor substrate to form an isolation insulating film so that the upper portions of the plurality of semiconductor lines are exposed and insulated from each other; A third step of forming protruding patterns on the plurality of semiconductor lines; A fourth step of forming a tip structure protruding upward from the upper portion of the portion where each bit line is to be formed by using the protruding pattern; Implanting ions onto the plurality of semiconductor lines to form a plurality of contacts and bit lines; Depositing a resistance change material on a substrate including a part of the exposed tip structure of each bit line to form a resistance variable layer and forming a plurality of contact holes to reach the respective contact portions; And a seventh step of forming a plurality of word lines with nanowires on the resistance variable layer and forming a plurality of bit line contacts filled in the contact parts of the plurality of word lines and the plurality of contact holes .

The protrusion patterns of the third step are formed in a rectangular shape and the word lines of the seventh step are formed so as to intersect perpendicularly to the respective bit lines having the wedge type tip structure, Another aspect of the array manufacturing method is as follows.

Depositing a second insulating material on top of the plurality of contacts and the bit lines and the isolation insulator between the fifth step and the sixth step and etching the second insulator and the isolation insulator, Further comprising the step of forming an interlayer insulating film surrounding the second insulating material while leaving only a part of an upper portion of the tip structure of the first insulating material, wherein the second insulating material is the same as the first insulating material, And then etching a portion of the bit line to protrude a part of the tip structure of the bit line.

The word lines in the seventh step are formed by transferring any one of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbon to the nanowire. Another aspect of the method of manufacturing a memory array according to the present invention is as follows.

The formation of the tip structure in the fourth step is another feature of the method of manufacturing a memory array according to the present invention that the plurality of semiconductor lines and / or the protruding pattern is formed by anisotropic etching.

The tip structure has another aspect of the method of manufacturing a memory array according to the present invention in which the size of the upper end in the cross section perpendicular to the semiconductor lines is 10 nm or less.

The protruding pattern of the third step is formed of a semiconductor material, which is another feature of the method of manufacturing a memory array according to the present invention.

The protruding pattern in the third step is an etch mask, which is another feature of the method for manufacturing a memory array according to the present invention.

The etch mask may be formed by any one of a photolithography process, a sidewall patterning process, and an e-beam process, according to another embodiment of the present invention.

The present invention is characterized in that a resistive memory element is formed at a position intersecting with a lower electrode having a tip structure protruding upward as the semiconductor substrate is etched and using the nanowire as an upper electrode, nm can be minimized to the order of several nanometers, which can improve the dispersion of the resistance value in the high resistance state and the low resistance state, lower the operating voltage and current, improve the switching speed, Can be improved.

In addition, since an anisotropic etching can form a lower electrode having a very sharp peak-like structure with a tip size of several nanometers and an upper electrode can be easily formed by a nanowire transfer method, It is possible to design a process with a high degree of completion, and thus it is possible to secure easiness of process, economical efficiency, and high yield.

1 is a cross-sectional view showing a basic structure of a conventional resistive memory device.
2 is a conceptual diagram showing switching operation characteristics of the resistive memory device having the structure of FIG.
3 is an electrical characteristic diagram showing the reset time and the energy relationship according to the applied voltage of the resistive memory device.
4 is a memory array in which a conventional resistive memory element is a unit memory cell.
FIGS. 5 to 14 are a process perspective view and a partial cross-sectional view taken along the line AA 'illustrating a manufacturing process of a memory array according to an embodiment of the present invention.
15 is a cross-sectional view taken along line AA 'and line BB' in FIG.
FIG. 16 is a cross-sectional view illustrating a structure (a) in which a conventional resistive memory device is formed and a structure (b) in which a resistive memory device is formed according to an embodiment of the present invention.
FIG. 17 is a process conceptual view showing that a wedge-type tip structure can be formed by anisotropic etching without patterning the silicon in the form of a fin. FIG.
FIG. 18 shows a nano wedge-shaped tip structure (a) and its enlarged cross-sectional view (b) that can be implemented in a manufacturing process of a memory array according to an embodiment of the present invention.
19 is a process conceptual diagram showing an example of forming a word line by transferring carbon nanotubes in a direction perpendicular to the tip structure on a nano wedge-shaped tip structure in a manufacturing process of a memory array according to an embodiment of the present invention.
FIGS. 20 and 21 are diagrams illustrating the method of the present invention as described in CHEMPHYSCHEM 2003, 4, pp. 131-138, which show that metal nanowires can be regularly formed using the stairs on the HOPG layer, and the metal nanowires thus formed are displayed, The word line of the memory array can be applied to the formation.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, referring to FIGS. 5 to 16, a resistive memory device according to an embodiment of the present invention will be described.

As shown in FIGS. 14 to 16, the resistive memory device according to an embodiment of the present invention includes a tip structure 50 having a tip protruding upward as the semiconductor substrate 10 is etched. A lower electrode (BL) formed in a first direction; A resistance change layer (80, 82; SL) formed on the lower electrode; And an upper electrode (WL) formed on the resistance variable layer in a second direction with a nanowire crossing the lower electrode (BL) and passing over the tip structure (50).

Here, the semiconductor substrate 10 may be a semiconductor substrate such as a germanium substrate other than a silicon substrate. 5 to 11, the lower electrode 22 (BL) is formed by etching the semiconductor substrate 10 and the upper surface of the semiconductor line 20 formed by etching the semiconductor substrate 10, And may be formed as a conductive line by ion implantation so as to have opposite polarities. Accordingly, if the semiconductor substrate 10 is a P-type substrate, the lower electrode 22 (BL) may be formed of an N-type conductive line. Of course, the opposite may be formed.

As shown in FIGS. 15 and 16, the lower electrode 22 (BL) has a tip structure 50 protruding upwardly as it goes up.

As shown in FIG. 16, the tip structure 50 may have a polygonal pyramid shape or a conical shape. However, the tip structure 50 may be formed in a wedge shape having a triangle in cross section cut in the second direction and having a predetermined length in the first direction. It is desirable in the process to make the wires the upper electrode 100 (WL).

The tip structure 50 is formed to have a sharp point toward the upper side so that the upper end size (minimum width) in the cross section cut in the second direction, which is the direction of the upper electrode 100 (WL), is several nanometers (nm) nm or less.

14, the upper electrode 100 may be formed of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbler with a diameter of less than several tens of nanometers or nanoribbon.

16, the upper electrode 100 (WL) and the lower electrode 22 (BL) intersect with each other in a minimized area and the electric field is concentrated to the tip of the tip structure 50 of the lower electrode 22 , It is possible to solve the conventional reliability problem by forming one or the minimum of the conductive filaments CF in the resistance-variable layer 82 (SL) much smaller than in the structure (a) in which the conventional resistive memory element is formed.

11, the lower electrode 22 (BL) is surrounded by an interlayer insulating film 70 while leaving only the upper part 52 of the tip structure 50, and the resistance variable layer 80 is surrounded by the tip And is formed on the upper part 52 of the structure and the interlayer insulating film 70.

Here, the interlayer insulating film 70 may be a known insulating film (a silicon oxide film when the semiconductor substrate is a silicon substrate), but is preferably the same material as the insulating film for isolating semiconductor lines, as described later.

As described above, when the interlayer insulating layer 70 is further formed and the thickness of the interlayer insulating layer 70 is adjusted, the degree of exposure of the upper portion of the tip structure 50 can be adjusted, The region to be formed can be effectively quadratically limited.

A known resistance change material may be used as the resistance variable layer 80. The resistance variable layer 80 may be deposited to a thickness not less than the height of the tip structure 50 exposed on the interlayer insulating layer 70 and planarized by a planarization process, The upper electrode 100 may be formed to protrude upward from the tip structure 50 as shown in FIG. 12, and the upper electrode 100 may be formed as shown in FIG. 15 (a) May be formed on the protrusions (82) of the resistance-variable layer.

Next, a memory array according to an embodiment of the present invention will be described.

The memory array according to an embodiment of the present invention uses the above-described resistive memory element of the present invention as a unit cell element, and as illustrated in FIGS. 14 and 15, includes a semiconductor substrate 10; A plurality of bit lines (22) formed in the first direction on the semiconductor substrate; And a plurality of word lines (100) intersecting the bit lines (22) and formed in a second direction with the resistance variable layer (80) therebetween on the plurality of bit lines, The bit line 22 is formed of a semiconductor line doped with impurities and having a tip structure 50 protruding upward toward the top and each word line 100 is formed in each of the plurality of bit lines 22 Is formed of nanowires that extend over the tip structure (50).

6 to 11, the bit lines 22 are integrated with the semiconductor substrate 10 and the semiconductor lines 20 electrically insulated from the neighboring ones by the isolation insulating film 30 are etched And may have a tip structure 50 protruding to the upper side and doped with impurities to form a lower electrode line. If the semiconductor substrate 10 is a P-type substrate, the bit lines 22 (BL) may be formed of N-type conductive lines. Of course, the opposite may be formed.

As described in the embodiment of the resistive memory device, the tip structure 50 may be a polygonal pyramid or a conical shape. However, as shown in FIG. 16, the tip structure 50 may have a predetermined length in the first direction, The cut cross section is formed in a triangular wedge shape, which is desirable in view of the fact that the nanowire is the upper electrode, word line 100 (WL).

The tip structure 50 is formed to be tapered toward the upper side so that the upper end size (minimum width) in the cross section cut in the second direction, which is the direction of the word line 100, is several nanometers (nm) It can be formed as small as possible.

14, the upper electrode 100 may be formed of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbler with a diameter of less than several tens of nanometers or nanoribbon.

Thus, as shown in Figure 16, each word line 100 (WL) and each bit line 22 (BL) intersect with a minimized area, and an electric field is applied to the tip structure 50 end of each bit line 22 So that one or the minimum of the conductive filaments CF are formed in the resistance-variable layer 82 (SL), as compared with the structure (a) in which the conventional resistive memory element is formed, so that the conventional solid- do.

11 and 12, between the plurality of bit lines 22 and the resistance-variable layer 80, a plurality of bit lines 22 are formed on the upper portion 52 of the tip structure of each bit line And an interlayer insulating film 70 surrounding the periphery may be further formed.

As described above, since the thickness of the interlayer insulating film 70 can be adjusted to control the degree of exposure of the upper portion of the tip structure 50, the region where the conductive filament is formed is secondarily effective . ≪ / RTI >

11 and 12, the resistance variable layer 80 is formed on the upper part 52 of the exposed tip structure of each bit line 22, the interlayer insulating film 70, and the isolation insulating film 30 And each of the word lines 100 is formed as an upper electrode line passing over the tip structures 50 and 52 formed in each of the plurality of bit lines 22 as shown in FIGS. .

In FIGS. 14 and 15, reference numeral 91 is a bit line contact, 92 is a bit line contact plug, 101 is a word line contact portion, and 102 is a word line contact plug.

Next, a method of manufacturing a memory array according to an embodiment of the present invention will be described with reference to FIGS. 5 to 15. FIG.

A method of manufacturing a memory array according to an embodiment of the present invention is a method of manufacturing the memory array of the present invention described above.

5, the semiconductor substrate 10 on which the memory array is to be fabricated is prepared, and the semiconductor substrate 10 is etched to form a plurality of semiconductor lines to be formed with a plurality of contacts and bit lines, (Step 1). Although the semiconductor substrate 10 is preferably a silicon substrate, other semiconductor substrates such as a germanium substrate may be used.

7, a first insulating material is deposited on the semiconductor substrate 10 and etched to form an isolation insulating film 30 so that the upper portions of the plurality of semiconductor lines 20 are exposed and isolated from each other Step 2). The first insulating material may be an oxide film. After the first insulating material is deposited, the first insulating material may be planarized by a known CMP process or the like and etched so that the upper portions of the plurality of semiconductor lines 20 are exposed.

8, a protrusion pattern 40 is formed on the plurality of semiconductor lines 20 (third step). The protruding pattern 40 can be formed by selecting one of two types. In this case, the protruding pattern 40 is formed of a semiconductor material which is the same as or similar to that of the semiconductor substrate 10. The protruding pattern 40 is formed by etching the next protruding pattern 40 itself to form a tip structure. The other is to form the protrusion pattern 40 as an etch mask to etch the exposed semiconductor line 20 around the etch mask to form a tip structure. In the latter case, the etch mask may be a dry mask, but it is preferably formed of oxide or nitride using a wet mask. Specifically, to form the etch mask, any one of a known photolithography process, a sidewall patterning process, and an e-beam process may be used.

Then, the shape of the tip structure is determined in accordance with the shape of the protruding pattern 40. Accordingly, the protrusion pattern 40 may be formed in one or a plurality of shapes in the longitudinal direction of each semiconductor line 20 in the shape of a regular polygon such as a square, a circle, an ellipse or a rectangle depending on the shape of the tip structure to be manufactured can do. 16, the tip structure has a predetermined length in the first direction, and a section cut in the second direction is a triangle (triangle) in the first direction, It is preferable to form it as a wedge type.

For this reason, as shown in FIG. 8, the protruding patterns 40 are preferably formed in a rectangular shape having a predetermined length in the longitudinal direction for each of the semiconductor lines 20.

Next, as shown in FIG. 9, the protrusion pattern 40 is used to form a tip structure 50 protruding upward from the upper portion of each bit line to be formed (step 4). That is, when the protruding pattern 40 is formed of a semiconductor material, the protruding pattern 40 and the exposed semiconductor lines 20 are etched to form the tip structure 50. When the protruding pattern 40 is etched, In the case of a mask, the semiconductor lines 20 exposed to the periphery of the etching mask are etched to form the tip structure 50.

9 shows an example in which a tip structure 50 is formed in a wedge shape having a predetermined length and each of which is triangular in cross section, as shown in Fig.

In the fourth step, when the plurality of semiconductor lines 20 and / or the protruding patterns 40 are etched to form the tip structure, anisotropic etching is preferably performed. Here, the term " anisotropic etching " refers to the use of the fact that a difference in etch rate occurs along the crystal plane of the semiconductor. This is different from isotropic etching in which evenly oriented anisotropic etching, such as vertically etched dry etching, is evenly etched in all areas where the etching compound is in contact. In the case where the semiconductor lines 20 and / or the protruding patterns 40 are formed of silicon, if anisotropic wet etching is performed with a solution such as TMAH, KOH, or the like, the anisotropic wet etching is performed at the upper end A peaked tip structure 50 can be realized which is extremely pointed at a size (upper end in the section cut in the second direction, that is, a minimum width) of several nanometers (nm), for example, 10 nm or less.

17 is a process conceptual view showing that a wedge-type tip structure can be formed by anisotropic etching without patterning an anisotropic etch mask by patterning silicon into a fin shape, as described above, It is possible to form the desired tip structure 50 even when the projecting pattern 40 is formed by a semiconductor material which is the same as or similar to that of the semiconductor substrate 10 but not an etch mask and is subjected to anisotropic etching.

Next, as shown in FIG. 10, ion implantation is performed on the plurality of semiconductor lines 20 to form a plurality of contacts and bit lines (step 5). Here, the ion implantation process increases the electrical conductivity of the upper portion of the semiconductor lines 20 as well as the protruding tip structure 50 to form a plurality of contact portions and bit lines in a conductive line (i.e., a lower electrode line) Since the semiconductor substrate 10 is for insulation from the lines 20 and the semiconductor substrate 10, if the semiconductor substrate 10 is a P-type substrate, a plurality of contact portions and bit lines are formed in N-type. Of course, the opposite may be formed.

11, a second insulating material may be deposited on the isolation insulating film 30 and on top of the plurality of contacts and the bit lines 22, and the second insulating material and / It is preferable that the isolation insulating film 30 is etched to leave an upper part 52 of the tip structure of each bit line 22 and to form an interlayer insulating film 70 surrounded by a second insulating material. However, if the word lines 100 are not formed of a material that can cover the protruding tip structure 50 in a subsequent process, this additional process may be omitted.

11 (b) is a sectional view taken along line AA 'in Fig. 11 (a). As can be seen from FIG. 11 (b), the thickness of the interlayer insulating film 70 can be adjusted to adjust the degree of exposure of the upper portion of the tip structure 50, whereby the region where the conductive filament is formed is referred to as a secondary As shown in FIG.

The second insulating material may be the same material as the first insulating material for forming the isolation insulating layer 30, and the second insulating material and the insulating layer 30 may be etched using the same The interlayer insulating film 70 and the dielectric isolation film 30 are etched while being maintained in a horizontal state so that the bit line 22 The upper portion 52 of the tip structure of the first and second tapered portions is protruded.

12, a resistance change material is deposited on the upper portion 52 of the exposed tip structure of each bit line 22, the interlayer insulating layer 70, and the isolation insulating layer 30 to form a resistance variable layer 80, and 82, and a plurality of contact holes 60 are formed to reach the respective contact portions (step 6).

The resistance change layers 80 and 82 may be made of a known resistance change material and may be deposited to a thickness not less than the height of the tip structure 50 exposed on the interlayer insulation layer 70 and planarized by a planarization process or the like As shown in FIG. 12, the word lines 100 may be formed to protrude upward from the tip structure 50, as shown in FIG. 12, The resistance change layers 80 and 82 are formed so as to form the protruding portions 82 of the resistance variable layer in the tip structure 50 exposed on the interlayer insulating film 70. In the subsequent process, (100) may be formed on the protrusion (82) of the resistance variable layer.

Thereafter, as shown in FIG. 15, a plurality of word lines 100 are formed of nanowires on the resistance-variable layer 82, and the contact portions 101 of the plurality of word lines and the plurality of contact holes Thereby forming a plurality of filled bit line contacts 91 (step 7).

Each of the word lines 100 may be formed by transferring one of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbon to the nanowire .

FIG. 19 is a cross-sectional view illustrating a process of manufacturing a memory array according to an embodiment of the present invention. Referring to FIG. 19, a carbon nano-structure is formed on a protruded resistance-variable layer 82 covered with a nano- And the word line 100 is formed by transferring the tube 110.

19A shows a single-walled carbon nanotube (SWNT) 110 grown on a quartz substrate 1 by mercury and FIG. 19B shows a single-walled carbon nanotube grown on the carbon nanotubes 110 FIG. 19 (c) shows a case where the thin film 2 is formed by a polymer coating such as gold film or polymethyl methacrylate on the thin film 2 by using an adhesive tape or the like 19 (d) shows a state in which the detached carbon nanotubes 110, for example, the adhesive tape / PMMA / SWNT 2 are removed, is removed from the back surface of the semiconductor substrate 10, And the nano-wedge-shaped tip structure 50 is placed on the protruding resistance-variable layer 82 in a direction perpendicular to the tip structure 50. After the above process, the adhesive tape is slowly peeled off on a predetermined hot plate at 100 ° C., and finally, the PMMA is removed using acetone. Then, the SWNT 110, which has been synthesized on the quartz substrate 1, (100).

Figures 20 and 21 illustrate how nanoparticles are deposited on highly ordered pyrolysis graphite (HOPG) in the form of a layered structure with uniformly biased step edges of graphene along the respective step edges by electrochemical step edge decorating Electrodeposition based on ESED can be used to produce homogeneous metal nanowires with desired diameters. For this, see CHEMPHYSCHEM 2003, 4, pp. 131-138. ≪ / RTI >

19, a gold film or a PMMA film is formed on the HOPG substrate and the metal nanowires are transferred to the word line 100 of the memory array according to the present invention by using an adhesive tape such as a scotch tape or the like .

10: semiconductor substrate
20: semiconductor line
22: lower electrode, bit line
30: Isolation insulating film
40: protruding pattern
50: Tip structure
52: a top portion of the exposed tip structure
60: contact hole
70: Interlayer insulating film
80: resistance variable layer
82, 84: protrusion of the resistance variable layer
92: bit line contact plug
100: upper electrode, word line
110: Carbon nanotubes

Claims (16)

A lower electrode formed in a first direction so as to have a tip structure protruding vertically as the semiconductor substrate is etched;
A resistance-variable layer formed on the lower electrode; And
And an upper electrode formed on the resistance variable layer in a second direction with nanowires crossing the lower electrode and over the tip structure.
The method according to claim 1,
Wherein the lower electrode is surrounded by an interlayer insulating film around the tip structure,
Wherein the resistance variable layer is formed on the upper portion of the tip structure and on the interlayer insulating film.
The method according to claim 1,
Wherein the tip structure is of a wedge shape having a predetermined length in the first direction and having a triangular cross section cut in the second direction,
Wherein the nanowire is one of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbon.
4. The method according to any one of claims 1 to 3,
Wherein the tip structure has a top end size of 10 nm or less in a cross section cut in the second direction.
A semiconductor substrate;
A plurality of bit lines formed in the first direction on the semiconductor substrate; And
And a plurality of word lines crossing the bit lines and formed in a second direction with the resistance variable layer therebetween on the plurality of bit lines,
Wherein each of the bit lines has a tip structure protruding in an upward direction and is formed of a semiconductor line doped with impurities,
Wherein each word line is formed of a nanowire extending over a tip structure formed in each of the plurality of bit lines.
6. The method of claim 5,
Each of the bit lines is integrally connected to the semiconductor substrate. The semiconductor line is electrically insulated from the neighboring semiconductor substrate by an isolation insulating film. The bit line is etched to have a tip structure protruding vertically. The bit line is doped with impurities to form a lower electrode line.
Between the plurality of bit lines and the resistance variable layer, an interlayer insulating film is formed on the plurality of bit lines so as to surround only the upper portion of the tip structure of each bit line,
Wherein the resistance variable layer is formed on an upper portion of an exposed tip structure of each bit line, the interlayer insulating film, and the isolation insulating film,
Wherein each word line is formed as an upper electrode line extending over a tip structure formed in each of the plurality of bit lines.
The method according to claim 5 or 6,
Wherein the tip structure is of a wedge shape having a predetermined length in the first direction and having a triangular cross section cut in the second direction,
Wherein the nanowire is one of a metal nanowire, a carbon nanotube (CNT), and a graphene nanoribbon.
A first step of etching a semiconductor substrate to project a plurality of semiconductor lines to be formed with a plurality of contact portions and bit lines;
A second step of depositing and etching a first insulating material on the semiconductor substrate to form an isolation insulating film so that the upper portions of the plurality of semiconductor lines are exposed and insulated from each other;
A third step of forming protruding patterns on the plurality of semiconductor lines;
A fourth step of forming a tip structure protruding upward from the upper portion of the portion where each bit line is to be formed by using the protruding pattern;
Implanting ions onto the plurality of semiconductor lines to form a plurality of contacts and bit lines;
Depositing a resistance change material on a substrate including a part of the exposed tip structure of each bit line to form a resistance variable layer and forming a plurality of contact holes to reach the respective contact portions; And
And a seventh step of forming a plurality of word lines with nanowires on the resistance variable layer and forming a plurality of bit line contacts filled in the contact parts of the plurality of word lines and the plurality of contact holes Wherein said method comprises the steps of:
9. The method of claim 8,
The protruding pattern of the third step is formed in a shape of a rectangle,
Wherein each word line of the seventh step is formed to intersect perpendicularly to each bit line having a wedge-shaped tip structure.
9. The method of claim 8,
Depositing a second insulating material on top of the plurality of contacts and the bit lines and the isolation insulator between the fifth step and the sixth step and etching the second insulator and the isolation insulator, Further comprising the step of forming an interlayer insulating film surrounding only the upper portion of the tip structure and surrounded by the second insulating material,
Wherein the second insulating material is the same as the first insulating material,
Depositing the second insulating material, further performing a planarization process, and etching the second insulating material to partially protrude a top portion of the tip structure of each bit line.
9. The method of claim 8,
The word lines in the seventh step are formed by transferring any one of a metal nanowire, a carbon nanotube (CNT) and a graphene nanoribbon to the nanowire Wherein said method comprises the steps of:
The method according to any one of claims 8 to 11,
Wherein the formation of the tip structure in the fourth step forms anisotropic etching of the plurality of semiconductor lines and / or the protruding pattern.
13. The method of claim 12,
Wherein the tip structure has a top end size of 10 nm or less in a cross section perpendicular to the semiconductor lines.
13. The method of claim 12,
Wherein the protruding pattern of the third step is formed of a semiconductor material.
13. The method of claim 12,
Wherein the protruding pattern in the third step is an etch mask.
16. The method of claim 15,
Wherein the etch mask is formed by any one of a photolithography process, a sidewall patterning process, and an e-beam process.

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