KR20180094474A - Magnetic sensor circuit - Google Patents

Abstract

A magnetic sensor circuit comprises: a first hall element outputting a first signal and a second signal; a second hall element outputting a third signal and a fourth signal; a signal switching part, among the first signal, the second signal, the third signal, and the fourth signal, selecting signals in which signal components are in opposite phases to each other when offset components are in phase with each other, selecting signals in which the signal components are in phase with each other when offset components are in opposite phases to each other, and outputting at least two kinds of signals as first output signals; and a signal processing part outputting a second output signal obtained by reducing the offset components of the first output signals by calculating the first output signals selected by the signal switching part. Therefore, the magnetic sensor circuit can reduce noise of flicker noise.

Description

[0001] MAGNETIC SENSOR CIRCUIT [0002]

The present invention relates to a magnetic sensor circuit.

A magnetic sensor circuit is used as a sensor for detecting the open / close state of a folding portable telephone, a notebook computer, or the like, and as a rotational position detecting sensor for a motor.

The magnetic sensor circuit includes a rotation converting element (for example, a Hall element) and a signal processing circuit. This rotation converting element outputs a voltage signal in accordance with the applied magnetic field strength or magnetic flux density. The voltage signal output from the rotation converting element is a signal of a minute voltage. The signal processing circuit amplifies the voltage signal output from the rotation converting element by an amplifier included in the signal processing circuit.

In the voltage signal output from the magnetic sensor circuit, an offset voltage is generated in the rotation converting element and the signal processing circuit. With this offset voltage, a voltage other than zero is output in the magnetic sensor circuit even in a zero magnetic field state in which no magnetic field is applied. In addition, an error is generated in the voltage output from the magnetic sensor circuit by noise. This noise is generated by the above-described offset voltage, flicker noise of a single transistor constituting the circuit, thermal noise of a single transistor or a resistance element.

BACKGROUND ART [0002] A magnetic sensor circuit for reducing the influence of an offset voltage of a rotating conversion element or an amplifier described above is known (see, for example, Patent Document 1). This conventional magnetic sensor circuit is shown in Fig. The magnetic sensor circuit 8100 includes a Hall element 81a, a Hall element 81b, and a signal processing circuit 83. [ The signal processing circuit 83 includes a differential amplifier 84a, a differential amplifier 84b, and a calculator 86. [ The differential amplifier 84a and the differential amplifier 84b operate as a fully differential amplifier. The operator 86 operates as an adder.

The magnetic sensor circuit 8100 supplies signals output from the Hall element 81a to different input terminals of the differential amplifier 84a. The magnetic sensor circuit 8100 outputs signals output from the Hall element 81b to different input terminals of the differential amplifier 84b.

The magnetic sensor circuit 8100 outputs the signal amplified by the differential amplifier 84a and the differential amplifier 84b to the arithmetic unit 86. [ The operator 86 adds the signals output from the differential amplifier 84a and the differential amplifier 84b to reduce the offset voltage included in the signal output from the Hall element 81a and the Hall element 81b.

Japanese Patent Application Laid-Open No. 2014-163692

However, it is preferable that the differential amplifier 84a and the differential amplifier 84b included in the above-described conventional magnetic sensor circuit 8100 are constituted by bipolar transistors. This is because the differential amplifier 84a and the differential amplifier 84b are constituted by a bipolar transistor and a case where they are constituted by a complementary metal oxide semiconductor (CMOS) process, The input offset voltage is high. In addition, when it is constituted by a CMOS process, noise such as flicker noise is generated.

In other words, when the differential amplifier 84a and the differential amplifier 84b are constituted by a CMOS process, since the voltage signal output from the rotational conversion element is a minute voltage, the quality of the signal is reduced due to noise.

An object of the present invention is to provide a magnetic sensor circuit capable of reducing noise such as flicker noise.

In order to solve such a conventional problem, the magnetic sensor circuit of the present invention has the following configuration.

According to one embodiment of the present invention, there is provided a magnetic sensor circuit for outputting a signal according to a magnetic field intensity applied to a Hall element, the magnetic sensor circuit comprising: a first signal which is two kinds of signals whose signal components are in opposite phases, A first Hall element for outputting a signal of a first phase and a second phase for outputting a signal of the first phase, A third signal having an offset component of an opposite phase to the offset component of the signal and a third signal having a signal component in phase with the signal component of the second signal and having an offset component opposite in phase to the offset component of the second signal, When the offset component of the first signal, the second signal, the third signal, and the fourth signal is in phase with each other, the signal component This And a signal switching unit for selecting a signal whose signal components are in phase with each other and selecting at least two signals of different types as first output signals when the offset components are in opposite phases to each other, And a signal processing section for outputting a second output signal obtained by reducing the offset component of the first output signals by calculating the first output signals selected by the signal switching section.

The magnetic sensor circuit according to an embodiment of the present invention further includes a second signal switching section for switching the output destination of the second output signal in accordance with the type of the signal to be switched by the signal switching section.

In the magnetic sensor circuit according to an embodiment of the present invention, the first Hall element, the second Hall element, the signal switching section, the signal processing section, and the second signal switching section may be the same semiconductor Is formed on the substrate.

According to the present invention, it is possible to provide a magnetic sensor circuit capable of reducing noise such as flicker noise.

1 is a circuit diagram of a magnetic sensor circuit according to the first embodiment.
2 is a time chart showing a circuit operation of the differential amplifier according to the first embodiment.
3 is a circuit diagram of the magnetic sensor circuit according to the second embodiment.
4 is a time chart showing the circuit operation of the differential amplifier according to the second embodiment.
5 is a time chart showing a circuit operation of the differential amplifier according to the second embodiment.
6 is a circuit diagram of the magnetic sensor circuit according to the third embodiment.
7 is a time chart showing a circuit operation of the differential amplifier according to the third embodiment.
8 is a circuit diagram of a conventional magnetic sensor circuit.

Hereinafter, this embodiment will be described with reference to the drawings.

[First Embodiment] Fig.

The configuration of the magnetic sensor circuit according to the first embodiment will be described with reference to Fig.

1 is a circuit diagram of a magnetic sensor circuit according to the first embodiment.

The magnetic sensor circuit 100 according to the first embodiment includes a Hall element 1a as a rotational conversion element, a Hall element 1b, a first switch circuit 2, a signal processing circuit 3, Respectively. The Hall element 1a is an example of a first Hall element. The Hall element 1b is an example of a second Hall element. The Hall element 1a has a terminal A, a terminal B, a terminal C and a terminal D. The Hall element 1b has a terminal E, a terminal F, a terminal G and a terminal H. The first switch circuit 2 includes a first switch 2a and a first switch 2b. The first switch circuit 2 is an example of a signal switching section. The signal processing circuit 3 includes a differential amplifier 4 and a second switch circuit 5. [ The signal processing circuit 3 is an example of a signal processing unit. The differential amplifier 4 has an input terminal V5, an input terminal V6, an output terminal VO3, and an output terminal VO4. The second switch circuit 5 includes a second switch 5a, a second switch 5b, a second switch 5c and a second switch 5d. The second switch circuit 5 is an example of the second signal switching section.

The Hall element 1a and the Hall element 1b are arranged close to each other. A straight line connecting the terminal A and the terminal C of the hall element 1a and a straight line connecting the terminal E and the terminal G of the hall element 1b are arranged at substantially parallel angular positions . A straight line connecting the terminal B and the terminal D of the hall element 1a and a straight line connecting the terminal F and the terminal H of the hall element 1b are arranged at positions substantially parallel to each other . When two Hall elements are arranged as described above, the magnetic field strength or the magnetic flux density applied to the two Hall elements can be made equal. This makes it possible to make the voltages of the voltage signals output from the two Hall elements equal in magnitude.

A power supply voltage is supplied to the terminal A of the Hall element 1a. A ground voltage is supplied to the terminal C of the Hall element 1a.

A power supply voltage is supplied to the terminal H of the Hall element 1b. A ground voltage is supplied to the terminal F of the Hall element 1b.

The first switch 2a has an input terminal V1, an input terminal V2, and an output terminal VO1. The input terminal V1 is connected to the terminal B of the Hall element 1a. The input terminal V2 is connected to the terminal D of the Hall element 1a. The output terminal VO1 is connected to the input terminal V5 of the differential amplifier 4. [

The first switch 2b includes an input terminal V3, an input terminal V4, and an output terminal VO2. The input terminal V3 is connected to the terminal E of the Hall element Ib. The input terminal V4 is connected to the terminal G of the Hall element 1b. And the output terminal VO2 is connected to the input terminal V6 of the differential amplifier 4. [

The second switch circuit 5 has an input terminal V7, an input terminal V8, an output terminal VO5, and an output terminal VO6.

The input terminal V7 is connected to the second switch 5a and the second switch 5c. The second switch 5a is connected to the output terminal VO5. And the second switch 5c is connected to the output terminal VO6.

The input terminal V8 is connected to the second switch 5b and the second switch 5d. And the second switch 5b is connected to the output terminal VO5. The second switch 5d is connected to the output terminal VO6.

[Outline of Operation of the Magnetic Sensor Circuit 100]

Next, the operation of the magnetic sensor circuit 100 of the present embodiment will be described.

The magnetic sensor circuit 100 outputs a signal in accordance with the magnetic field intensity or the magnetic flux density applied to the Hall element 1a and the Hall element 1b.

The Hall element 1a and the Hall element 1b output a voltage signal according to the applied magnetic field strength or magnetic flux density as a Hall element signal. The voltage of the Hall element signal includes a voltage indicating a signal component and an offset voltage indicating an offset component.

Here, the Hall element signals output from the Hall element 1a and the Hall element 1b will be described. The Hall element signals outputted from the Hall element 1a and the Hall element 1b are expressed by the equations (1) to (4). Vsig included in equations (1) to (4) represents the voltage of the signal component output from the Hall element 1a and Hall element 1b. Vos included in the expressions (1) to (4) represents the voltage of the offset component output from the Hall element 1a and Hall element 1b.

(1) shows the Hall element signal V _T2 output from the terminal B of the Hall element 1a. Here, the Hall element signal V _T2 is an example of the first signal.

[Equation 1]

(2) shows the Hall element signal V _T4 output from the terminal D of the Hall element 1a. Here, the Hall element signal V _T4 is an example of the second signal.

&Quot; (2) "

That is, the Hall element 1a outputs the first signal and the second signal, which are two types of signals whose signal components are in opposite phases and whose offset components are in opposite phases to each other.

(3) shows the Hall element signal (V _T1 ) output from the terminal E of the Hall element 1b. Here, the Hall element signal (V _T1 ) is an example of the third signal. The Hall element signals (V _T1) has a signal component of a signal component in phase with the signal of the Hall element (V _T2) further has an offset component and the negative sequence component of the offset of the Hall element signals (V _T2).

&Quot; (3) "

(4) shows the Hall element signal V _T3 output from the terminal G of the Hall element 1b. Here, the Hall element signal V _T3 is an example of the fourth signal. The Hall element signals (V _T3) has a signal component of a signal component in phase with the signal of the Hall element (V _T4) also has an offset component and the negative sequence component of the offset of the Hall element signals (V _T4).

&Quot; (4) "

That is, the Hall element 1b outputs the third signal and the fourth signal, which are two types of signals whose signal components are in opposite phases and whose offset components are in opposite phases to each other.

Next, the first switch circuit 2 will be described.

The first switch circuit 2 includes at least two different types of signals among the Hall element signal V _T1 , the Hall element signal V _T2 , the Hall element signal V _T3 and the Hall element signal V _T4 , As a first output signal. The output terminal VO1 of the first switch circuit 2 outputs the selected Hall element signal as the signal S1. The output terminal VO2 of the first switch circuit 2 outputs the selected Hall element signal as a signal S2. The first output signal is a signal S1 and a signal S2 output from the first switch circuit 2. [ Specifically, when the offset components are in phase with each other, the first switch circuit 2 selects a signal whose signal components are opposite to each other. In addition, when the offset components are in phase with each other, the first switch circuit 2 selects a signal whose signal components are in phase with each other.

More specifically, when the first switch 2a selects the Hall element signal V _T2 , the first switch 2b selects the Hall element signal V _T3 . The state in which the first switch 2a selects the Hall element signal V _T2 and the first switch 2b selects the Hall element signal V _T3 is also described as the first phase.

When the first switch 2a selects the Hall element signal V _T4 , the first switch 2b selects the Hall element signal V _T1 . The state in which the first switch 2a selects the Hall element signal V _T4 and the first switch 2b selects the Hall element signal V _T1 is also described as the second phase.

In this example, the first switch circuit 2 switches between the first phase and the second phase in accordance with a signal from an oscillator (not shown). This oscillator outputs a signal of a frequency of several hundreds (kHz). The frequency of the signal output by the oscillator is also referred to as the clock frequency. The first switch circuit (2) alternates between the first phase and the second phase in accordance with the clock frequency.

The signal processing circuit 3 outputs a second output signal in which the offset component of the first output signals is reduced by calculating the first output signals selected by the first switch circuit 2. [ Specifically, the differential amplifier 4 calculates the difference between the signal S1 supplied to the input terminal V5 and the signal S2 supplied to the input terminal V6. The differential amplifier 4 outputs the signal S3 from the output terminal VO3. The differential amplifier 4 outputs the signal S4 from the output terminal VO4. These signals S3 and S4 are differential signals. The second output signal includes the signal S3 and the signal S4.

2 is a time chart showing the circuit operation of the differential amplifier 4 according to the first embodiment. An example of a first output signal supplied to the differential amplifier 4 and a second output signal outputted from the differential amplifier 4 will be described with reference to Fig.

Fig. 2 (A) shows a time chart of the signal S1 supplied to the input terminal V5. Fig. 2 (B) shows a time chart of the signal S2 supplied to the input terminal V6. Fig. 2 (C) shows a time chart of the signal S3 output from the output terminal VO3.

2 (A) to 2 (C), in the first phase P1, the Hall element signal V _T2 shown in equation (1) is inputted to the input terminal V5, The Hall element signal V _T3 shown in the equation (4) is supplied. The differential amplifier 4 subtracts the Hall element signal V _T3 from the Hall element signal V _T2 . More specifically, the differential amplifier 4 inverts the phase of the Hall element signal V _T3 . The differential amplifier 4 adds the inverted Hall element signal V _T3 and the Hall element signal V _T2 . The differential amplifier 4 outputs the subtracted voltage signal from the output terminal VO3 as the signal S3.

In the second phase P2, the Hall element signal V _T4 shown in Expression (2) is inputted to the input terminal V5 and the Hall element signal V (4) shown in Expression (3) _T1 . The differential amplifier 4 subtracts the Hall element signal V _T1 from the Hall element signal V _T4 . Specifically, the differential amplifier 4 inverts the phase of the Hall element signal V _T1 . The differential amplifier 4 adds the inverted Hall element signal V _T1 and the Hall element signal V _T4 . The differential amplifier 4 outputs the subtracted voltage signal as the signal S3 from the output terminal VO3.

The output terminal VO4 outputs, as the signal S4, a signal whose voltage is opposite in phase to the voltage signal output from the output terminal VO3.

The differential amplifier 4 outputs the signal S3 having the voltage + Aop × Vsig / 2 from the output terminal VO3 when the first switch circuit 2 is the first phase P1, And outputs a signal S4 having a voltage of -Aop x Vsig / 2 from the VO4. Here, Aop is the amplification factor of the differential amplifier 4. When the first switch circuit 2 is the second phase P2, the differential amplifier 4 outputs a signal S3 having a voltage of -Aop x Vsig / 2 from the output terminal VO3 , And outputs a signal S4 whose voltage is + Aop x Vsig / 2 from the output terminal VO4.

The signal S3 output from the output terminal VO3 is a signal in which the offset component Vos is reduced. The signal S4 output from the output terminal VO4 is a signal in which the offset component Vos is reduced.

Next, the circuit operation of the second switch circuit 5 will be described. The second switch circuit 5 outputs the signal S3 supplied from the input terminal V7 and the output destination of the signal S4 supplied from the input terminal V8 to the first switch circuit 2 Switch according to the type of signal to be switched. Specifically, the second switch circuit 5 switches the signal to be output in synchronization with the operation of the first switch circuit 2 to select the signal.

More specifically, when the first switch circuit 2 is the first phase P1, the second switch circuit 5 is connected to the second switch 5a and the second switch 5d Thereby establishing conduction. The second switch circuit 5 makes the second switch 5b and the second switch 5c non-conductive. In this case, the signal S3 supplied from the input terminal V7 is outputted from the output terminal VO5. Further, a signal S4 supplied from the input terminal V8 is outputted from the output terminal VO6.

When the first switch circuit 2 is the second phase P2, the second switch circuit 5 turns the second switch 5b and the second switch 5c into a conductive state do. The second switch circuit 5 brings the second switch 5a and the second switch 5d into a non-conductive state. In this case, the signal S4 supplied from the input terminal V8 is outputted from the output terminal VO5. The signal S3 supplied from the input terminal V7 is output from the output terminal VO6.

The above-described second switch circuit 5 is not essential. The second switch circuit 5 is a circuit for returning the frequency of the amplified voltage signal outputted from the differential amplifier 4 to the frequency of the original voltage signal. The voltage signal after the amplification is a signal having a higher voltage than the minute voltage signal supplied from the Hall element 1a and Hall element 1b. The voltage signal after the amplification is less susceptible to noise when compared with the voltage signal before amplification. Since the voltage signal after the amplification is hardly affected by noise, various signal processing can be performed.

To summarize the above, the magnetic sensor circuit 100 according to the first embodiment has a chopping circuit composed of a Hall element 1a, a Hall element 1b, and a first switch circuit 2 . The first switch circuit 2 selects a Hall element signal of a combination in which the offset component is reduced. The differential amplifier 4 reduces the offset component, which is the noise generated from the Hall element, by calculating the Hall element signals selected by the first switch circuit 2. [ The chopping circuit modulates the frequency range of the Hall element signal selected by the first switch circuit 2 to the clock frequency range in which the Hall element signal selected by the first switch circuit 2 is switched. The frequency of the flicker noise is the noise of the low frequency water. Flicker noise can be removed by removing the noise in this low frequency water area. That is, the flicker noise generated from the differential amplifier 4 can be removed by the above-described chopping circuit and a post-filter (not shown). Therefore, it is possible to provide the magnetic sensor circuit 100 capable of reducing noise such as flicker noise.

Also, the first switch circuit 2 can use a switch smaller than the switch circuit used in the spinning current of the prior art. Spinning current is a technique for reducing an offset component generated from a Hall element by switching a terminal of a power source supplied to a Hall element and a terminal for taking out a Hall element signal output from the Hall element. The switch for switching the terminal of the power source supplied to the Hall element is larger than the first switch circuit 2 for switching the Hall element signal. Further, when the switching noise generated by switching the terminal of the power source is compared with the switching noise generated by switching the Hall element signal, the noise generating the switching noise for switching the Hall element signal is small. As a result, the first switch circuit 2 can use a switch smaller than the switch circuit used for the spinning current. Further, the first switch circuit 2 can reduce the switching noise compared with the switch circuit used for spinning current.

In the above description, the case where the differential amplifier 4 is a subtracter has been described, but the present invention is not limited to this. The differential amplifier 4 may also be added. When the differential amplifier 4 is an adder, the first switch circuit 2 selects a signal whose signal component is in phase and whose offset component is in opposite phase. For example, the first switch circuit 2 selects the above-described Hall element signal V _T2 and Hall element signal V _T1 as the first phase. The first switch circuit 2 selects the above-described Hall element signal V _T4 and Hall element signal V _T3 as the second phase.

The Hall element 1a, the Hall element 1b, the first switch circuit 2, the differential amplifier 4 and the second switch circuit 5 may be formed on the same semiconductor substrate . In this case, the semiconductor substrate can be manufactured by a CMOS process. The differential amplifiers 84a and 84b of the prior art preferably use a bipolar transistor that does not generate flicker noise. This is because the offset component and the flicker noise generated in the CMOS device are reduced. However, in the case of constituting by the bipolar transistor, the process cost of the semiconductor substrate is higher than that of the CMOS, and the size of the semiconductor substrate is large. That is, the magnetic sensor circuit 100 is provided with the chopping circuit so that the frequency component of the flicker noise generated in the differential amplifier 4 can be separated from the Hall element signal. By manufacturing the magnetic sensor circuit 100 by the CMOS process, Can be made smaller.

[Second Embodiment]

Up to this point, a configuration in which a differential amplifier with one signal processing circuit is provided has been described.

Next, with reference to Fig. 3 which is a circuit diagram of a magnetic sensor circuit according to a second embodiment of the present invention, a configuration including a differential amplifier with two signal processing circuits will be described. The same components and operations as those of the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

The magnetic sensor circuit 3100 according to the second embodiment includes a Hall element 1a as a rotational conversion element, a Hall element 1b, a first switch circuit 32, a signal processing circuit 33, Respectively. The first switch circuit 32 includes a first switch 32a, a first switch 32b, a first switch 32c, and a first switch 32d. The signal processing circuit 33 includes a differential amplifier 34a, a differential amplifier 34b, a subtracter 36 and a second switch circuit 35. [

The differential amplifier 34a has an input terminal V39, an input terminal V40, an output terminal VO35, and an output terminal VO36.

The differential amplifier 34b has an input terminal V41, an input terminal V42, an output terminal VO37, and an output terminal VO38.

The subtracter 36 has an input terminal V43, an input terminal V44, an input terminal V45, an input terminal V46, an output terminal VO39, and an output terminal VO40. The subtractor 36 is an example of an arithmetic unit used for the calculation of the first output signals.

The second switch circuit 35 has an input terminal V47, an input terminal V48, an output terminal VO41, and an output terminal VO42.

The first switch 32a includes an input terminal V31, an input terminal V32, and an output terminal VO31. The input terminal V31 is connected to the terminal B of the Hall element 1a. The input terminal V32 is connected to the terminal D of the Hall element 1a. The output terminal VO31 is connected to the input terminal V39 of the differential amplifier 34a.

The first switch 32b has an input terminal V33, an input terminal V34 and an output terminal VO32. The input terminal V33 is connected to the terminal E of the Hall element 1b. The input terminal V34 is connected to the terminal G of the Hall element 1b. And the output terminal VO32 is connected to the input terminal V40 of the differential amplifier 34a.

The first switch 32c includes an input terminal V35, an input terminal V36, and an output terminal VO33. The input terminal V35 is connected to the terminal B of the Hall element 1a. The input terminal V36 is connected to the terminal D of the Hall element 1a. The output terminal VO33 is connected to the input terminal V41 of the differential amplifier 34b.

The first switch 32d includes an input terminal V37, an input terminal V38, and an output terminal VO34. The input terminal V37 is connected to the terminal E of the Hall element 1b. The input terminal V38 is connected to the terminal G of the Hall element 1b. The output terminal VO34 is connected to the input terminal V42 of the differential amplifier 34b.

The output terminal VO35 of the differential amplifier 34a is connected to the input terminal V43 of the subtractor 36. [ The output terminal VO36 of the differential amplifier 34a is connected to the input terminal V44 of the subtracter 36. [

The output terminal VO37 of the differential amplifier 34b is connected to the input terminal V45 of the subtractor 36. [ The output terminal VO38 of the differential amplifier 34b is connected to the input terminal V46 of the subtractor 36. [

The output terminal VO39 of the subtractor 36 is connected to the input terminal V47 of the second switch circuit 35. [

The output terminal VO40 of the subtractor 36 is connected to the input terminal V48 of the second switch circuit 35. [

The input terminal V47 of the second switch circuit 35 is connected to the second switch 35a and the second switch 35c. The second switch 35a is connected to the output terminal VO41. The second switch 35c is connected to the output terminal VO42.

The input terminal V48 is connected to the second switch 35b and the second switch 35d. And the second switch 35b is connected to the output terminal VO41. And the second switch 35d is connected to the output terminal VO42.

[Outline of Operation of the Magnetic Sensor Circuit 3100]

Next, the operation of the magnetic sensor circuit 3100 will be described.

The first switch circuit 32 selects the Hall element signal supplied from the Hall element 1a and the Hall element 1b. The first switch 32a outputs the selected Hall element signal as a signal S31. The first switch 32b outputs the selected Hall element signal as a signal S32. The first switch 32c outputs the selected Hall element signal as the signal S33. The first switch 32d outputs the selected Hall element signal as a signal S34. The first output signal of the present embodiment includes the signal S31, the signal S32, the signal S33, and the signal S34.

The first switch circuit 32 alternately switches between the first state and the second state, as in the first embodiment.

The case where the first switch circuit 32 is the first phase will be described.

The first switch 32a selects the Hall element signal V _T2 supplied to the input terminal V31. The first switch 32b selects the Hall element signal V _T3 supplied to the input terminal V34. The first switch 32c selects the Hall element signal V _T4 supplied to the input terminal V36. The first switch 32d selects the Hall element signal V _T1 supplied to the input terminal V37.

Next, the case where the first switch circuit 32 is the second phase will be described.

The first switch 32a selects the Hall element signal V _T4 supplied to the input terminal V32. The first switch 32b selects the Hall element signal V _T1 supplied to the input terminal V33. The first switch 32c selects the Hall element signal V _T2 supplied to the input terminal V35. The first switch 32d selects the Hall element signal V _T3 supplied to the input terminal V38.

The differential amplifier 34a calculates the difference between the voltage signals supplied to the input terminal V39 and the input terminal V40. The differential amplifier 34a outputs the differential signal which is the calculated voltage signal from the output terminal VO35 and the output terminal VO36.

The differential amplifier 34b calculates the difference between the voltage signals supplied to the input terminal V41 and the input terminal V42. The differential amplifier 34b outputs a differential signal which is a calculated voltage signal from the output terminal VO37 and the output terminal VO38.

4 is a time chart showing the circuit operation of the differential amplifier 34a according to the second embodiment. An example of a first output signal supplied to the differential amplifier 34a and a differential signal outputted from the differential amplifier 34a will be described with reference to Fig.

Fig. 4 (A) shows a time chart of the signal S31 supplied to the input terminal V39. Fig. 4B shows a time chart of the signal S32 supplied to the input terminal V40. Fig. 4 (C) shows a time chart of the signal S35 output from the output terminal VO35.

4 (A) to 4 (C), in the first phase P1, the Hall element signal V _T2 shown in equation (1) is inputted to the input terminal V39, The Hall element signal V _T3 shown in the equation (4) is supplied. The differential amplifier 34a subtracts the Hall element signal V _T3 from the Hall element signal V _T2 . The differential amplifier 34a outputs the subtracted voltage signal as the signal S35 from the output terminal VO35. Specifically, the differential amplifier 34a inverts the phase of the Hall element signal V _T3 . The differential amplifier 34a adds the inverted Hall element signal V _T3 and the Hall element signal V _T2 .

In the second phase P2, the Hall element signal V _T4 shown in Expression (2) is inputted to the input terminal V39 and the Hall element signal V _T1 shown in Expression (3) is inputted to the input terminal V40. Is supplied. The differential amplifier 34a subtracts the Hall element signal V _T1 from the Hall element signal V _T4 . The differential amplifier 34a outputs the subtracted voltage signal as a signal S35 from the output terminal VO35. More specifically, the differential amplifier 34a inverts the phase of the Hall element signal V _T1 . The differential amplifier 34a adds the inverted Hall element signal V _T1 and the Hall element signal V _T4 .

The output terminal VO36 outputs a signal having a voltage opposite in phase to the voltage signal output to the output terminal VO35 as the signal S36. In this example, the differential amplifier 34a outputs a signal S35 whose voltage is + Aop x Vsig / 2 from the output terminal VO35 when the first switch circuit 32 is the first phase, And outputs a signal S36 whose voltage is -Aop x Vsig / 2 from the VO36. The differential amplifier 34a outputs the signal S35 whose voltage is -Aop x Vsig / 2 from the output terminal VO35 when the first switch circuit 32 is the second phase, And outputs a signal S36 whose voltage is + Aop x Vsig / 2. Here, Aop is the amplification factor of the differential amplifier 34a.

5 is a time chart showing the circuit operation of the differential amplifier 34b according to the second embodiment. An example of a first output signal supplied to the differential amplifier 34b and a differential signal outputted from the differential amplifier 34b will be described with reference to Fig.

Fig. 5 (A) shows a time chart of the signal S33 supplied to the input terminal V41. Fig. 5B shows a time chart of the signal S34 supplied to the input terminal V42. FIG. 5C shows a time chart of the signal S37 output from the output terminal VO37.

5A to 5C, in the first phase P1, the Hall element signal V _T4 shown in equation (2) is inputted to the input terminal V41 and the Hall element signal V _T4 shown in the equation ) Is supplied with the Hall element signal (V _T1 ) shown in Expression (3). The differential amplifier 34b subtracts the Hall element signal V _T1 from the Hall element signal V _T4 . The differential amplifier 34b outputs the subtracted voltage signal as the signal S37 from the output terminal VO37. More specifically, the differential amplifier 34b inverts the phase of the Hall element signal V _T1 . The differential amplifier 34b adds the inverted Hall element signal V _T1 and the Hall element signal V _T4 .

In the second phase P2, the Hall element signal V _T2 shown in equation (1) is inputted to the input terminal V41 and the Hall element signal V (V) shown in the equation (4) _T3 ) are supplied. The differential amplifier 34b subtracts the Hall element signal V _T3 from the Hall element signal V _T2 . The differential amplifier 34b outputs the subtracted voltage signal from the output terminal VO37 as the signal S37. More specifically, the differential amplifier 34b inverts the phase of the Hall element signal V _T3 . The differential amplifier 34b adds the inverted Hall element signal V _T3 and the Hall element signal V _T2 .

The output terminal VO38 outputs a signal having a voltage opposite in phase to the voltage signal output to the output terminal VO37 as a signal S38. In this example, when the first switch circuit 32 is the first phase P1, the differential amplifier 34b outputs a signal S37 whose voltage is -Aop x Vsig / 2 from the output terminal VO37 And outputs a signal S38 whose voltage is + Aop x Vsig / 2 from the output terminal VO38. The differential amplifier 34b outputs the signal S37 whose voltage is + Aop x Vsig / 2 from the output terminal VO37 when the first switch circuit 32 is the second phase P2, And outputs a signal S38 whose voltage is -Aop x Vsig / 2 from the signal VO38. Here, Aop is the amplification factor of the differential amplifier 34b.

Next, the operation of the subtracter 36 will be described. The subtracter 36 subtracts the signal S35 supplied from the input terminal V43 and the signal S37 supplied from the input terminal V45. The signal S35 supplied from the input terminal V43 and the signal S37 supplied from the input terminal V45 are signals of opposite phases.

The subtractor 36 subtracts the signal S36 supplied from the input terminal V44 and the signal S38 supplied from the input terminal V46. The signal S36 supplied from the input terminal V44 and the signal S38 supplied from the input terminal V46 are signals of opposite phases.

That is, the subtracter 36 outputs a signal emphasizing the signal component. The signal S39 and the signal S40 output from the subtracter 36 are an example of the second output signal.

Next, the circuit operation of the second switch circuit 35 will be described. The second switch circuit 35 switches the output destination of the signal S39 supplied from the input terminal V47 and the signal S40 supplied from the input terminal V48 to the first switch circuit 32 Switch according to the type of signal to be switched. Specifically, the second switch circuit 35 switches the signal to be output in synchronization with the operation of the first switch circuit 32 to select the signal.

More specifically, when the first switch circuit 32 is the first phase P1, the second switch circuit 35 turns on the second switch 35a and the second switch 35d Thereby establishing conduction. The second switch circuit 35 brings the second switch 35b and the second switch 35c into a non-conductive state. In this case, the signal S39 supplied from the input terminal V47 is outputted from the output terminal VO41. The signal S40 supplied from the input terminal V48 is output from the output terminal VO42.

When the first switch circuit 32 is the second phase P2, the second switch circuit 35 turns the second switch 5b and the second switch 5c into a conductive state do. The second switch circuit 35 brings the second switch 5a and the second switch 5d into a non-conductive state. In this case, the signal S40 supplied from the input terminal V48 is outputted from the output terminal VO41. Further, a signal S39 supplied from the input terminal V47 is outputted from the output terminal VO42.

[Third Embodiment]

6 is a circuit diagram of the magnetic sensor circuit according to the third embodiment.

Referring to Fig. 6 and Fig. 7, a circuit in the case where the signal processing circuit includes an adder will be described. The same components and operations as those of the first and second embodiments are denoted by the same reference numerals and the description thereof is omitted.

The magnetic sensor circuit 6100 and the magnetic sensor circuit 3100 described above are connected differently in connection with a part of the first switch circuit 32 and the Hall element 1a and Hall element 1b indicated by the broken line WM . The signal processing circuit 63 included in the magnetic sensor circuit 6100 is provided with an adder 66. The adder 66 adds the signals supplied from the differential amplifier 34a and the differential amplifier 34b, respectively.

The input terminal V35 of the first switch 32c is connected to the terminal G of the Hall element 1b. The input terminal V36 of the first switch 32c is connected to the terminal E of the Hall element 1b.

The input terminal V37 of the first switch 32d is connected to the terminal D of the Hall element 1a. The input terminal V38 of the first switch 32d is connected to the terminal B of the Hall element 1a.

The adder 66 has an input terminal V61, an input terminal V62, an input terminal V63, an input terminal V64, an output terminal VO61, and an output terminal VO62.

The output terminal VO35 of the differential amplifier 34a is connected to the input terminal V61 of the adder 66. [ The output terminal VO36 of the differential amplifier 34a is connected to the input terminal V62 of the adder 66. [

The output terminal VO37 of the differential amplifier 34b is connected to the input terminal V63 of the adder 66. [ The output terminal VO38 of the differential amplifier 34b is connected to the input terminal V64 of the adder 66. [

The output terminal VO61 of the adder 66 is connected to the input terminal V47 of the second switch circuit 35. [

The output terminal VO62 of the adder 66 is connected to the input terminal V48 of the second switch circuit 35. [

[Outline of Operation of the Magnetic Sensor Circuit 6100]

Next, the operation of the magnetic sensor circuit 6100 will be described.

The case where the first switch circuit 32 is the first phase will be described.

The first switch 32c selects the Hall element signal V _T1 supplied from the input terminal V36. The first switch 32d selects the Hall element signal V _T4 supplied from the input terminal V37.

Next, the case where the first switch circuit 32 is the second phase will be described.

The first switch 32c selects the Hall element signal V _T3 supplied from the input terminal V35. The first switch 32d selects the Hall element signal V _T2 supplied from the input terminal V38.

7 is a time chart showing the circuit operation of the differential amplifier 34b according to the third embodiment. An example of a first output signal supplied to the differential amplifier 34b and a differential signal outputted from the differential amplifier 34b will be described with reference to Fig. The signals input to and output from the differential amplifier 34a are the same as those shown in Fig.

Fig. 7 (A) shows a time chart of a Hall element signal supplied to the input terminal V41. Fig. 7B shows a time chart of the Hall element signal supplied to the input terminal V42. Fig. 7 (C) shows a time chart of the voltage signal output from the output terminal VO37.

As shown in Figs. 7A to 7C, in the first phase P1, the Hall element signal (V _T1 ) shown in Formula (3) is inputted to the input terminal V41, and the Hall element signal ) Is supplied with the Hall element signal V _T4 shown in Expression (2). The differential amplifier 34b subtracts the Hall element signal V _T4 from the Hall element signal V _T1 . The differential amplifier 34b outputs the subtracted voltage signal as the signal S37 from the output terminal VO37. More specifically, the differential amplifier 34b inverts the phase of the Hall element signal V _T4 . The differential amplifier 34b adds the inverted Hall element signal V _T4 and the Hall element signal V _T1 .

In the second phase P2, the Hall element signal V _T3 shown in Expression (4) is inputted to the input terminal V41 and the Hall element signal V _T3 shown in Expression (1) is inputted to the input terminal V42. V _T2 ) is supplied. The differential amplifier 34b subtracts the Hall element signal V _T3 from the Hall element signal V _T2 . The differential amplifier 34b outputs the subtracted voltage signal as the signal S37 from the output terminal VO37. More specifically, the differential amplifier 34b inverts the phase of the Hall element signal V _T3 . The differential amplifier 34b adds the inverted Hall element signal V _T3 and the Hall element signal V _T2 .

The output terminal VO38 outputs a signal having a voltage opposite in phase to the voltage signal output from the output terminal VO37 as a signal S38. In this example, when the first switch circuit 32 is the first phase P1, the differential amplifier 34b outputs a signal S37 whose voltage is + Aop x Vsig / 2 from the output terminal VO37 And a signal S38 whose voltage is -Aop x Vsig / 2 from the output terminal VO38. The differential amplifier 34b outputs the signal S37 whose voltage is -Aop x Vsig / 2 from the output terminal VO37 when the first switch circuit 32 is the second phase P2, And outputs a signal S38 whose voltage is + Aop x Vsig / 2 from the signal VO38. Here, Aop is the amplification factor of the differential amplifier 34b.

Next, the operation of the adder 66 will be described. The adder 66 adds the signal S35 supplied from the input terminal V61 and the signal S37 supplied from the input terminal V63. The signal S35 supplied from the input terminal V61 and the signal S37 supplied from the input terminal V63 are voltage signals having the same voltage. The adder 66 outputs the added voltage signal from the output terminal VO61 as the signal S61. The signal S61 is supplied to the input terminal V47 of the second switch circuit 35. [

The adder 66 adds the signal S36 supplied from the input terminal V62 and the signal S38 supplied from the input terminal V64. The signal S36 supplied from the input terminal V62 and the signal S38 supplied from the input terminal V64 are voltage signals having the same voltage. The adder 66 outputs the added voltage signal from the output terminal VO62 as the signal S62. The signal S62 is supplied to the input terminal V48 of the second switch circuit 35. [

That is, the adder 66 outputs a signal S61 and a signal S62 which emphasize the signal component. The signals S61 and S62 are examples of the second output signal.

To summarize the above, the magnetic sensor circuit 3100 according to the second embodiment and the magnetic sensor circuit 6100 according to the third embodiment have the Hall element 1a, the Hall element 1b, (32) constitute a chopping circuit. The first switch circuit 32 selects a combination of the Hall element signals in which the offset components are reduced among the four Hall element signals output from the Hall element 1a and the Hall element 1b. The magnetic sensor circuit 3100 and the magnetic sensor circuit 6100 can use all the Hall element signals output from the Hall element. That is, the magnetic sensor circuit 3100 and the magnetic sensor circuit 6100 can increase the utilization efficiency of the electric power used for detecting the magnetic field strength or the magnetic flux density, as compared with the magnetic sensor circuit 100.

While the embodiment of the present invention and its modifications have been described above, these embodiments and modifications are provided by way of example and are not intended to limit the scope of the invention. These embodiments and modifications thereof can be implemented in various other forms, and various omissions, substitutions, and alterations can be made without departing from the gist of the invention. These embodiments and their modifications fall within the scope and spirit of the invention and are included in the scope of the invention as defined in the claims and their equivalents. It is to be noted that the above-described embodiments and modifications thereof can be combined with each other as appropriate.

1a, 1b: Hall element 2, 32: First switch circuit
2a, 2b, 32a, 32b, 32c and 32d:
3, 33, 63: Signal processing circuit 4, 34a, 34b: Differential amplifier
5, 35: second switch circuit
5a, 5b, 5c, 5d, 35a, 35b, 35c and 35d:
36: subtractor 66: adder

Claims (3)

A magnetic sensor circuit for outputting a signal according to a magnetic field intensity applied to a Hall element,
A first Hall element for outputting a first signal and a second signal which are two kinds of signals whose signal components are in opposite phases and whose offset components are opposite to each other,
A second signal having a signal component in phase with the signal component of the first signal and an offset component opposite in phase to the offset component of the first signal, A second Hall element for outputting a fourth signal having a signal component in phase with the signal component of the second signal and an offset component opposite to the offset component of the second signal;
And selects a signal whose phase is opposite to that of the first signal, the second signal, the third signal, and the fourth signal when the offset components are in phase with each other, A signal switching section for selecting a signal whose signal components are in phase with each other and selecting at least two signals different in kind from each other as a first output signal;
And a signal processing section for outputting a second output signal in which the offset components of the first output signals are reduced by calculating the first output signals selected by the signal switching section. The method according to claim 1,
And a second signal switching section for switching the output destination of the second output signal in accordance with the type of the signal to be switched by the signal switching section. The method of claim 2,
Wherein the first Hall element, the second Hall element, the signal switching portion, the signal processing portion, and the second signal switching portion are formed on the same semiconductor substrate.

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