JP5248425B2 - Current switch circuit and digital-analog converter using the same - Google Patents

Description

  The present invention relates to a current switch circuit and a current steering type digital-analog converter using the current switch circuit.

  A switch circuit that obtains an output current by switching an input current is used in, for example, a current steering type digital-analog converter (hereinafter referred to as a current steering DAC), a mixer circuit, or the like. The mixer circuit is a multiplier used for a frequency converter, a modulator, a demodulator, and the like. In such a current switch circuit, noise and distortion called glitch are generally generated due to the parasitic capacitance of the switch during the switching transition period. Since the glitch component appears in the output as harmonic spurious, the spurious free dynamic range (SFDR) is degraded.

  As a technique for reducing such a glitch, Patent Document 1 includes a dummy switch having the same conductivity type as a main switch that performs current switching, and this dummy switch, for example, inverts a clock signal supplied to the main switch. A method is disclosed in which switching is performed by a clock signal and the glitch of the main switch is absorbed using the parasitic capacitance of the dummy switch.

JP 2002-94378 A

  However, the technique described in Patent Document 1 has a problem that glitch mismatch occurs due to different slew rates of complementary clock signals for driving the main switch and the dummy switch, and the glitch cannot be effectively canceled. is there.

  An object of the present invention is to make it possible to effectively reduce glitches particularly in a differential current switch circuit.

  According to an aspect of the present invention, a first input terminal and a second input terminal that respectively receive a first voltage signal and a second voltage signal whose levels change complementarily, a current source that generates an input current, and the first Switching is performed by a first delay signal and a second delay signal obtained by delaying the voltage signal and the second voltage signal or the first voltage signal and the second voltage signal, respectively, and the input current is divided into the first switch current and the second switch current. Generating a first output current and a second output current based on the first switch current and the second switch current, and the first switch current and the second switch during the switching transition period. A common-mode circuit that makes the glitch component generated in each switch current in phase in the first output current and the second output current, and the first output current and the second output current A first output terminal for outputting and second output terminals, and provides a current switch circuit having a.

  According to the present invention, the glitch generated in the transition period of switching between the switch currents output from the two switches is made in phase in the two output currents, so that when the two output currents are observed as differential signals, the glitch component Will be cancelled.

1 is a block diagram showing a current switch circuit according to a first embodiment. The figure explaining the principle of the glitch cancellation in 1st Embodiment A block diagram showing a current switch circuit concerning a 2nd embodiment. Block diagram showing a current switch circuit according to a third embodiment The figure which shows an example of the short circuit in 3rd Embodiment Timing chart showing the operation of the third embodiment The figure which shows the other example of the short circuit in 3rd Embodiment The figure which shows N bit electric current steering DAC which concerns on 4th Embodiment The figure which shows the mixer circuit which concerns on 5th Embodiment A block diagram showing a current switch circuit concerning a 6th embodiment

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a current switch circuit according to a basic first embodiment of the present invention. In FIG. 1, clock signals D and D_, which are first and second voltage signals whose levels change complementarily, are input to first and second input terminals 11 and 12, respectively. The clock signals D and D_ are input to the glitch in-phase circuit 15 and supplied to the gate terminals of the transistors M1 and M2 as the first switch and the second switch of the switch pair 13 through the glitch in-phase circuit 15. . In this example, NMOS transistors are used as the transistors M1 and M2.

  The source terminals of the transistors M1 and M2 are connected in common, and the common source terminal, which is a current input terminal, is connected to the current source 14 that generates the input current Iin. The transistors M1 and M2 switch the input current Iin according to the clock signals D and D_ or a delayed signal (described later) obtained by delaying them, and output the first and second switch currents from the respective drain terminals.

  The drain terminals of the transistors M 1 and M 2 are connected to the glitch in-phase circuit 15. First and second output terminals 16 and 17 are connected to the glitch in-phase circuit 15, and differential first and second output currents Iom and Iop are taken out from these output terminals 16 and 17. The glitch in-phase circuit 15 generates a glitch component (generated during the switching transition period of the transistors M1 and M2) generated in the switch currents output from the drain terminals of the transistors M1 and M2 as the clock signals D and D_ change in level. Functions in phase with the output currents Iom and Iop.

  In general, a differential circuit such as the current switch circuit of FIG. 1 outputs two single-phase signals having opposite phases, that is, differential signals. In this case, if an unnecessary signal (noise, distortion, glitch, etc.) is generated in the differential circuit as an in-phase signal, the unnecessary signal appears in the output single-phase signal, but is unnecessary when viewed as a differential signal. The signal is completely removed. Focusing on this point, in the present embodiment, the glitch components included in the output currents Iom and Iop output from the differential current switch circuit as shown in FIG. Iop) effectively reduces glitches. In other words, instead of performing the cancellation of the glitch component on the two single-phase signals as in the above-mentioned Patent Document 1, the glitch components included in the two single-phase signals are effectively in phase with each other. Cancel glitches in differential signals.

Hereinafter, the operation of the current switch circuit of FIG. 1 will be described with reference to FIGS.
FIG. 2 (a) shows the operation of a conventional general current switch circuit. In the conventional general current switch circuit, the glitch in-phase circuit 15 of FIG. Connected to.

  As shown in FIG. 2A, in the switching transition period T by the clock signals D and D_, charges and channel charges are charged and discharged in the parasitic capacitances (gate-source capacitances) of the transistors M1 and M2. An instantaneous spike-like error current is generated. These error currents are called glitches and generally appear as different values in the output currents Iom and Iop in FIG. 1, and therefore cannot be completely removed even by observing the differential signal Iop-Iom.

  On the other hand, FIG. 2B shows the operation of the current switch circuit of FIG. The glitch in-phase circuit 15 in FIG. 1 operates so that the glitch components are in phase in the output currents Iom and Iop in the switching transition period T of the transistors M1 and M2, and therefore the glitch is canceled when the differential signal Iop-Iom is observed. The

  As described above, according to the current switch circuit of FIG. 1, the glitch generated in the switching transition period is made in phase in the output currents Iom and Iop to the switch current output from the transistors M1 and M2. As a result, when the output currents Iom and Iop are observed as differential signals Iom-Iop, the glitch component is canceled, so that extra components such as distortion and noise due to the glitch can be reduced, and the quality of the output signal can be reduced. Can be improved.

  Next, the current switch circuits according to the second and third embodiments that further embody the glitch in-phase circuit 15 in FIG. 1 will be described.

(Second Embodiment)
FIG. 3 shows a current switch circuit according to the second embodiment of the present invention. The clock signals D and D_ are directly supplied to the gate terminals of the transistors M1 and M2 of the switch pair 13 though they pass through the glitch in-phase circuit 15 in the figure. The glitch in-phase circuit 15 in the present embodiment includes transistors M3 and M4 that are third and fourth switches. In this example, NMOS transistors are used as the transistors M3 and M4.

  The transistors M3 and M4 of the glitch in-phase circuit 15 are duplicates of the transistors M1 and M2 of the switch pair 13 and have the same characteristics as the M1 and M2. The common source terminal that is the current input terminal of the transistors M1 and M2 is connected to the current source 14, whereas the common source terminal that is the current input terminal of the transistors M3 and M4 is not connected to a current source. Is open. The gate terminals of the transistors M3 and M4 are connected to the input terminals 11 and 12, respectively, the drain terminal of the transistor M3 is connected to the output terminal 17, and the drain terminal of the transistor M4 is connected to the output terminal 16.

  The operation of the glitch in-phase circuit 15 in FIG. 3 is as follows. When the clock signal D transitions from a high level (“H”) to a low level (“L”), that is, during the switching transition period of the transistors M1 and M2, a glitch component is generated by the discharge from the parasitic capacitances of the transistors M1 and M2. Is generated, and the current due to the glitch (glitch current) is shunted to the output currents Iom and Iop.

  Now, let the glitch currents shunted to the output currents Iom and Iop due to the discharge from the parasitic capacitance of the transistor M1 be Igm and Igp. Here, in general, Igm ≠ Igp. On the other hand, the same amount of glitch is generated in the transistor M3 as in the transistor M1, and the glitch currents Igp and Igm are shunted to the output currents Iom and Iop, respectively. Therefore, the amount of glitch current at the output terminals 16 and 17 from which the output currents Iom and Iop are output is equal to Igp + Igm, and the glitch is in phase. The glitch generated by the discharge from the parasitic capacitance of the transistor M2 is also in phase with the output currents Iom and Iop. Therefore, when the output currents Iom and Iop are observed as the differential signal Iom-Iop, the glitch component is canceled and the above-described effect can be obtained.

(Third embodiment)
FIG. 4 is a current switch circuit according to the third embodiment of the present invention. The glitch in-phase circuit 15 in the present embodiment is configured to in-phase the glitch in the output currents Iom and Iop by short-circuiting the output terminals 16 and 17 during the transition period of the clock signals D and D_. Specifically, the glitch in-phase circuit 15 includes a short circuit 20 and four delay elements 21 to 24. The short circuit 20 includes, for example, first and second short-circuit switches SW1 and SW2 connected in cascade between the output terminals 16 and 17, as shown in FIG.

The clock signal D is supplied to the short circuit 20 and the delay element 21, and the clock signal D_ is supplied to the short circuit 20 and the delay element 22. The first delay signal (first delay clock signal) D ₁ that is the output of the delay element 21 is supplied to the gate terminal of the transistor M ₁ and the delay element 23, and the second delay signal (second delay clock) that is the output of the delay element 22. The signal D ₁ _ is supplied to the gate of the transistor M 2 and the delay element 24. Further, the third delay signal (second delay clock signal) D ₂ that is the output of the delay element 23 and the fourth delay signal (fourth delay clock signal) D ₂ _ that is the output of the delay element 24 are supplied to the short circuit 20. Supplied.

  Output currents Iom and Iop are output from the drain terminals of the transistors M1 and M2 to the output terminals 16 and 17, respectively. Of the short-circuit switches SW1 and SW2 cascaded between the output terminals 16 and 17, SW1 is controlled by the clock signal D_ or D, and SW2 is controlled by the delayed clock signal D2 or D2_.

FIG. 6 is a diagram showing the timing of each of the clock signals D, D_, D ₁ , D ₁ _ and D ₂ , D ₂ _ shown in FIG. 4, and also shows a control signal A (described later). . The short circuit 20 works so that the output terminals 16 and 17 are short-circuited at the timing of the edges of D (or D_) and D ₂ (or D ₂ _). In the short circuit 20 of FIG. 5, SW1 operates so as to be turned on when D ₁ _ is “H”, or turned on when D is “L”, and SW2 is turned on when D ₂ is “H”. _{2 It} shall operate to turn on when _ is “L”. Needless to say, the arrangement of the switches SW1 and SW2 may be interchanged.

On the other hand, FIG. 7 shows an example in which the short circuit 20 is composed of one short switch SW and two AND gates G1 and G2 connected between the output terminals 16 and 17. AND gate G1 takes the logical product of the clock signal D_ and delayed cardiac signal D _2, pulsed control signals having a slightly longer duration than the transition period of the switching of the transistors M1, M2 as shown in FIG. 6 A is output. With this control signal A, the switch SW is controlled. On the other hand, the AND gate G2 is a dummy gate provided to make the load conditions for the clock signals D and D2_ uniform, and its output terminal is open. With such a configuration, the short-circuit switch SW is turned on for a period slightly longer than the switching transition period of the transistors M1 and M2 driven by the clock signals D ₁ and D ₁ _, and the output terminals 16 and 17 are short-circuited. It acts to make the glitch in phase in the output currents Iom and Iop.

  As described above, in the third embodiment, the output terminals 16 and 17 are short-circuited during the switching transition period in which the glitch occurs, so that the glitch is in phase with the output currents Iom and Iop in the same manner as in the second embodiment, The glitch can be canceled when the currents Iom and Iop are viewed as differential signals.

(Fourth embodiment)
FIG. 8 shows an N (N is an arbitrary integer greater than or equal to 2) bit current steering DAC using the above-described current switch circuit. The DAC shown in FIG. 8 includes N current source cells 31-3N. Each current source cell 31-3N includes a current switch circuit and a latch circuit 41, respectively. The latch circuit 41 latches each bit B <n-1> of the N-bit input digital signal (Data) 40 with the clock CK, and performs complementary digital signal pair (first) corresponding to the clock signals D and D_ described above. 1 and the second voltage signal). The current value of the current source 14 included in the current switch circuit of the current source cell 31-3N is weighted to 2 ^n-1 LSB (least significant bit), (n = 1, 2,..., N), respectively. Yes. That is, the weight of the current value of the current source 14 included in the current switch circuit is 2 LSB in the current source cell 32 and 4 LSB in the current source cell 33, assuming that the current source cell 31 has LSB (least significant bit). The current source cell 34 is set to ⁸ LSB, and similarly, the current source cell 3N is set to 2 ^{N + 1} LSB.

  The output terminals 16 and 17 of the current switch circuit of the current source cell 31-3N are connected to first and second common output terminals 42 and 43, respectively, for extracting an output analog signal. The output current of the glitch in-phase circuit 15 included in the current switch circuit of the current source cell 3n is the output current itself of the current source cell 3n, and is added to the other current source cells, via the common output terminals 42 and 43. It is output as an output analog signal of DAC.

  According to this embodiment, in each current source cell 31-3N, the glitch is in-phased in the output current and canceled in accordance with the operation described in the first to third embodiments, and thus is observed in the output signal of the DAC. The glitch is also canceled. Therefore, an analog signal with reduced distortion due to glitch can be obtained.

(Fifth embodiment)
FIG. 9 shows a single-balance mixer circuit according to the fifth embodiment of the present invention using the current switch circuit shown in FIG. Local signals (local oscillation signals) LO and LO_ are input to the input terminals 11 and 12 (local input terminals) in place of the clock signals D and D_ as first and second voltage signals whose levels change complementarily. The On the other hand, an input current Iin to be multiplied by the local signals LO and LO_ is input from the current source 14. The local signals LO and LO_ are input to the glitch in-phase circuit 15 and supplied to the gate terminals of the transistors M1 and M2 of the switch pair 13 through the glitch in-phase circuit 15. As a result, the input current Iin is distributed to one of the output terminals 16 and 17 according to the local signals LO and LO_.

  In the present embodiment, output currents Iom and Iop corresponding to the multiplication result of the local signals LO and LO_ and the input current Iin are output from the output terminals 16 and 17, respectively. In this case, as described in the first embodiment, the glitch generated during the switching transition period of the transistors M1 and M2 by the local LO and LO_ is made in-phase by the glitch in-phase circuit 15, and the output currents Iom and Iop are changed to be differential. When observed as a signal, it acts to cancel the glitch.

(Sixth embodiment)
In the above embodiments, the case where NMOS transistors are used as the transistors M1 and M2 of the switch pair 13 has been described, but it goes without saying that PMOS transistors may be used as shown in FIG. In that case, for example, PMOS transistors may be used for the transistors M3 and M4 shown in FIG.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  The current switch circuit can be applied to a current steering DAC and a mixer circuit (frequency converter, modulator, demodulator, etc.).

DESCRIPTION OF SYMBOLS 11, 12 ... Input terminal 13 ... Switch pair 14 ... Current source 15 ... Glitch in-phase circuit 16, 17 ... Output terminal 20 ... Short circuit 21-24 ... 1st To fourth delay element 31 to 3N ... current source cell 40 ... input digital signal 41 ... latch circuit 42, 43 ... common output terminal M1-M4 ... transistor (first to fourth switches) )
SW1, SW2, SW ... short-circuit switch G1, G2 ... AND gate

Claims (4)

A first input terminal and a second input terminal that respectively receive a first voltage signal and a second voltage signal whose levels change complementarily;
A current source for generating input current;
The first voltage signal and the second voltage signal or the first voltage signal and the second voltage signal are switched by a first delay signal and a second delay signal, respectively, and the input current is switched to a first switch current and a second switch. A first switch and a second switch for shunting current;
A first output current and a second output current are generated based on the first switch current and the second switch current, and glitch components respectively generated in the first switch current and the second switch current during the switching transition period A common-mode circuit that makes the same phase in one output current and the second output current;
A first output terminal and a second output terminal for outputting the first output current and the second output current;
Comprising
The in-phase circuit is
A third switch and a fourth switch, each having an open common current input terminal, for switching according to the first voltage signal and the second voltage signal to output a third switch current and a fourth switch current;
Generating the first output current by adding the first switch current and the fourth switch current;
A current switch circuit, wherein the second output current is generated by adding the second switch current and the third switch current. A first input terminal and a second input terminal that respectively receive a first voltage signal and a second voltage signal whose levels change complementarily;
A current source for generating input current;
The first voltage signal and the second voltage signal or the first voltage signal and the second voltage signal are switched by a first delay signal and a second delay signal, respectively, and the input current is switched to a first switch current and a second switch. A first switch and a second switch for shunting current;
A first output current and a second output current are generated based on the first switch current and the second switch current, and glitch components respectively generated in the first switch current and the second switch current during the switching transition period A common-mode circuit that makes the same phase in one output current and the second output current;
A first output terminal and a second output terminal for outputting the first output current and the second output current;
Comprising
The in-phase circuit is
A first delay element that delays the first voltage signal and outputs the first delay signal;
A second delay element that delays the second voltage signal and outputs the second delay signal;
A third delay element that delays the first delay signal and outputs a third delay signal;
A fourth delay element that delays the second delay signal and outputs a fourth delay signal;
A first shorting switch that is connected in cascade between the first output terminal and the second output terminal, and is turned on when the second voltage signal is at a high level or when the first voltage signal is at a low level;
A second short-circuit switch that is turned on when the third delay signal is at a high level or when the fourth delay signal is at a low level;
A current switch circuit comprising: A first input terminal and a second input terminal that respectively receive a first voltage signal and a second voltage signal whose levels change complementarily;
A current source for generating input current;
The first voltage signal and the second voltage signal or the first voltage signal and the second voltage signal are switched by a first delay signal and a second delay signal, respectively, and the input current is switched to a first switch current and a second switch. A first switch and a second switch for shunting current;
A first output current and a second output current are generated based on the first switch current and the second switch current, and glitch components respectively generated in the first switch current and the second switch current during the switching transition period A common-mode circuit that makes the same phase in one output current and the second output current;
A first output terminal and a second output terminal for outputting the first output current and the second output current;
Comprising
The in-phase circuit is
A first delay element that delays the first voltage signal and outputs the first delay signal;
A second delay element that delays the second voltage signal and outputs the second delay signal;
A third delay element that delays the first delay signal and outputs a third delay signal;
A fourth delay element that delays the second delay signal and outputs a fourth delay signal;
A first AND gate that performs a logical product of the second voltage signal and the third delay signal and outputs a control signal;
A second AND gate that takes a logical product of the first voltage signal and the fourth delay signal;
A short-circuit switch connected between the first output terminal and the second output terminal and turned on when the control signal is at a high level;
A current switch circuit comprising: The current switch circuit according to any one of claims 1 to 3 and each bit of an input digital signal of N (N is an arbitrary integer greater than or equal to 2) bits are respectively latched, and the first voltage signal and the second voltage are latched. N current source cells each including a latch circuit for generating a signal,
The current value of the current source included in the current switch circuit of the N current source cells is weighted to 2 ⁿ⁻¹ LSB (n = 1, 2,..., N),
The first output terminal and the second output terminal of the current switch circuit of the N current source cells are respectively connected to a first common output terminal and a second common output terminal for extracting an output analog signal. converter.

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