KR20180074237A - Multi-layered printed circuit board - Google Patents

Abstract

Disclosed is a printed circuit board. The printed circuit board according to an aspect of the present invention comprises: a metal layer having a through hole formed therein; an upper conductor pattern layer and a lower conductor pattern layer respectively formed on the metal layer; an upper insulating layer formed between the metal layer and the upper conductor pattern layer; a lower insulating layer formed between the metal layer and the lower conductor pattern layer; and a low melting point metal layer and a high melting point metal layer having a melting point higher than a melting point of the low melting point metal layer.In order to connect the upper conductor pattern layer and the lower conductor pattern layer to each other, the present invention also includes: the upper insulating layer; the lower insulating layer; and a through via formed in the through hole.

Description

[0001] MULTI-LAYERED PRINTED CIRCUIT BOARD [0002]

The present invention relates to a printed circuit board.

Typically, a printed circuit board is produced by sequentially laminating a plurality of buildup layers on a core substrate. The production of the printed circuit board by sequentially stacking the build-up layers can be referred to as a sequential layer construction method.

When a printed circuit board is manufactured by a sequential lamination method, the number of lamination steps increases as the number of printed circuit boards increases. Such a lamination process may cause unnecessary and unpredictable deformation because heat is applied to a portion already existing in the lamination process. The more such deformation, the more difficult the interlayer matching becomes.

Accordingly, a batch lamination method has been developed in which a plurality of unit substrates are collectively laminated at the same time after the respective buildup layers are separated and produced as a unit substrate to produce a printed circuit board.

Korean Patent Publication No. 10- 2011-0066044 (June 16, 2011)

According to the embodiment of the present invention, a printed circuit board capable of preventing warpage can be provided.

1 shows a printed circuit board according to a first embodiment of the present invention.
2 shows a printed circuit board according to a second embodiment of the present invention.
3 shows a printed circuit board according to a third embodiment of the present invention.
4, 5, and 8 to 18 are views sequentially illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention,
FIGS. 4 and 5 are views sequentially illustrating a process of manufacturing a metal unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention,
8 to 13 are views sequentially illustrating a manufacturing process of a general unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention,
14 to 16 are views sequentially illustrating the steps of manufacturing a protective unit substrate to be applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention,
FIGS. 17 and 18 are views showing the lamination of the metal unit substrate, the general unit substrate, and the protective unit substrate manufactured through FIGS. 3, 4, 6 and 8 to 16 collectively.
6 is a view showing a first modification of a metal unit substrate applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention.
7 is a view showing a second modification of a metal unit substrate applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In the specification, "on" means to be located above or below the object portion, and does not necessarily mean that the object is located on the upper side with respect to the gravitational direction.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

The sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to the same or corresponding components, A description thereof will be omitted.

Printed circuit board

(First Example )

1 is a view showing a printed circuit board according to a first embodiment of the present invention.

1, a printed circuit board 1000 according to a first embodiment of the present invention includes a metal layer 510, an upper conductive pattern layer 110, a lower conductive pattern layer 210, an upper insulating layer 120, A lower insulating layer 220 and through vias V1 and may further include a solder resist layer 620. [

The metal layer 510 includes a material having relatively higher rigidity than the material constituting the upper and lower conductor pattern layers 110 and 210 to be described later. By way of example, the metal layer 510 may comprise Invar, which is more rigid than copper (Cu) used to form the conductor pattern of a conventional printed circuit board.

The metal layer 510 may be formed in a three-layer structure including Invar. For example, the metal layer 510 may have a structure in which outer layers 512 and 513 including copper (Cu) are formed on both surfaces of an inner layer 511 including Invar. Alternatively, the metal layer 510 may have a structure in which outer layers 512 and 513 including Invar are formed on both surfaces of the inner layer 511 including copper.

The through hole (H) penetrates the metal layer (510). In the through hole H, a through via V1 to be described later is formed.

The upper and lower conductor pattern layers 110 and 210 are formed on the metal layer 510, respectively. That is, the upper conductor pattern layer 110 is formed on the upper portion of the metal layer 510 and the lower conductor pattern layer 210 is formed on the lower side of the metal layer 510. Each of the upper and lower conductor pattern layers 110 and 210 may include at least one of a signal pattern, a power pattern, a ground pattern, and an external connection terminal of a conventional printed circuit board.

The upper conductor pattern layer 110 and the lower conductor pattern layer 210 are only different in formation position from each other. Therefore, in the following description of the printed circuit board 1000 according to the present embodiment, the conductor pattern layer is generally referred to as a conductor pattern layer except for the case where the upper conductor pattern layer 110 and the lower conductor pattern layer 210 need to be distinguished . 1, the upper conductor pattern layer 110 is referred to as a first conductor pattern layer and the lower conductor pattern layer 210 is referred to as a second conductor pattern layer.

The conductor pattern layers 110 and 210 may be formed of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti) Pt) or the like. The pattern shapes of the first conductor pattern layer 110 and the second conductor pattern layer 210 may be identical to each other, but may be different from each other depending on design requirements.

The upper insulating layer 120 is formed between the metal layer 510 and the first conductive pattern layer 110 and the lower insulating layer 220 is formed between the metal layer 510 and the second conductive pattern layer 210 do.

The upper insulating layer 120 and the lower insulating layer 220 are only different in formation position from each other. Therefore, in the following description of the printed circuit board 1000 according to the present embodiment, the insulating layer will be referred to as an insulating layer except for the case where the upper insulating layer 120 and the lower insulating layer 220 need to be distinguished. 1, the upper insulating layer 120 is referred to as a first insulating layer, and the lower insulating layer 120 is referred to as a second insulating layer. In the following description, only the first insulating layer 120 will be described for convenience of explanation.

The insulating layer 120 may be a photosensitive insulating layer made of a material that reacts with light including a photocurable resin. Or the insulating layer 120 may be formed of a non-photosensitive insulating material such as a prepreg or an Ajinomoto Build-up Film (ABF) which is a typical interlayer insulating material.

The degree of curing of the photosensitive insulating layer 120 can be controlled by light. However, the photosensitive insulating layer 220 is also thermosetting, and the degree of curing can be controlled by heat.

Since the photosensitive insulating layer 120 is capable of a photolithography process, it is more advantageous to realize fine holes than a hole is formed in a non-photosensitive insulating layer such as a prepreg, and a plurality of Holes can be simultaneously formed, so that the hole forming process can be simplified. Further, the photosensitive insulating layer 120 can be formed into various shapes in a hole shape more easily due to the photolithography process. For example, the shape of the vertical cross-section of the hole may be an inverted trapezoid, an orthogonal trapezoid, a rectangle, or the like.

The photosensitive insulating layer 120 may be a positive type or a negative type. In the case of the positive type photosensitive insulating layer 120, the photopolymer polymer bond of the exposed portion is broken. Thereafter, when the developing process is performed, a portion where the photopolymer polymer bond breaks due to light is removed. In the case of the negative type photosensitive insulating layer 220, the exposed portions cause a photopolymerization reaction to form a three-dimensional network structure of a chain structure in a single structure. When a developing process is performed, do.

The photosensitive insulating layer 120 may contain an inorganic filler in the photocurable resin. The inorganic filler improves the rigidity of the photosensitive insulating layer 120 and reduces the thermal expansion coefficient. As the inorganic filler, silica (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), barium sulfate (BaSO ₄ ), talc, clay, mica powder, aluminum hydroxide (AlOH ₃ ), magnesium hydroxide OH) ₂ ), calcium carbonate (CaCO ₃ ), magnesium carbonate (MgCO ₃ ), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO ₃ ), barium titanate (BaTiO ₃ ) and calcium zirconate ₃ ) may be used.

Each of the first insulating layer 120 and the second insulating layer 220 includes a first conductor pattern layer 110 and a second conductor pattern layer 120 together with first and second general unit substrates 100 and 200 ). That is, the first insulating layer 120 is included in the first general unit substrate 100 together with the first conductor pattern layer 110. The first insulating layer 120 and the second insulating layer 220 are formed separately from each other and are stacked at the same time, unlike the sequential layering method.

The through vias V1 are formed in the first insulating layer 120, the second insulating layer 220 and the through holes H so as to connect the first conductor pattern layer 110 and the second conductor pattern layer 120 to each other do. Both ends of the through vias V1 are in contact with the first conductor pattern layer 110 and the second conductor pattern layer 210 to electrically connect the first conductor pattern layer 110 and the second conductor pattern layer 210 to each other Connect.

The through vias (V1) include a refractory metal layer (10) having a melting point higher than the melting point of the low melting point metal layer (20) and the low melting point metal layer (20). 1, the through vias V1 used in the present embodiment are formed of a high melting point metal layer 10 and a high melting point metal layer 10 formed in the first conductor pattern layer 110 and the second conductor pattern layer 210 And a low melting point metal layer (20) interposed between the through holes (H).

The refractory metal layer 10 is made of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), or the like, which has excellent electrical characteristics and has a melting point higher than the melting point of the low melting point metal layer Titanium (Ti), gold (Au), platinum (Pt), or the like. For example, both the refractory metal layer 10 and the conductor pattern layers 110 and 210 may be formed of copper. In this case, since both are formed of the same material, the bonding strength between the refractory metal layer 10 and the conductor pattern layers 110 and 210 is improved. Further, the process can be simplified and the production cost can be reduced as compared with the case where the two materials are formed of different materials. However, the above-mentioned examples are illustrative and the scope of the present invention is not limited thereto.

The melting point of the low melting point metal layer (20) is lower than the melting point of the high melting point metal layer (10). The low melting point metal layer 20 may be made of a solder material. Here, 'solder' means a metal material which can be used for solder, and may be an alloy including lead (Pb), but may not contain lead. For example, the solder may be tin (Sn), silver (Ag), copper (Cu), or an alloy of metals selected therefrom. Specifically, the solder used in the embodiment of the present invention may be an alloy containing tin, silver and copper having a tin (Sn) content of 90% or more with respect to the entire solder.

The low-melting-point metal layer 20 melts at least partly when the unit substrates 100, 200, 500, and 600 to be described later are laminated together to alleviate pressure unevenness between the unit substrates 100, 200, 500, and 600 .

The low-melting-point metal layer 20 is melted at least partially due to the temperature and pressure in the laminating process, so that the low-melting-point metal layer 20 is easily melted by the material constituting the high- melting point metal layer 10 or the conductor pattern layers 110 and 210 You can react. Accordingly, an intermetallic compound (IMC) layer may be formed between the low melting point metal layer 20 and the high melting point metal layer 10 or between the conductor pattern layers 110 and 210. The physical bonding force between the conductor pattern layers 110 and 210 is improved due to the intermetallic compound layer.

The insulating layers 120 and 220 fill the space between the inner wall of the through hole H and the through via V1. As will be described later, the insulating layers 120 and 220 maintain the semi-cured state (B-stage) until collectively laminated. In this embodiment, the diameter of the through hole H is larger than the diameter of the through via V1. Therefore, the insulating layers 120 and 220 fill the space between the inner wall of the through hole H and the through via V1 due to the fluidity of the insulating layers 120 and 220 in the batch lamination.

A solder resist layer 620 is formed on the conductor pattern layers 110 and 210. The solder resist layer 620 includes an electrically insulating material to protect the conductor pattern layers 110 and 210 from the outside and prevent a short circuit. In addition, the solder resist layer 620 may comprise a photosensitive material and may include an inorganic filler depending on the need to adjust the stiffness or thermal expansion coefficient.

The solder resist layer 620 may have openings for opening the external connection terminals out of the conductor pattern layers 110 and 210 to the outside.

(Second Example )

2 is a view showing a printed circuit board according to a second embodiment of the present invention.

2, the printed circuit board 2000 according to the present embodiment includes a metal layer 510, an upper conductive pattern layer 110, a lower conductive pattern layer 210, an upper insulating layer 120, Layer V2, a via hole V1, and an insulating film 520, and may further include a solder resist layer 620. [

Since the printed circuit board 2000 according to the present embodiment differs from the printed circuit board 1000 according to the first embodiment of the present invention in the insulating film 520 and the through vias V1, The insulating film 520 and the through vias V1 applied to the present embodiment will be mainly described.

The insulating film 520 is formed between the inner wall of the through hole H and the through via V1. More specifically, the insulating film 520 is formed on the surface of the metal layer 510 including the inner wall of the through hole H. [ The insulating layer 520 is formed on the surface of the metal layer 510 made of an electrically conductive material to prevent a short between the metal layer 510 and the conductor pattern layers 110 and 210.

The insulating layer 520 may be formed by depositing an insulating material such as ferrolein on the metal layer 510, but is not limited thereto.

The insulating film 520 is formed to have a very thin thickness so that a conductor pillar 30 to be described later is formed in the through hole H. [ Since the insulating film 520 is formed on the inner wall of the through hole H, a through hole H 'defined by the insulating film 520 is formed in the through hole H.

The through vias V1 applied to the present embodiment include a high melting point metal layer 10, a low melting point metal layer 20, and a conductor pillar 30. [

The conductor pillar 30 is formed in the through hole H '. The conductor pillar 30 may be formed by plating or may be formed of a conductive paste. The conductor pillar 30 is made of a material such as copper, silver, palladium, aluminum, nickel, titanium, gold, platinum But is not limited thereto.

The conductor pillar 30 may be formed of the same material and the same method as the low melting point metal layer 20 described above. Alternatively, the conductor pillar 30 may be formed of a material different from the low melting point metal layer 20. When the material of the conductor pillar 30 and the low melting point metal layer 20 are different from each other, an intermetallic compound layer may be formed between the conductor pillar 30 and the low melting point metal layer 20.

(Third Example )

3 is a view illustrating a printed circuit board according to a third embodiment of the present invention.

3, the printed circuit board 3000 according to the present embodiment includes a metal layer 510, an upper conductive pattern layer 110, a lower conductive pattern layer 210, an upper insulating layer 120, Layer vias V2 and may include a solder resist layer 620. The solder resist layer 620 may be formed of a conductive material such as silicon oxide.

The printed circuit board 3000 according to the present embodiment further includes the interlayer vias V2 as compared with the printed circuit board 2000 according to the second embodiment of the present invention, And / or the number of the lower conductor pattern layers 210 are different. In the following description of the present embodiment, the difference will be mainly described.

The upper conductor pattern layer 110 and / or the lower conductor pattern layers 210, 310, and 410, which are applied to the present embodiment, are each formed in a plurality. At this time, the number of the upper conductor pattern layers 110 and the number of the lower conductor pattern layers 210, 310, and 410 may be different from each other.

In the case of a general printed circuit board, the rigidity and the thermal expansion coefficient may be different from each other in the upper and lower portions of the substrate depending on the density difference of the conductor pattern and the density difference of the insulating material. As a result, warpage may occur at the top or bottom of the substrate. Therefore, in the case of the present embodiment, the metal layer 510 is disposed in the region where the warpage of the substrate occurs, thereby preventing warpage of the substrate.

Fig. 3 exemplarily shows that the metal layer 510 is formed on the upper side of the substrate when the warpage of the substrate occurs on the upper side. 3 shows that the upper conductive pattern layer 110 is formed in a single number and the lower conductive pattern layers 210, 310, and 410 are formed in plural, but this is only an illustrative example. Therefore, the number of the upper conductor pattern layer 110 and the lower conductor pattern layers 210, 310, and 410 may be variously changed.

The description of the conductor pattern layers 110 and 210 described in the printed circuit board according to the first embodiment of the present invention can be directly applied to the third conductor pattern layer 310 and the fourth conductor pattern layer 410 .

The interlayer vias V2 connect adjacent upper conductor pattern layers 110 or connect adjacent lower conductor pattern layers 210, 310 and 410 to each other. 3, the interlayer vias V2 are formed on the lower insulating layers 220, 320 and 420 so as to connect the adjacent lower conductive pattern layers 210, 310 and 410 to each other. However, the upper conductive pattern layer 110 The interlayer vias V2 may be formed in the upper insulating layer 120 to connect the adjacent upper conductive pattern layers 110. [

Manufacturing method of printed circuit board

4, 5, and 8 to 18 are views sequentially illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention. 4, 5 and 8 to 18 correspond to an exemplary manufacturing method for manufacturing the printed circuit board 3000 according to the third embodiment of the present invention described above.

4 and 5 are views sequentially illustrating a process of manufacturing a metal unit substrate according to an embodiment of the present invention. FIGS. 8 to 13 are views FIGS. 14 to 16 are views showing a process of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 14 to FIG. FIGS. 17 and 18 show the steps of manufacturing the unit substrate, the unit substrate and the protection unit substrate manufactured through FIGS. 3, 4, 6 and 8 to 16 in a batch As shown in Fig. 6 and 7 are views showing a modification of the metal unit substrate, respectively.

Hereinafter, a process for manufacturing a metal unit substrate, a process for manufacturing a general unit substrate, and a process for manufacturing a protective unit substrate will be described in order and a process for laminating a plurality of unit substrates will be described. Unless otherwise required to distinguish the metal unit substrate, the general unit substrate, and the protection unit substrate, they are collectively referred to as a unit substrate.

(Manufacturing Method of Metal Unit Substrate)

FIGS. 4 and 5 are views sequentially illustrating a process of manufacturing a metal unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention.

4, a metal plate MP having outer layer plates 512 'and 513' formed on both sides of the inner layer plate 511 'is prepared.

The inner layer board 511 ', the outer layer boards 512' and 513 'and the metal disk MP are connected to the printed circuit boards 1000, 2000 and 3000 according to the first to third embodiments of the present invention, respectively, The inner layer 511, the outer layer 512 and the metal layer 510 described in connection with FIG.

The inner lamina 511 'may comprise Invar and the outer lamina 512', 513 'may comprise copper Cu. The outer layer plates 512 'and 513' may be laminated on both sides of the inner layer board 511 'in a film form or may be formed by electrolytic plating.

Next, referring to FIG. 5, a through hole H is formed in the metal disk MP, and then an insulating film 520 is formed.

The metal layer 510 may be manufactured by selectively removing the metal plate MP to form a through hole H. [ The selective removal of a portion of the metal original plate (MP) may be performed by at least one of chemical etching, laser drilling, and mechanical drilling.

The insulating film 520 is formed along the surface of the metal layer 510 including the inner wall of the through hole H. [ At this time, since the thickness of the insulating film 520 is formed to be smaller than half of the diameter of the through hole H, a through hole H 'is formed in the through hole H. That is, the through hole H 'is formed in the through hole H and is defined by the insulating film 520.

The insulating layer 520 may be formed by depositing an insulating material such as paralin on the metal layer 110, but is not limited thereto. As another example, after forming an insulating material covering the entire surface of the metal layer 510 in the metal layer 510, a part of the insulating material is removed so that the through hole H 'is formed in the through hole H, .

6 and 7 are views showing a modification of the metal unit substrate according to the present embodiment. 6 and 7 are metal unit substrates 500 'and 500' 'applied to the printed circuit boards 1000 and 2000 according to the first and second embodiments of the present invention, respectively.

The metal unit substrate 500 'applied to the printed circuit board 1000 according to the first embodiment is formed such that the space between the inner wall of the through hole H and the through vias V1 is filled with the insulating layers 120 and 220 do. Therefore, unlike the metal unit substrate 500 described with reference to FIGS. 4 and 5, the insulating layer 520 is not formed.

The metal unit substrate 500 '' applied to the printed circuit board 2000 according to the second embodiment is similar to the metal unit substrate 500 described with reference to FIGS. 4 and 5 except that the through holes H ' The conductor pillar 30 is charged.

(Manufacturing method of general unit substrate)

FIGS. 8 to 13 are views sequentially illustrating a process of manufacturing a general unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention.

First, referring to FIG. 8, first metal foils F1 and F1 'are formed on both surfaces of the first carrier C1. The first carrier C1 may be formed of any one of metal materials, inorganic materials, and organic materials having required rigidity. The first metal foils F1 and F1 'may be copper foils, but may include other conductive metals. The first metal foils F1 and F1 'may be laminated on both sides of the first carrier C1 in a film form or may be formed on both sides of the first carrier C1 through a plating process.

Next, referring to FIG. 9, the first conductor pattern layer 110 is selectively formed on the first metal foils F1 and F1 '. The first conductor pattern layer 110 may be formed by an MSAP (Modified Semi-Additive Process) method using the first metal foils F1 and F1 'as seed layers. The first conductor pattern layer 110 is formed by forming a plating resist having a pattern opposite to that of the first conductor pattern layer 110 on the first metal foils F1 and F1 'and performing electrolytic plating. After completion of electrolytic plating, And removing it. In the above example, the MSAP method in the conventional circuit pattern forming method is described. However, the first conductor pattern layer 110 may be formed using any one of the well-known Substractive method, Full-Additive method, or Semi- .

Next, referring to FIG. 10, a first insulating layer 120 is formed on the first conductor pattern layer 110). The first insulating layer 120 is formed with openings selectively exposing a part of the first conductor pattern layer 110 to the outside. The opening may be formed by a photolithography method. That is, the first insulating layer 120, which is a photosensitive insulating material, may be formed on the entire surface of the first conductor pattern layer 110, and an opening may be formed through selective exposure and development. Further, the opening may be formed by laser drilling.

The first insulating layer 120 may be laminated to the first conductor pattern 110 using a vacuum laminator. However, since the first insulating layer 120 laminated and subjected to the selective exposure process is not subjected to the post-curing process until the lamination is performed in a lump, it is in a semi-cured state (B-stage). For example, the first insulating layer 120 having undergone the selective exposure process may have a degree of curing of 10 to 20% as compared with the C-stage. On the other hand, if necessary, the first insulating layer 120 may be semi-cured through a separate process so as to have a 50% curability relative to the fully cured state (C-stage). A separate semi-curing process may be performed using UV light used in the photolithography process to form the openings. However, also in this case, the first insulating layer 120 is not completely cured until collectively laminated.

Next, referring to FIG. 11, a refractory metal layer 10 and a refractory metal layer 20 are sequentially formed in the opening of the first insulating layer 120. The refractory metal layer 10 and the low melting point metal layer 20 of the first general unit substrate 100 together with the refractory metal layer 10 and the low melting point metal layer 20 of the second general unit substrate 200 Thereby forming the through vias V1 after the collective lamination.

The refractory metal layer 10 is formed through electrolytic plating. In the case of electrolytic plating, it includes both anisotropic and isotropic plating. The refractory metal layer 10 may be formed through copper electroplating to include copper (Cu). In forming the refractory metal layer 10 by electrolytic plating, the seed layer may be the first conductor pattern layer 110. Or the seed layer may be formed through a separate process other than the first conductor pattern layer 110.

The low melting point metal layer 20 can be formed by selectively plating a low melting metal such as i) a low melting metal such as solder, or ii) selectively applying a low melting metal paste such as a solder paste and then drying the low melting metal paste . The solder or solder paste may be based on tin, silver, copper or an alloy of the metals selected here. In addition, the solder paste used in the present invention may not contain flux. Solder pastes are sintered at relatively high temperatures (eg 800 ° C) and hardened at relatively low temperatures (eg 200 ° C). The solder paste used in this embodiment may be curable at a relatively low temperature to prevent complete curing of the first insulating layer 220 when the solder paste is cured.

The low melting point metal paste may have a relatively high viscosity and may maintain its shape after being formed on the high melting point metal layer 10. Further, the low melting point metal paste has low melting point metal particles, and the surface of the low melting point metal layer 20 formed by hardening of the low melting point metal paste by these particles can be rugged.

Next, referring to FIG. 12, a cover film CF covering the low melting point metal layer 20 and the first insulating layer 120 is formed. The cover film CF protects the general unit substrates 100, 200, 300 and 400 from the outside. Specifically, the cover film CF is bonded to the general unit substrates 100, 200, 300, and 400 and is separated from each of the general unit substrates 100, 200, 300, and 400 immediately before the collective stacking process.

13, the first carrier C1 is separated from the first metal foils F1 and F1 ', the first metal foils F1 and F1' are removed, and then the cover film CF is removed. 1 general unit substrate 100 is manufactured. The first metal foils F1 and F1 'may be removed by chemical etching, but are not limited thereto.

8-13 illustrate that the first common unit substrate 100 is formed on both sides of the first carrier C1 but only the first common unit substrate 100 is formed on only one side of the first carrier C1. Can be formed. In addition, the first common unit substrate 100 may be formed on one surface of the first carrier C1 and other general unit substrates such as the second general unit substrate 200 may be formed on the other surface of the first carrier C1.

Although the second general unit substrate 200, the third general unit substrate 300 and the fourth general unit substrate 400 are also described in the first general unit substrate 100, And may be manufactured according to a manufacturing method of the unit substrate 100.

(Manufacturing method of protective unit substrate)

FIGS. 14 to 16 are views sequentially illustrating steps of manufacturing a protective unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention.

First, referring to FIG. 14, second metal foils F2 and F2 'are formed on both surfaces of a second carrier C2. The second carrier C2 may be formed of any one of metal materials, inorganic materials, and organic materials having required rigidity. The second metal foils F2 and F2 'may be copper foils, but may also include other conductive metals. The second metal foils F2 and F2 'may be laminated on both sides of the second carrier C2 in a film form or may be formed on both sides of the second carrier C2 through a plating process.

Next, referring to FIG. 15, a solder resist layer 620 is formed on the second metal foils F2 and F2 '. The solder resist layer 620 is formed with openings selectively exposing a part of the second metal foils F2 and F2 'to the outside. The opening may be formed by a photolithography method. That is, an opening may be formed by forming a solder resist, which is a photosensitive insulating material, on the entire surfaces of the second metal foils F2 and F2 ', and then selectively exposing and developing the solder resist. Further, the opening may be formed by laser drilling. The solder resist layer 620 may be formed by laminating a DFR film on the second metal foils F2 and F2 'using a vacuum laminator, but is not limited thereto.

16, the protection unit substrate 600 is manufactured by removing the second carrier C2 from the second metal foils F2 and F2 '. At this time, although not shown, the cover film CF may be laminated on the protection unit substrate 600 so as to easily remove the second carrier C2 and to support and protect the protection unit substrate 600 until lamination . Since the cover film CF has been described above, the description is omitted.

(Step of collectively laminating unit substrates)

FIGS. 17 and 18 are views showing the lamination of the metal unit substrate, the general unit substrate, and the protective unit substrate manufactured through FIGS. 3, 4, 6 and 8 to 16 collectively.

Referring to FIG. 17, a plurality of unit substrates 100, 200, 300, 400, 500, and 600 are vertically stacked and stacked. At this time, a plurality of unit substrates 100, 200, 300, 400, 500, 600 are aligned through alignment marks formed on each of the plurality of unit substrates 100, 200, 300, 400, press laminator to bond all the layers together at high temperature.

In the batch lamination, the temperature may be set to 180 to 200 DEG C and the press pressure may be set to 30 to 50 kg / cm < 2 > 120, 220, 320, 420 or the component of the low-melting-point metal layer 20, and the like. In particular, the temperature at the time of laminating may be more than the melting point of the low melting point metal layer 20. [

The low melting point metal layer 20 is melted and bonded to neighboring conductor pattern layers 110, 210, 310, and 410 at the time of laminating. In this case, the upper cross-sectional area of the low-melting-point metal layer 20 and the lower cross-sectional area of the low-melting-point metal layer 20 may be formed to have different sizes by spreading the low melting point metal layer 20 after the batch lamination.

In addition, the first to fourth insulating layers 120, 220, 320, and 420 in the semi-cured state are completely cured by the temperature and pressure at the time of lamination.

Next, referring to FIG. 18, the second metal foils F2 and F2 'remaining on each of the protection unit substrates 600 are removed to expose the solder resist layer 620 to the outside. The second metal foils F2 and F2 'may be removed from the solder resist layer 620 through chemical etching or removed by physical exfoliation.

17 and 18 illustrate that the solder resist layer 620 is formed on the first conductor pattern layer 110 and the fourth conductor pattern layer 410 respectively, The solder resist layer 620 is formed only on either the first conductor pattern layer 110 or the fourth conductor pattern layer 410 by disposing the solder resist layer 620 on any one of the first general unit substrate 100 or the fourth general unit substrate 400. [ May be formed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

C1, C2: Carrier
CF: Cover film
F1, F1 ', F2, F2': Metal foil
H: Through hole
H ': Through hole
MP: metal disc
V1: Via through
V2: Interlayer vias
10: High melting point metal layer
20: Low melting point metal layer
30: conductor pillar
100, 200, 300, 400: general unit substrate
110, 210, 310, 410: conductor pattern layer
120, 220, 320, 420: insulating layer
500: metal unit substrate
510: metal layer
511: inner layer
512, 513: outer layer
511 ': My laminate
512 ', 513': outer layer plate
600: Protection unit substrate
620: solder resist layer
1000, 2000, 3000: printed circuit board

Claims (9)

A metal layer having a through hole formed therein;
An upper conductor pattern layer and a lower conductor pattern layer respectively formed on the metal layer;
An upper insulating layer formed between the metal layer and the upper conductive pattern layer;
A lower insulating layer formed between the metal layer and the lower conductor pattern layer; And
Melting metal layer and a refractory metal layer having a melting point higher than a melting point of the low melting point metal layer, wherein the upper insulating layer, the lower insulating layer, and the through hole Through vias formed in the substrate;
And a printed circuit board.
The method according to claim 1,
The upper insulating layer and / or the lower insulating layer
And filling the space between the inner wall of the through hole and the through via.
The method according to claim 1,
And an insulating film formed between the inner wall of the through hole and the through via.
The method according to claim 1,
Wherein the metal layer comprises Invar.
The method according to claim 1,
Wherein the low melting point metal layer comprises tin (Sn).
The method according to claim 1,
Wherein the upper insulating layer and / or the lower insulating layer comprises a photocurable resin.
The method according to claim 1,
Wherein the upper conductor pattern layer and / or the lower conductor pattern layer are formed in a plurality of.
8. The method of claim 7,
Wherein the number of the upper conductor pattern layers and the number of the lower conductor pattern layers are different from each other.
8. The method of claim 7,
Further comprising interlayer vias connecting the upper conductor pattern layers adjacent to each other or connecting the lower conductor pattern layers adjacent to each other,
The interlaminar vias may include,
The low melting point metal layer and the high melting point metal layer.

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