KR20180072838A - Self-alignment shielding of silicon oxide - Google Patents

Abstract

Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional materials on silicon nitride are also described. Both exposed portions of silicon nitride and silicon oxide may be present on the patterned substrate. The self-assembled monolayer (SAM) is selectively deposited over the silicon oxide, but not on the exposed silicon nitride. The molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with an OH group on the exposed silicon oxide moiety, and the tail moiety extending in a direction away from the patterned substrate. Subsequent exposure to an etchant or deposition precursor can then be used to selectively remove silicon nitride or selectively deposit additional material on the silicon nitride.

Description

Self-alignment shielding of silicon oxide

Cross reference to related applications

This application is a continuation-in-part of U.S. Patent Application No. 15 / 235,048, filed on August 11, 2016, which claims the benefit of U.S. Provisional Patent Application No. 62 / 258,122 filed on November 20, The disclosures of Nos. 15 / 235,048 and 62 / 258,122 are hereby incorporated by reference in their entirety for all purposes.

Technical field

The embodiments described herein relate to selectively shielding silicon oxide from etching and deposition.

The integrated circuits are enabled by processes that create complexly patterned material layers on the substrate surfaces. Generating the patterned material on the substrate requires controlled methods for removal of the exposed material. Chemical etching is used for a variety of purposes, including transferring the pattern in the photoresist to the base layers, thinning the layers, or thinning the lateral dimensions of features already present on the surface. Often, it is desirable to have an etch process to remove one material faster than other materials, e.g., to assist in the progress of the pattern transfer process. Such an etch process is said to be selective for the first material. As a result of the variety of materials, circuits and processes, etch processes have been developed with selectivity for various materials. However, there are a few options for selectively removing silicon nitride faster than silicon or silicon oxide.

Dry etching processes are often desirable for selectively removing material from semiconductor substrates. Such desirability results from the ability to carefully remove material from small structures, with minimal physical disturbance. In addition, dry etching processes allow abrupt interruption of the etch rate by removing gas phase reagents. Some dry etch processes involve exposure of the substrate to remote plasma byproducts formed from one or more precursors. For example, remote plasma excitation of ammonia and nitrogen triflates allows for the selective removal of silicon oxide from the patterned substrate when plasma effluents flow into the substrate processing region do. Remote plasma etch processes have also been developed to remove silicon nitride, but the silicon nitride selectivity (for silicon or silicon oxide) of these etch processes can still benefit from further improvements.

Methods are needed to improve the silicon nitride etch selectivity for silicon or silicon oxide for dry etch processes.

Methods for etching silicon nitride faster than silicon oxide are described. Methods of selectively depositing additional materials on silicon nitride are also described. Both exposed portions of silicon nitride and silicon oxide may be present on the patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide, but not over the exposed silicon nitride. The molecules of the self-assembled monolayer include a head moiety and a tail moiety, wherein the head moiety forms a bond with an OH group on the exposed silicon oxide moiety, The Te extends in a direction away from the patterned substrate. Next, to selectively remove silicon nitride much faster than silicon oxide, a subsequent vapor etch using anhydrous vapor-phase HF may be used, since the SAM is used to delay etching and reduce the etch rate . Due to the presence of the SAM, subsequent depositions can be similarly used to selectively deposit additional material on the silicon nitride much faster than on the silicon oxide phase.

DETAILED DESCRIPTION OF THE INVENTION In this document, methods involving removing silicon nitride from a patterned substrate are described. The methods include (i) selectively forming a partial layer over the silicon oxide portions of the patterned substrate without forming over the silicon nitride portions of the patterned substrate. The partial layer is patterned after formation, without applying any type of lithography. The methods further include (ii) selectively etching the silicon nitride from the silicon nitride portions faster than etching the silicon oxide from the silicon oxide portions.

The patterned layer may be patterned after formation, without any intermediate lithography or etching operations being applied. Operation (i) may occur before operation (ii). The operations (i) and (ii) may be repeated an integer number of times. Operation (i) and operation (ii) may occur simultaneously.

In the present specification, methods including etching silicon nitride from a patterned substrate are described. The methods further comprise providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion. The methods further comprise exposing the patterned substrate to an alkylsilane precursor. The methods further comprise forming a self-assembled monolayer on the exposed silicon oxide portion, but not on the exposed silicon nitride portion. The methods further comprise exposing the patterned substrate to a halogen-containing precursor. The methods further include removing silicon oxide from the exposed silicon oxide portion with a silicon oxide etch rate of less than 1 percent of the silicon nitride etch rate while etching the silicon nitride from the exposed silicon nitride portion with a silicon nitride etch rate.

The methods may further comprise removing the self-assembled monolayer after forming the thickness of the patterned layer to re-expose the exposed silicon oxide portion. The step of forming the self-assembled monolayer may occur prior to etching the silicon nitride. Exposing the patterned substrate to alkyl silane precursors may occur simultaneously with exposing the patterned substrate to a halogen containing precursor. Both forming the self-assembled monolayer and etching the silicon nitride can occur while the patterned substrate is in a plasma-free substrate processing region. The halogen-containing precursor may comprise fluorine. The halogen-containing precursor may comprise anhydrous HF. The halogen-containing precursor may be a gas-phase precursor. Each molecule of the self-assembled monolayer can include a head moiety and a tail moiety. The head moiety may form a bond with the exposed silicon oxide portion and the tail moiety may extend in a direction away from the patterned substrate. The self-assembled monolayer can reduce the subsequent etch rate of the exposed silicon oxide portion compared to the etch rate of the exposed silicon nitride portion.

Methods comprising selectively depositing an additional layer on a patterned substrate are described. The methods include providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion. The methods further include selectively forming a self-assembled monolayer on the exposed silicon oxide portion, without forming on the exposed silicon nitride portion. The methods further comprise exposing the patterned substrate to a deposition precursor. The methods further include depositing additional material on the exposed silicon nitride portion at least 100 times faster than depositing on the silicon oxide portion.

The step of flowing the deposition precursor within the substrate processing region may occur after the step of selectively forming the self-assembled monolayer. The step of selectively forming the self-assembled monolayer and depositing additional material on the exposed silicon nitride portions may occur while the patterned substrate is in the plasma-free substrate processing region, respectively.

For a better understanding of the nature and advantages of the present invention, reference should be had to the following detailed description and accompanying drawings. It is to be understood, however, that each of the drawings is provided for the purpose of illustration only and is not intended as a definition of the limits of the scope of the invention.

A better understanding of the nature and advantages of the disclosed technique may be realized by reference to the remaining portions and drawings of the specification.
Figure 1 illustrates a method for selectively etching silicon nitride according to embodiments.
Figure 2 illustrates a method of selectively forming a film on silicon nitride in accordance with embodiments.
Figures 3a and 3b are side views of the patterned substrate during selective etching and after selective etching according to embodiments.
Figures 3C and 3D are side views of the patterned substrate during selective deposition and after selective deposition according to embodiments.
4A shows a schematic cross-sectional view of a substrate processing chamber according to embodiments.
Figure 4B shows a schematic cross-sectional view of a portion of a substrate processing chamber in accordance with embodiments.
4C shows a lower view of a showerhead according to embodiments.
Figures 5A and 5B are schematic diagrams of substrate processing equipment according to embodiments.
Figure 6 shows a top view of an exemplary substrate processing system according to embodiments.
In the accompanying drawings, similar components and / or features may have the same reference label. Also, various components of the same type can be distinguished by a dash after the reference label, followed by a second label that identifies similar components. If only a first reference label is used in the specification, the description may be applied to any of the similar components having the same first reference label regardless of the second reference label.

Methods for etching silicon nitride faster than silicon oxide are described. Methods of selectively depositing additional materials on silicon nitride are also described. Both exposed portions of silicon nitride and silicon oxide may be present on the patterned substrate. The self-assembled monolayer (SAM) is selectively deposited over the silicon oxide, but not on the exposed silicon nitride. The molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with an OH group on the exposed silicon oxide moiety, and the tail moiety extending in a direction away from the patterned substrate. Next, in order to selectively remove silicon nitride much faster than silicon oxide, a subsequent vapor etch using anhydrous vapor-phase HF may be used, since the SAM is used to delay etching and reduce the etch rate . Due to the presence of the SAM, subsequent depositions can be similarly used to selectively deposit additional material on the silicon nitride much faster than on the silicon oxide phase.

Selective remote vapor etch processes have used aggressive oxidizing precursors with remotely-excited fluorine-containing precursors to achieve etch selectivity of silicon nitride for silicon. Aggressive oxidation precursors were used to oxidize a thin layer of silicon to prevent further etching. The methods presented herein can eliminate the need for oxidation and eliminate or eliminate remote plasma components that can further enhance effective etch selectivity. These benefits become increasingly desirable for reduced feature sizes. In embodiments, methods are described that preferentially form a self-assembled monolayer (SAM) on exposed silicon oxide portions, but do not form on exposed silicon nitride portions that are also present on the patterned substrate. Next, in order to selectively remove the silicon nitride, an etchant is introduced into the substrate processing region having the substrate.

To better understand and understand the embodiments, reference is now made to Fig. 1, which is a flow diagram of a silicon nitride selective etch process 101 according to embodiments. Before the first operation, a structure is formed in the patterned substrate (act 110). The structure possesses exposed portions of silicon nitride and silicon oxide. Next, the patterned substrate may be transferred into the substrate processing region. Next, the alkyl silane can flow into the substrate processing region through the showerhead. In operation 120, a self-assembled monolayer (SAM) is selectively formed over the exposed silicon oxide portion, but not over the exposed silicon nitride portion.

In operation 130, the flow of anhydrous hydrogen fluoride into the substrate processing region housing the substrate is initiated. The gaseous HF (e.g., anhydrous HF) may flow into the substrate processing region through the showerhead to evenly react with the patterned substrate. The showerhead may include through holes that open into the substrate processing region to more evenly distribute the HF (and / or the prior alkylsilane) to the substrate surface. In embodiments, within the substrate processing area, or upstream from the substrate processing area, the plasma is not ignited. The substrate processing region may be referred to as a plasma free substrate processing region for any or all of the operations described herein. In embodiments, the anhydrous hydrogen fluoride may not have passed any remote plasma before entering the substrate processing region. Alternatively, in accordance with embodiments, a remote plasma may be used to excite the fluorine containing precursor / hydrogen containing precursor combination to form HF or anhydrous HF.

The patterned substrate is selectively etched to selectively remove the exposed silicon nitride at a higher etch rate than the exposed silicon oxide (act 140). The exposed silicon oxide portion may be referred to herein as "exposed" silicon oxide, despite the thin layer of SAM on its surface. The exposed silicon oxide may comprise silicon and oxygen according to embodiments, or it may consist of silicon and oxygen. The presence of the SAM only over the silicon oxide can substantially increase etch selectivity towards the exposed silicon nitride for the exposed silicon oxide. In operation 150, the process effluents and unreacted reactants are removed from the substrate processing region, and then any remaining self-assembled monolayer portion may be removed. In some embodiments, the self-assembled monolayer may be removed when the silicon nitride is selectively removed, and thus operation 150 may be optional. According to embodiments, the substrate may be removed from the substrate processing region before or after the remaining self-assembled monolayer portion is removed, at operation 150.

All of the etch processes described herein utilize a self-assembled monolayer (SAM) selectively deposited on the exposed silicon oxide portions to increase the etch selectivity of the exposed portions of the silicon nitride. The etching of the exposed portions of the silicon nitride is an aggressive etch, which can degrade the integrity of the self-assembled monolayer on exposed silicon oxide portions. The SAM is gradually degraded and removed over time. In embodiments, all of the processes described herein may exhibit satisfactory silicon nitride etch selectivity for a number of semiconductor processes where the etch lasts from 0.5 to 4 minutes, or from 1 to 3 minutes. Alternatively, the SAM may be applied again before repeating the etch process, as indicated by the dashed line in FIG. In embodiments, operations 120-140 may be repeated an integer number of times to remove more material while maintaining much higher silicon nitride selectivity than one pass through method 101. [ Operations 120-150 may be repeated an integer number of times in embodiments that may benefit by completely removing the residual SAM prior to reapplying the new self-assembled monolayer over the exposed silicon oxide portion. The silicon oxide moiety can be treated to re-terminate the surface with OH groups, for example, by exposure to potassium hydroxide.

Generally speaking, fluorine-containing precursors (or plasma effluents formed in a remote plasma from plasma effluents formed from fluorine-containing precursors) can flow into the substrate processing region to etch the substrate. According to embodiments, the fluorine containing precursor may comprise at least one of F ₂ , NF _3, or FCl ₃ . In embodiments, the fluorine containing precursor may be hydrogen, while the fluorine containing precursor may be HF. In embodiments, the plasma effluents may be formed from a combination of a fluorine containing precursor and a hydrogen containing precursor. According to embodiments, the plasma effluents may comprise HF or anhydrous HF, or may be composed of HF or anhydrous HF. Utilizing a remote plasma to form plasma effluents containing HF may be an in-situ method for generating HF or anhydrous HF. In embodiments, the hydrogen containing precursor may comprise at least one of H ₂ or H ₂ O. According to embodiments, the fluorine containing precursor may comprise or consist of HF. In embodiments, the fluorine-containing precursor may be formed by bubbling a carrier gas through a liquid hydrogen-fluorine solution. According to embodiments, the liquid hydrogen-fluoride solution may be a 49% HF solution or a 70% HF-pyridine solution.

In embodiments, after the alkylsilane has flowed into the substrate processing region, HF may flow into the substrate processing region. However, according to embodiments, at the same time as the alkylsilane precursor is flowing into the substrate processing region, HF can flow into the substrate processing region. Simultaneous exposure can recreate the SAM layer on the exposed silicon oxide when the etching process 101 is in progress, which can provide the benefit of reducing processing time. In embodiments, selectively etching the patterned substrate may occur simultaneously with, or after, the formation of the self-assembled monolayer. According to embodiments, a self-assembled monolayer can be initially formed before initiating simultaneous regeneration of the self-assembled monolayer with selective etching of the patterned substrate. In embodiments, the initial formation of the self-assembled monolayer on the exposed silicon oxide portion ensures that the exposed silicon oxide portion is protected (at least temporarily) from an aggressive etchant (e.g., HF). Generally speaking, in accordance with embodiments, forming a self-assembled monolayer and selectively etching a patterned substrate may be performed in separate substrate processing chambers, and thus in separate substrate processing regions.

In addition, the silicon nitride selective etch process 101 can be used to remove silicon nitride faster than silicon. Instead of oxidizing the exposed silicon to prevent etching, the etchants described herein have been found to produce reactive materials that predominantly etch silicon nitride and leave essentially silicon alone. As a result, silicon is essentially not consumed in producing a protective silicon oxide layer to achieve high etch selectivities. As such, in embodiments, the exposed silicon portions may also be present on the patterned substrate, and may comprise or consist of silicon. In embodiments, the selectivity (exposed silicon nitride: exposed silicon oxide or exposed silicon) of the etching process 101 may be greater than 100: 1, greater than 120: 1, or greater than 140: 1.

It has been found that the etching processes described herein provide silicon nitride etch selectivity for low density silicon oxide films as well as for high density silicon oxide films. The achieved silicon nitride selectivities enable vapor etchings to be used in a wider range of process sequences. Exemplary deposition techniques that result in low density silicon oxides include chemical vapor deposition, spin-on glass (SOG), or plasma enhanced chemical vapor deposition using dichlorosilane as a deposition precursor. According to embodiments, the high density silicon oxide may be deposited as a thermal oxide (e.g., exposing silicon to O ₂ at high temperature), disilane precursor furnace oxidation, or high density plasma chemical vapor deposition . In embodiments, the selectivity (exposed silicon nitride: exposed high quality silicon oxide) of the etch process 101 may be greater than 100: 1, greater than 120: 1, or greater than 140: 1. Depending on the embodiments, the selectivity of the etch process 101 (exposed silicon nitride: low-quality silicon oxide exposed) may be greater than 100: 1, greater than 120: 1, or greater than 140: 1

The anhydrous hydrogen fluoride may further comprise one or more relatively inert gases (e.g., He, N ₂ , Ar). The flow rates and flow ratios of the different gases can be used to control etch rates and etch selectivity. In an embodiment, anhydrous hydrogen fluoride can flow into the substrate processing region at flow rates of about 10 sccm (standard cubic centimeters per minute) to 1,000 sccm in embodiments. Argon (Ar) and / or helium (He) may flow with either one precursor (or both, separately) at a flow rate between 0 sccm and 3,000 sccm. It will be appreciated by those of ordinary skill in the art that other gases and / or flows can be used depending on a number of factors including the process chamber configuration, substrate size, geometry and layout of the features to be etched. These process parameters apply to all the examples described herein. In the example of FIG. 2 and following the example of FIG. 2, additional process parameters will be given.

Reference is now made to Fig. 2, which is a flow chart of a method for selectively forming a film on silicon nitride according to embodiments. Before the first operation, a structure is formed in the patterned substrate (act 210). The structure possesses exposed portions of silicon nitride and silicon oxide. Next, the patterned substrate may be transferred into the substrate processing region.

The alkyl silane can flow into the substrate processing region through the showerhead. The self-assembled monolayer is selectively formed on the exposed silicon oxide portion, but not on the exposed silicon nitride portion (act 220). In operation 230, the deposition precursor is flowed into the substrate processing region through the showerhead. The showerhead may include through holes opened into the substrate processing region to more evenly distribute any one precursor to the substrate surface.

Additional layers are selectively deposited (act 240) so that the additional layer is deposited onto the silicon nitride at a deposition rate that is higher than any deposition rate onto the exposed silicon oxide. As a result of the presence of the SAM layer, the deposition rate of the additional layer onto the exposed silicon nitride may be less than the deposition rate onto the exposed silicon oxide. The additional layer may already be patterned (during deposition and immediately after deposition in embodiments) and may not involve etching to be patterned or patterned. In embodiments, the substrate processing region may be plasma-free during all operations of the selective film-forming process 201 or during operations 220-240. The exposed silicon oxide portion may comprise silicon and oxygen, or may be comprised of silicon and oxygen, according to embodiments. The presence of the SAM on the exposed silicon oxide portion may substantially inhibit or remove the deposition rate of the additional layer onto the exposed silicon oxide, but may allow the deposition to proceed on the exposed silicon nitride. As before, the exposed silicon oxide will be described herein as "exposed" irrespective of whether a thin SAM layer is adsorbed. Process effluents and / or unreacted reactants can be removed from the substrate processing region, and then the substrate can be removed from the processing region.

As in the previous example, to remove the SAM layer from the exposed silicon oxide portion, the SAM layer may optionally be removed (act 250). According to embodiments, the selective deposition method 201 deposits additional material of the additional layer only on exposed silicon nitride portions, without lithographic patterning. Lithographic patterning may involve depositing a photoresist, performing photolithography, and etching the exposed portions of the silicon nitride, none of the three may be performed, and the additional layer may still be etched It will be patterned as described. In embodiments, after operation 210, lithography is not performed up to operation 250, including operation 250. In other words, the additional layer can be patterned after formation without applying any intermediate lithographic operations. In embodiments, the deposited thickness of the additional layer on the exposed silicon nitride portion may be greater than 5 nm, greater than 10 nm, greater than 20 nm, or greater than 30 nm. On the other hand, the deposited thickness of the additional layer on the exposed silicon oxide portion may be so small that it can not be measured by the most sensitive means. According to embodiments, the deposited thickness of the additional layer may be less than 0.3 nm, less than 0.2 nm, or less than 0.1 nm.

The etch and deposition processes described herein may be applied to patterned substrates having high aspect ratio features in the form of trenches or vias. In embodiments, the etch rate or deposition rate near the bottom of the high aspect ratio features may be within 12%, within 7%, within 5%, or within 3% of the etch rate or deposition rate near the opening of the high aspect ratio features. According to embodiments, the depth of the via or trench (high aspect ratio features) may be greater than 0.5 占 퐉, greater than 1.0 占 퐉, or greater than 2.0 占 퐉. In embodiments, the width (narrower dimension) of the via or trench may be less than 30 nm, less than 20 nm, or less than 10 nm. According to embodiments, the depth-to-width aspect ratio may be greater than 10, greater than 50, or greater than 100. [

The etch rate of the exposed silicon nitride portion or the deposition rate on the exposed silicon nitride portion may not be affected by the SAM because the SAM is selectively deposited only on the exposed silicon oxide portion and the exposed silicon nitride portion or And is not deposited on any exposed silicon portions. The etch rate of the exposed silicon nitride portion may be greater than 100, greater than 150, or greater than 200 times the etch rate of the exposed silicon oxide portion. Similarly, the deposition rate of additional material of the additional layer onto the exposed silicon nitride portion may be more than 100 times, more than 150 times, or more than 200 times the deposition rate on the exposed silicon oxide portion.

In embodiments, a SAM (not shown) may be formed on the substrate by exposing the exposed silicon oxide of the patterned substrate to an alkylsilane, either within the same substrate processing region as used for etching (as in the examples) or within a different substrate processing region Can be deposited. Generally speaking, a SAM precursor can be used to deposit a SAM, and a SAM precursor can include silicon, oxygen, carbon, and hydrogen, or can be composed of silicon, oxygen, carbon, and hydrogen have. In embodiments, the SAM precursor may comprise silicon, oxygen, carbon, chlorine, and hydrogen, or it may be comprised of silicon, oxygen, carbon, chlorine, and hydrogen. According to embodiments, the SAM precursor may comprise silicon, oxygen, carbon, nitrogen, and hydrogen, or it may be comprised of silicon, oxygen, carbon, nitrogen, and hydrogen. In embodiments, the SAM precursor may comprise any of the above-mentioned three groups of elements and fluorine, or may be composed of any of the three groups of elements and fluorine.

The SAM precursor may include a head moiety and a tail moiety, or may consist of a head moiety and a tail moiety. In embodiments, the head moiety may have silicon covalently bonded to the three methoxyl groups, and the tail moiety may be an alkyl chain covalently bonded to the remaining bonds of the silicon atoms of the head moiety. The silicon atom of the head moiety may lose the methoxyl group, and then, if the chemical termination is properly formed, the silicon atom may be bonded to the exposed silicon oxide moiety. The hydroxyl groups on the surface are believed to promote chemical reactions between the SAM precursor and the exposed silicon oxide moiety. The alkylsilane may further comprise a halogen. According to embodiments, the alkylsilane is selected from the group consisting of C8-methoxysilane, C7-methoxysilane, C6-methoxysilane, C5-methoxysilane, C4- methoxysilane, C4-chlorosilane, or C3-chlorosilane. The tail moieties can serve to prevent or inhibit the deposition of silicon oxide onto the etch or silicon oxide. In embodiments, the tail moiety of the SAM molecule (alkylsilane) may have more than 2 carbon atoms, more than 3 carbon atoms, more than 4 carbon atoms, more than 5 carbon atoms, or more than 6 carbon atoms Atoms, an alkyl group having more than 8 carbon atoms, more than 12 carbon atoms, more than 14 carbon atoms, or more than 16 carbon atoms. Depending in part on the length of the tail moiety, the SAM precursor may be in the form of a gas, liquid, or solid that may be provided in a variety of suitable techniques on the patterned substrate. In embodiments, the liquids and solids can be vaporized and transported into the chemical vapor deposition chamber using a relatively inert carrier gas. Exemplary hardware used to deposit a self-assembled monolayer using a liquid precursor will be briefly described.

The SAM precursors used herein to deposit the self-assembled monolayers are described in particular as tail moieties (TM) and head moieties (HM), and minor interactions between the precursors and the patterned substrate Can be accounted for as SAM molecules. Generally speaking, in embodiments, the tail moiety may be a linear or branched alkyl chain or may be a cyclic hydrocarbon. According to embodiments, the tail moiety may comprise carbon and hydrogen, or it may be composed of carbon and hydrogen. In embodiments, regardless of the shape, the tail moiety can be a fluorinated hydrocarbon and can include carbon, hydrogen, and fluorine, or can be composed of carbon, hydrogen, and fluorine. The head moiety is selected from the group consisting of methoxysilane (e.g., dimethoxysilane or trimethoxysilane), ethoxysilane (e.g., diethoxysilane or triethoxysilane), amine silane, aminosilane, Chlorosilane. In embodiments, the SAM precursor may have a tail that is fluorinated alkyl silane. According to embodiments, the SAM molecules can be at least one of n-propyltrimethoxysilane, n-octyltrimethoxysilane, or trimethoxy (octadecyl) silane. In embodiments, the SAM precursor may have a phenyl group tail and may be a phenyl alkyl silane.

In embodiments, the exposed silicon and the exposed silicon nitride (if exposed silicon is present) are not chemically modified by the same chemical preparation affecting the silicon oxide, and thus may not develop the hydroxyl termini, And may not subsequently react with the SAM precursor. The SAM is formed from the SAM precursor by the head moiety being chemisorbed onto the substrate from either the vapor or liquid phase and is followed by a general alignment of the tail moiety on the far side from the silicon oxide binding sites. According to embodiments, the tail moiety may not chemically bond to any of silicon, silicon oxide, or silicon nitride. Once all of the silicon oxide binding sites on the exposed silicon oxide moieties are occupied by the SAM molecules, the bonding process can be stopped, thereby becoming a self-limiting process.

According to embodiments, during operation to selectively etch exposed silicon nitride or selectively deposit additional material onto exposed silicon nitride, the pressure in the substrate processing region may be greater than 0.5 Torr, greater than 5 Torr, greater than 10 Torr, 15 Torr, or greater than 25 Torr. In embodiments, the pressure in the substrate processing region may be less than 1,000 Torr, less than 750 Torr, less than 500 Torr, less than 250 Torr, or less than 100 Torr. The upper limits of all parameters may be combined with the lower limits of the same parameters to form further embodiments. In accordance with embodiments, the pressure in the substrate processing region during the selective etching and selective deposition operations described herein may be from 0.5 Torr to 1,000 Torr. In a preferred embodiment, the pressure in the substrate processing region during selective etching or selective deposition operations is 20 Torr to 110 Torr.

In embodiments, during an optional etching operation, the temperature of the patterned substrate may be between -20 占 폚 and 300 占 폚, or between 0 占 폚 and 250 占 폚. According to embodiments, during the operation of selectively depositing additional material, the temperature of the patterned substrate may be between -20 캜 and 500 캜, or between 0 캜 and 450 캜. In preferred embodiments, during the operation of selectively etching the exposed silicon nitride or selectively depositing additional material on the exposed silicon nitride, the temperature of the patterned substrate may be between 40 캜 and 200 캜, or between 50 캜 and 150 캜 . Conventional processes involving anhydrous hydrogen fluoride have etched silicon oxide faster than silicon nitride by maintaining substrate temperatures below the ranges provided as preferred embodiments. The etch selectivity of silicon nitride for silicon oxide may be in the highest ranges for patterned substrate temperatures of 55 [deg.] C to 75 [deg.] C. In embodiments, the patterned substrate temperature may be between 55 캜 and 75 캜. In accordance with embodiments, the temperature of the patterned substrate may be within all of these ranges during operations 240, 220, 140, and / or 120.

Self-assembled monolayers can be thermally stable and can withstand heat treatments at relatively high temperatures of up to 400 ° C, up to 450 ° C, or even up to 500 ° C. In accordance with embodiments, the temperature of the patterned substrate is less than 400 占 폚, less than 450 占 폚, or less than 500 占 폚 during each of the operations of forming the self-assembled monolayer and the etching of the exposed silicon nitride portions. Similarly, in accordance with embodiments, the temperature of the patterned substrate is less than 400 占 폚, less than 450 占 폚 during each of the operations of forming a self-assembled monolayer and selectively depositing additional material on the exposed silicon nitride portion , Or less than 500 ° C.

In all of the etch processes described herein, during the operation of selectively etching the exposed silicon nitride, the substrate processing region may not have nitrogen. For example, the substrate processing region may not have ammonia (or in general NxHy) during silicon nitride etch. In order to enhance the etch rate of silicon oxide, sources of ammonia are often added to conventional processes involving anhydrous hydrogen fluoride, but are not preferred in the embodiments described herein. Compared to the exposed silicon oxide portions, such a reaction reduces the selectivity of exposed silicon nitride portions.

The substrate processing region may be referred to as "plasma free" during an optional deposition process, and during any deposition and etch processes described herein. Maintaining the plasma free substrate processing region and using the precursors described herein enable the achievement of high etch selectivity of silicon nitride for silicon and silicon oxides. Similarly, maintaining the plasma-free substrate processing area enhances the deposition rate difference between the exposed surfaces. With alternative definitions, according to embodiments, the electron temperature in the substrate processing region during any or all of the operations described herein may be less than 0.5 eV, less than 0.45 eV, less than 0.4 eV, or less than 0.35 eV have. The benefits of the processes described herein include the reduction of plasma damage by using predominantly neutral species to perform selective silicon nitride etch and deposition processes. Conventional localized plasma processes may include sputtering and impacting components. Another benefit of the processes described herein is the reduction of stresses to delicate features on patterned substrates as compared to conventional wet etch processes that can cause bending and delamination of small features as a result of surface tension of liquid etchants .

In embodiments, the SAM precursors may be deposited on all two or more chemically distinct portions of the patterned layer, but only one of the two portions may form covalent bonds. On other parts, the precursors can be bonded by physical adsorption, which means that no covalent bonds are formed between the precursors and the second exposed surface portion. In such a scenario, physically adsorbed precursors can be easily removed while allowing chemisorbed (covalently bonded) precursors to be retained. This is an alternative method for creating a selectively deposited SAM layer for all of the processes described herein.

Figures 3a and 3b are side views of the patterned substrate during selective etching and after selective etching according to embodiments. Figures 3C and 3D are side views of the patterned substrate during selective deposition and after selective deposition according to embodiments. 3A and 3C, the self-assembled monolayer 310 is selectively deposited and grown on the exposed silicon oxide portion 305 of the patterned substrate 301, Is not deposited on the silicon nitride portions 315 that are formed. 3B shows that the etchant (e.g., anhydrous HF) removes the exposed silicon nitride portion 315, but leaves the exposed silicon oxide 305 on the patterned substrate 301. Similarly, FIG. 3D shows that the deposition precursors add material (additional layer 320) on the exposed silicon nitride portion 315, but add material on the exposed silicon oxide 305 of the patterned substrate 301 . In embodiments, the additional deposition may proceed only on areas without the SAM coating. For both selective and selective deposition, the methods described herein can provide cost savings and increased overlay accuracy compared to traditional methods that relied on lithographic patterning. Subsequent to SAM selective deposition, subsequent deposition of additional layer 320 may also be referred to as selective deposition, but is an inverted image of the selectively deposited SAM layer. Subsequent deposited films may have greater utility in the function of the finished integrated circuit or in additional processing (as compared to SAM).

Exemplary hardware will now be described. 4A shows a cross-sectional view of an exemplary substrate processing chamber 1001 having regions defined within the processing chamber. During the film etch, the process gas may flow into the remote region 1015 through the gas inlet assembly 1005. A substrate support 1065 (also known as a pedestal) having a cooling plate 1003, a faceplate 1017, an ion suppressor 1023, a showerhead 1025 and a substrate 1055 disposed thereon Are shown and may be included, respectively, in accordance with the embodiments. The pedestal 1065 can have a heat exchange channel and the heat exchange fluid flows through such heat exchange channels to control the temperature of the substrate. This configuration may allow the temperature of the substrate 1055 to be cooled or heated to maintain a relatively low temperature, e.g., -40 ° C to 500 ° C. In addition, the pedestal 1065 can be resistively heated to a relatively high temperature, such as 100 占 폚 to 1100 占 폚, using the built-in heater element.

Exemplary arrangements include having a gas inlet assembly 1005 open into the gas supply region 1058 defined by the front plate 1017 from the remote region 1015 such that the gases / Lt; RTI ID = 0.0 > 1015 < / RTI > A precursor, e.g., anhydrous HF, may be flowed into the substrate processing region 1033 by embodiments of the showerhead described herein. The excited species derived from the process gas in the remote region 1015 may include HF and may move through the apertures in the showerhead 1025 and optionally move the substrate processing region 1033 from a separate portion of the showerhead, , And thus may be referred to as a dual channel showerhead. An optional second precursor, such as silane or water vapor, can further increase the etch rate of silicon nitride or reduce the etch rate of silicon or silicon oxide when combined with HF in this manner.

4B shows a detail view of the features affecting the process gas distribution through the front plate 1017. Fig. Gas distribution assemblies, such as showerhead 1025 for use in process chamber section 1001, may be referred to as dual-channel showerheads (DCSH) Lt; RTI ID = 0.0 > embodiment < / RTI > The dual channel showerhead includes an etchant that allows separation of etchants outside the substrate processing region 1033 to limit interaction with the chamber components and with each other before the etchants are transferred into the substrate processing region 1033 Processes.

The showerhead 1025 may include a top plate 1014 and a bottom plate 1016. The plates may be coupled to one another to define a volume 1018 between the plates. The coupling of the plates may be to provide first fluid channels 1019 through the upper and lower plates and second fluid channels 1021 through the lower plate 1016. The formed channels may be configured to provide fluid access through the lower plate 1016 only through the second fluid channels 1021 alone from the volume 1018 and the first fluid channels 1019 may be configured to communicate with the plates May be fluidly isolated from the volume 1018 between the second fluid channels 1021. The volume 1018 may be fluidly accessible through the side of the gas distribution assembly 1025. It should be understood that the exemplary system of Figures 4A-4C includes a dual channel showerhead, but alternative dispersion assemblies may be used to maintain the first and second precursors that are fluid isolated prior to the substrate processing region 1033 . For example, perforated plates and tubes below the plate may be used, but other configurations may operate at reduced efficiency or may not provide as uniform treatment as the described dual channel showerhead.

The process gas may flow into the remote region 1015 and then through the first fluid channels 1019 of the showerhead 1025. The process gas may include HF for etching or alkylsilane for deposition. The plasma may not be generated and may not be present in the substrate processing region 1033 for any or all of the operations presented herein. The plasma may not be generated and may not be in the remote region 1015 for any or all of the operations presented herein. In the embodiments, the two regions may be referred to as a plasma free substrate processing region 1033 and a plasma free region 1015. Particularly when a liquid precursor source is used, the process gas may also include a carrier gas such as helium, argon, nitrogen (N ₂ ), and the like. The showerhead may be referred to as a dual channel showerhead due to two separate passages into the substrate processing area. Hydrogen fluoride can flow through the through holes in the showerhead, and the secondary precursor can pass through separate channels in the dual channel showerhead. As described above, the separate channels open into the substrate processing region but not into the remote region. The combined flow rates of the precursors into the substrate processing region may account for from 0.05% to about 20% of the volume of the overall gas mixture; The rest are carrier gases.

4C is a bottom view of the showerhead 1025 for use with the process chamber in the embodiments. The showerhead 1025 corresponds to the showerhead shown in Fig. 4A. Through holes 1031 showing a view of the first fluid channels 1019 may have a plurality of shapes and configurations to control the flow of precursors through the showerhead 1025 and to affect such flow. The small holes 1027 showing a view of the second fluid channels 1021 can be distributed substantially evenly across the surface of the showerhead or even between the through holes 1031, It can help to provide a more uniform mixture of precursors compared to other configurations.

Figures 5A and 5B are schematic diagrams of substrate processing equipment according to embodiments. FIG. 5A shows the hardware used to expose the substrate 1105 to the liquid SAM precursor solution 1115-1 in the tank 1101. FIG. Substrate 1105 can be lowered into solution 1115-1 using a robot and supported by substrate supports 1110 during processing. 5B shows an alternative hardware for rotating the substrate 1105 while pouring the liquid SAM precursor solution 1115-2 from the dispenser 1120 over the top surface of the substrate.

Embodiments of the systems described herein may be incorporated into larger manufacturing systems for making integrated circuit chips. Figure 6 shows one such processing system (mainframe) 2101 of deposition, etch, bake and cure chambers in embodiments. In the figure, a pair of front opening unified pods (load lock chambers 2102) supply substrates of various sizes, which are received by robotic arms 2104, 2108a-f). A second robotic arm 2110 can be used to transfer substrate wafers from the holding region 2106 to the substrate processing chambers 2108a-f and vice versa. Each of the substrate processing chambers 2108a-f may be formed by any one or more of cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, May be prepared to perform a number of substrate processing operations, including the dry etching processes described herein, in addition to degas, orientation, and other substrate processes.

In general, the term "gap" is used without implication that the etched geometry has a large horizontal aspect ratio. From above the surface, the gaps may be circular, elliptical, polygonal, rectangular, or various other shapes. "Trench" is a long gap. A trench can be the shape of a moat around an island of material, whose aspect ratio is the length or perimeter of the moat divided by the width of the moat. The term "via" is used to refer to a low aspect ratio trench (as viewed from above) that may or may not be filled with metal to form a vertical electrical connection. As used herein, the shape-following etching process refers to substantially uniform removal of material on a surface into the same shape as the surface, i.e., the surface of the etched layer and the pre-etched surface are generally parallel. It will be appreciated by those of ordinary skill in the art that the etched interface will not be 100% contour following, thus the term "generally" allows for acceptable tolerances.

As used herein, a "substrate" may be a support substrate on which layers are formed or not. The patterned substrate may be an insulator or semiconductor of various doping concentrations and profiles and may be, for example, a semiconductor substrate of the type used in the manufacture of integrated circuits. Exposed "silicon oxide" of the patterned substrate, but most of SiO _2, for example, may include a concentration of the other elements, components, such as nitrogen, hydrogen, and carbon. In some embodiments, the silicon oxide portions described herein consist of silicon and oxygen, or consist essentially of silicon and oxygen. The exposed "silicon nitride" or "SiN" of the patterned substrate is mostly Si ₃ N _4, but may include concentrations of other elemental components such as, for example, oxygen, hydrogen and carbon. In some embodiments, the silicon nitride portions described herein consist of silicon and nitrogen, or consist essentially of silicon and nitrogen.

The term "precursor" is used to refer to any process gas that participates in a reaction to remove material from a surface or deposit material on a surface. The phrase "inert gas" refers to any gas that does not form chemical bonds when etched or incorporated into the film. Exemplary inert gases include noble gases but may include other gases (unless the chemical bonds are formed when a trace amount is trapped in the membrane).

Although several embodiments have been disclosed, those of ordinary skill in the art will recognize that various modifications, alternative constructions, and equivalents may be utilized without departing from the spirit of the disclosed embodiments. Additionally, numerous well known processes and elements have not been described in order to avoid unnecessarily obscuring the embodiments of the present invention. Accordingly, the above description should not be construed as limiting the scope of the claims.

Where a range of values is provided, it is understood that each intermediate value up to one-tenth of a unit of the lower limit between the upper and lower limits of the range is also specifically disclosed, unless the context clearly indicates otherwise. Each small range of between any stated value or intermediate value within the stated range and any other stated value or intermediate value within the stated range is encompassed. The upper and lower limits of these smaller ranges may be independently included within the range or excluded, and each range that includes either or both of these upper and lower limits, or both, Are also encompassed within the claims, subject to any specifically excluded limitations within the claims. Where the stated ranges include one or both of the upper and lower limits, the scope excluding one or both of these included limits is also included.

As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a "process" includes a plurality of such processes, and references to "dielectric material" refer to one or more dielectric materials and their equivalents known to those of ordinary skill in the art And so on.

It is also to be understood that the word "comprises," " comprise, "" include," Or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims (15)

1. A method for removing silicon nitride from a patterned substrate,
(i) selectively forming a partial layer over the silicon oxide portions of the patterned substrate, without forming over the silicon nitride portions of the patterned substrate, wherein the partial layer does not apply any type of lithography after the formation Patterned; And
(ii) selectively etching silicon nitride from the silicon nitride portions faster than etching the silicon oxide from the silicon oxide portions
≪ / RTI > 2. The method of claim 1, wherein selectively etching the silicon nitride occurs without application of lithography. The method of claim 1, wherein step (i) occurs prior to step (ii). 4. The method of claim 3, wherein step (i) and step (ii) are repeated an integer number of times. 3. The method of claim 1, wherein step (i) and step (ii) occur simultaneously. A method of etching silicon nitride from a patterned substrate,
Providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion;
Exposing the patterned substrate to an alkylsilane precursor;
Forming a self-assembled monolayer on the exposed silicon oxide portion without forming on the exposed silicon nitride portion;
Exposing the patterned substrate to a halogen-containing precursor;
Etching the silicon nitride from the exposed silicon nitride portion with a silicon nitride etch rate while removing silicon oxide from the exposed silicon oxide portion with a silicon oxide etch rate of less than 1 percent of the silicon nitride etch rate
≪ / RTI > 7. The method of claim 6, further comprising removing the self-assembled monolayer after etching the silicon nitride. 7. The method of claim 6, wherein forming the self-assembled monolayer occurs prior to etching the silicon nitride. 7. The method of claim 6, wherein exposing the patterned substrate to alkylsilane precursors occurs simultaneously with exposing the patterned substrate to a halogen-containing precursor. 7. The method of claim 6, wherein both forming the self-assembled monolayer and etching the silicon nitride occur while the patterned substrate is in a plasma-free substrate processing region. . 7. The method of claim 6, wherein the halogen-containing precursor is anhydrous HF. 7. The method of claim 6, wherein each molecule of the self-assembled monolayer includes a head moiety and a tail moiety, the head moiety having a covalent bond with the exposed silicon oxide moiety And wherein the tail moieties extend in a direction away from the patterned substrate. A method of selectively depositing an additional layer on a patterned substrate,
Providing a patterned substrate having an exposed silicon nitride portion and an exposed silicon oxide portion;
Selectively forming a self-assembled monolayer on the exposed silicon oxide portion without forming on the exposed silicon nitride portion;
Exposing the patterned substrate to a deposition precursor; And
Depositing additional material on the exposed silicon nitride portion at least 100 times faster than depositing on the exposed silicon oxide portion
≪ / RTI > 14. The method of claim 13, wherein depositing the additional material occurs after selectively forming the self-assembled monolayer. 14. The method of claim 13, wherein selectively forming the self-assembled monolayer, and depositing additional material on the exposed silicon nitride portion, are performed while the patterned substrate is in the plasma- , Way.

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