KR20180062574A - Display device - Google Patents

Abstract

The present invention relates to a display device in which a bezel size is reduced to enhance design aesthetic appearance. According to an embodiment of the present invention, the display device comprises: a plurality of data lines located in a display panel in a first direction; a plurality of first gate lines located in the display panel in the first direction at a different layer from the plurality of data lines; and a plurality of second gate lines which is located in the display panel in a second direction at a different layer from the plurality of first gate lines and is paired with at least one of the first gate lines while being electrically connected through a contact hole.

Description

Display device {DISPLAY DEVICE}

TECHNICAL FIELD The present invention relates to a display device for displaying an image.

As portable electronic devices such as mobile communication terminals and notebook computers are developed, there is an increasing demand for display devices applicable thereto.

Examples of the display device include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display device, an organic light emitting diode (OLED) Display device) have been developed.

When a gate driver for applying a gate signal is fabricated as a separate integrated circuit and connected to a display panel or when a gate driver is mounted on a display panel by a GIP method or the like, the display device increases the bezel size on the left and right sides of the display panel can do.

It is a technical object of the present invention to provide a display device having a reduced size of a bezel disposed at the periphery of a display panel.

 It is a technical object of the present invention to provide a display device with high design aesthetics.

A display device according to an embodiment includes a plurality of data lines arranged in a first direction in a display panel and a plurality of data lines in a display panel and a plurality of first gate lines A plurality of first gate lines and a plurality of second gate lines arranged in the display panel in a second direction in another layer and paired with the plurality of first gate lines through at least one line to electrically connect through the contact holes, .

The display device according to an embodiment may further include a plurality of pixels arranged in a plurality of regions where the plurality of data lines and the plurality of second gate lines cross each other on the display panel and a non- And a driver connected to the plurality of first gate lines to supply a scan signal to the plurality of pixels and to supply a data voltage to the plurality of pixels in connection with the plurality of data lines.

The display device according to the embodiments can reduce the size of the bezel disposed at the outer periphery of the display panel.

The display device according to the embodiments can improve the design aesthetics.

1 is a view schematically showing a display device according to an embodiment.
2A and 2B show one drive IC included in the drive unit.
3A is a diagram showing a pixel structure of a display device according to an embodiment.
3B is a diagram showing a pixel structure of a display device according to another embodiment.
3C is a diagram showing a pixel structure of a display device according to another embodiment.
4 is a diagram showing a pixel structure of a display device according to another embodiment.
5 is an enlarged view of region A in Fig.
6 is an enlarged view of the area B in Fig.
7A is a cross-sectional view taken along line I-I 'of FIG.
7B is a cross-sectional view taken along line II-II 'of FIG.
8 is an enlarged plan view of a non-display area of the display device according to still another embodiment.
9A is a cross-sectional view taken along line III-III 'of FIG.
FIG. 9B is a cross-sectional view taken along the line IV-IV 'in FIG.
10 is a plan view of a part of a display device according to still another embodiment.
11 is a cross-sectional view showing a non-display region of the display device of Fig.
12 is a diagram showing a non-display region of a display device including a common voltage link region including only a base layer.
13 is a diagram showing a pixel structure of a display device according to yet another embodiment.

In the drawings, the same reference numerals have been used for the same components, even if they are shown in different drawings.

Meanwhile, the meaning of the terms described in the present specification should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the rights is not limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the first item, the second item and the third item Means a combination of all items that can be presented from two or more.

In describing an embodiment of the present invention, when it is described that some structure (electrode, line, wiring, layer, contact) is disposed over or on another structure and under or under, It should be interpreted as including the case where the third structure is interposed between these structures as well as when they are in contact with each other.

Hereinafter, a display device according to embodiments will be described with reference to the accompanying drawings.

1 is a view schematically showing a display device according to an embodiment.

1, a display device 1 according to an embodiment includes a display panel 10 in which a plurality of pixels are arranged in a matrix form, a driver 40 for driving the display panel 10, And a printed circuit board 30 (PCB) on which a control unit (not shown) for supplying a control signal for driving the driving unit 40 is mounted. The driver 40 may be implemented as a plurality of drive ICs.

The display panel 10 includes a display region (active region) 12 for displaying an image and a non-display region (non-active region) 14 for displaying no image.

2A and 2B show one drive IC included in the drive unit.

The drive IC 40 may be disposed on a COG (Chip On Glass) or a COF (Chip On Flexible Printed Circuit).

Referring to FIG. 2A, the drive IC 40 includes a gate driver logic and a data driver logic merged into one chip. 2B, in the drive IC 40 of the display device 1 according to the embodiment, the data drive IC 42 and the gate drive IC 43 are integrated into one chip.

The data drive logic or data drive IC 42 generates an analog data voltage to be supplied to the pixels using the data control signal and digital image data applied from the control unit mounted on the printed circuit board 30. [

The gate drive logic or gate drive IC 43 generates a scan signal (gate signal) for switching the thin film transistors disposed in the pixels by using a gate control signal applied from a control unit mounted on the printed circuit board 30 do.

On both sides of the drive IC 40, a plurality of link lines 41 are arranged. Here, the plurality of link lines 41 includes a plurality of gate link lines 45 and a plurality of data link lines 44.

The drive IC 40 receives a gate signal from the control unit through a plurality of gate link lines 45 and supplies the generated scan signal to the pixels arranged on the display panel.

The drive IC 40 receives the data control signal and the digital image data from the control unit through the plurality of data link lines 44 and outputs the analog data voltage generated according to the digital image data to the pixels arranged on the display panel Supply.

Since the data line DL and the plurality of first gate lines VGL and vertical gate lines arranged on the display panel 10 are not the same number, the gate line line 45 and the plurality of data link lines 44 must be connected to each other, Are not alternately arranged in the same number.

But may be arranged in units of one gate link line 45 and one or more data link lines 44, depending on the pitch and resolution of the pixels. The same number of data link lines may be disposed between gate link lines 45, but a different number of data link lines may be alternately arranged. Two data link lines 44 may be disposed on one gate link line 45 and three data link lines 44 may be disposed on the next one gate link line 45, for example. The number relationship of the gate link line 45 and the data link line 44 may be the same as the number relationship of the first gate line VGL and the data line DL.

Hereinafter, the structure of the display panel 10 of the present invention will be described in detail with reference to the drawings.

3A is a diagram showing a pixel structure of a display device according to an embodiment.

1 and 3A, a display panel 10 includes a display area 12 in which a plurality of pixels for displaying an image are arranged, a display area 12 in which a plurality of drive ICs 40 are arranged, And a display area 14.

A plurality of first gate lines (VGL), a plurality of second gate lines (HGL), and a plurality of data lines (DL) are arranged in the display region (12) of the display panel (10).

A plurality of pixels are defined by a plurality of first gate lines (VGL), a plurality of second gate lines (HGL), and a plurality of data lines (DL). Each pixel may be an element for displaying an image, for example, a passive element such as a liquid crystal cell, or an active element such as an organic light emitting element. Hereinafter, it is exemplarily described that each pixel is a liquid crystal cell, but the present invention is not limited thereto.

2B, the drive IC 40, in which the gate drive IC (or gate drive logic) and the data drive IC (or data drive logic) are integrated into one chip, For example, on the upper side. 2B, the drive IC 40 is disposed on the upper side of the display panel 10, but the present invention is not limited thereto. The drive IC 40 may be disposed on the other side of the display panel 10, for example, .

3A, the display device 1 includes a plurality of data lines DL arranged in the first direction in the display panel 10, a plurality of data lines DL arranged in the first direction in the display panel 10, A first gate line (VGH); A plurality of second gate lines HGL arranged in the second direction in the display panel 10 and a plurality of data lines DL and a plurality of second gate lines HGL crossing the display panel 10 And a plurality of pixels (P) arranged in the region.

A plurality of first gate lines (VGL) and a plurality of data lines (DL) are arranged in a first direction in the display panel (10). The plurality of first gate lines (VGL) and the plurality of data lines (DL) may be arranged in the display panel (10) in a first direction. In FIG. 3A, the plurality of data lines DL are shown as being overlapped with the plurality of data lines DL in the first direction, but they may not overlap or overlap each other.

The plurality of second gate lines HGL are arranged to intersect the plurality of first gate lines VGL and the plurality of data lines DL.

The display device 1 may correspond to a plurality of first gate lines VGL arranged in the first direction and a plurality of second gate lines HGL arranged in the second direction in a one-to-one correspondence. On the other hand, in the display device 1, a plurality of first gate lines VGL and a plurality of second gate lines HGL may correspond to n (n is a natural number greater than 2): 1. For example, a plurality of first gate lines (VGL) and a plurality of second gate lines (HGL) correspond in a 2: 1 relationship so that two first gate lines (VGL) correspond to one second gate line (HGL) .

Here, the plurality of second gate lines (HGL) arranged in the second direction are located in the first layer, and the plurality of first gate lines (VGL) and the plurality of data lines (DL) arranged in the first direction are The second layer and the third layer.

The plurality of first gate lines (VGL) arranged in the first direction and the plurality of second gate lines (HGL) arranged in the second direction are arranged in different layers with an insulating layer interposed therebetween, The gate line VGL and the plurality of second gate lines HGL can be electrically connected through the contact holes CNT1 and CNT2 in pairs in at least one line. The contact holes CNT1 and CNT2 may be disposed on the first gate line VGL which is linear, but may be disposed on a part of the protruding region of the first gate line VGL as shown in FIG. 3A.

Specifically, the first gate line VGL1 arranged in the first direction and the first gate line HGL1 arranged in the second direction are electrically connected through the first contact hole CNT1. Thus, a pair of vertical gate lines and horizontal gate lines, that is, the first vertical gate line VGL1 and the first horizontal gate line HGL1 are electrically connected through the first contact hole CNT1.

The second first gate line VGL2 arranged in the first direction and the second gate line HGL2 arranged in the second direction are electrically connected to each other through the second contact hole CNT2 in the overlapping region Respectively. In this way, a pair of vertical gate lines and horizontal gate lines, that is, a second vertical gate line VGL2 and a second horizontal gate line HGL2 are electrically connected through the second contact hole CNT2.

The n first gate lines VGL and the n second gate lines HGL are electrically connected to each other through the contact holes CNT1, CNT2, ..., CNTn in the same structure as described above.

The first and second expressions described in the foregoing description are for illustrating the order and relationship among a plurality of lines and do not indicate that the first expression is the first among the entire lines, . Hereinafter, the meanings of the first and second expressions are applied equally to the contents of the specification.

The plurality of first gate lines VGL arranged in the first direction are connected to the plurality of gate link lines 45 shown in Figs. 2A and 2B, respectively. Thus, the scan signal output from the drive IC 40 is applied to the plurality of first gate lines VGL. The scan signal is supplied to the TFTs of the plurality of pixels arranged on the display panel 10 via the plurality of second gate lines HGL connected to the plurality of first gate lines VGL, (turn-on). At this time, the scan signals are supplied to all the pixels of the display panel, and are sequentially supplied in units of one horizontal line.

On the other hand, the plurality of data lines DL arranged in the first direction are connected to the plurality of data link lines 44 shown in Figs. 2A and 2B, respectively. Thus, the data voltage Vdata output from the drive IC 40 is applied to the plurality of data lines DL.

The data voltage Vdata is supplied to the source electrode of the thin film transistor arranged on the display panel 10 via the data line DL and the data voltage Vdata supplied to the source electrode And then supplied to the pixel electrode via the drain electrode.

A scan signal is applied to the pixel through the first gate line arranged in the first direction and a data voltage Vdata is applied to the pixel through the data line arranged in the first direction, The width of the bezel can be reduced by deleting the link line and the gate driver disposed in the non-display area of the display device.

The display device 101 can be arranged such that the data line DL and the first gate line VGL are overlapped with each other to reduce the width of the wiring portion, thereby increasing the aperture ratio.

3B is a diagram showing a pixel structure of a display device according to another embodiment.

Referring to FIG. 3B, a plurality of first gate lines VGL may be connected to at least one of the plurality of first gate lines VGL and the plurality of second gate lines HGL, And may further include patterns CP1 and CP2.

And can be electrically connected through the contact holes CNT1 and CNT2 in the region where the connection patterns CP1 and CP2 and the second gate line HGL overlap.

The connection patterns CP1 and CP2 may be located on both sides of the plurality of first gate lines VGL and the non-display areas of two adjacent pixels P, respectively.

Specifically, the first first gate line (VGL1) arranged in the first direction is located on each of the non-display regions of the two pixels (P) adjacent to the first first gate line (VGL1) And two connection patterns CP1 and CP2 overlapping the two gate lines HGL1 and extending in the second direction. Can be electrically connected through the contact holes CNT1 and CNT2 in a region where the connection patterns CP1 and CP2 and the first second gate line HGL1 overlap.

The second first gate line VGL2 arranged in the first direction is located on both sides of the non-display areas of the two pixels P adjacent to each of the second first gate lines VGL2, And may include two connection patterns CP1 and CP2 which overlap the gate line HGL2 and extend in the second direction. Can be electrically connected through the contact holes CNT1 and CNT2 in a region where the connection patterns CP1 and CP2 and the second second gate line HGL2 overlap.

It can be electrically connected through the contact holes CNT1 and CNT2 in the region where the connection patterns CP1 and CP2 and the respective second gate lines HGL overlap with each other with the same structure as described above.

Since the first gate line VGL and the second gate line HGL are directly connected to the connection patterns CP1 and CP2 so that the first gate line VGL and the second gate line HGL are contacted The pattern may not be recognized along the points, i.e., the contact holes CNT1 and CNT2.

3C is a diagram showing a pixel structure of a display device according to another embodiment.

Referring to FIG. 3C, the display device 1 overlaps each of the plurality of second gate lines HGL to form a connection pattern (hereinafter referred to as a connection pattern) in non-display areas of the pixels P in which the connection patterns CP1 and CP2 are not located. CP1 and CP2, and the auxiliary pattern AP separated from the auxiliary pattern AP2. At this time, the auxiliary pattern AP is electrically connected to each of the plurality of second gate lines HGL through another contact hole CNT3.

Specifically, in the non-display region of each of the pixels P13 and P14 which are overlapped with the first second gate line HGL1 and in which the connection patterns CP1 and CP2 are not located, the connection patterns CP1 and CP2 are separated from the connection patterns CP1 and CP2, And may further include an auxiliary pattern (AP). At this time, the auxiliary patterns AP are electrically connected to the first second gate line HGL1 through the other contact holes CNT3.

The connection patterns CP1 and CP2 are overlapped with the second second gate lines HGL2 so that the connection patterns CP1 and CP2 are separated from the connection patterns CP1 and CP2 in the non-display areas of the pixels P21 and P24, And may further include a pattern (AP). At this time, each of the auxiliary patterns AP is electrically connected to the second second gate line HGL1 through another contact hole CNT3.

Each auxiliary pattern AP is overlapped with each of the plurality of second gate lines HGL so that each auxiliary pattern AP overlaps each of the plurality of second gate lines HGL in the non-display area of each of the pixels P in which the connection patterns CP1 and CP2 are not located. Can be electrically connected through the contact holes CNT1 and CNT2 in the region where the auxiliary pattern AP and each second gate line HGL overlap.

In addition, since the contact area between the first gate line (VGL) and the second gate line (HGL) is the same as the contact area, the difference in the pixel charge voltage does not occur due to the change of the parasitic capacitance.

4 is a diagram showing a pixel structure of a display device according to another embodiment.

4, a display device 101 according to another embodiment includes a plurality of data lines DL arranged in a first direction in a display panel 110, a plurality of data lines DL arranged in a first direction in a display panel 110, A plurality of second gate lines HGL arranged in a second direction in the display panel 110, a plurality of data lines DL and a plurality of second gate lines HGL arranged in the display panel 110, And a plurality of pixels P arranged in a plurality of regions in which the second gate lines HGL of the plurality of pixels cross.

The display device 101 according to another embodiment includes a common voltage line VCL1 to which the common voltage Vcom is applied. The common voltage line VCL1 may be formed adjacent to the upper side or the lower side of the gate wiring HGL and may be substantially parallel to the gate wiring HGL, but is not limited thereto. The common voltage line VCL1 is electrically connected to the common voltage link region VCL2 located on one side of the display panel as described later with reference to Fig.

In the case of a liquid crystal display device, the display device 101 may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) mode.

In the IPS mode and the FFS mode, the pixel electrode 112 and the common electrode 114 are arranged on the lower substrate to control the alignment of the liquid crystal layer by the electric field between the pixel electrode 112 and the common electrode 114 Is a horizontal electric field system. The display device 101 according to another embodiment can be applied regardless of the mode, but the IPS mode will be described as an example.

Referring again to FIG. 4, in the display device 101 according to another embodiment, each of the plurality of pixels P includes a pixel electrode 112 to which a data voltage Vdata is applied, a common electrode Vdata to which a common voltage Vcom is applied, (114), a storage capacitor (Cst), and a thin film transistor (Tr) as a switching element. The thin film transistor Tr may be composed of a gate electrode 116a, a semiconductor layer (116d shown in Fig. 7A), a source electrode 116b and a drain electrode 116c.

Here, the semiconductor layer 116d of the thin film transistor Tr may be formed of amorphous silicon (a-Si), low temperature polysilicon (LTPS) or an indium gallium zinc oxide (IGZO) But is not limited thereto.

The display device 101 including the above-described configuration changes the arrangement state of the liquid crystal in each pixel according to the electric field arranged between the pixel electrode 112 and the common electrode 114, and controls the backlight unit (not shown) To display an image by adjusting the transmittance of the light.

One of the pixel electrode 112 and the common electrode 114 is patterned to include a plurality of slits. The pixel electrode 112 and the common electrode 114 may have a folded structure in a first direction. Accordingly, the viewing angle of the display device 101 is further improved as compared with the mono-domain because the liquid crystal molecules are arranged in two directions to form a two-domain. However, the pixel electrode 112 and the common electrode 114 are not limited to a two-domain structure, may have a multi-domain structure of two or more domains, and may have no bending structure. The pixel electrode 112 and the common electrode 114 may be located on the same or different layers.

A plurality of first gate lines (VGL) and a plurality of data lines (DL) are arranged in the display panel (110) in a first direction. The plurality of first gate lines VGL and the plurality of data lines DL have a folded structure in the first direction like the pixel electrodes 112 and the common electrodes 114. [

The plurality of second gate lines HGL are arranged to cross the plurality of first gate lines VGL and the plurality of data lines DL.

The common voltage line VCL1 may be disposed adjacent to the upper or lower layer of the second gate line HGL, for example, the upper side, and may be substantially parallel to the second gate line HGL.

5 is an enlarged view of region A in Fig. 6 is an enlarged view of the area B in Fig.

Referring to FIGS. 5 and 6, a plurality of first gate lines VGL extend from a plurality of first gate lines VGL to a plurality of second gate lines HGL, respectively, And one connection pattern (CP1, CP2).

Are electrically connected through the contact holes CNT1 and CNT2 in the region where the connection patterns CP1 and CP2 and the second gate line HGL overlap. The connection patterns CP1 and CP2 are located on both sides of the non-display areas of the two pixels P adjacent to each of the plurality of first gate lines VGL.

The display device 101 according to another embodiment overlaps each of the plurality of second gate lines HGL to form connection patterns CP1 and CP2 in non-display areas of the pixels P in which the connection patterns CP1 and CP2 are not located, , CP2, and an auxiliary pattern (AP) separated from each other. At this time, the auxiliary pattern AP is electrically connected to each of the plurality of second gate lines HGL through another contact hole CNT3.

7A is a cross-sectional view taken along line I-I 'of FIG. 7B is a cross-sectional view taken along line II-II 'of FIG.

7A and 7B, a plurality of first gate lines VGL are arranged in a first direction on a substrate 111 in a display panel 110 in a layer different from the plurality of data lines DL. The first gate line VGL overlaps the first gate line VGL in a different layer from the data line DL and the width of the first gate line VGL may be wider than the width of each data line DL to be overlapped.

The second gate line HGL is disposed in the display panel 110 in a second direction at a plurality of first gate lines VGL and another layer.

More specifically, the display device 101 includes a first insulating layer 118 located on the plurality of second gate lines HGL, a second insulating layer 120 located on the plurality of data lines, And a third insulating layer 122 overlying the layer 120. At this time, the plurality of first gate lines (VGL) may be located on the third insulating layer 122.

The plurality of first gate lines VGL are connected to the plurality of second gate lines HGL through the contact holes CNT1 and have a first layer VGLa made of a metal or a metal alloy, And a second layer VGLb made of the same material as the pixel electrode 112 of each pixel.

If the pixel electrode 112 of each pixel includes a metal oxide, for example, ITO or IZO, the second layer VGLb may also be made of a metal oxide. The pixel electrode 112, the common electrode 114 and the second layer VGLb are formed in the display panel 110 by the same process using the same material as the common electrode 114. [ .

A color layer 124 of a specific color corresponding to each pixel P may be further included in the display region of each pixel P under the third insulating layer 122. [ The red color layer 124a may be located on the left side of the third insulating layer 122 and the green color layer 124b may be located on the right side of the third insulating layer 122 as shown in FIG. Since the color layers 124a and 124b are formed under the third insulating layer 122, it is not necessary to provide a separate color filter substrate.

On the other hand, two or more color layers 126a and 126b may be sequentially disposed in the non-display region of each pixel P under the third insulating layer 122. [ For example, as shown in FIG. 7A, blue and red color layers 126a and 126b may be sequentially disposed in a non-display region of each pixel P below the third insulating layer 122. [ Since the color layers 126a and 126b of two or more specific colors are sequentially disposed in the non-display region of each pixel P below the third insulating layer 122, the black matrix may serve as a black matrix. A black specific layer, for example, a black matrix, may be disposed in the non-display region of each pixel P below the third insulating layer 122. [

8 is an enlarged plan view of a non-display area of the display device according to still another embodiment.

Referring to FIG. 8, a plurality of second gate lines HGL arranged in a second direction in the display device 201 according to another embodiment are arranged in a first layer, and a plurality of second gate lines HGL arranged in a second direction The first gate line VGL and the plurality of data lines DL are arranged in the same second layer.

The plurality of first gate lines VGL and the plurality of second gate lines HGL arranged in the first direction are disposed in different layers with an insulating layer interposed therebetween, And a plurality of second gate lines (HGL) are selectively connected through contact holes (CNT) in regions overlapping each other.

9A is a cross-sectional view taken along line III-III 'of FIG. FIG. 9B is a cross-sectional view taken along the line IV-IV 'in FIG.

The display device 201 according to another embodiment includes a plurality of second gate lines HGL located on a substrate 211, a first insulating layer 218 located on the plurality of second gate lines HGL, And a third insulating layer 222 disposed on the second insulating layer 220 and the second insulating layer 220 on the plurality of data lines. The first gate line is also located on the second insulating layer 220.

The second gate line HGL and the first gate line VGL are electrically connected to the third insulating layer 222 and the first contact hole CNT1 and the third insulating layer 218, Through the jumping patterns JP disposed between the first contact holes CNT1 and the second contact holes CNT2 through the second contact holes CNT2 disposed in the first insulating layer 222 and the second insulating layer 220. [ And can be electrically connected.

If the jumping pattern JP disposed between the two first contact holes CNT1 and the second contact holes CNT2 is made of the same metal oxide as the pixel electrode 212, the resistivity of the jumping pattern JP can be increased have. In addition, when the second gate line HGL is a single line, the wiring resistance of the second gate line HGL may be relatively large.

In addition, since the first gate line VGL and the data line DL are arranged side by side in the same layer, the width of the wiring portion between the first gate line VGL and the data line DL can be increased.

A pattern can be recognized along the contact hole CNT at a point at which the first gate line VGL and the second gate line HGL are in contact with each other when the display panel is driven. In the region where the first gate line (VGL) and the second gate line (HGL) are in contact with each other, a difference in contact area occurs between the pixel and the non-pixel region. Therefore, a change in parasitic capacitance occurs, It can be recognized as stain.

On the other hand, in the display device 101 according to another embodiment described with reference to FIGS. 5 to 7B, the data line DL and the first gate line VGL are arranged so as to overlap with each other, The aperture ratio can be increased.

The display device 101 according to another embodiment described with reference to FIGS. 5 to 7B is a display device in which the second gate line HGL is made of a metal or a metal alloy having a low resistivity through the first and second contact holes CNT1 and CNT2 And the second gate line HGL is electrically connected to the auxiliary pattern AP including the metal or metal alloy having a low resistivity through the third contact hole CNT3 and the auxiliary pattern AP electrically connected to the connection pattern CP1, And wiring resistances of the second gate lines, which are formed by the second gate lines and the connection patterns CP1 and CP2 and the auxiliary patterns AP, can be reduced.

Since the first gate line VGL and the second gate line HGL are directly connected to the connection patterns CP1 and CP2 so that the first gate line VGL and the second gate line HGL are contacted The pattern may not be recognized along the point, i.e., the contact hole CNT.

In addition, since the contact area between the first gate line (VGL) and the second gate line (HGL) is the same as the contact area, the difference in the pixel charge voltage does not occur due to the change of the parasitic capacitance.

10 is a plan view of a part of a display device according to still another embodiment.

10, a display device 301 according to another embodiment includes a plurality of data lines DL, a plurality of first gate lines VGL, a plurality of second gate lines A common voltage line VCL1 and a plurality of pixels P arranged in a plurality of regions where a plurality of data lines DL and a plurality of second gate lines HGL cross the display panel 310 And may be the same as the display device 101 according to the other embodiment described with reference to Figs.

The common voltage line VCL1 is electrically connected to the common voltage link region VCL2 located at one side of the display panel 310 as described above in the display device 301 according to another embodiment.

The common voltage link region VCL2 is located at one side of the display panel 310 and is connected to a common voltage line VCL1 for applying a common voltage to the common electrode 314. [

The common voltage link region VCL2 includes a base layer VCL21 made of the same material as the second gate line HGL and an additional layer VCL22 made of the same material as the first layer VGL1 of the first gate line VGL ).

11 is a cross-sectional view showing a non-display region of the display device of Fig. 12 is a diagram showing a non-display region of a display device including a common voltage link region including only a base layer.

11, in the case where the display device 301 is a liquid crystal display device, the seal 330 is formed in a non-display area where pixels are formed, (341) and the lower substrate (342) are bonded together. The chamber 330 may be disposed on a black matrix 344 located on the rim of the upper substrate 341 to prevent light leakage. The chamber 330 may be located between the dams 346. This dam 346 can be formed by the same process with the same material as a general column space existing in the display panel.

As shown in FIG. 11, the ground link region GND and the common voltage link region VCL2 may overlap with the chamber 330 in order to reduce the increase of the bezel size. Between the ground link region GND and the common voltage link region VCL2 and the chamber 330, one of the insulating layers 340 existing in the display region may be positioned.

On the other hand, even if the line width of the seal 330 can be reduced by improving the material of the seal 330, the bezel width is reduced due to the wiring resistance of the common voltage link region VCL2 including only the base layer VCL21 shown in Fig. 12 There was a limit.

The common voltage link region VCL2 is connected to the first layer VGL1 of the first gate line VGL and the base layer VCL21 made of the same material as the second gate line HGL as described with reference to Fig. The bezel width W11 < W21 is further reduced as compared with the case where only the base layer VCL21 is included in the common voltage link region VCL2 shown in Fig. 12 since the additional layer VCL22 made of the same material is included, Can be implemented.

13 is a diagram showing a pixel structure of a display device according to yet another embodiment.

13, a display apparatus 401 according to another embodiment includes a display panel 410 in which a plurality of pixels are arranged in a matrix form, a driving unit 440 for driving the display panel 410, And a printed circuit board (PCB) 430 on which a control unit (not shown) for supplying a control signal for driving the driving unit 440 is mounted. The driving unit 440 may be implemented by a plurality of drive ICs.

13, the display device 401 according to another embodiment rotates the pixel structure shown in FIG. 1 by 90 degrees to reduce the ratio occupied by the vertical gate line (VGL) in the entire area of each pixel to secure the aperture ratio Respectively.

A plurality of first gate lines (VGL) and a plurality of data lines (DL) are arranged from the upper side to the lower side in the first direction. The plurality of second gate lines HGL are arranged from the left side to the right side (or from the right side to the left side) in the second direction.

The display device according to the embodiments has been described with reference to the drawings.

The display device according to the above-described embodiments can reduce the size of the left and right sides of the bezel arranged to surround the non-display area of the display panel. By reducing the size of the bezel, a relatively large display screen can be provided to the user, and the design aesthetics of the display device can be enhanced.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1, 101, 201, 301, 401: display device 10: display panel
30: printed circuit board 40:
VGL: first gate line HGL: second gate line
DL: Data line VCL: Common voltage line

Claims (12)

A plurality of data lines arranged in a first direction in a display panel;
A plurality of first gate lines arranged in the first direction in a layer different from the plurality of data lines in the display panel;
A plurality of first gate lines and a plurality of second gate lines arranged in the display panel in a second direction in a second direction and electrically connected to the plurality of first gate lines through the contact holes, Gate lines;
A plurality of pixels arranged on the display panel in a plurality of regions in which the plurality of data lines and the plurality of second gate lines cross each other;
A plurality of first gate lines connected to the plurality of data lines to supply scan signals to the plurality of pixels, And a driver for supplying a voltage. The method according to claim 1,
Wherein the plurality of first gate lines and the plurality of second gate lines are arranged in a one-to-one correspondence with the same number. The method according to claim 1,
The plurality of first gate lines each further include at least one connection pattern extending from the plurality of first gate lines in each of the plurality of second gate lines in the second direction
Wherein the connection pattern is electrically connected to the second gate line through the contact hole in a region where the connection pattern overlaps with the second gate line. The method of claim 3,
Wherein the connection pattern is located on both sides of non-display areas of two pixels adjacent to each of the plurality of first gate lines. 5. The method of claim 4,
Further comprising an auxiliary pattern separated from the connection pattern in a non-display area of each of the pixels overlapping the plurality of second gate lines and not having the connection pattern,
Wherein the auxiliary pattern is electrically connected to each of the plurality of second gate lines through a contact hole. The method according to claim 1,
Wherein each of the plurality of first gate lines is overlapped in the first direction at a layer different from that of one of the plurality of data lines,
Wherein a width of each of the plurality of first gate lines is wider than a width of each data line to be overlapped. The method according to claim 1,
A first insulating layer located on the plurality of second gate lines;
A second insulating layer located on the plurality of data lines; And
Further comprising a third insulating layer located on the second insulating layer,
And the plurality of first gate lines are located on the third insulating layer.
8. The method of claim 7,
Wherein the plurality of first gate lines comprise:
A first layer connected to the plurality of second gate lines through the contact hole and made of a metal or a metal alloy and a second layer formed on the first layer and made of the same material as the pixel electrode of the pixel Device. 8. The method of claim 7,
Further comprising a color layer of a specific color corresponding to each pixel in a display region of each pixel below the third insulating layer,
Wherein at least two color layers of a specific color are sequentially disposed in a non-display region of each pixel below the third insulating layer. The method according to claim 1,
The plurality of pixels including a pixel electrode and a common electrode,
A common voltage line for applying a common voltage to the common electrode in the second direction in a non-display region of the display panel, and a common voltage link region located at one side of the display panel and connected to the common voltage line In addition,
Wherein the common voltage link region includes a base layer made of the same material as the second gate line and an additional layer made of the same material as the first layer of the first gate line. The method according to claim 1,
The driving unit may be arranged in a COG (Chip On Glass) or COF (Chip On Flexible Printed Circuit)
Wherein the gate driver logic for generating the scan signal and the data driver logic for generating the data voltage are integrated into one chip,
Wherein the data drive IC and the gate drive IC are integrated into one chip. The method according to claim 1,
Wherein the plurality of pixels are a plurality of liquid crystal cells or organic light emitting elements.

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