KR20180058277A - EPROM device with 2-bit cells and method of programing EPROM device - Google Patents

Abstract

An EPROM device including 2-bit cells in which three transistors can store two bits of data is presented. The EPROM device includes unit cells arranged at the intersections of bit lines and cell select lines and including an access transistor and first and second floating gate transistors; a first ground selection transistor which controls connection between the drains of the first floating gate transistors and the ground; and a second ground selection transistor which controls connection between the drains of the second floating gate transistors and the ground.

Description

[0001] EPROM device with 2-bit cells and method [0002]

The present invention relates to non-volatile memory devices, and more particularly, to EPROM devices and programming methods that include 2-bit cells.

Unlike a typical random access memory (RAM) device, a nonvolatile memory device can retain stored data even when power is removed. As an example of a nonvolatile memory device capable of holding data, a read-only memory (ROM) device is applied to various electronic devices. The ROM device has memory nonvolatile characteristics and has characteristics such that stored information is not removed even if the power source is removed.

The ROM device can be classified according to whether or not it is possible to input data from the user side. A programmable ROM (Programmable ROM) device is sold in an initial state in which data is not programmed according to the use, so that the user can directly program necessary information on the spot. A mask ROM (mask ROM) device is pre-programmed with data according to a user's order at the time of manufacture. One-time programmable ROM (OTP ROM) or multi-time programmable ROM (MTP) and PROM devices are used depending on the input method. There have been attempts to implement a PROM device as an element that stores data as an electric charge such as an EPROM (Electrically Programmable ROM) or an EEPROM (Electrically Erasable PROM).

The present application seeks to provide an EPROM device in which three transistors include 2-bit cells capable of storing 2-bit data.

The present application proposes a method of programming an EPROM device including two bits cells in which three transistors can store two bits of data.

One aspect of the present application relates to a semiconductor memory device comprising bit lines and cell select lines crossing the bit lines; An access transistor having unit cells arranged at intersections of the bit lines and the cell selection lines and having a source coupled to the bit line and a gate coupled to the cell selection line, Unit cells including first and second floating gate transistors having sources coupled to a drain of the access transistor; A first ground selection transistor disposed between the drains of the first floating gate transistors and a ground and interrupting a connection with the ground; And a second ground selection transistor disposed between the drains of the second floating gate transistors and the ground and interrupting the connection with the ground.

Another aspect of the present application relates to a semiconductor memory device comprising bit lines and cell select lines crossing the bit lines; An access transistor having unit cells arranged at intersections of the bit lines and the cell selection lines and having a source coupled to the bit line and a gate coupled to the cell selection line, Unit cells including first and second floating gate transistors having sources coupled to a drain of the access transistor; A first ground selection transistor disposed between the drains of the first floating gate transistors and a ground and interrupting a connection with the ground; And a second ground selection transistor disposed between the drains of the second floating gate transistors and the ground and interrupting a connection to the ground, wherein in the program operation of the EPROM device, Applying a program bit line voltage to the source of the access transistor through the bit line and turning on the access transistor having a gate coupled to any one of the cell select lines, The drain of the first floating gate transistor is disconnected from the ground by turning on the ground select transistor to connect the drain of the first floating gate transistor to the ground and turning off the second ground select transistor to disconnect the drain of the second floating gate transistor from the ground, EPROM devices that selectively program transistors We suggest how to program.

Embodiments of the present application can provide an EPROM device in which three transistors can contain two bits of data that can store two bits of data, thereby improving the memory density in a limited cell area.

FIG. 1 is a diagram showing an EPROM device including a unit cell according to an example.
2 is a cross-sectional view showing an initial state of a floating gate transistor of an EPROM device according to an example.
3 is a cross-sectional view showing a program state of a floating gate transistor of an EPROM device according to an example.
4 is a cross-sectional view showing an unprogrammed state of a floating gate transistor of an EPROM device according to an example.
5 is a diagram illustrating an EPROM device including a cell array according to an example.
FIGS. 6 and 7 are diagrams showing the program operation of the EPROM device of FIG.

The terms used in describing the example of the present application are selected in consideration of the functions in the illustrated embodiments, and the meaning of the terms may be changed according to the intentions or customs of the user, the operator in the technical field, and so on. The meaning of the term used is in accordance with the defined definition when specifically defined in this specification and can be interpreted in a sense generally recognized by those skilled in the art without specific definition.

For example, in the description of the examples of the present application, descriptions such as " first "and" second "are for distinguishing members, and are not used to limit members or to denote specific orders. Further, the description that a substrate located on the "upper "," lower ", or "outer side " of a member means a relative positional relationship and is directly contacted with the member, The present invention is not limited to a particular case. The description of either element being "connected" or "coupled" to another element means that the elements are electrically or mechanically directly connected to each other or connected to each other And other separate components may be interposed in the middle to form a connection relationship or a connection relationship. The same interpretation can be applied to other expressions that describe the relationship between the components.

Like reference characters throughout the specification may refer to the same elements. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

FIG. 1 is a diagram showing an EPROM device 10 according to an example.

Referring to FIG. 1, the EPROM 10 may include a 2-bit unit cell 100 for storing 2-bit data. A 2-bit unit cell 100 may be disposed at a position where a first bit line BL1 and a first cell selection line CSL1 cross each other. The 2-bit unit cell 100 may include one access transistor 110 and two floating gate transistors 120 and 130.

The access transistor 110 of the 2-bit unit cell 100 is arranged at the intersection of the first bit line BL1 and the first cell select line CSL1 so that the first bit line BL1 and the first cell selection line CSL1. The select gate of the access transistor 110 is coupled to the first cell select line CSL1 and the source of the access transistor 110 is coupled to the first bit line BL1 have. The source of the first floating gate transistor 120 and the source of the second floating gate transistor 130 may be coupled to the drain of the access transistor 110. [ Each of the first and second floating gate transistors 120 and 130 may be provided as mutually independent storage elements. The access transistor 110 may be addressed to select the first and second floating gate transistors 120 and 130 during a program operation and the first and second floating gates 120 and 130 may be selected during a read operation. May be a read transistor that is addressed to access the transistors 120 and 130.

Since the first and second floating gate transistors 120 and 130 are commonly coupled to the access transistor 110 to form the unit cell 100, the first and second floating gate transistors 120 and 130 In order to program different bits, the first and second floating gate transistors 120 and 130 do not share a ground. The sources of the first and second floating gate transistors 120 and 130 are coupled to the first bit line BL1 through the access transistor 110 and the source of the first and second floating gate transistors 120 and 130 Each of the drains can be coupled to the grounds independently of each other.

A first ground select transistor 210 may be disposed between the drain of the first floating gate transistor 120 and ground so that the drain and ground of the first floating gate transistor 120 are coupled . A second ground selection transistor 230 may be disposed between the drain of the second floating gate transistor 130 and the ground so that the drain of the second floating gate transistor 130 and ground may be coupled. The first ground selection line GSL1 is coupled to the gate of the first ground selection transistor 210 and the gate of the first ground selection transistor 210 is controlled by the first ground selection line GSL1 . The second ground selection line GSL2 may be coupled to the gate of the second ground selection transistor 230 and the gate of the second ground selection transistor 230 may be interrupted by the second ground selection line GSL2.

When the first ground selection transistor 210 is turned on, the ground and the drain of the first floating gate transistor 120 are coupled and the first ground selection transistor 210 is turned off The ground and the drain of the first floating gate transistor 120 can be disconnected without being connected. When the first ground selection transistor 210 is turned on and the second ground selection transistor 230 is turned off, the ground and the drain of the first floating gate transistor 120 are coupled and the second floating gate transistor 130 May be floating. When the second ground selection transistor 230 is turned on and the first ground selection transistor 210 is turned off, the ground and the drain of the second floating gate transistor 130 are coupled and the first floating gate transistor 120 May be floating.

As described above, the first floating gate transistor 120 and the second floating gate transistor 130 may not share the ground due to the intermittent operation or the switching operation of the ground selection transistors 210 and 230. The drain of the first floating gate transistor 120 may be coupled to ground by turning on or off of the first ground select transistor 210 and to a floating state that is not coupled to ground. The first floating gate transistor 120 and the second floating gate transistor 130 are coupled to the ground differently from each other by the intermittent operation of the ground selection transistors 210 and 230, Each of the two floating gate transistors 130 may have different bits stored or read out.

Bit unit cell 100 may include a first floating gate transistor coupled to the access transistor 110 and a second floating gate transistor coupled to the access transistor 110. The first floating gate transistor 120 and the second floating gate transistor 130 may store different bits, And a second sub-cell 100A including a second floating gate transistor 130 coupled to the same access transistor 110 and storing a second bit, 0.0 > 100B. ≪ / RTI >

FIG. 2 is a cross-sectional view showing the initial state of the first floating gate transistor 120 of the EPROM device (10 in FIG. 1) according to an example.

Referring to FIG. 2, a first sub-cell 100I in an initial state may include an N-type well region 102 disposed in a P-type substrate 101. FIG. The second sub-cell (100B in FIG. 1) may also be provided in the same manner as the first sub-cell 100I in the initial state. On the P-type substrate 101, trench isolation layers 103 defining an active region may be disposed. The first P + type junction region 113, the second P + type junction region 114, and the third P + type junction region 125 may be spaced apart from each other in a first region above the N type well region 102 have. A second region isolated from each other by the first region and the trench isolation layer 103 is disposed above the N-type well region 102 and an N + -type contact region 102 is formed in the second region above the N-type well region 102 contact region 107 may be disposed.

The first P + type junction region 113 and the second P + type junction region 114 may be arranged to be spaced apart by the first channel region 104. The second P + type junction region 114 and the third P + type junction region 125 may be arranged to be spaced apart by the second channel region 105. An access gate insulating layer 112 and an access gate electrode layer 111 may be disposed on the first channel region 131. A first floating gate insulating layer 122 and a first floating gate electrode layer 121 may be disposed on the second channel region 105. The first P + type junction region 113, the first channel region 104, the second P + type junction region 114, the access gate insulating layer 112, and the access gate electrode layer 111 are formed on the upper surface of the access transistor 110, (PMOS Tr) can be constituted. The second P + type junction region 114, the second channel region 105, the third P + type junction region 125, the first floating gate insulating layer 122, and the first floating gate electrode layer 152 are formed in the 1 floating gate transistor 120 may be composed of a second PMOS transistor.

The first P + type junction region 113 of the access transistor 110 may be coupled to the first bit line BL1 as the source of the first PMOS transistor. The second P + type junction region 114 of the access transistor 110 may serve as a drain opposite to the source of the first PMOS transistor. The access gate electrode layer 111 of the access transistor 110 may be coupled to the first cell selection line CSL1 as the gate of the first PMOS transistor. The access gate electrode layer 111 may receive a cell selection signal for selecting a 2-bit unit cell (100 in FIG. 1) through the first cell selection line CSL1.

Although the first floating gate transistor 120 is comprised of a second PMOS transistor, the first floating gate electrode layer 121 may have a floating state that is not directly coupled to any electrical connection line. The second P + type junction region 114 and the third P + type junction region 125 can constitute the source and the drain of the second PMOS transistor. The second P + type junction region 114 serves as a drain of the first PMOS transistor and also serves as a source of the second PMOS transistor. The second P + type junction region 114 may be arranged to couple the first floating gate transistor 120 to the access transistor 110 to the source of the access transistor 110 and to the drain of the first floating gate transistor 120 have. The second P + type junction region 114 may be disposed in a floating state in which a separate electrical electrode is not directly connected. The drain of the first floating gate transistor 120 may have a floating state in an initial state.

In the initial state, the first floating gate electrode layer 121 of the first floating gate transistor 120 may have a state where electrons are not charged, for example, an unprogrammed state.

FIG. 3 is a cross-sectional view showing the programmed state of the first floating gate transistor 120 of the EPROM device (10 of FIG. 1) according to an example.

Referring to FIG. 3, a first subcell (100A in FIG. 1) may be selected and programmed to derive a programmed first subcell 120S. A low level signal is applied to the access gate electrode layer 111 of the first PMOS transistor which is the access transistor 110 through the first cell selection line CSL1 to form the programmed first sub cell 120S. And applies the first cell selection signal as an enable signal. For example, 0 V can be applied to the access gate electrode layer 111, for example. A positive program bit line voltage (Vpbl) can be applied to the first P + type junction region 113 which is the source of the first PMOS transistor. At this time, the positive program bit line voltage Vpbl may be applied to approximately 8V. As Vpbl is applied to the source and 0 V, for example, is applied to the access gate electrode layer 111, the first PMOS transistor may be turned on. The access transistor 110 is turned on and the program bit line voltage Vpbl applied to the first P + type junction region 113 can be induced to the second P + type junction region 114 in the floating state. At this time, the first floating gate transistor 120 and the second floating gate transistor (130 in FIG. 1) coupled to the access transistor 110 in the second P + type junction region 114 are turned on Can be selected. That is, a 2-bit unit cell (100 in Fig. 1) can be selected.

The third P + type junction region 125, which is disposed opposite to the second P + type junction region 114 of the first floating gate transistor 120, is coupled to the ground through the first ground select transistor 210. The first ground selection transistor 210 may be composed of an NMOS transistor unlike the access transistor 110. A turn-on voltage Von for turning on the NMOS Tr through the first ground selection line GSL1 is applied to the gate of the first ground selection transistor 210 to turn on the first ground selection transistor 210 and the third P + type junction region 125 of the first floating gate transistor 120 to the ground. The turn-on voltage applied to the gate of the first ground selection transistor 210 may be VDD. In some cases, a bias voltage may be applied to the gate of the first ground selection transistor 210.

Since the ground is led to the third P + type junction region 125 through the turned on first ground selection transistor 210, the voltage difference between the second P + type junction region 112 and the third P + type junction region 113 An electric field caused by the electric field can be induced. Due to the electric field between the second P + type junction region 112 and the third P + type junction region 113 of the first floating gate transistor 120, hot electrons are implanted into the second P + type junction region 114 And hot electrons may be injected into the first floating gate electrode layer 121 of the first floating gate transistor 120. [ Electrons are injected into the first floating gate electrode layer 121 and a P type inversion layer is formed in the second channel region 105. Accordingly, the second pomost transistor, which is the first floating gate transistor 120, The on state is maintained. That is, the first floating gate transistor 120 may be programmed. A positive program bit line voltage Vpbl may also be applied to the N + type contact region 107, although not shown in the figure.

Thus, when the first floating gate transistor 120 is programmed, a P-type inversion layer is formed in the second channel region 105, and thus the second PMOS transistor, which is the first floating gate transistor 120, Maintain on-state. In this case, when the access transistor 110 is turned on and the first ground selection transistor 210 is turned on by the read operation, a current flows between the first bit line BL1 and the ground.

FIG. 4 is a cross-sectional view showing the second floating gate transistor 130 of the EPROM device (10 of FIG. 1) according to one example in an unprogrammed state.

Referring to FIG. 4, the second sub-cell (100B in FIG. 1) may derive the second sub-cell 130NS in an unselected and unprogrammed program forbidden state. In order to maintain the second sub-cell 130NS in the program inhibited state while forming the programmed first sub-cell 120S (FIG. 3), the first ground selection transistor 210 of FIG. 3 is turned on, The transistor 230 can be turned off.

The access gate electrode layer 111 of the first PMOS transistor which is the access transistor 110 constituting the 2-bit unit cell (100 of FIG. 1) is connected to the access gate electrode layer 111 through the first cell selection line CSL1 1 cell coupled to the access transistor 110 as well as the first floating gate transistor 120 (FIG. 3) coupled to the access transistor 110 when applying the one-cell select signal to the enable signal, The positive program bit line voltage Vpbl may also be combined.

A positive cell bit line voltage (Vpbl) is applied to the first P + type junction region 113, which is a source of the first PMOS transistor, by applying, for example, 0 V as a first cell selection signal to the access gate electrode layer 111, (110) may be turned on. The access transistor 110 is turned on and the program bit line voltage Vpbl applied to the first P + type junction region 113 can be induced to the second P + type junction region 114 in the floating state.

At this time, since the second floating gate transistor 130 as well as the first floating gate transistor 120 (FIG. 3) are also coupled to the second P + type junction region 114, The positive program bit line voltage Vpbl may be applied to the 2 < + > -type junction region 114. [ That is, the positive program bit line voltage Vpbl may also be coupled to the second floating gate transistor 130 during the programming operation of the first floating gate transistor 120. A fourth P + type junction region 135 is disposed opposite and disposed to the second P + type junction region 114 of the second floating gate transistor 130 to prevent program operation from being performed on the second floating gate transistor 130. [ Do not combine with ground.

The second floating gate transistor 130 may include a second P + type junction region 114 and a fourth P + type junction region 135 disposed above the N type well region 201 to be spaced therefrom. The second floating gate transistor 130 may share a first floating gate transistor (120 in FIG. 3) and a second P + type junction region 114 as a source. The fourth P + type junction region 135 of the second floating gate transistor 130 serves as a drain and is arranged to be spaced apart from the third P + type junction region 125 of the first floating gate transistor 120 .

The second P + type junction region 114 and the fourth P + type junction region 135 may be arranged to be spaced apart by the third channel region 106. A second floating gate insulating layer 132 and a second floating gate electrode layer 131 may be disposed on the third channel region 106 to form a second floating gate transistor 130. The second P + type junction region 114, the third channel region 106, the fourth P + type junction region 135, the second floating gate insulating layer 132, and the second floating gate electrode layer 131 And the second floating gate transistor 130 may be composed of a third PMOS transistor. The second floating gate transistor 130 may be configured to share the access transistor 110 with the first floating gate transistor 120.

The second floating gate transistor 130 is composed of a third PMOS transistor, but the second floating gate electrode layer 131 can have a floating state that is not directly coupled to any electrical connection line. The second P + type junction region 114 and the fourth P + type junction region 135 can constitute the source and the drain of the third PMOS transistor. The second P + type junction region 114 serves as a drain of the first PMOS transistor and also serves as a source of the third PMOS transistor.

A second ground selection transistor 230 may be disposed between the drain of the third PMOS transistor and the fourth P + type junction region 135 of the second floating gate transistor 130. The second ground selection transistor 230 may be formed of an NMOS transistor unlike the access transistor 110. A turn-off voltage Voff for turning off the NMOS Tr through the second ground selection line GSL2 is applied to the gate of the second ground selection transistor 230 to turn on the second floating gate transistor MN2. The fourth P + type junction region 135 of the transistor 130 can be disconnected from the ground and held in a floating state. VSS may be applied to the gate of the second ground selection transistor 230 to turn off the NMOS transistor.

Since the fourth P + type junction region 135 of the second floating gate transistor 130 is not coupled to ground but is floating, the second floating gate transistor 130 is connected to the first floating gate transistor (120 in FIG. 3) Other voltage conditions, i.e., program inhibit conditions, can be applied. The turned off second ground selection transistor 230 blocks the ground from being induced in the fourth P + type junction region 135 so that the drain of the second floating gate transistor 130 remains floating. Thus, although the program bit line voltage Vpbl is induced in the second P + type junction region 112, an electric field for inducing hot electrons in the second P + type junction region 112 is not induced. The hot electrons can not be injected into the second floating gate electrode layer 131 of the second floating gate transistor 130 and the P type inversion layer is not formed in the third channel region 106. As a result, the third PMOS transistor, which is the second floating gate transistor 130, is turned off to maintain the turn-off state. That is, the second floating gate transistor 130 may be in a program inhibited state.

As described above, since the second floating gate transistor 130 is not programmed, a P-type inversion layer is not formed in the third channel region 106, and therefore, the third floating gate transistor 130, Maintains an off-state. In this case, even if the access transistor 110 is turned on and the second ground selection transistor 230 is turned on by the read operation, no current flows between the first bit line BL1 and the ground. In this read operation, the first ground selection transistor 210 coupled to the first floating gate transistor 120 is turned off so that even though the first floating gate transistor 120 is in the programmed state, Is not connected to the ground, so that current does not flow to the ground via the first floating gate transistor (120).

In this manner, the first ground selection transistor 210 (FIG. 3) and the second ground selection transistor 230 may be turned on or off, respectively, so that the first floating gate transistor 120 or the second floating gate transistor 130 may be selectively programmed. The first floating gate transistor 120 and the second floating gate transistor 130 commonly coupled to the access transistor 100 are respectively connected to a first ground selection transistor 210 And can be selected independently of each other in the program operation by the second ground selection transistor 230. [

Accordingly, it is possible to independently store different bits of data in the first floating gate transistor 120 and the second floating gate transistor 130 coupled to one access transistor 110, respectively. The second floating gate transistor 130 may be coupled to the access transistor 110 to which the first floating gate transistor 120 is coupled to form one 2-bit unit cell (100 of FIG. 1) Another separate access transistor for accessing the transistor 130 may be omitted. Therefore, the 2-bit unit cell 100 can be substantially composed of three PMOS transistors, and the area occupied by the unit cell 100 can be reduced. That is, it is possible to increase the storage density within a limited cell area.

FIG. 5 is a diagram showing an EPROM device 10S including a cell array according to an example.

5, the EPROM device 10S includes n bit lines BL1, BL2, ..., BLn and m cell selection lines CSL1, CSL2, ... CLSm arranged to intersect them, Bit unit cells 100-1, 100-2, 100-3, ... are arranged at the intersections of the bit lines BL1, BL2, ..., BLn and the cell selection lines CSL1, CSL2, ... CLSm, . The 2-bit unit cells 100-1, 100-2, 100-3, ... have one access transistor 110-1, 110-2, 110-3, ... and the first floating gate transistor 120-1 , 120-2, 120-3, ..., and second floating gate transistors 130-1, 130-2, and 130-3. Each of the 2-bit unit cells 100-1, 100-2, 100-3, ... may be configured in the form of a unit cell (100 in FIG. 1) as described with reference to FIG. Each of the access transistors 110-1, 110-2, 110-3, ... is configured in the form of an access transistor (110 of FIGS. 2 and 3) as described with reference to FIGS. 2 and 3 . Each of the first floating gate transistors 120-1, 120-2, 120-3, ... is in the form of a first floating gate transistor (120 of Figures 2 and 3) as described with reference to Figures 2 and 3 Lt; / RTI > Each of the third floating gate transistors 130-1, 130-2, 130-3, ... may be configured in the form of a third floating gate transistor 130 (FIG. 4) as described with reference to FIG.

The first ground selection transistor 210 may be disposed between the first floating gate transistors 120-1, 120-2, 120-3,... And substantially all of the first floating gate transistors 120-1, 120-2, 120-3,. Substantially all of the first floating gate transistors 120-1, 120-2, 120-3, ... disposed in the cell array are coupled to one first ground selection transistor 210 to form a first ground selection transistor 210 may be turned on, the drains may be connected to ground, and when the first ground selection transistor 210 is turned off, the drains may be disconnected from ground, so that the drains may be floating.

The second ground selection transistor 230 may be disposed between the second floating gate transistors 130-1, 130-2, 130-3,... And substantially all of the second floating gate transistors 130-1, 130-2, 130-3,. Substantially all of the second floating gate transistors 130-1, 130-2, 130-3, ... disposed in the cell array are coupled to one second ground selection transistor 230 so that the second ground selection transistor 230 may be turned on and the drains may be in a floating state when the second ground selection transistor 230 is turned off when the drains are disconnected from the ground.

In this manner, the first ground selection transistor 210 is commonly coupled to substantially all of the first floating gate transistors 120-1, 120-2, 120-3, ... in the cell array, Since the second ground selection transistor 230 is commonly connected to the first and second ground selection transistors 210 and 230, Only two within the cell array may be required. The first floating gate transistors 120-1, 120-2, 120-3, ... in the 2-bit unit cells 100-1, 100-2, and 100-3 and the second floating gate transistors 120-1, 120-2, 120-3, It is possible to access or select the gate transistors 130-1, 130-2, 130-3,... Different from each other. That is, the first and second floating gate transistors can be selected by only two ground selection transistors 210 and 230 that intercept the connection to the ground regardless of the number of bit lines BL1, BL2, ..., BLn. Since the NMOS transistor can pass the ground better than the PMOS transistor, the first floating gate transistors 120-1, 120-2, 120-3, ... or the second floating gate transistors 130- 1, 130-2, 130-3, ...) to the ground.

 FIG. 6 is a view showing selective programming of the 1-1 second floating gate transistor 120-1 of the first unit cell 100-1 of the EPROM device 10S according to an example.

Referring to FIG. 6, a first cell selection signal of a low level is applied to the gate of the first access transistor 110-1 of the first unit cell 100-1 through the first cell selection line CSL1, The positive program bit line voltage Vpbl may be applied to the source of the first access transistor 110-1 through the first bit line BL1 to select and turn on the first access transistor 110-1 . 0 V or VSS may be applied to the gate of the first access transistor 110-1 and approximately 8 V may be applied to the source of the first access transistor 110-1.

A second cell selection signal Vfb of high level is applied to the second cell selection line CSL2 and the remaining cell selection lines, for example, at about 8V, and the second access transistor 110-2 to turn off. The remaining bit lines including the second bit line BL2 are brought into a floating state, and the remaining access transistors including the third access transistor 110-3 coupled to the first cell select line CSL1 are turned off .

In this way, only the first access transistor 110-1 disposed at the intersection of the first cell select line CSL1 and the first bit line BL1 is selectively turned on, and the first unit cell 100-1 is turned on, Lt; / RTI >

The first ground selection transistor 210 is turned on by applying a turn on voltage Von to the first ground selection transistor 210 so that the ground and the first floating transistor 210-1 coupled to the first access transistor 110-1, So that the drains of the gate transistors 120-1 are connected to each other. The turn-off voltage Voff is applied to the second ground selection transistor 230 to turn off the second ground selection transistor 230 and the ground and the 2-1 floating So that the drain of the gate transistor 130-1 is disconnected from each other.

The positive program bit line voltage Vpbl of the first bit line BL1 is induced via the first access transistor 110-1 turned on to the source of the 1-1th floating gate transistor 120-1, 1-1 Ground is induced to the drain of the floating gate transistor 120-1, so that the 1-1th floating gate transistor 120-1 is programmed to the ON state as described with reference to FIG.

On the other hand, the positive program bit line voltage Vpbl of the first bit line BL1 is induced through the first access transistor 110-1 turned on to the source of the 2-1th floating gate transistor 130-1 However, since the drain of the 2-1th floating gate transistor 130-1 is not connected to the ground and is floating, as described with reference to FIG. 4, the 2-1th floating gate transistor 130-1 is turned off It remains unprogrammed.

FIG. 7 is a view showing selective programming of the second-1 floating gate transistor 130-1 of the first unit cell 100-1 of the EPROM device 10S according to an example.

Referring to FIG. 7, a first cell selection signal of a low level is applied to the gate of the first access transistor 110-1 of the first unit cell 100-1 through the first cell selection line CSL1, The positive program bit line voltage Vpbl may be applied to the source of the first access transistor 110-1 through the first bit line BL1 to select and turn on the first access transistor 110-1 .

A turn-on voltage Von is applied to the second ground selection transistor 230 to turn on the second ground selection transistor 230 and the ground and the 2-1 floating So that the drains of the gate transistors 130-1 are connected to each other. The first ground selection transistor 210 is turned off by applying a turnoff voltage Voff to the first ground selection transistor 210 so that the ground and the first floating transistor 210-1 coupled to the first access transistor 110-1, So that the drains of the gate transistors 120-1 are disconnected from each other.

The positive program bit line voltage Vpbl of the first bit line BL1 is induced via the first access transistor 110-1 turned on to the source of the second-first floating gate transistor 130-1, Since the ground is induced in the drain of the 2-1 floating gate transistor 130-1, the gate hot electrons of the 2-1 floating gate transistor 130-1 are injected in the same process as described with reference to FIG. 3, The 2-1th floating gate transistor 130-1 is programmed to the ON state.

On the other hand, the positive program bit line voltage Vpbl of the first bit line BL1 is induced through the first access transistor 110-1 turned on to the source of the 1-1th floating gate transistor 120-1 However, since the drain of the 1-1th floating gate transistor 120-1 is not connected to the ground and is floating, as described with reference to FIG. 4, the programming operation of the 2-1th floating gate transistor 130-1 You can stay in the previous state without being affected.

As described above, the two floating gate transistors 120-1 and 120-2 (in the 2-bit unit cells 100-1, 100-2, and 100-3) , 120-3, ..., and the second floating gate transistors 130-1, 130-2, 130-3, ... may be accessed or selected differently from each other. Accordingly, one access transistor 110-1, 110-2, 110-3, ..., the first floating gate transistor 120-1, 120-2, 120-3, ..., and the second floating gate transistor (130-1, 130-2, 130-3, ...).

Although the embodiments of the present application as described above illustrate and describe the drawings, it is intended to illustrate what is being suggested in the present application and is not intended to limit what is presented in the present application in a detailed form. Various other modifications will be possible as long as the technical ideas presented in this application are reflected.

100: 2-bit unit cell,
110: access transistor,
120, and 130: floating gate transistors,
210, and 230: a ground selection transistor.

Claims (8)

Bit lines and cell select lines crossing the bit lines;
Unit cells arranged at intersections of the bit lines and the cell selection lines,
An access transistor having a source coupled to the bit line and a gate coupled to the cell select line,
Unit cells including first and second floating gate transistors whose sources are coupled to a drain of the access transistor;
A first ground selection transistor disposed between the drains of the first floating gate transistors and a ground and interrupting a connection with the ground; And
And a second ground selection transistor disposed between the drains of the second floating gate transistors and the ground and interrupting a connection to the ground. The method according to claim 1,
The access transistor
An access gate electrode layer coupled to any one of said cell select lines;
A first P + type junction region coupled to any one of the bit lines; And
Type junction region and a second P + type junction region spaced apart from the first P + type junction region. 3. The method of claim 2,
The first floating gate transistor
Sharing the second P + type junction region as a source,
A first floating gate electrode layer; And
And a third P + type junction region disposed to be spaced apart from the second P + type junction region. The method of claim 3,
The first ground selection transistor
On turn on
Connecting the ground to the third P + type junction region,
To disconnect the third P + type junction region and the ground at turn-off
And an EPROM device disposed between the third P + type junction and the ground. The method of claim 3,
The second floating gate transistor
Sharing the second P + type junction region as a source,
A second floating gate electrode layer; And
And a fourth P + type junction region disposed to be spaced apart from the second P + type junction region. 6. The method of claim 5,
The second ground selection transistor
On turn on
Connecting the ground to the fourth P + type junction region,
To disconnect the fourth P + type junction region and the ground at turn-off
And an EPROM device disposed between the fourth P + type junction and the ground. The method according to claim 1,
The first and second ground selection transistors
An EPROM device comprising an NMOS transistor, respectively. Bit lines and cell select lines crossing the bit lines;
Unit cells arranged at intersections of the bit lines and the cell selection lines,
An access transistor having a source coupled to the bit line and a gate coupled to the cell select line,
Unit cells including first and second floating gate transistors whose sources are coupled to a drain of the access transistor;
A first ground selection transistor disposed between the drains of the first floating gate transistors and a ground and interrupting a connection with the ground; And
And a second ground selection transistor arranged between the drains of the second floating gate transistors and the ground and interrupting a connection with the ground, wherein, in a programming operation of an EPROM device,
Applying a program bit line voltage to the source of the access transistor through any one of the bit lines,
Turning on the access transistor whose gate is coupled to any one of the cell select lines,
The first ground selection transistor is turned on to connect the drain of the first floating gate transistor to the ground,
The second ground selection transistor is turned off to disconnect the drain of the second floating gate transistor from the ground,
(EPROM) device that selectively programs the first floating gate transistor.

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