KR20180056145A - Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure - Google Patents

Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure Download PDF

Info

Publication number
KR20180056145A
KR20180056145A KR1020160154013A KR20160154013A KR20180056145A KR 20180056145 A KR20180056145 A KR 20180056145A KR 1020160154013 A KR1020160154013 A KR 1020160154013A KR 20160154013 A KR20160154013 A KR 20160154013A KR 20180056145 A KR20180056145 A KR 20180056145A
Authority
KR
South Korea
Prior art keywords
oxide layer
layer
indium oxide
indium
metal oxide
Prior art date
Application number
KR1020160154013A
Other languages
Korean (ko)
Other versions
KR101914835B1 (en
Inventor
서형탁
이상연
박아영
Original Assignee
아주대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아주대학교산학협력단 filed Critical 아주대학교산학협력단
Priority to KR1020160154013A priority Critical patent/KR101914835B1/en
Priority to PCT/KR2017/011403 priority patent/WO2018093048A1/en
Priority to CN201780071720.9A priority patent/CN110268528A/en
Publication of KR20180056145A publication Critical patent/KR20180056145A/en
Application granted granted Critical
Publication of KR101914835B1 publication Critical patent/KR101914835B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432—Heterojunction gate for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

A metal oxide heterojunction structure comprising an indium oxide layer and an aluminum oxide layer in contact with the indium oxide layer,
Wherein an interfacial layer is provided between the indium oxide layer and the aluminum oxide layer, the interfacial layer including indium ions, aluminum ions and oxygen ions, and providing a charge transport channel.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a metal oxide heterojunction structure, a method of manufacturing the same, and a thin film transistor including the metal oxide heterogeneous junction structure, and a thin film transistor including the metal oxide heterostructure,

The present invention relates to a metal oxide heterojunction structure in which electrical conductivity can be controlled, a method for manufacturing the same, and a thin film transistor including the same.

Metal oxides can exhibit various physical properties not obtainable with conventional semiconductor materials. In the case of the heterojunction structure of the metal oxide, since the symmetry is locally broken at the surface and the interface, a new physical property which is not exhibited in the bulk state can be expressed. For example, it has been found that "quasi two-dimensional electron gas (2DEG)" exists at the interface between LaAlO 2 and SrTiO 3 , which are insulators, and the metal oxide heterostructure, have. In particular, it has been reported that the heterojunction structure of LaAlO 2 and SrTiO 3 not only exhibits a very high electron mobility of about 104 cm 2 V -1 s -1 , but also exhibits superconducting properties at cryogenic temperatures.

However, the mechanisms of various physical phenomena in metal oxide matching have not yet been clarified, and the world's leading researchers in the US, Europe, and Japan are engaged in theoretical and experimental research. In recognition of its importance, the American Physical Society held an independent session on the "Metal Oxide Thin Film Interface / Surface" in 2006, and the 2007 International Technology Roadmap for Semiconductors (ITRS) ) Are classified as emergent materials, and industry expectations for their applicability are growing.

However, the conventional metal oxide heterojunction structure has been formed through a method such as molecular beam epitaxy, pulse laser deposition, or the like for realizing the above characteristics, but this method is not compatible with the semiconductor integrated circuit device process Therefore, there was difficulty in actual commercialization.

It is an object of the present invention to provide a metal oxide heterojunction structure capable of adjusting the electrical conductivity by controlling the thickness of the indium oxide layer.

It is another object of the present invention to provide a method of manufacturing the above-described metal oxide heterojunction structure.

It is still another object of the present invention to provide a thin film transistor including the metal oxide heterojunction structure.

The metal oxide heterojunction structure according to an embodiment of the present invention includes an indium oxide layer and an aluminum oxide layer in contact with the indium oxide layer, and an indium ion, an aluminum ion, and an oxygen ion And an interfacial layer is provided which provides a transfer channel for the charge.

In one embodiment, the indium oxide layer may have a thickness of 8 nm or more and 15 nm or less, the aluminum oxide layer may have a thickness of 10 nm or more, and the interface layer may have a semiconductor characteristic. In this case, the indium oxide layer may include at least a part of the nanocrystallized region.

In one embodiment, the indium oxide layer may have a thickness of at least 100 nm, the aluminum oxide layer may have a thickness of at least 10 nm, and the interface layer may have electrical conductor properties. In this case, the indium oxide layer may be crystallized in an area of 90% or more.

Meanwhile, the interface layer may be formed to a thickness of 3 nm or more and 5 nm or less.

A method of fabricating a metal oxide heterojunction structure according to an embodiment of the present invention includes: forming an indium oxide layer by a sputtering method performed at room temperature on a substrate; And forming an aluminum oxide layer on the indium oxide layer through a vacuum deposition process performed at 150 ° C to 250 ° C.

A thin film transistor according to an exemplary embodiment of the present invention may be controlled by a gate voltage applied to a gate electrode to transmit a signal of a source electrode to a drain electrode through a semiconductor channel layer, And a metal oxide heterojunction structure including an aluminum oxide layer in contact with the indium oxide layer, wherein the indium ion, the aluminum ion, and the oxygen ion are included between the indium oxide layer and the aluminum oxide layer, An interfacial layer providing a channel may be formed.

In one embodiment, the indium oxide layer may have a thickness of 8 nm or more and 15 nm or less, and the aluminum oxide layer may have a thickness of 10 nm or more.

In one embodiment, the source electrode and the drain electrode may be disposed in contact with the interface layer and spaced apart from each other.

In one embodiment, the gate electrode may be located above the aluminum oxide layer, in which case the aluminum oxide layer may electrically isolate the interface layer from the gate electrode.

According to the present invention, the electrical characteristics of the metal oxide heterojunction structure can be easily controlled by adjusting the thickness of the indium oxide layer.

FIG. 1 is a voltage-current graph for explaining the change in electric characteristics according to the thickness of the indium oxide layer in the metal oxide heterojunction structure of the present invention. FIG.
FIGS. 2A to 2E are graphs of voltage-current for illustrating changes in electrical characteristics of the metal oxide heterostructure of the present invention over time. FIG.
3A to 3E are graphs showing electron mobility, carrier concentration, sheet resistance and Hall coefficient of the metal oxide heterojunction structures according to the present invention. admit.
FIG. 4A is TEM images of an indium oxide layer formed by a room temperature sputtering process on a glass substrate, and FIG. 4B is TEM images after forming an aluminum oxide layer by an atomic layer deposition method on the indium oxide layer of FIG.
FIG. 5A is a result of XPS analysis measured on the surface of the indium oxide layer immediately after the indium oxide layer is formed on the glass substrate by the room temperature sputtering method, FIGS. 5B and 5C are cross- And the XPS analysis results of the surface of the aluminum oxide layer and the interface layer with the indium oxide layer after the formation of the aluminum oxide layer.
6A to 6C show a sample (black solid line) immediately after the indium oxide layer was formed on a glazed substrate, a sample obtained by forming an indium oxide layer on a glazed substrate and thermally treating the indium layer in vacuum at 300 DEG C for 5 minutes ), A sample immediately after an indium oxide layer and an aluminum oxide layer were successively formed on a gallium substrate (blue solid color), and an indium oxide layer and an aluminum oxide layer formed continuously on a gallium substrate, Graphs showing the transmittance according to the wavelength of light measured for a sample heat treated for 5 minutes (green solid line).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the term "comprises" or "having ", etc. is intended to specify that there is a feature, step, operation, element, part or combination thereof described in the specification, , &Quot; an ", " an ", " an "

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

≪ Metal Oxide Heterostructure >

The metal oxide heterojunction structure according to an embodiment of the present invention may include an indium oxide (In 2 O 3 ) layer and an aluminum oxide (Al 2 O 3 ) layer. By controlling the thickness of the indium oxide layer, Conductor properties.

The indium oxide layer may be disposed on a substrate and may have a thickness of about 8 nm or more. In one embodiment, when the metal oxide heterojunction structure has semiconductor properties, the indium oxide layer may have a thickness of about 8 nm or more and 15 nm or less, and at least a portion may include a nanocrystallized region. In another embodiment, when the metal oxide heterostructure has electrical conductor properties, the indium oxide layer may have a thickness of at least about 100 nm, and most of the region, for example, at least about 90% Lt; / RTI >

The indium oxide layer may be formed on the substrate by a vacuum deposition method. For example, the indium oxide layer may be formed on the substrate by a sputtering method performed at a room temperature, and may be heat-treated for a predetermined time in a high-temperature vacuum state after the sputtering process. For example, after the sputtering process, it may be heat-treated at about 250 ° C to 350 ° C for about 5 minutes to 30 minutes. In this case, when the thickness of the indium oxide layer is less than 8 nm, the indium oxide layer is in an amorphous form. However, when the indium oxide layer has a thickness of 100 nm or more, most regions may be crystalline.

The aluminum oxide layer may be disposed on the indium oxide layer. The aluminum oxide layer may be formed by a vacuum deposition method performed at a relatively high temperature. For example, the aluminum oxide layer may be formed on the indium oxide layer by atomic layer deposition which is performed at about 150 ° C to 250 ° C.

As described above, when the aluminum oxide layer is formed on the indium oxide layer, the diffusion of aluminum in the aluminum oxide layer or the diffusion of indium oxide in the aluminum oxide layer may cause the semiconductor characteristic or An interface layer may be formed that exhibits electrical conductor properties. That is, the interface layer may include indium ions, aluminum ions, and oxygen ions. In this case, defects such as unsaturated bonds and oxygen vacancies existing on the surface of the indium oxide layer remove the diffusion of aluminum, thereby changing the electrical characteristics of the interface layer. In particular, the electrical characteristics of the interfacial layer have been shown to be greatly affected by the crystallization state of the indium oxide layer, and the crystallization state of the indium oxide layer has been found to be strongly influenced by the thickness of the indium oxide layer.

Meanwhile, the interface layer may be formed to a thickness of about 3 to 5 nm. In one embodiment, the aluminum oxide layer may be formed to a thickness of about 10 nm or more to form an interface layer having the same thickness. However, as a result of the experiment, when the thickness of the aluminum oxide layer is about 10 nm or more, the electrical conductivity of the metal oxide heterojunction structure according to the present invention is hardly affected by the thickness of the aluminum oxide layer. The thickness of the aluminum oxide layer is not particularly limited.

FIG. 1 is a voltage-current graph for explaining the change in electric characteristics according to the thickness of the indium oxide layer in the metal oxide heterojunction structure of the present invention. FIG. 1, black curves, blue curves, red curves, and green curves are voltage-current curves for metal oxide heterogeneous junction structures, each containing 12 nm, 50 nm, 30 nm and 100 nm thick indium oxide layers , And the metal oxide heterojunction structures all include a 100 nm thick aluminum oxide layer.

Referring to FIG. 1, as the thickness of the indium oxide layer increases, the electrical conductivity of the metal oxide heterojunction structure increases. Thus, it can be seen that the electrical conductivity of the metal oxide heterojunction structure can be controlled by adjusting the thickness of the indium oxide layer.

FIGS. 2A to 2E are graphs of voltage-current for illustrating changes in electrical characteristics of the metal oxide heterostructure of the present invention over time. FIG. In each of FIGS. 2A-2E, black curves, red curves, blue curves, and green curves represent the voltage-currents measured after 0 hours, 12 hours, 36 hours, and 60 hours after manufacture of the metal oxide hetero- And the metal oxide heterojunction structures all include a 100 nm thick aluminum oxide layer.

Referring to FIGS. 2A to 2E, in the metal oxide heterojunction structures of the present invention each including 8 nm, 10 nm, 30 nm, 50 nm and 100 nm thick indium oxide layers, voltage-current characteristics It can be confirmed that there is almost no change. That is, it can be seen that the metal oxide heterojunction structures of the present invention are covered with a stable aluminum oxide layer in the air to be protected, so that electrical characteristics can be stably maintained for a long time.

3A to 3E are graphs showing electron mobility, carrier concentration, sheet resistance and Hall coefficient of the metal oxide heterojunction structures according to the present invention. admit. The metal oxide heterojunction structures all include a 100 nm thick aluminum oxide layer.

3A to 3E, metal oxide heterojunction structures with the thicknesses of 8 nm and 10 nm of the indium oxide layer were found to have electrically semiconductive properties, and the metal oxide heterojunctions including 30 nm and 50 nm thick indium oxide layers The structures were found to have electrical properties close to that of metals, and the metal oxide heterojunction structure including a 100 nm thick indium oxide layer was found to have completely electrical conductor properties.

From these results, it can be seen that in the metal oxide heterojunction structure of the present invention, the characteristics from the semiconductor to the electric conductor can be realized by controlling the thickness of the indium oxide layer.

FIG. 4A is TEM images of an indium oxide layer formed by a room temperature sputtering process on a glass substrate, and FIG. 4B is TEM images after forming an aluminum oxide layer by an atomic layer deposition method on the indium oxide layer of FIG. Then,

4A, when an indium oxide layer is formed on a glass substrate through a room temperature sputtering process, a nanocrystalline interface layer is formed at an interface with the glass substrate, and crystalline indium oxide Layer is formed.

However, as a result of further experiments not shown in the drawing, an amorphous indium oxide layer is formed when the thickness of the indium oxide layer is 8 nm or less, but when the thickness of the indium oxide layer is 15 nm or more, a crystalline indium oxide layer is formed, As the thickness of the indium layer increases, the crystal size increases.

Referring to FIG. 4B, when an aluminum oxide layer is formed on the indium oxide layer through the atomic layer deposition method, an interface layer having a thickness of about 4 nm is formed.

FIG. 5A shows XPS analysis results measured on the surface of the indium oxide layer immediately after the indium oxide layer was formed on the glass substrate by the room temperature sputtering method. FIG. 5B and FIG. 5C show the result of XPS analysis on the indium oxide layer surface, XPS analysis results measured on the surface of the aluminum oxide layer and the interface layer with the indium oxide layer after the formation of the aluminum oxide layer by the method.

Referring to FIG. 5A, when the indium oxide layer is formed on the glass substrate by the room temperature sputtering method, it can be seen that the In3d composition stably exists.

Next, referring to FIGS. 5B and 5C, the surface of the aluminum oxide layer was found to be free of In3d. In the interfacial layer, In3d was measured to be highly reduced, and in the case of O1s, Al-O and In-O were mixed. From these results, it is considered that indium is reduced by aluminum at the interface between the aluminum oxide layer and the indium oxide layer, and as a result, a channel capable of charge transfer is formed in the interface layer.

6A to 6C show a sample (black solid line) immediately after the indium oxide layer was formed on a glazed substrate, a sample obtained by forming an indium oxide layer on a gallium substrate and thermally treating the indium layer in vacuum at 300 DEG C for 5 minutes ), A sample immediately after an indium oxide layer and an aluminum oxide layer were successively formed on a gallium substrate (blue solid color), and an indium oxide layer and an aluminum oxide layer formed continuously on a gallium substrate, Graphs showing the transmittance according to the wavelength of light measured for a sample heat treated for 5 minutes (green solid line). The aluminum oxide layers of Figs. 6A to 6C were all formed to a thickness of 100 nm.

6A and 6B, when a 100 nm thick aluminum oxide layer is formed on the 30 nm and 50 nm thick indium oxide layers, respectively, the transmittance of the visible light region in comparison with the single indium oxide layers of 30 nm and 50 nm thick But the transmittance of the ultraviolet region having a wavelength of 320 nm or more is remarkably increased, and the transmittance of visible light is more than 90%. In the case of forming an aluminum oxide layer on the indium oxide layer, the heat treatment was found to have little influence on the transmittance.

Referring to FIG. 6C, when a 100 nm thick aluminum oxide layer is formed on a 100 nm thick indium oxide layer, the transmittance of a visible light region of 400 nm or more and 800 nm or less is remarkably increased compared to a 100 nm thick single indium oxide layer And the transmittance of ultraviolet region was similar. In the case of forming an aluminum oxide layer on the indium oxide layer, the heat treatment was found to have little influence on the transmittance. From these results, it can be considered that the metal oxide heterojunction structure of FIG. 6C can be used as a transparent electrode.

<Electronic Apparatus>

The metal oxide heterojunction structure according to an embodiment of the present invention can be applied to various electronic devices as a semiconductor structure or an electric conductor structure.

In one embodiment, the metal oxide heterojunction structure according to the present invention may be applied as a semiconductor channel layer of a thin film transistor. In this case, in the metal oxide heterojunction structure, the indium oxide layer may have a thickness of about 8 nm or more and 15 nm or less. And the source electrode and the drain electrode of the thin film transistor may be positioned in contact with the interface layer of the indium oxide layer and the aluminum oxide layer. On the other hand, in the case of a top gate structure thin film transistor, when the gate electrode of the thin film transistor is disposed on the aluminum oxide layer, the aluminum oxide layer may function as a gate insulating film, so that a separate gate insulating film may not be required .

In another embodiment, the metal oxide heterojunction structure according to the present invention may be applied as a transparent electrode of an electronic device. In this case, in the metal oxide heterojunction structure, the indium oxide layer may have a thickness of about 100 nm or more.

According to the present invention, the electrical characteristics of the metal oxide heterojunction structure can be easily controlled by adjusting the thickness of the indium oxide layer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. It can be understood that it is possible.

none

Claims (11)

A metal oxide heterojunction structure comprising an indium oxide layer and an aluminum oxide layer in contact with the indium oxide layer,
Wherein an interfacial layer is provided between the indium oxide layer and the aluminum oxide layer, the interfacial layer including indium ions, aluminum ions and oxygen ions, and providing a charge transport channel. The method according to claim 1,
The indium oxide layer has a thickness of 8 nm or more and 15 nm or less,
The aluminum oxide layer has a thickness of 10 nm or more,
Wherein the interface layer has a semiconductor property. 3. The method of claim 2,
Wherein the indium oxide layer comprises at least a portion of the nanocrystallized region. The method according to claim 1,
The indium oxide layer has a thickness of 100 nm or more,
The aluminum oxide layer has a thickness of 10 nm or more,
Wherein the interface layer has electrical conductor properties. &Lt; RTI ID = 0.0 &gt; 11. &lt; / RTI &gt; 5. The method of claim 4,
Wherein the indium oxide layer is crystallized in an area of 90% or more. 6. The method according to any one of claims 1 to 5,
Wherein the interface layer has a thickness of 3 nm or more and 5 nm or less. Forming an indium oxide layer by a sputtering method performed at room temperature on a substrate; And
And forming an aluminum oxide layer on the indium oxide layer through a vacuum deposition process performed at 150 to 250 ° C. A thin film transistor for controlling a gate voltage applied to a gate electrode to transmit a signal of a source electrode through a semiconductor channel layer to a drain electrode,
Wherein the semiconductor channel layer comprises a metal oxide heterojunction structure comprising an indium oxide layer and an aluminum oxide layer in contact with the indium oxide layer,
Wherein an interfacial layer is formed between the indium oxide layer and the aluminum oxide layer, the interfacial layer including indium ions, aluminum ions, and oxygen ions to provide a moving channel of the signal. 9. The method of claim 8,
Wherein the indium oxide layer has a thickness of 8 nm or more and 15 nm or less, and the aluminum oxide layer has a thickness of 10 nm or more. 10. The method of claim 9,
Wherein the source electrode and the drain electrode are disposed in contact with the interface layer and spaced apart from each other. 10. The method of claim 9,
Wherein the gate electrode is located on the aluminum oxide layer,
Wherein the aluminum oxide layer insulates the interface layer from the gate electrode.
KR1020160154013A 2016-11-18 2016-11-18 Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure KR101914835B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020160154013A KR101914835B1 (en) 2016-11-18 2016-11-18 Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure
PCT/KR2017/011403 WO2018093048A1 (en) 2016-11-18 2017-10-16 Metal oxide heterojunction structure, method for manufacturing same, and thin film transistor containing same
CN201780071720.9A CN110268528A (en) 2016-11-18 2017-10-16 The heterogeneous connected structure of metal oxide, its manufacturing method and the thin film transistor (TFT) containing it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160154013A KR101914835B1 (en) 2016-11-18 2016-11-18 Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure

Publications (2)

Publication Number Publication Date
KR20180056145A true KR20180056145A (en) 2018-05-28
KR101914835B1 KR101914835B1 (en) 2018-11-02

Family

ID=62145661

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160154013A KR101914835B1 (en) 2016-11-18 2016-11-18 Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure

Country Status (3)

Country Link
KR (1) KR101914835B1 (en)
CN (1) CN110268528A (en)
WO (1) WO2018093048A1 (en)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5116290B2 (en) * 2006-11-21 2013-01-09 キヤノン株式会社 Thin film transistor manufacturing method
US20100006837A1 (en) * 2008-07-09 2010-01-14 Electronics And Telecommunications Research Institute Composition for oxide semiconductor thin film, field effect transistor using the composition and method of fabricating the transistor
US7812346B2 (en) * 2008-07-16 2010-10-12 Cbrite, Inc. Metal oxide TFT with improved carrier mobility
US9269573B2 (en) * 2008-09-17 2016-02-23 Idemitsu Kosan Co., Ltd. Thin film transistor having crystalline indium oxide semiconductor film
KR20180059577A (en) * 2009-11-27 2018-06-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
KR20110066370A (en) * 2009-12-11 2011-06-17 한국전자통신연구원 Oxide thin film transistor and method for manufacturing the same
KR101097322B1 (en) * 2009-12-15 2011-12-23 삼성모바일디스플레이주식회사 Thin film transistor, method of manufacturing the thin film transistor and organic electroluminiscent device having the thin film transistor
JP2012169344A (en) * 2011-02-10 2012-09-06 Sony Corp Thin film transistor, display device and electronic equipment
KR102089505B1 (en) * 2011-09-23 2020-03-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
DE102011084145A1 (en) * 2011-10-07 2013-04-11 Evonik Degussa Gmbh Process for the preparation of high-performance and electrically stable, semiconducting metal oxide layers, layers produced by the process and their use
KR101943077B1 (en) * 2012-12-12 2019-04-17 한국전자통신연구원 A transistor hanving nano layer structured oxides and method of manufacturing the same

Also Published As

Publication number Publication date
WO2018093048A1 (en) 2018-05-24
KR101914835B1 (en) 2018-11-02
CN110268528A (en) 2019-09-20

Similar Documents

Publication Publication Date Title
KR100889796B1 (en) Field effect transistor employing an amorphous oxide
US7309895B2 (en) Semiconductor device
US7691715B2 (en) Method of fabricating oxide semiconductor device
JP5116290B2 (en) Thin film transistor manufacturing method
US8389996B2 (en) Method for forming semiconductor film, method for forming semiconductor device and semiconductor device
US20080277663A1 (en) Thin film transistor and method of manufacturing the same
JP2010040552A (en) Thin film transistor and manufacturing method thereof
KR20140074742A (en) Transistor, method of manufacturing the same and electronic device including transistor
CN104425620B (en) Semiconductor device and method for manufacturing the same
Zhang et al. Ultrathin-Body TiO 2 Thin Film Transistors With Record On-Current Density, ON/OFF Current Ratio, and Subthreshold Swing via O 2 Annealing
JP6036984B2 (en) Oxynitride semiconductor thin film
JP2016201458A (en) Microcrystalline oxide semiconductor thin film and thin film transistor using the same
KR102163565B1 (en) Oxide semiconductor thin film transistor
KR101914835B1 (en) Metal oxide heterojunction structure, method of manufacturing the metal oxide heterojunction structure, and thin film transistor having the metal oxide heterojunction structure
KR20150045761A (en) Thin film transistor and method of manufacturing the same
KR20090059494A (en) Oxide semiconductor and thin film transistor comprising the same
KR102389220B1 (en) Thin film transistor including crystalline izto oxide semiconductor and fabrication method for the same
KR102000829B1 (en) Thin Film Transistor Including a High-k Insulating Thin Film and Method for Manufacturing The Same
JP5612299B2 (en) Method for manufacturing transistor
Yoon et al. Improvement in IGZO-based thin film transistor performance using a dual-channel structure and electron-beam-irradiation
KR102214812B1 (en) Amorphous thin film transistor and manufacturing method thereof
KR102685952B1 (en) Thin film transistor including spinel single-phase crystalline izto oxide semiconductor
KR102661897B1 (en) Thin film transistor which can be manufactured by low-temperature process, manufacturing method of the same transistor, semiconductor part and electronic device including the same transistor
KR101519480B1 (en) Oxide Semiconductor and Thin Film Transistor comprising the same
KR101993383B1 (en) Method for forming insulator film and manufacturing method of thin film transistor by applied the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant