KR20180053939A - Solar cell and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a solar cell according to an embodiment of the present invention includes the steps: forming a first tunneling layer on one surface of a semiconductor substrate; forming a first conductive region on the first tunneling layer; and forming a first electrode electrically connected to the first conductive region. In the step of forming the first conductive region, the first conductive region is formed to include a binary metal oxide layer with an amorphous structure. Accordingly, the present invention can obtain high efficiency and reliability.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell including a binary metal oxide and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize a solar cell, it is required to overcome a low efficiency and a low productivity, and a solar cell capable of maximizing the efficiency and productivity of the solar cell is required.

For example, in a conventional solar cell manufactured by doping a semiconductor substrate with a dopant, the doping process and the like are very complicated, and the interfacial characteristics of the semiconductor substrate are degraded, resulting in poor passivation characteristics. In order to prevent this, in the solar cell formed without doping the dopant, characteristics and efficiency of the solar cell are largely changed depending on the characteristics of the layer included therein, and the reliability of the solar cell is not high.

The present invention provides a solar cell having excellent and uniform efficiency and characteristics and high productivity, and a method for manufacturing the solar cell.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a first tunneling layer on one surface of a semiconductor substrate; Forming a first conductive type region on the first tunneling layer; And forming a first electrode electrically connected to the first conductive type region. In the forming of the first conductive type region, the first conductive type region may include a binary metal oxide layer having an amorphous structure.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A tunneling layer located on one side of the semiconductor substrate; A first conductive type region located above the tunneling layer and extracting a first carrier; And a first electrode electrically connected to the first conductive type region. And the first conductivity type region includes an amorphous binary metal oxide layer. At least the boundary portion of the first conductive type region adjacent to the tunneling layer is composed of an amorphous portion in which the amorphous portion having the amorphous structure is formed wider than the crystalline portion having the crystalline structure.

In this embodiment, the boundary portion of the conductive type region is formed of an amorphous portion, and the solar cell including the binary metal oxide layer has excellent efficiency and reliability, and is formed by a simple process and can have high productivity.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a front plan view of the solar cell shown in FIG.
FIG. 3A is a band diagram of a semiconductor substrate, a second tunneling layer, and a second conductivity type region in a solar cell according to an embodiment of the present invention, and FIG. 3B is a band diagram of a semiconductor substrate, , The first tunneling layer, and the first conductive type region.
4 is a cross-sectional view of a solar cell according to a modification of the present invention.
5A to 5C are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
6 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
7 is a rear plan view of the solar cell shown in Fig.
FIG. 8A is a transmission electron microscope (TEM) photograph of a solar cell according to Example 1, and FIG. 8B is a transmission electron microscope photograph of a solar cell according to Comparative Example 2. FIG.
FIG. 9 is a graph showing the implied open-circuit voltage (implied Voc) of the solar cells according to Examples 1, 5 and 6 and Comparative Example 3. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, the expressions "first "," second "and the like are used only for distinguishing each other, and the present invention is not limited thereto.

Hereinafter, a solar cell and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10, a first tunneling layer 52 formed on one surface of the semiconductor substrate 10, a first tunneling layer 52 And a first electrode 42 electrically connected to the first conductive type region 20. The first conductive type region 20 and the second conductive type region 30 are electrically connected to each other, Two electrodes 44 may be included. At this time, in the present embodiment, at least one of the first conductive type region 20 and the second conductive type region 30 is composed of a binary metal oxide layer having an amorphous structure. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type including a first or a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be comprised of a single crystalline semiconductor (e.g., a single single crystal or polycrystalline semiconductor, such as single crystal or polycrystalline silicon, particularly monocrystalline silicon) comprising an n-type or p-type dopant. The base region 110 having a high degree of crystallinity and having few defects or the solar cell 100 based on the semiconductor substrate 10 has excellent electrical characteristics. In this embodiment, the semiconductor substrate 10 may include only the base region 110 having no doping region formed by additional doping or the like. As a result, the passivation property of the semiconductor substrate 10 due to the doped region can be prevented from deteriorating.

For example, in this embodiment, the base region 110 may be doped with an n-type dopant to have an n-type. If the base region 10 has an n-type conductivity, it is possible to easily form and obtain a binary metal oxide layer used as the first and second conductivity type regions 20 and 30. Concrete materials of the first and second conductivity type regions 20 and 30 will be described later in detail.

An anti-reflection structure capable of minimizing reflection can be formed on the front surface and the rear surface of the semiconductor substrate 10. For example, a texturing structure having a concavo-convex shape in the form of a pyramid or the like may be provided as an antireflection structure. The texturing structure formed in the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (e.g., (111) plane) of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased due to the unevenness formed on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident into the semiconductor substrate 10 can be reduced to minimize optical loss. However, the present invention is not limited thereto, and a texturing structure may be formed on only one side of the semiconductor substrate 10, or a texturing structure may not be formed on the front and back sides of the semiconductor substrate 10.

On the front surface of the semiconductor substrate 10, a first tunneling layer 52 is formed (e.g., contacted). The first tunneling layer 52 acts as a kind of barrier for electrons and holes to prevent the minority carriers from passing through and after many carriers are accumulated in the portion adjacent to the first tunneling layer 52 Only a majority carrier having energy above a certain level can pass through the first tunneling layer 52. At this time, a plurality of carriers having an energy of a certain level or higher can easily pass through the first tunneling layer 52 by the tunneling effect. And the first tunneling layer 52 can improve the passivation property on the surface of the semiconductor substrate 10.

The first tunneling layer 52 may be formed entirely on the front surface of the semiconductor substrate 10. Accordingly, it can be easily formed without additional patterning while having excellent passivation characteristics. And the first tunneling layer 52 may be an undoped film containing no dopant. In this embodiment, since the first conductive type region 20 is made of a binary metal oxide and the first tunneling type layer 52 can be formed relatively thick, The layer 52 or the semiconductor substrate 10 does not occur. Accordingly, the first tunneling layer 52 may be composed of an undoped film.

The first tunneling layer 52 may include various materials through which a plurality of carriers can be tunneled. For example, the first tunneling layer 52 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the first tunneling layer 52 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, intrinsic amorphous semiconductor, intrinsic polycrystalline semiconductor, and the like. In particular, the first tunneling layer 52 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier. Such a silicon oxide layer may be formed by thermal oxidation or chemical oxidation. Alternatively, the first tunneling layer 52 may be an intrinsic amorphous silicon (i-a-Si) layer. Since the first tunneling layer 52 has similar characteristics including the same semiconductor material as the semiconductor substrate 10, the passivation characteristics can be improved more effectively. However, the present invention is not limited thereto. Accordingly, the first tunneling layer 52 may be composed of an intrinsic amorphous silicon carbide (i-a-SiCx) layer or an intrinsic amorphous silicon oxide (i-a-SiOx) layer. According to this, although the effect due to the wide energy band gap can be improved, the passivation characteristic may be somewhat lower than in the case of including an intrinsic amorphous silicon (i-a-Si) layer.

The first conductive type region 20 is positioned (e.g., in contact) on the first tunneling layer 52. The first conductive type region 20 may be formed entirely on the first tunneling layer 52. Accordingly, the area of the first conductivity type region 20 having a sufficient area contributes to the photoelectric conversion can be maximized. In this embodiment, the first conductive type region 20 includes a metal oxide layer having an amorphous structure, which will be described later in more detail.

The thickness of the first tunneling layer 52 may be equal to, less than, or greater than the thickness of the first conductivity type region 20. In this embodiment, the first conductivity type region 20 may be formed of a binary metal oxide layer having an amorphous structure, and the amorphous structure may be formed and maintained when the amorphous structure has a thin thickness. Accordingly, the thickness of the first tunneling layer 52 is not necessarily limited to the thickness of the first conductivity type region 20 because the first conductivity type region 20 has a small thickness in this embodiment . For example, when the thickness of the first conductive type region 20 is minimized so that the first conductive type region 20 has a more stable amorphous structure, the thickness of the first conductive type region 20 may be equal to or greater than the thickness of the first tunneling type layer 52 It can be smaller. As another example, if the thickness of the first tunneling layer 52 is reduced in order to maximize the tunneling effect through the first tunneling layer 52, the thickness of the first tunneling layer 52 may be less than the thickness of the first tunneling layer 52. May be less than the thickness.

Alternatively, the first tunneling layer 52 may have a thickness of 10 nm or less, and the first conductivity type region 20 may have a thickness of 30 nm or less (for example, 10 nm or less). When the thickness of the first tunneling layer 52 exceeds 10 nm, the tunneling does not smoothly occur and the solar cell 100 may not operate smoothly. If the thickness of the first conductivity type region 20 is 30 nm or less, it may be difficult to have an amorphous structure and the carrier may not flow smoothly due to low electrical conductivity. At this time, if the first conductivity type region 20 has a thickness of 10 nm or less, the amorphous structure can be stably maintained.

For example, the first tunneling layer 52 may have a thickness of 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm) in order to sufficiently realize the tunneling effect. If the thickness of the first tunneling layer 52 is less than 0.5 nm, it may be difficult to form the first tunneling layer 52 of desired quality. The first conductive type region 20 may have a thickness of 2 nm or more (for example, 6 nm or more) so as to stably function as the conductive type region 20. However, the present invention is not limited thereto, and the thickness of the first tunneling layer 52 and / or the first conductivity type region 30 may have various values.

A first electrode 42 electrically connected to the first conductive type region 20 is formed on the first conductive type region 20. For example, the first electrode 42 may include a first transparent electrode layer 420 and a first metal electrode layer 422 that are sequentially stacked on the first conductive type region 20.

Here, the first transparent electrode layer 420 may be formed in a relatively large area (for example, in contact) on the first conductive type region 20. For example, the first transparent electrode layer 420 may be formed entirely on the first conductive type region 20. [ When the first transparent electrode layer 420 is formed on the first conductive type region 20 as described above, the carrier can easily reach the first metal electrode layer 422 through the first transparent electrode layer 420, Can be reduced. Particularly, in this embodiment, since the first conductive type region 20 is undoped and composed of a metal compound layer that does not include a dopant, the resistance may be lowered. Therefore, the first transparent electrode layer 420 may be provided to effectively reduce the resistance .

Since the first transparent electrode layer 420 is formed over the first conductive type region 20 as described above, the first transparent electrode layer 420 may be formed of a light-transmitting material (transparent material). That is, the first transparent electrode layer 420 is made of a transparent conductive material so that the carrier can be easily moved while allowing transmission of light. Accordingly, even if the first transparent electrode layer 420 is formed over the first conductivity type region 20 in a wide area, the transmission of light is not blocked. For example, the first transparent electrode layer 420 may include indium tin oxide (ITO), carbon nanotube (CNT), or the like. However, the present invention is not limited thereto and may include the first transparent electrode layer 420 and various other materials.

A first metal electrode layer 422 may be formed on the first transparent electrode layer 420. For example, the first metal electrode layer 422 may be formed in contact with the first transparent electrode layer 420 to simplify the structure of the first electrode 42. However, the present invention is not limited to this, and various modifications such as the existence of a separate layer between the first transparent electrode layer 420 and the first metal electrode layer 422 are possible.

The first metal electrode layer 422 located on the first transparent electrode layer 420 may be formed of a material having a higher electrical conductivity than the first transparent electrode layer 420. Thus, characteristics such as carrier collection efficiency and resistance reduction by the first metal electrode layer 422 can be further improved. For example, the first metal electrode layer 422 may be composed of a transparent or opaque metal having a lower electrical conductivity than the first transparent electrode layer 420.

As described above, the first metal electrode layer 422 may be opaque or have a low transparency and may interfere with the incidence of light, so that it may have a certain pattern so as to minimize shading loss. The first metal electrode layer 422 has a smaller area than the first transparent electrode layer 420. Thus, light can be incident on a portion where the first metal electrode layer 422 is not formed. The planar shape of the first metal electrode layer 422 will be described later in more detail with reference to FIG.

In this embodiment, since the first metal electrode layer 422 is formed adjacent to or in contact with the first transparent electrode layer 420, a fire-through penetrating the insulating film or the like is not required. The first metal electrode layer 422 is coated (e.g., printed) with a low temperature firing paste that can be fired by firing at a low temperature (350 占 폚 or less, for example, 300 占 폚 or less, And then heat treating it.

The low-temperature firing paste or the first metal electrode layer 422 formed by the paste is a glass frit composed of a certain metal compound (for example, an oxide containing oxygen, a carbide containing carbon, a sulfide containing sulfur) ), But may include metal particles and a cross-linking resin, and may contain only other resins (for example, a curing agent, an additive). If the low temperature firing paste or the first metal electrode layer 422 is not provided with the glass frit, the metal particles of the first metal electrode layer 422 are not sintered but are contacted with each other to aggregate, curing).

The metal particles may include various materials that provide conductivity. For example, the metal particles may be silver (Ag), aluminum (Al), copper (Cu), silver, aluminum or copper particles coated with silver or tin (Sn) alone or in combination of two or more.

The cross-linking resin may include a material capable of cross-linking between metals. In this embodiment, the first metal electrode layer 422 may be an electrode layer to which a solder layer for bonding a wiring material or the like is attached. The bridging resin may also prevent penetration of the solder layer. Unlike the present embodiment, the solder layer penetrates into the first metal electrode layer 422 and has brittleness, so that the first metal electrode layer 422 can be easily broken by a small impact or the like . In this embodiment, it is predicted that the cross-linking resin fills in between the metal particles to prevent penetration of the solder layer. For example, the cross-linking resin may include a phenoxy-based resin, an epoxy-based resin, a cellulose-based resin, and the like. They are excellent in crosslinking properties and do not change the characteristics of the electrodes. In particular, an epoxy-based resin is used and it can have excellent crosslinking properties. In addition, the first metal electrode layer 422 may further include a curing agent. As the curing agent, an amine curing agent can be used. Examples of the amine-based curing agent include phthalic anhydride, diethylamino propylamine, diethylene triamine, and the like. In addition, additives and the like may be included.

The low temperature paste for forming the first metal electrode layer 422 includes a solvent, but the solvent may be volatilized during the heat treatment and may not be contained in the first metal electrode layer 422 or may be included in a very small amount. As the solvent, an organic solvent can be used. For example, butyl carbitol acetate (BCA), cellulose acetate (CA) or the like can be used, but the present invention is not limited thereto.

At this time, metal or metal particles may be included in the first metal electrode layer 422 more than the crosslinking resin. Thus, the first metal electrode layer 422 can have sufficient conductivity. For example, when the sum of the metal particles and the crosslinking resin is 100 parts by weight, the metal particles may be contained in an amount of 80 to 95 parts by weight, the crosslinking resin may be contained in an amount of 5 to 20 parts by weight, and the curing agent may be included in an amount of 0.1 to 5 parts by weight. The solvent may be contained in an amount of 3 to 10 parts by weight based on 100 parts by weight of the sum of the metal particles and the crosslinking resin before the heat treatment, but is not volatilized after the heat treatment or only a trace amount exists. Since the content of other materials such as a hardening agent after the heat treatment is not large, the weight of the metal or metal particles in the first metal electrode layer 422 may be 80 to 95 parts by weight.

If the weight ratio of the metal particles is less than 80 or the weight portion of the crosslinking resin exceeds 20, the conductivity by the metal particles may not be sufficient. If the weight percentage of the metal particles exceeds 95 or the weight percentage of the crosslinking resin is less than 5, the crosslinking resin is not sufficient and the effect of preventing the penetration of the solder layer by the crosslinking resin may not be sufficient. The curing agent is contained in such an amount as to ensure sufficient curing without deteriorating the characteristics of the low-temperature paste, and the solvent is included in such an amount that the various materials are uniformly mixed and volatilized during the heat treatment so as not to degrade the electrical characteristics. However, the present invention is not limited to these numerical values.

In this embodiment, the metal particles may have the same shape, or different metal particles having different shapes, particle sizes, materials, etc. may be mixed and used.

Hereinafter, an example of the planar shape of the first metal electrode layer 422 of the first electrode 42 will be described in detail with reference to FIGS. 1 and 2. FIG. 2 is a front plan view of the solar cell shown in FIG. The first transparent electrode layer 420 of the first electrode 42 is not shown in FIG. 2 for the sake of simplicity.

Referring to FIG. 2, the first metal electrode layer 422 of the first electrode 42 may include a plurality of finger electrodes 42a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a are parallel to each other and parallel to the edge of the semiconductor substrate 10, the present invention is not limited thereto. The first metal electrode layer 422 of the first electrode 42 is formed in a direction intersecting (for example, orthogonal to) the finger electrodes 42a so that the bus bar electrode 42b connecting the finger electrodes 42a . Only one bus bar electrode 42b may be provided or a plurality of bus bar electrodes 42b may be provided with a larger pitch than the pitch of the finger electrodes 42a as shown in FIG. At this time, the width of the bus bar electrode 42b may be larger than the width of the finger electrode 42a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrode 42b may be equal to or smaller than the width of the finger electrode 42a.

Referring again to FIG. 1, a second tunneling layer 54 is positioned (e.g., in contact) on the back surface of the semiconductor substrate 10 and a second conductive type region 30 is located on the second tunneling layer 54 (For example, contact). And the second electrode 44 electrically connected to the second conductivity type region 30 may be positioned (e.g., in contact). The second electrode 44 may include a second transparent electrode layer 440 and a second metal electrode layer 442 which are sequentially stacked on the second conductive type region 30. Except that the second tunneling layer 54, the second conductivity type region 30 and the second electrode 44 are located on the backside of the semiconductor substrate 10, the first tunneling layer 52, Type region 20 and the second electrode 44, the description thereof can be applied as it is. However, the first conductive type region 20 and the second conductive type region 30 have different materials because the polarities of carriers extracted from the first conductive type region 20 and the second conductive type region 30 are different from each other. The first tunneling layer 52 and the second tunneling layer 54 may have the same thickness, shape, material, or the like, or may have different thicknesses, shapes, materials, and the like. The first transparent electrode layer 420 and / or the first metal electrode layer 422 and the second transparent electrode layer 440 and / or the second metal electrode layer 442 may have the same shape and / or material, And / or materials. The width and pitch of the finger electrode 42a and the bus bar electrode 42b of the first metal electrode layer 422 are the same as the width and pitch of the finger electrode and the bus bar electrode of the second metal electrode layer 442 Or may be different. Alternatively, the planar shapes of the first metal electrode layer 422 and the second metal electrode layer 442 may be different from each other, or the lamination structure of the first electrode 42 and the second electrode 44 may be different from each other. Various other variations are possible.

Although not shown in FIG. 1, an insulating film constituting a passivation film, an antireflection film, a reflection film, or the like is formed on the first and second conductive type regions 20 and 30 and / or on the first and second transparent electrode layers 422 and 442 Or may be formed additionally.

At this time, in this embodiment, at least one of the first and second conductivity type regions 20 and 30 is composed of a binary metal oxide layer having an amorphous structure. Hereinafter, the first and second conductivity type regions 20 and 30 are each a binary metal oxide layer having an amorphous structure.

Specifically, the first conductive type region 20 and the second conductive type region 30 may have first or second carriers (electrons or holes) having different polarities in consideration of the energy band with respect to the semiconductor substrate 10 And a metal compound that can be selectively extracted and collected. Accordingly, the first conductive type region 20 and the second conductive type region 30 do not include a semiconductor material, or a material that acts as a dopant in the semiconductor material. This will be described in more detail with reference to FIG.

3 (a) is a band diagram of the semiconductor substrate 10, the second tunneling layer 54 and the second conductivity type region 30 in the solar cell 100 according to the embodiment of the present invention, and FIG. 3 (b) The band diagram of the semiconductor substrate 10, the first tunneling layer 52, and the first conductivity type region 20 in the solar cell 100 according to the embodiment of the present invention. Here, as described above, the semiconductor substrate 10 may be configured as an n-type base region 110. [

Referring to FIGS. 3A and 3B, in this embodiment, one of the first conductive type region 20 and the second conductive type region 30 extracts and collects the first carrier, A second carrier having an opposite polarity to the one carrier is extracted and collected.

Hereinafter, the first conductive type region 20 extracts holes and the second conductive type region 30 extracts electrons. The first conductivity type region 20 functions as an emitter region by extracting holes of opposite polarity from electrons which are the majority carriers of the n type base region 110 and the second conductivity type region 30 functions as an n- (Back electric field region) by extracting electrons which are majority carriers of the base region 110 of the light emitting element. According to this, the first conductivity type region 20, which is located on the front side of the semiconductor substrate 10 and functions as an emitter region for substantially photoelectric conversion, can effectively extract and collect holes having a relatively low moving speed. However, the present invention is not limited thereto. The second conductive type region 30 which is located on the rear surface of the semiconductor substrate 10 and is composed of the front electric field region for extracting electrons and the first conductive type region 20 located on the front surface of the semiconductor substrate 10, And an emitter region for extracting the holes.

More specifically, the binary metal compound layer constituting the first conductive type region 20 capable of selectively extracting and collecting holes has a Fermi level lower than the fermi level of the semiconductor substrate 10, And may have a work function that is greater than the work function of the semiconductor substrate 10. For example, the work function of the semiconductor substrate 10 can be about 3.7 eV, and the work function of the first conductivity type region 20 can be greater than 3.8 eV. More specifically, the work function of the first conductivity type region 20 may be 7 eV or less (for example, 3.8 eV to 7 eV). If the work function of the first conductivity type region 20 exceeds 7 eV, it may be difficult to selectively collect holes. If the above-mentioned energy band gap is less than 3.8 eV, it may be difficult to selectively collect only holes except electrons.

When the first conductive type region 20 composed of the metal compound layer having the Fermi level and the work function is bonded to the semiconductor substrate 10 with the first tunneling layer 52 therebetween, The Fermi level of the semiconductor substrate 10 and the first conductivity type region 20 are aligned and bonded so as to have the same value. 3 (b), holes in the electrical current path within the semiconductor substrate 10 can easily move according to electrical conductivity of the first conductivity type region 20 when passing through the first tunneling layer 52 . On the other hand, electrons in the semiconductor substrate 10 do not pass through the first tunneling layer 52.

Examples of the binary metal compound layer that can be used for the first conductive type region 20 include a molybdenum oxide layer composed of molybdenum oxide, a tungsten oxide layer composed of tungsten oxide (e.g., WO ₃ ), a vanadium oxide composed of vanadium oxide An oxide layer, a nickel oxide layer composed of nickel oxide, and a rhenium oxide layer composed of rhenium oxide. In particular, if the first conductive type region 20 includes a molybdenum oxide layer or a tungsten oxide layer, the effect of selectively collecting holes may be excellent.

The metal compound layer of the second conductivity type region 30 capable of selectively collecting electrons has a Fermi level higher than the Fermi level of the semiconductor substrate 10 and has a work function smaller than the work function of the semiconductor substrate 10 Lt; / RTI > For example, the work function of the semiconductor substrate 10 can be about 3.7 eV, and the work function of the second conductivity type region 30 can be 0.1 eV to 3.6 eV. More specifically, the energy band gap between the conduction band of the second conduction type region 30 and the conduction band of the semiconductor substrate 10 may be 1 eV or less (for example, 0.1 eV to 1 eV). If the energy band gap described above exceeds 1 eV, it may be difficult to selectively collect electrons. If the energy band gap is less than 0.1 eV, the energy band gap may be small and it may be difficult to selectively collect only electrons except the holes.

When the second conductive type region 30 composed of the metal compound layer having the Fermi level and the work function is bonded to the semiconductor substrate 10 with the second tunneling layer 54 sandwiched therebetween, The Fermi level of the semiconductor substrate 10 and the second conductivity type region 30 are aligned and bonded so as to have the same value. Electrons in the conduction band in the semiconductor substrate 10 can easily move to the conduction band of the second conduction type region 30 when passing through the second tunneling layer 54. [ On the other hand, holes in the semiconductor substrate 10 do not pass through the second tunneling layer 54.

For example, the metal compound layer that can be used for the second conductivity type region 30 as described above includes a titanium oxide layer composed of titanium oxide (for example, TiO ₂ ), a titanium oxide layer composed of zinc oxide (for example, ZnO) A zinc oxide layer, and a niobium oxide layer composed of niobium oxide (for example, Nb ₂ O ₅ ). In particular, if the second conductivity type region 30 includes a titanium oxide layer, the effect of selectively collecting electrons can be excellent.

The first and second conductivity type regions 20 and 30 having a binary metal oxide layer are materials that can easily extract and collect the first or second carriers and prevent recombination by the dopant to improve the open circuit voltage . In addition, the loss due to light absorption can be reduced as compared with the doped region or the doped film, and the short circuit current density can be improved. Thus, the efficiency of the solar cell 100 can be improved. Further, it can be manufactured by omitting a dopant doping process, a dopant activating process, and the like. In particular, since a high temperature process is not required, a process can be performed at a low temperature, thereby simplifying a manufacturing process and reducing a manufacturing cost. Therefore, the productivity of the solar cell 100 can be improved.

At this time, the first and second conductivity type regions 20 and 30 formed of the binary metal oxide layer in this embodiment have an amorphous structure. This is because if the binary metal oxide layer has a crystalline structure, the passivation property is significantly lowered and the efficiency of the solar cell 100 is greatly lowered. The exact reason for this is not known, but it can be confirmed experimentally. Although it is not clear, if the crystal structure is abundantly included, the optical absorption is greatly increased to cause a current loss, and the surface roughness of the metal oxide layer increases, and the interfacial bond acts to increase the recombination loss.

For example, the boundary between the first and second conductive regions 20 and 30 adjacent to the first or second tunneling layer 52 and 54 may be formed such that an amorphous portion having an amorphous structure is formed wider than a crystalline portion having a crystalline structure And an amorphous portion (AA). Only in this case can we have sufficient passivation properties. Particularly, when the amorphous portion AA located at the boundary between the first and second conductive type regions 20 and 30 adjacent to the first or second tunneling layer 54 has an amorphous structure as a whole, . For example, the ratio of the area occupied by the amorphous portion at the boundary of the first and second conductivity type regions 20 and 30 adjacent to the first or second tunneling layer 54 is 95% to 100% (for example, 99% To 100%). With such a range, excellent efficiency can be obtained in the solar cell 100 having the first and second conductivity type regions 20 and 30 of a binary metal oxide layer.

In the figure, it is illustrated that the amorphous portion AA is formed entirely in the thickness direction of the first and second conductivity type regions 20 and 30. However, the present invention is not limited thereto. 4, the amorphous portion AA may be partially located in the thickness direction of the first and / or the second conductive type regions 20 and 30, and the amorphous portion AA May be located at the portion closest to the first or second tunneling layer 52, 54 or the semiconductor substrate 10. At this time, the ratio of the thickness of the amorphous portion AA to the total thickness of the first or second conductivity type regions 20 and 30 is 0.2 or more (that is, 0.2 to 1) or the ratio of the thickness of the first or second conductivity type region 20, and 30, the thickness of the amorphous portion AA may be 1 nm or more. The passivation property can be sufficiently realized if the amorphous portion AA having a thickness of at least a certain thickness (for example, a thickness ratio of 0.2 or more or a thickness of 1 nm or more) is located at the boundary portion adjacent to the first or second tunneling layer 52 or 54 . Although the non-amorphous portion AA having a crystalline portion wider than the amorphous portion AA is formed entirely on the amorphous portion AA, the present invention is not limited thereto. The portion NA that is not the amorphous portion AA may be partially formed in plan view. The first and / or second conductivity type regions 20 and 30 of such a shape may appear when the process conditions of the forming process are somewhat unstable or when the process conditions in the subsequent process are somewhat unstable. However, the present invention is not limited thereto, and the first and / or second conductivity type regions 20 and 30 may be formed by intentionally controlling the process conditions. The portion (NA) which is not the amorphous portion (AA) can be formed with a wide crystalline portion to improve the carrier mobility, so that the efficiency of transferring the carrier to the first or second electrode (42, 44) can be improved.

In the above description and drawings, it is exemplified that the first and second conductivity type regions 20 and 30 are all composed of a binary metal compound layer. However, the present invention is not limited thereto, and it is also possible that only one of the first and second conductivity type regions 20 and 30 is composed of the above-described two-component metal compound layer. Various other variations are possible.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by photoelectric conversion, and one of the generated holes and electrons is tunneled through the first tunneling layer 52 to form the first conductivity- 20 and then transferred to the second electrode 44 after the second tunneling layer 54 is tunneled to the second conductivity type region 30 after the first tunneling layer 54 is transferred to the first electrode 42. The holes and electrons transferred to the first and second electrodes 42 and 44 move to an external circuit or another solar cell 100. Thereby generating electrical energy.

In this embodiment, since the first and second metal electrode layers 422 and 442 of the solar cell 100 have a predetermined pattern, the solar cell 100 can receive light from the front and back surfaces of the semiconductor substrate 10 And has a bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto.

Since the first and second conductive regions 20 and 30 are formed on the semiconductor substrate 10 with the first or second tunneling layer 52 and 54 interposed therebetween, . As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region. In particular, the first and second conductivity type regions 20 and 30 are composed of a semiconductor material and a binary metal oxide layer that does not contain a dopant to improve the open-circuit voltage and the short-circuit current density, 20 and 30 can be simplified. Thus, efficiency and productivity of the solar cell 100 can be improved.

Particularly, in this embodiment, the solar cell 100 including the biconstituent metal oxide layer is composed of the amorphous portion AA at the boundary portion of the first and / or the second conductivity type regions 20 and 30, .

The solar cell 100 including the first and second conductivity type regions 20 and 30 having the amorphous portion AA described above can be formed by various manufacturing methods. Hereinafter, a method of manufacturing the solar cell 100 according to the present embodiment will be described in detail.

Hereinafter, a method of manufacturing the solar cell 100 according to the embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5C. FIG. 5A to 5C are cross-sectional views illustrating a method of manufacturing a solar cell 100 according to an embodiment of the present invention.

As shown in FIG. 5A, first and second tunneling layers 52 and 54 are formed on the front surface and the rear surface of the semiconductor substrate 10, respectively. For example, the first tunneling layer 52 located on the front surface of the semiconductor substrate 10 and the second tunneling layer 54 located on the rear surface of the semiconductor substrate 10 may be simultaneously formed. This can simplify the manufacturing process. However, the present invention is not limited thereto, and the first tunneling layer 52 and the second tunneling layer 54 may be formed in different processes.

The first and second tunneling layers 52 and 54 may be formed by thermal growth, deposition (e.g., chemical vapor deposition (PECVD), atomic layer deposition (ALD)), chemical oxidation, However, the present invention is not limited thereto, and the first and second tunneling layers 52 and 54 may be formed by various methods.

At this time, the front surface and / or the rear surface of the semiconductor substrate 10 may be textured to have an anti-reflection structure. Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

5B, a first conductive type region 20 is formed on the first tunneling layer 52 and a second conductive type region 30 is formed on the second tunneling layer 54. Next, as shown in FIG. In this embodiment, the first conductive type region 20 and the second conductive type region 30 (hereinafter referred to as the conductive type regions 20 and 30) each made of a binary metal oxide layer have an amorphous structure. Particularly, in this embodiment, at least the boundary of the conductive regions 20 and 30 adjacent to the first tunneling layer 52 or the second tunneling layer 54 (hereinafter referred to as the tunneling layers 52 and 54) . The binary metal oxide layer easily undergoes a phase change according to process conditions and electrical and optical characteristics can be greatly changed due to the phase of the metal oxide layer, so that conductive regions 20 and 30 must be formed in a specific manufacturing process do. This will be described in detail below.

In this embodiment, the conductive regions 20 and 30 are formed by atomic layer deposition (ALD) or physical vapor deposition (PVD). In the atomic layer deposition process, the first raw material and the second raw material for forming the two-component metal oxide layer are alternately injected, and the first raw material or the second raw material is purged between them, The conductive type regions 20 and 30 are deposited. Since the deposition is performed in the atomic layer deposition process, the crystal structure of the conductive regions 20 and 30 can be easily controlled by controlling the process temperature, so that the desired amorphous structure (particularly, the amorphous structure (AA)) can be easily formed. For physical vapor deposition, sputtering or vapor deposition can be used. In particular, vapor deposition can be performed at room temperature so that the conductive regions 20 and 30 are formed into an amorphous structure.

In particular, by using the atomic layer deposition process, thin and uniform conductive regions 20 and 30 can be formed on the semiconductor substrate 10 having an antireflective structure, and the mass productivity is also excellent.

More specifically, if the process temperature of the atomic layer deposition process or the physical vapor deposition process is high, the binary metal oxide is bonded to the tunneling layer 52, 54 or the existing formed layer with sufficient energy to have a crystalline structure, Can have an amorphous structure.

The process temperature of the atomic layer deposition process may be below 250 ° C. When the process temperature of the atomic layer deposition process is less than 250 DEG C, the conductive type regions 20 and 30 are formed by amorphous portions in which an amorphous portion is widely formed at the boundary portion adjacent to the tunneling layers 52 and 54 (for example, (AA) can be formed. And the process temperature of the atomic layer deposition process may be 100 DEG C or higher (e.g., 150 DEG C or higher). If the process temperature is less than 100 캜, the conductivity type regions 20 and 30 may have porosity and the characteristics of extracting and delivering a desired carrier may be degraded. Alternatively, the process temperature of the physical vapor deposition process may be from room temperature to 250 캜 (for example, 5 to 250 캜, for example, 5 to 150 캜). This is because the conductive regions 20 and 30 are formed stably at this temperature and the amorphous portion AA can also be improved.

At this time, the process temperature may be slightly different depending on the materials constituting the conductive regions 20 and 30 even within the above-mentioned process temperature range. This is because the process margin may be slightly different depending on the type of oxide.

If the thickness of the conductive regions 20 and 30 exceeds a certain level even if the deposition is performed by the atomic layer deposition process at a low process temperature, the crystal structure may be gradually changed or the defect density may be increased And the passivation characteristic may be deteriorated. Accordingly, the thickness of the conductive regions 20 and 30 formed by the atomic layer deposition process may be 30 nm or less. According to this, the number of cycles can be reduced to reduce the process time, and the conductive regions 20 and 30 having a desired phase can be stably formed. This thickness may vary depending on the material of the oxide layer constituting the conductive regions 20 and 30, for example, the thickness of the conductive regions 20 and 30 may be 15 nm. Alternatively, if the second conductivity type region 30 is composed of a molybdenum oxide layer, it is preferable to have a thickness (particularly, a smaller thickness) that is equal to or smaller than the first conductivity type region 20 composed of another oxide layer .

For example, the thickness of the conductive type regions 20 and 30 may be 5 nm or more. When the thickness of the conductive type regions 20 and 30 is less than 5 nm, the characteristics of the conductive type regions 20 and 30 are reduced by the first or second transparent electrode layers 420 and 440 located on the conductive type regions 20 and 30, The surface recombination characteristics may be deteriorated. Further, it may be difficult to sufficiently perform the role of extracting and delivering electrons only when the conductive regions 20 and 30 (for example, the second conductive region 30) for extracting electrons are thicker than a certain thickness. This is because, when the conductive regions 20 and 30 for extracting electrons are bonded to the n-type semiconductor substrate 10, the passivation effect by the electric field region is large, so that it is difficult to extract electrons if the thickness is thin. However, the present invention is not limited thereto.

The second conductive type region 30 may be formed after the first conductive type region 20 is formed in the present embodiment and the first conductive type region 20 may be formed after the second conductive type region 30 is formed. May be formed.

For example, when the first process temperature for forming the first conductivity type region 20 and the second process temperature for forming the second conductivity type region 30 are different from each other, the first and second conductivity type regions 920 and 30, Which is formed at a higher processing temperature than at the first processing step, and then formed at a lower processing temperature. That is, if the first process temperature is higher than the second process temperature, the second conductivity type region 30 is formed after forming the first conductivity type region 20. If the second process temperature is higher than the first process temperature, The first conductivity type region 20 may be formed after the formation of the first conductivity type region 30. If a material to be formed at a low temperature process temperature is formed first and then a process at a high temperature process temperature is performed, the possibility that a material formed at a low process temperature deteriorates at a high temperature process temperature, This is to prevent this. For example, when the first conductive type region 20 is composed of a molybdenum oxide layer and the second conductive type region 30 is composed of a titanium oxide layer, after the second conductive type region 30 is formed The first conductive type region 20 can be formed. This is because the process margin for the process temperature is slightly smaller in the molybdenum oxide layer than in the titanium oxide layer so that the molybdenum oxide layer can have a lower process temperature. However, the present invention is not limited thereto.

Although the first and second tunneling layers 52 and 54 are first formed and then the first and second conductive regions 20 and 30 are formed in the above description and drawings, the present invention is not limited thereto. The first tunneling layer 52, the first conductive type region 20, the second tunneling layer 54 and the second conductive type region 30 or the second tunneling layer 54, 30, the first tunneling layer 52, and the first conductivity type region 20 in this order.

Although the first and second conductivity type regions 20 and 30 are all the binary metal oxide layers in the above description and drawings, any one of the first and second conductivity type regions 20 and 30 may be a semiconductor A doped region formed on the substrate 10, or a semiconductor layer formed separately from the semiconductor substrate 10. At this time, the tunneling layers 52 and 54 corresponding to the conductive regions 20 and 30 without the binary metal oxide layer may or may not be provided. At this time, the doped region may be formed on the semiconductor substrate 10 by a doping process such as ion implantation, thermal diffusion, or laser doping, and the semiconductor layer may be formed by a method such as deposition. The doping of the semiconductor layer may be performed together with the deposition of the semiconductor layer or may be performed by a separate doping process after the deposition of the semiconductor layer. Various other methods may also be used.

The first electrode 42 connected to the first conductive type region 20 and the second electrode 44 electrically connected to the second conductive type region 30 are formed as shown in FIG.

For example, the first transparent electrode layer 420 and the second transparent electrode layer 422 can be formed by a deposition method (for example, chemical vapor deposition (PECVD)), a coating method, or the like. At this time, the first transparent electrode layer 420 and the second transparent electrode layer 440 may be formed simultaneously to simplify the manufacturing process. However, the present invention is not limited thereto, and the first and second transparent electrode layers 420 and 440 may be formed by various methods.

The first metal electrode layer 422 and the second metal electrode layer 442 may be formed by plating, printing, or the like. For example, the first metal electrode layer 422 and the second metal electrode layer 442 may be formed by printing a low-temperature printing paste and then drying or firing it. The low-temperature printing paste has been described in detail in the description of the first metal electrode layer 422, and thus a detailed description thereof will be omitted. At this time, the first metal electrode layer 422 and the second metal electrode layer 442 may be formed in the same process, thereby simplifying the manufacturing process. However, the present invention is not limited thereto, and the first and second metal electrode layers 422 and 442 can be formed by various methods.

Accordingly, in this embodiment, the step of forming the first and / or second electrode 44 may be performed at a process temperature of 350 占 폚 or lower (e.g., 300 占 폚 or lower, for example, 250 占 폚 or lower). And all steps performed after the step of forming the conductive regions 20 and 30 can be performed at a process temperature of 350 占 폚 or lower (e.g., 300 占 폚 or lower, for example, 250 占 폚 or lower). By this temperature, the amorphous structure or the amorphous portion AA of the conductive type region 20 can be retained in the final structure without being crystallized.

According to this embodiment, the conductive regions 20 and 30 made of the binary metal oxide layer having an amorphous structure can be formed by a simple process. Thus, the solar cell 100 having excellent characteristics and efficiency can be formed by a simple process.

Hereinafter, a solar cell according to another embodiment of the present invention will be described in detail. Detailed descriptions will be omitted for the same or extremely similar parts as those described above, and only different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

FIG. 6 is a cross-sectional view of a solar cell according to another embodiment of the present invention, and FIG. 7 is a rear plan view of the solar cell shown in FIG. The first transparent electrode layer 420 of the first electrode 42 and the second transparent electrode layer 440 of the second electrode 44 are not shown in FIG. 7 for simplicity.

6 and 7, in this embodiment, a tunneling layer 56 is disposed on the rear surface of the semiconductor substrate 10, and first and second conductive regions 20, 30) can be located. A transparent electroconductive film 22 and an antireflection film 24 may be disposed on a front surface electric field generating layer (or a front electric field area) 60 on the entire surface of the semiconductor substrate 10.

As for the tunneling layer 56, the description of the first or second tunneling layer 52, 54 of the above-described embodiment can be applied as it is. The first and second conductivity type regions 20 and 30 except for the positions and shapes of the first and second conductivity type regions 20 and 30 are the same as the first and second conductivity type regions 20 and 20 of the above- , 30) can be applied as it is. The shape of the first and second conductivity type regions 20 and 30 will be described later in more detail with reference to FIG.

At this time, an anti-reflection structure may be formed on the front surface of the semiconductor substrate 10, and a rear surface of the semiconductor substrate 10 may be a mirror polished surface. This is because the characteristics of the tunneling layer 56 can greatly change the carrier transport characteristics.

In this embodiment, the first conductive type region 20 and the second conductive type region 30 may be positioned (for example, in contact with) the tunneling layer 56 and be in contact with each other. Since the first conductive type region 20 and the second conductive type region 30 do not contain a semiconductor material and a dopant, a problem such as a short circuit does not occur even if the side faces are in contact with each other. However, the present invention is not limited thereto. Thus, as an alternative, a barrier region may be located between the first and second conductive regions 20 and 30 on the tunneling layer 20 to prevent them from contacting. The barrier region may be composed of an empty space, or may be composed of an intrinsic semiconductor layer, a compound such as an oxide, or the like.

The front electro-depositing layer 60 positioned (for example, contacting) on the front surface of the semiconductor substrate 10 may be a film having a fixed charge or a binary metal oxide layer capable of selectively collecting electrons or holes as described above Lt; / RTI > For example, the front electro-depositing layer 60 may be an aluminum oxide layer comprising aluminum oxide with a fixed charge. Alternatively, the front electro-forming layer 60 may include a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a nickel oxide layer, a rhenium oxide layer, a titanium oxide layer, a zinc oxide layer, a niobium oxide layer, An oxide layer or the like. Or the front electro-forming layer 60 may be a layer including a plurality of the above-described layers. The front electroluminescent layer 60 may be formed of an oxide layer to effectively passivate the entire surface of the semiconductor substrate 10. [

At this time, the front electroplating layer 60 may be formed of the same layer as one of the metal compound layers constituting the first or second conductivity type regions 20 and 30, thereby simplifying the manufacturing process. For example, the front electro-depositing layer 60 and the second conductive region 30 may be formed of a titanium oxide layer.

The front electric field generating layer 60 may include a fixed electric charge in a state where it is not connected to the electrodes 42 and 44 connected to an external circuit or another solar cell 100 or may selectively collect electrons or holes, It is possible to exhibit the effect of having a constant electric field region preventing the recombination in the vicinity of the front surface of the substrate 10. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [

At this time, the thickness of the front electro-forming layer 60 may be equal to or less than the thickness of the first or second conductivity type regions 20 and 30. This is because the front field-effect forming layer 60 is not a layer for transferring the carriers to the outside, and thus may have a relatively small thickness. For example, the thickness of the front electro-film forming layer 60 may be 1 nm to 10 nm. It is possible to sufficiently realize the effect of the front field-generating layer 60 in this thickness. However, the present invention is not limited to the thickness of the front electrode layer 60.

The transparent conductive film 22 can be positioned (for example, in contact) on the front surface of the semiconductor substrate 10 or on the front electro-forming layer 60. This transparent conductive film 22 is a floating electrode that is not connected to an external circuit or other solar cell 100. Such a floating electrode can prevent unnecessary ions and the like from gathering on the surface side of the semiconductor substrate 10. [ Accordingly, it is possible to prevent degradation caused by ions or the like (for example, a potential induced degradation (PID)) in a solar cell module in a high temperature and high humidity environment. The transparent conductive film 22 is not an indispensable film and the transparent conductive film 22 may not be provided.

For example, the transparent conductive film 22 may include indium tin oxide (ITO), carbon nano tube (CNT), and the like. However, the present invention is not limited thereto, and the transparent conductive film 22 may include various other materials.

The antireflection film 24 may be positioned (e.g., in contact) on the front surface of the semiconductor substrate 10 or on the transparent conductive film 22. The antireflection film 24 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. Thus, the amount of light reaching the solar cell 100 can be increased. Accordingly, the short circuit current of the solar cell 100 can be increased.

The antireflection film 24 may be formed of various materials. For example, the antireflection film 24 may be formed of any one selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO _2, and CeO ₂ A single film or a multilayer film structure in which two or more films are combined. In one example, the antireflection film 24 may be a silicon nitride film.

The front electro-film forming layer 60, the transparent conductive film 22, and the anti-reflection film 24 may be formed entirely on the entire surface of the semiconductor substrate 10. Thus, the manufacturing process can be simplified and the role of each layer can be sufficiently exhibited.

Alternatively, a doped region of a conductive type such as the base region 110 may be doped to the entire surface of the semiconductor substrate 10 at a high concentration to form a doped region without forming the front electric field generating layer 60, It can also be used as a front electric field area. And a passivation film and antireflection film 24 may be placed on the doped region.

Referring to FIG. 7, in the present embodiment, the first conductive type region 20 and the second conductive type region 30 are alternately arranged in a direction intersecting the longitudinal direction, while being formed to be long in a stripe shape. Although not shown in the drawing, a plurality of first conductive regions 20 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 30 spaced from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

Here, a plurality of carriers (i.e., holes) different from the majority carriers in the base region 110 are collected than the area of the second conductivity type region 30 that collects the same carriers (i.e., electrons) as the majority carriers in the base region 110 The area of the first conductivity type region 20 can be made wider. As a result, the first conductive type region 20 functioning as the emitter region can be formed with a sufficient area. By the first conductive type region 20 formed to be wider, it is possible to effectively collect holes having a relatively slow moving speed. In one example, the areas of the first conductive type region 20 and the second conductive type region 30 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 20 may be greater than the width W2 of the second conductivity type region 30. [

The first metal electrode layer 422 of the first electrode 42 is formed in a stripe shape corresponding to the first conductivity type region 20 and the second metal electrode layer 442 of the second electrode 44 is formed in the second And may be formed in a stripe shape corresponding to the conductive type region 30. [ The first transparent electrode layer 420 of the first electrode 42 is formed in a stripe shape having a wider area than the first metal electrode layer 422 and the second transparent electrode layer 420 of the second electrode 44 The second transparent electrode layer 440 may have a larger area than the second metal electrode layer 442 and may be formed in a stripe shape. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

In this embodiment, the first transparent electrode layer 420 and the second transparent electrode layer 440 are not indispensable and the first transparent electrode layer 420 and the second transparent electrode layer 440 may not be formed. In this case, the first metal electrode layer 422 and the second metal electrode layer 442 may be formed in contact with the first and second conductivity type regions 20 and 30. In this case, the structure can be simplified.

In the unit solar cell 100 according to the present embodiment, the first and second electrodes 42 and 44 (particularly, the first and second metal electrode layers 422 and 442) are all located on the rear side of the semiconductor substrate 10 So that there is no part for blocking the light on the front side, so that the light loss can be minimized. Particularly, in this embodiment, at least one of the first and second conductivity type regions 20 and 30 is formed of a metal compound layer, so that the first metal electrode layer 42 and the second metal electrode layer 44, (422, 442) may be widely formed. In this case, the rear electrode structure can be applied to prevent the problem caused by the shading loss.

5A, a tunneling layer 56 is formed on the rear surface of the semiconductor substrate 10, and the first and second conductivity-type regions < RTI ID = 0.0 > And the first and second electrodes 42 and 44 are formed thereon by the method described in Fig. 5C. The first and second conductive type regions 20 and 30 and the first and second transparent electrode layers 420 and 440 and / or the first and second metal electrode layers 422 and 442 have a predetermined pattern, A mask or a mask layer may be used.

Hereinafter, the present invention will be described in more detail with reference to experimental examples of the present invention. The examples of the present invention are for illustrating the present invention, but the present invention is not limited thereto.

Example  One

First and second tunneling layers, each composed of a silicon oxide layer, were formed on the front surface and the rear surface of the n-type single crystal silicon substrate. And a second conductive type region composed of a first conductive type region composed of a molybdenum oxide layer and a titanium oxide layer was formed. The first conductive type region is formed by performing an atomic layer deposition process at a processing temperature of 200 DEG C and has a thickness of 10 nm and the second conductive type region is formed by performing an atomic layer deposition process at a processing temperature of 200 DEG C, Respectively. Then, a transparent electrode layer and a metal electrode layer are sequentially formed to form first and second electrodes.

Example  2

A solar cell was manufactured in the same manner as in Example 1 except that the thickness of the first conductivity type region was 20 nm and the thickness of the second conductivity type region was 20 nm.

Example  3

A solar cell was manufactured in the same manner as in Example 1 except that the thickness of the first conductivity type region was 30 nm and the thickness of the second conductivity type region was 30 nm.

Example  4

A solar cell was manufactured in the same manner as in Example 1 except that the thickness of the first conductivity type region was 6 nm and the thickness of the second conductivity type region was 6 nm.

Example  5

Except that the process temperature of the atomic layer deposition process for forming the first conductivity type region is 150 ° C and the process temperature of the atomic layer deposition process for forming the second conductivity type region is 150 ° C. Thereby manufacturing a solar cell.

Example  6

Except that the deposition temperature in the atomic layer deposition process for forming the first conductivity type region was 250 ° C and the deposition temperature in the atomic layer deposition process for forming the second conductivity type region was 250 ° C. Thereby manufacturing a solar cell.

Comparative Example  One

A solar cell was manufactured in the same manner as in Example 1, except that the first conductive type region was formed by chemical vapor deposition and the second conductive type region was formed by chemical vapor deposition.

Comparative Example  2

Except that the process temperature of the atomic layer deposition process for forming the first conductivity type region is 350 DEG C and the second conductivity type region is 350 DEG C for the atomic layer deposition process, A battery was prepared.

Comparative Example  3

Except that the process temperature of the atomic layer deposition process for forming the first conductivity type region is 80 DEG C and the deposition temperature of the atomic layer deposition process is 80 DEG C for the second conductivity type region. A battery was prepared.

Comparative Example  4

A solar cell was manufactured in the same manner as in Example 1 except that the thickness of the first conductivity type region was 40 nm and the thickness of the second conductivity type region was 40 nm.

Comparative Example  5

A solar cell was manufactured in the same manner as in Example 1 except that the thickness of the first conductivity type region was 3 nm and the thickness of the second conductivity type region was 3 nm.

In the solar cell according to Examples 1 to 4, the ratio of the first area, which is the ratio of the area of the amorphous portion at the boundary portion of the first conductivity type region to the ratio of the area of the amorphous portion at the boundary portion of the second conductivity type region, And the results are shown in Table 1. Hereinafter, the area ratio of the amorphous portion was determined from a transmission electron microscope (TEM) photograph. The high-resolution transmission electron microscope is suitable for discriminating between an amorphous structure and a crystalline structure because the lattice can be confirmed. In addition, the area ratio of the amorphous portion can be confirmed by X-ray crystallographic analysis (XRD).

First area ratio [%] Second area ratio [%] Example 1 99.5 99.5 Example 2 99 99 Example 3 99 99 Example 4 99 99

Referring to Table 1, it can be seen that Examples 1 to 4 have an amorphous structure at a high area ratio (for example, 95% or more) at the boundary portion. It is predicted that the amorphous structure can be formed at a high area ratio at boundaries depending on a specific process, temperature and thickness.

The ratio of the first area and the second area of the solar cell according to Example 1 and Comparative Example 1 were determined and are shown in Table 2.

First area ratio [%] Second area ratio [%] Example 1 99.5 99.5 Comparative Example 1 60 60

Referring to Table 2, it can be seen that Example 1 has an amorphous structure with a high area ratio (for example, 95% or more) at the boundary, whereas Comparative Example 1 has an amorphous structure with a low area ratio at the boundary. According to this, according to chemical vapor deposition, it is difficult to form an amorphous structure at a high area ratio at the boundary.

Thus, it can be seen that in Embodiments 1, 5 and 6, amorphous structures can be maintained at a large area ratio at the boundaries of the first and second conductivity type regions by using a specific process.

The first area ratio and the second area ratio of the solar cell according to Example 1 and Comparative Example 2 were determined and shown in Table 3, and a transmission electron microscope photograph of the solar cell according to Example 1 and Comparative Example 2 is shown in FIG. 8 (a) and (b). The implied open-circuit voltage (implied Voc) of the solar cells according to Examples 1, 5 and 6 and Comparative Example 3 was measured and shown in FIG.

First area ratio [%] Second area ratio [%] Example 1 99.5 99.5 Comparative Example 2 90 90

Referring to Table 3, it can be seen that Example 1 has an amorphous structure at a high area ratio (for example, 95% or more) at a boundary portion, whereas Comparative Example 2 has a low area ratio of an amorphous structure at a boundary portion. According to this, when the process temperature exceeds a certain temperature (for example, more than 250 ° C.), it is difficult to form an amorphous structure at a high area ratio at the boundary portion.

Referring to FIG. 8 (a), in the solar cell of Example 1, a pattern due to a constant crystal structure is not seen in the conductive type region, whereas in Comparative Example 2, referring to FIG. 8 (b) (Line), because the conductivity type region has crystallinity. Referring to FIG. 9, it can be seen that the implicit open-circuit voltages of Examples 1, 5, and 6 having a process temperature of 250 ° C or less are excellent, while the implicit open-circuit voltage is very low in Comparative Example 2 where the process temperature is 350 ° C. This is because the amorphous structure can not be formed at a high area ratio at the boundary of the first and / or the second conductivity type regions.

Accordingly, in Examples 1, 5, and 6, the amorphous structure can be maintained at a large area ratio at the boundary of the first and second conductivity type regions by maintaining the process temperature at a constant level, have.

The ratio of the first area and the second area of the solar cell according to Example 1 and Comparative Example 3 were determined and are shown in Table 4.

Porosity Porosity Example 1 lowness lowness Comparative Example 3 height height

Referring to Table 4, in Example 1, the porosity of the first and second conductivity type regions is low, which is suitable for extracting and collecting desired carriers, while in Comparative Example 3, the porosity of the first and second conductivity type regions is high, It is not suitable for extracting and collecting the carrier.

As a result, it can be seen that the first and second conductivity type regions can be fabricated to have excellent characteristics by setting the process temperature higher than a certain temperature.

The first area ratio and the second area ratio in the solar cell according to Examples 1 to 4 and Comparative Example 4 were determined and the implicit open-circuit voltage in the solar cell according to Examples 1 to 4 and Comparative Example 5 was measured And these are shown in Table 5.

First area ratio [%] Second area ratio [%] Implicit open-circuit voltage [mW] Example 1 99.5 99.5 680 mV or higher Example 2 99 99 680 mV or higher Example 3 99 99 680 mV or higher Example 4 99 99 680 mV or higher Comparative Example 4 90 90 - Comparative Example 5 - - 680 mV or less

Referring to Table 5, in the solar cells according to Examples 1 to 4, in which the thicknesses of the first and second conductivity type regions are in the range of 5 nm to 30 nm, the amorphous structure (for example, Whereas in Comparative Example 2 in which the thicknesses of the first and second conductivity type regions are 40 nm, the area ratio of the amorphous structure at the boundary portion is low. If the thickness of the first and second conductivity type regions exceeds a certain level, it is difficult to maintain the amorphous structure.

The solar cell according to Comparative Example 5 having a thickness of the first and second conductivity type regions of less than 5 nm as compared to the solar cells according to Examples 1 to 4 in which the thickness of the first and second conductivity type regions is in the range of 5 nm to 30 nm It can be seen that the battery has a low implicit open-circuit voltage.

Accordingly, in Embodiments 1 to 4, the first and second conductivity type regions are formed with a certain range of thickness, so that the amorphous structure can be maintained at a large area ratio at the boundary portions of the first and second conductivity type regions. Can be obtained.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
52, 54, 56: Tunneling layer
20: first conductivity type region
30: second conductivity type region
AA: amorphous part
42: first electrode
44: Second electrode

Claims (20)

Forming a first tunneling layer on one surface of a semiconductor substrate;
Forming a first conductive type region on the first tunneling layer; And
Forming a first electrode electrically connected to the first conductive type region
Lt; / RTI >
Wherein forming the first conductive type region comprises forming the first conductive type region so that the first conductive type region includes a binary metal oxide layer having an amorphous structure. The method according to claim 1,
In the forming of the first conductive type region, at least a boundary portion of the first conductive type region adjacent to the tunneling layer is formed of an amorphous portion having an amorphous structure wider than a crystalline portion having a crystalline structure A method of manufacturing a solar cell. The method according to claim 1,
Wherein the ratio of the area occupied by the amorphous portion in the boundary portion or the amorphous portion is 95% to 100% in the step of forming the first conductivity type region. The method according to claim 1,
Wherein the forming of the first conductive type region uses atomic layer deposition (ALD) or physical vapor deposition (PVD). 5. The method of claim 4,
In the forming of the first conductive type region, atomic layer deposition (ALD) is used,
Wherein the process temperature of the atomic layer deposition process in forming the first conductivity type region is 250 DEG C or less. 6. The method of claim 5,
Wherein the process temperature of the atomic layer deposition process in forming the first conductivity type region is 100 DEG C or more. The method according to claim 6,
Wherein the binary metal oxide layer comprises at least one of a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a nickel oxide layer, a rhenium oxide layer, a titanium oxide layer, a zinc oxide layer and a niobium oxide layer. The method according to claim 1,
Wherein the thickness of the first conductivity type region is 30 nm or less. The method according to claim 1,
Further comprising the step of extracting a second carrier having a polarity opposite to that of the first carrier and forming a second conductive type region including a binary metal oxide layer having an amorphous structure,
The first process temperature of the step of forming the first conductivity type region and the second process temperature of the step of forming the second conductivity type region are different from each other,
If the first process temperature is higher than the second process temperature, the second conductivity type region is formed after the first conductivity type region is formed. If the second process temperature is higher than the first process temperature, And forming the first conductive type region after forming the first conductive type region. The method according to claim 1,
Wherein the forming of the first electrode is performed at a temperature of 350 DEG C or less. A semiconductor substrate;
A tunneling layer located on one side of the semiconductor substrate;
A first conductive type region located above the tunneling layer and extracting a first carrier; And
A first electrode electrically connected to the first conductive type region;
/ RTI >
Wherein the first conductive type region comprises a binary metal oxide layer including an amorphous structure. 12. The method of claim 11,
Wherein at least a boundary portion of the first conductive type region adjacent to the tunneling layer is composed of an amorphous portion in which the amorphous portion having the amorphous structure is formed wider than the crystalline portion having the crystalline structure. 13. The method of claim 12,
Wherein the ratio of the area occupied by the amorphous portion in the boundary portion of the first conductive type region or the amorphous portion is 95% to 100%. 13. The method of claim 12,
The thickness of the amorphous portion is 1 nm or more,
Wherein the ratio of the thickness of the amorphous portion to the total thickness of the first conductivity type region is 0.2 to 1. < Desc / Clms Page number 19 > 13. The method of claim 12,
Wherein the amorphous portion is formed entirely in the thickness direction of the first conductivity type region. 13. The method of claim 12,
And the thickness of the first conductivity type region is 30 nm or less. 13. The method of claim 12,
Wherein the binary metal oxide layer comprises at least one of a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a nickel oxide layer, a rhenium oxide layer, a titanium oxide layer, a zinc oxide layer and a niobium oxide layer. 13. The method of claim 12,
A second conductive type region for extracting a second carrier having a polarity opposite to that of the first carrier; And
And a second electrode electrically connected to the second conductivity type region
Further comprising:
Wherein the second conductivity type region comprises a binary metal oxide layer having an amorphous structure,
Wherein at least a boundary portion of the tunneling layer or the second conductive type region adjacent to the semiconductor substrate is composed of an amorphous portion in which the amorphous portion having the amorphous structure is formed wider than a crystalline portion having a crystalline structure. 19. The method of claim 18,
And a second tunneling layer located on the other surface of the semiconductor substrate,
And the second conductive type region and the second electrode are located on the second tunneling layer. 19. The method of claim 18,
Wherein the first conductive type region and the second conductive type region are coplanar on the first tunneling layer.

Images