KR20180047048A - Methods of manufacturing vertical memory devices - Google Patents

Abstract

A vertical semiconductor device includes a plurality of gate patterns stacked in a first direction perpendicular to a substrate and extended in a second direction horizontal to the substrate. The vertical semiconductor device also includes a conductive connection pattern connecting the gate patterns, provided in a word line, in a third direction perpendicular to the second direction. The vertical semiconductor device may include an insulating structure which includes a pillar part disposed on both sides in the third direction of the conductive connection pattern and penetrating the gate pattern in the first direction, and a bridge pattern connected to the lower part of the pillar part while filling a gap of the lowermost gate pattern in the third direction. In the vertical semiconductor device, the upper surfaces of the gate patterns may be flat without unevenness.

Description

TECHNICAL FIELD [0001] The present invention relates to a vertical memory device,

The present invention relates to a method of manufacturing a vertical type memory device. More particularly, the present invention relates to a vertical NAND flash memory device and a method of manufacturing the same.

Recently, vertical memory devices in which memory cells are vertically stacked from the substrate surface are being developed. It may not be easy to manufacture a vertical memory device as the memory cells are stacked in the vertical direction.

One aspect of the present invention is to provide a method of manufacturing the vertical memory device.

According to an aspect of the present invention, there is provided a vertical memory device comprising: a plurality of vertical memory devices arranged in a first direction perpendicular to a substrate, Gate patterns are provided. And a conductive connection pattern for connecting the gate patterns provided in a word line in a third direction perpendicular to the second direction are disposed on both sides in the third direction of the conductive connection pattern, And a bridge pattern connected to a lower portion of the pillar portion while filling a gap between the pillar portion passing through the pillar portion and the third direction of the lowermost gate pattern.

According to another aspect of the present invention, there is provided a method of fabricating a vertical type memory device, including forming a lower insulating film and a lower sacrificial layer on a substrate sequentially. A sacrificial region is formed in at least one of the substrate, the lower insulating film, and the lower sacrificial layer located in the pattern cut region. An insulating film and a sacrifice film are alternately and repeatedly laminated on the lower sacrificial film. The insulating layer, the sacrificial layer, the lower insulating layer, and the lower sacrificial layer are etched to expose the substrate surface, and dummy holes are formed to expose both ends of the sacrificial region in the third direction. The lower sacrificial layer disposed between the sacrificial region and the dummy holes is removed through the dummy holes to form a connection portion connected to the dummy holes and a lower sacrificial pattern cut by the connection portion. The lower sacrificial patterns and the sacrificial layers are replaced with a gate pattern.

According to the vertical memory device according to the exemplary embodiments, the process of etching the lower sacrificial layer to isolate the gate pattern GSL of the ground selection transistor may be performed after forming the stepped preliminary mold structure. Therefore, the upper surfaces of the sacrificial layers and the insulating layers included in the stepped mold structure may be flat.

Therefore, when the mold structure is formed by forming the sacrificial layer and the insulating layer thereon, the lower sacrificial layer is etched in advance to form the opening, and the films stacked on the opening can be prevented from being bent.

Also, when performing the dummy channel hole forming processes, for example, a step pattern of the lower sacrificial layer can be formed together, thereby reducing the manufacturing process steps.

1 to 25 are plan views, cross-sectional views, and perspective views illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.
26 is a plan view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.
FIGS. 27 to 31 are a plan view and a sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.
32 and 35 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.
36 and 39 are a plan view and a sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.
40 and 47 are a plan view and a cross-sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.
48 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 25 are plan views, cross-sectional views, and perspective views illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.

1, 3, 5, 9, 15, 22 and 24 are plan views, and FIGS. 2, 4, 6 to 8, 10 to 14, 16 to 21 and 23 are sectional views. 25 is a perspective view showing a part of a vertical type memory device.

Figures 3, 5, 9, 15, 22 and 24 illustrate a portion of a cell region and a wiring region in a substrate.

4, 6 and 17 are sectional views taken along the line I_I 'in FIG. 3, and FIGS. 7, 16, 18, 20 and 23 are sectional views taken along line II_II' , 11, 12, 13, 14, 19 and 21 are cross-sectional views taken along line III_III '.

Hereinafter, a direction perpendicular to the upper surface of the substrate will be referred to as a first direction. Further, the directions parallel to the substrate upper surface and perpendicular to each other are referred to as a second direction and a third direction.

1 and 2, a mask pattern 102 is formed on a substrate 100, and a substrate processing process is performed on a surface of the substrate 100 exposed by the mask pattern 102 to form the substrate 100 A sacrificial region 104 may be formed. The upper surface of the substrate including the sacrificial region may be flat.

The substrate 100 may include a cell region A, a wiring region B, and a peripheral region C. [ The cell region A may be a region where memory cells are formed. The wiring region B may be a region where wirings electrically connected to the memory cells are formed. The peripheral region C may be a region other than the cell region A and the wiring region B. [ The wiring region B and the peripheral region C may have a shape surrounding the cell region A. [

The wiring region B may include a first portion to which the ground selection line GSL is to be cut. Although not shown, the first portion may be repeatedly arranged with a gap in the wiring region B.

The mask pattern 102 may selectively expose a portion of the substrate 100 corresponding to the first portion. Therefore, the mask pattern 102 may cover both the cell region A and the peripheral region C. [ The mask pattern 102 may include, for example, a photoresist pattern.

In an exemplary embodiment, the first portion may overlap with the first end of the word line at the top in the wiring region (B) in the first direction. In addition, the first portion may correspond to a portion between a pair of gate patterns neighboring in the third direction.

The sacrificial region 104 may be formed to have a high etch selectivity with a portion of the substrate 100 other than the sacrificial region 104.

In an exemplary embodiment, the substrate processing process may include an ion implantation process or a plasma process process.

For example, when the ion implantation process is performed, a sacrificial region 104 doped with an impurity may be formed on the substrate 100. Thus, the sacrificial region 104 can be etched faster than the undoped substrate portion. Alternatively, when the plasma process is performed, a sacrificial region 104 where plasma damage is generated may be formed on the substrate 100. Thus, the sacrificial region 104 may be etched faster than the substrate portion where the damage has not occurred.

In some other exemplary embodiments, the substrate processing process may include etching the substrate and forming a buried film at the etched portion. Specifically, the sacrifice region 104 can be formed by forming a recessed portion by etching a portion of the substrate 100 exposed by the mask pattern 102, and forming a buried film in the recessed portion. The buried layer may include a material having a high etch selectivity with the substrate 100, and may include, for example, silicon germanium, polysilicon, and the like.

Referring to FIGS. 3 and 4, a preliminary stepped mold structure 115 may be formed on the substrate 100. The first interlayer insulating film 120 covering the preliminary stepped mold structure 115 can be formed.

Specifically, a lower insulating layer 112a and a lower sacrificial layer 114a are sequentially formed on the substrate 100. [ The lower sacrificial layer may have a flat upper surface. The mold structure may be formed by alternately and repeatedly laminating the insulating films 112b, 112c, 112d, 112e, 112f, and 112g and the sacrificial films 114b, 114c, 114d, 114e, and 114f on the lower sacrificial layer . The insulating films 112b, 112c, 112d, 112e, 112f and 112g and the sacrificial films 114b, 114c, 114d, 114e and 114f formed on the lower sacrificial layer may have a flat upper surface.

For example, the lower insulating film and the insulating films 112a, 112b, 112c, 112d, 112e, 112f, and 112g may be formed using an oxide-based material such as silicon oxide, silicon carbonate, or silicon oxide. For example, the lower sacrificial layer and the sacrificial layers 114a, 114b, 114c, 114d, 114e and 114f may be formed using a nitride-based material such as silicon nitride (SiN) or silicon boron nitride have.

Then, the preliminary stepped mold structure 115 may be formed by stepwise etching the edge portions of the mold structure. That is, the preliminary stepped mold structure 115 may have a stepped shape at each corner portion located in the wiring region B and the peripheral region C.

The lower sacrificial layer and the sacrificial layers 114a, 114b, 114c, 114d, 114e, and 114f may be removed through a subsequent process to provide a space in which gate patterns are formed. The gate patterns may include GSL, word lines, and SSL. In an exemplary embodiment, the lower sacrificial layer 114a may be provided as GSL, and at least one sacrificial layer (e.g., 114f) formed at the top may be provided by SSL. Also, the sacrificial layers (e.g., 114b, 114c, 114d, and 114e) located between the sacrificial layers formed by GSL and SSL may be provided as word lines. In an exemplary embodiment, the lower sacrificial layer may be provided in two or more layers, whereby two or more GSLs may be formed.

In the following description, one GSL and one SSL are provided in one string, and the word lines are provided between the GSL and SSL, but the present invention is not limited thereto.

The first interlayer insulating layer 120 may be formed using an insulating material such as silicon oxide.

5 to 8, the filler structures 138 may be formed through the preliminary stepped mold structure 115 located in the cell region A. [ The filler structures 138 may include a semiconductor pattern 127, a channel structure 136, and a pad pattern 137. The second interlayer insulating film 140 covering the first interlayer insulating film 120, the preliminary stepped mold structure 115, and the pillar structure 138 may further be formed.

Specifically, the channel holes 125 may be formed by anisotropically etching the insulating layers and the sacrificial layers of the preliminary stepped mold structure 115 located in the cell region. The surface of the substrate 100 may be exposed through the channel hole 125. In an exemplary embodiment, a selective epitaxial growth process may be performed on the bottom surface of the channel hole 125 to form the semiconductor pattern 127. A channel structure 136 filling the channel hole 125 on the semiconductor pattern 127 may be formed. The channel structure 136 may include a dielectric layer structure 130, a channel 132, and a buried insulation pattern 134. The dielectric layer structure 130 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. For example, the pad pattern 137 including polysilicon may be formed on the channel structure 136.

The second interlayer insulating layer 140 may be formed using an insulating material such as silicon oxide. In the exemplary embodiment, the second interlayer insulating layer 140 may be formed of a material substantially the same as the first interlayer insulating layer 120. Therefore, they may be merged into one interlayer insulating film.

9 and 10, the insulating films, the sacrificial films, and the first and second interlayer insulating films 120 and 140 of the preliminary stepped mold structure 115 located in the wiring region are subjected to anisotropic etching, The hole 141 and the second dummy hole 142 can be respectively formed. The first and second dummy holes 141 and 142 may expose the surface of the substrate 100.

A dummy channel structure 147 may be formed in the first dummy hole 141 through a subsequent process. The dummy channel structure 147 may be provided as a support pattern for supporting the gate patterns.

The second dummy holes 142 may be formed at both edge portions of the first portion. That is, the sacrifice region 104 may be positioned between the second dummy holes 142, and the edge of the sacrifice region 104 may be partially exposed to the bottom of the second dummy hole 142 have. The second dummy hole 142 may be provided in a subsequent process to form an opening for cutting the GSL.

Referring to FIG. 11, the substrate 100 of the sacrificial region 104 is selectively removed. The removal process may be performed through an isotropic etching process.

The isotropic etching process may include a wet etching process, a dry isotropic etching process, and the like. The etchant used in the etching process may be provided through the second dummy holes 142.

When the isotropic etching process is performed, a preliminary first connection portion 142a may be formed under the second dummy holes 142 to connect the lower portions of the second dummy holes 142 to each other. The second dummy holes 142 and the preliminary first connection portion 142a may have a U-shape.

Referring to FIG. 12, an isotropic etching process is performed to remove the lower insulating film 114a exposed on the preliminary first connecting portion 142a. Therefore, a spare second connecting portion 142b that exposes the bottom surface of the lowermost sacrificial film can be formed.

The lower insulating layer 114a exposed on the preliminary first connecting portion 142a is connected to the other insulating layer exposed through the side wall of the second dummy hole 142 because the etchants are transferred through the preliminary first connecting portion 142a The area in contact with the etchants is larger. Therefore, the lower insulating layer 112a exposed on the preliminary first connecting portion 142a may be etched faster than other insulating layers exposed on the side walls of the second dummy holes 142. [ The insulating layer exposed on the sidewall of the second dummy hole 142 may be etched by a part of the thickness of the second dummy hole 142, thereby forming a concave portion on the sidewall of the second dummy hole 142.

Although not shown, in the etching process, the insulating film exposed to the side walls of the first dummy holes 141 may have a thickness of a certain thickness. Therefore, the concavo-convex portion can also be formed on the side wall of the first dummy hole 141. [

Referring to FIG. 13, an isotropic etching process is performed to remove the lower sacrificial layer 114a exposed on the preliminary second connection portion 142b. Accordingly, a first connection portion 142c connecting the lower portions of the first dummy holes 142 may be formed.

The lower sacrificial layer 114a exposed on the preliminary second connection part 142b is transferred to the second dummy hole 142b through the preliminary second connection part 142b, The area of contact with the etchants is larger than that of the film. Therefore, the lower sacrificial layer 114a exposed on the preliminary second connection portion 142b can be etched faster than other sacrificial layers exposed on the side walls of the second dummy holes 142. [ Therefore, the sacrificial layer exposed at the side wall of the second dummy hole 142 can be etched by a certain thickness. In an exemplary embodiment, the etch thickness of the sacrificial layer exposed in the sidewall of the second dummy hole 142 may be different from the etch depth of the insulating layer exposed in the sidewall of the second dummy hole 142. Therefore, a concavo-convex portion can be formed on the side wall of the second dummy hole 142.

Meanwhile, although not shown, the sacrificial layer exposed on the side wall of the first dummy hole 141 may be etched by a certain thickness. Therefore, the concavo-convex portion can also be formed on the side wall of the first dummy hole 141. [

When the above process is performed, only the lowermost insulating film and the lowermost sacrificial layer located on the substrate 100 in the first region are selectively removed.

In general, after the lowermost insulating film and the lowermost sacrificial film are deposited, the lowermost insulating film and the lowermost sacrificial film of the first portion are etched to form openings for GSL cutting. Thereafter, an insulating film and a sacrificial film are continuously deposited on the substrate of the lowermost sacrificial film and the cut portion to form a preliminary mold structure. In this case, the height of the upper surface of the insulating film and the sacrifice layer formed inside the cut-off portion may be lower than the height of the upper surface of the other insulating film and the sacrifice layer formed on the lowermost sacrificial layer. That is, at the opening portion, the insulating film and the sacrificial film have stepped portions, so that a bent portion is formed in the insulating film and the sacrificial film at the opening portion. Failure may occur in the subsequent process due to the bent portion.

However, according to exemplary embodiments, the insulating layer and the sacrificial layer are sequentially and repeatedly laminated on the lowermost insulating layer and the sacrificial layer without forming openings for GSL cutting, thereby forming the preliminary stepped mold structure 115. Therefore, the insulating layer and the sacrificial layer in the preliminary stepped mold structure 115 may not be bent due to the lower step. In addition, after the preliminary stepped mold structure 115 is formed, the lowermost insulating film and the lowermost sacrificial layer located at the first portion can be selectively removed. Thus, the GSL of the ground selection transistor can be cut off at the first portion through a subsequent process.

14, a first insulation structure 146 filling the inside of the second dummy hole 142 and the first connection part 142c is formed, and a dummy channel structure (also shown in FIG. 14) is formed in the first dummy hole 141 15, and 147 can be formed.

In an exemplary embodiment, the first insulating structure 146 and the dummy channel structure 147 may be formed using a material having a high etch selectivity and a material provided as the sacrificial layer. For example, the first dielectric structure 146 and the dummy channel structure 147 may comprise silicon oxide.

In the exemplary embodiment, the first insulating structure 146 and the dummy channel structure 147 form an insulating film that completely fills the second dummy hole 142, the first connecting portion 142c, and the first dummy hole 141 And then planarizing the insulating film. The planarization process may be performed such that the upper surface of the second interlayer insulating film 140 is exposed. Alternatively, the planarization process may be performed such that the upper surface of the first interlayer insulating film 120 is exposed. In this case, the first insulation structure 146 includes an insulation pattern that completely fills the second dummy hole 142 and the first connection part 142c, and the dummy channel structure 147 includes the first dummy hole 142, (Not shown).

In some embodiments, the first insulating structure 146 and the dummy channel structure 147 are formed in the first dummy hole 142, the first connecting portion 142c, and the first dummy hole 141, A buried film is formed on the insulating film to completely fill the second dummy holes 142, the first connecting portions 142c, and the first dummy holes 141. The buried film and the insulating film are planarized to form can do. In this case, the first insulation structure 146 includes an insulation pattern formed conformally along the surfaces of the second dummy holes 142 and the first connection portions 142c, and the second dummy holes 142c, 142 and the first connection portion 142c. The dummy channel structure 147 may include an insulation pattern formed conformally along the surface of the first dummy hole 141 and an embedding pattern for completely filling the first dummy hole 141 on the insulation pattern You may.

The first insulating structure 146 may have a U-shape in cross-section. That is, the first insulating structure 146 includes a filler portion located at both ends of the first portion and extending to the surface of the substrate through the preliminary stepped mold structure 115 and the first interlayer insulating film 120, And a bridge pattern connecting the sub-portions to each other.

 15 and 16, an opening 150a extending in the second direction may be formed while cutting at least the preliminary stepped mold structure 115 of the cell region. By this process, the preliminary stepped mold structures 115 of the cell region may be formed as stepped mold structures 115a that are spaced apart from each other in the third direction. The stepped mold structure 115a may have an insulating pattern 116 and a sacrificial pattern 118 stacked thereon.

In the etching process for forming the opening 150a, the preliminary stepped mold structure 115 of the first portion may not be etched. The preliminary stepped mold structure 115 may be etched to both sides of the first portion in the second direction. Accordingly, the unetched portion may be provided as a connection pattern 150b connecting the stepped mold structures 115a to each other.

In the exemplary embodiment, the opening 150a including the connection pattern 150b and the opening 150a not including the connection pattern 150b may alternately be formed in the third direction. Accordingly, the pair of adjacent step-like mold structures 115a may be connected to each other by the connection pattern 150b at the first portion.

The first portion may overlap a sacrificial pattern (e.g., 118e) corresponding to an end of the uppermost word line in the second direction. Thus, the top sacrificial pattern (e. G., 118f) provided by the SSL may have a truncated shape. On the other hand, the sacrificial patterns (for example, 118b to 118e) provided in the word line located under the sacrificial patterns may have a shape connected to each other in the third direction by the connection pattern 150b. In addition, the lowermost sacrificial pattern 118a provided to the GSL may have a shape cut by the previous process. That is, the sacrificial pattern provided by the SSL and the GSL may not be provided in the first region.

17 to 19, the sacrificial patterns 118 in which the side walls are exposed by the opening 150a can be removed. According to exemplary embodiments, the sacrificial patterns 118 may be removed through an isotropic etching process.

As the sacrificial patterns 118 are removed, a gap 152 may be formed between the insulating patterns 116 of each layer. At this time, as shown in FIG. 20, the sacrificial patterns 118 remaining in the first region are also removed, so that the gap 152 can be formed.

20 and 21, the gate patterns 160 can be formed by filling a conductive material into the gaps 152 of the respective layers. That is, the sacrificial patterns 118 of each layer may be replaced with the gate patterns 160, respectively. According to exemplary embodiments, the gate pattern 160 may be formed using a metal or a metal nitride.

As described above, the lowermost gate pattern 160a is provided as GSL, the uppermost gate pattern 160f is provided as SSL, and the gate patterns 160b, 160c, 160d, and 160e between the GSL and SSL are provided as word lines . ≪ / RTI >

However, the conductive material may be filled in the gap 152 of the first portion, and may be provided as a conductive connection pattern 161 connecting the adjacent two word lines in the third direction with each other. Thus, the two adjacent word lines in the third direction may be electrically connected.

However, since the gap 152 is not formed in the portion corresponding to the SSL and the GSL in the first portion, the conductive connection pattern 161 is not formed because the gap 152 is filled with the insulating material. Thus, between the SSLs neighboring in the third direction and between GSLs can be electrically isolated.

Referring to FIGS. 22 and 23, an impurity region 105 may be formed on the substrate 100 exposed through the opening 150a by performing an ion implantation process. The insulating pattern 155 filling the opening 150a and the common source line 157 may be formed on the impurity region 105. [

Subsequently, although not shown, an upper interlayer insulating film may be formed on the second interlayer insulating film, contacts may be formed through the interlayer insulating films located in the interconnection region, and wirings connected to the contacts may be formed .

Through this process, a vertical type memory device can be manufactured.

FIG. 24 is a plan view of a vertical memory device, and FIG. 25 is a perspective view showing a connection pattern portion in the vertical memory device.

22 to 25, the vertical memory devices may include gate patterns 160 extending in the second direction and being stacked while being spaced apart from each other in the first direction. The edge portions of the gate patterns 160 may be located in a wiring region, and the edge portions may have a stepped shape.

Channel structures 136 are formed through the gate patterns 160 located in the cell region and the gate patterns 160 and the first interlayer insulating layer 120 located in the wiring region are formed, Channel structures 147 may be provided. In addition, the first insulating structure 146 may be provided in the first region where the GSL is cut in the wiring region. The first dielectric structure 146 may include substantially the same material as the dummy channel structure 147.

The first insulating structure 146 includes the pillar portion and the bridge pattern, and the GSL neighboring in the third direction by the bridge pattern can be cut from each other.

As shown in FIG. 21, the side wall of the pillar portion of the first insulating structure 146 may have irregularities.

The conductive connection pattern 161 may include a pair of gate patterns 160 provided as a word line, the conductive connection pattern 161 may be formed on the bridge pattern, They can be electrically connected to each other in three directions.

The upper surfaces of the gate patterns 160 are not bent, and the upper surfaces of the gate patterns 160 may be formed flat.

26 is a plan view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Referring to FIG. 26, the preliminary stepped mold structure 115 and the first interlayer insulating film are formed on the substrate by performing the same process as described with reference to FIGS.

Thereafter, a first insulating structure and a dummy channel structure 147 are formed in the preliminary stepped mold structure 115 by performing the same process as described with reference to FIGS. 9 to 14.

Thereafter, the processes described with reference to FIGS. 5 to 8 are performed to form the filler structure.

That is, the first insulating structure and the dummy channel structure 147 may be formed in the preliminary stepped mold structure 115 without forming the pillar structure in the cell region. Then, the filler structure is formed in the cell region.

Subsequently, the vertical memory device can be manufactured by performing the processes described with reference to FIGS. 15 to 23. FIG. The vertical memory device may be substantially the same as the vertical memory device shown in FIGS.

FIGS. 27 to 31 are a plan view and a sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Referring to FIG. 27, a lower insulating layer 112a and a lower sacrificial layer 114a are formed on a substrate 100. Referring to FIG.

A mask pattern 102 is formed on the lower sacrificial layer 114a. The mask pattern 102 may selectively expose the lower sacrificial layer 114a corresponding to the first region where the ground selection line GSL is to be cut in the wiring region B. [

A sacrificial region 104a is formed on a portion of the lower sacrificial layer 114a by performing a substrate processing process on the surface of the lower sacrificial layer 114a exposed by the mask pattern 102. [

The substrate processing step may include an ion implantation step or a plasma processing step. The sacrificial region 104a may have high etch selectivity with the bottom sacrificial layer 114a and the sacrificial layer formed thereafter. That is, when the same etching process is performed, the sacrificial region 104a can be removed faster than the lower sacrificial film and the other sacrificial films.

Thereafter, the mask pattern is removed.

28, insulating films 112b, 112c, 112d, 112e and 112f and sacrificial films 114b, 114c, 114d, 114e and 114f are formed on the lower sacrificial layer 114a and the sacrificial region 104a, And alternately repeatedly laminated to form a mold structure.

Thereafter, the end of the mold structure is etched stepwise to form the preliminary stepped mold structure 115 (see Figs. 3 and 4). The process of forming the preliminary stepped mold structure may be substantially the same as that described with reference to FIGS.

Subsequently, the same processes as those described with reference to FIGS. 5 to 8 are carried out so as to pass the filler structures 138 (see FIG. 5) through the preliminary stepped mold structure 115 located in the cell region A .

29, the insulating films 112, the sacrificial films 114, and the first and second interlayer insulating films of the preliminary stepped mold structure 115 located in the wiring region are anisotropically etched to form first dummy holes, And the second dummy holes 143 can be formed. The process of forming the first and second dummy holes 143 may be the same as that described with reference to FIGS. 9 and 10. FIG.

A sacrificial region 104a formed on the lower sacrificial layer 114a may be exposed on a lower side wall of the second dummy hole 143. [

Referring to FIG. 30, the sacrificial region 104a is removed through an isotropic etching process. The sacrificial region 104a may be etched faster than the lower sacrificial layer 114a and other sacrificial layers 114b, 114c, 114d, and 114e. Accordingly, the first connection part 143a connecting the lower side walls of the second dummy holes 142 may be formed. The first connection part 143a may be a part where the GSL of the ground selection transistor formed in the subsequent process is cut off. The lower sacrificial layer 114a on both sides of the first connection part 143a may be replaced with a gate pattern through a subsequent process and provided to the GSL.

In the step of etching the sacrificial region 104a, the lower sacrificial layer 114a and the other sacrificial layers 114b, 114c, 114d, and 114e may be etched by a certain thickness. Therefore, a concavo-convex portion can be formed on the side wall of the second dummy hole 143. [

 Referring to FIG. 31, a vertical type memory device can be manufactured by performing the same processes described with reference to FIGS. 14 to 23.

That is, a first insulation structure 146 filling the inside of the second dummy hole 143 and the first connection part 143a (FIG. 30) is formed, and a dummy channel structure (FIG. 15 , 147 can be formed.

The first insulating structure 146 may include a pillar portion extending through the preliminary stepped mold structure 115 and the first interlayer insulating film 120 and extending to the surface of the substrate 100, Lt; / RTI > pattern. The height of the top and bottom of the bridge pattern may be the same as the height of the top and bottom of the bottom sacrificial pattern, respectively.

In the exemplary embodiment, the bridge pattern and the lower insulating layer 112a may include the same insulating material. In this case, the bridge pattern and the lower insulating layer 112a may be combined into a single layer.

Thereafter, an opening (FIG. 22, 150a) extending in the second direction can be formed while cutting at least the preliminary stepped mold structure 115 of the cell region. The gate patterns 160 may replace the sacrificial patterns.

22 to 25, except that a recess is not formed in the substrate and the bridge pattern of the first insulating structure 146 is provided apart from the upper surface of the substrate. Type memory element.

32 and 35 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to exemplary embodiments.

Referring to FIG. 32, a lower insulating film 112a is formed on a substrate 100. FIG.

A mask pattern 102 is formed on the lower insulating film 112a. The mask pattern 102 may selectively expose a portion of the lower insulating layer 112a corresponding to the first portion where the ground selection line GSL is to be cut in the wiring region B. [

A sacrificial region 104b is formed on the lower insulating layer 112a by performing a substrate processing process on the surface of the lower insulating layer 112a exposed by the mask pattern 102. [

The substrate processing step may include an ion implantation step or a plasma processing step. The sacrificial region 104b may have high etch selectivity with the lower insulating layer 112a and the insulating layers formed thereafter. That is, when the same etching process is performed, the sacrificial region 104b can be removed more quickly than the lower insulating film 112a and other insulating films.

Thereafter, the mask pattern 102 is removed.

Referring to FIG. 33, a lower sacrificial layer 114a is formed on the lower insulating layer 112a and the sacrificial region 104b. Insulating films 112b, 112c, 112d, 112e and 112f and sacrificial films 114b, 114c, 114d and 114e are alternately and repeatedly laminated on the lower sacrificial layer 114a to form a mold structure. Thereafter, the end of the mold structure is etched stepwise to form the preliminary stepped mold structure 115 (see Figs. 3 and 4). The process of forming the preliminary stepped mold structure 115 may be substantially the same as that described with reference to FIGS.

5 to 8) to form pillar structures 138 (FIG. 5) through the preliminary stepped mold structure 115 located in the cell region A can do.

Thereafter, the insulating films, the sacrificial films, the lower insulating film, the lower sacrificial film, and the first and second interlayer insulating films of the preliminary stepped mold structure 115 located in the wiring region are anisotropically etched to form first dummy holes and second Dummy holes 143b are formed. The process of forming the first and second dummy holes 143b may be the same as that described with reference to FIGS. A sacrificial region 104b formed on the lowermost insulating layer 112a may be exposed on a side wall of the second dummy hole 143b.

Referring to FIG. 34, the sacrificial region 104b is removed through an isotropic etching process. The sacrificial region may be etched faster than the lower insulating film 112a and the other insulating films 112b, 112c, 112d, 112e and 112f. Accordingly, a preliminary first connection part 143c connecting the lower side walls of the second dummy holes 143b can be formed. The surface of the substrate and the bottom surface of the lower sacrificial layer can be exposed by the preliminary first connecting portion 143c.

In the step of etching the sacrificial region, the lowermost insulating film and another insulating film may be etched by a certain thickness. Therefore, a concavo-convex portion can be formed on the side wall of the second dummy hole 143b.

Referring to FIG. 35, an isotropic etching process is performed so that the lower sacrificial layer 114a exposed by the preliminary first connection portion 143c is removed. Accordingly, a first connection portion 143d connecting lower portions of the second dummy holes 143b may be formed.

The lower sacrificial layer 114a exposed on the preliminary first connection portion 143c is etched faster than the other sacrificial layers 114b, 114c, 114d, and 114e exposed on the sidewalls of the second dummy holes 143b . Therefore, concaves and convexes can be formed on the side walls of the second dummy holes 143b through the etching process.

Thereafter, a vertical memory device is manufactured by performing substantially the same process as described with reference to Figs. 14 to 23.

In the vertical memory device, the first insulating structure 146b may include a pillar portion extending to the surface of the substrate 100 and a bridge pattern connecting the lower portions of the pillar portions. The height of the top surface of the bridge pattern may be substantially the same as the height of the top surface of the lowermost gate pattern 118a. Further, the bridge pattern may be in contact with the upper surface of the substrate 100.

The vertical memory element may be substantially the same as the vertical memory element shown in Figs. 22 to 25, except that no recess is formed in the substrate.

36 and 39 are a plan view and a sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Referring to FIG. 36, the same process as described with reference to FIGS. 1 to 4 is performed. Thus, a preliminary stepped mold structure (Figs. 4 and 115) can be formed on the substrate 100. [ The first interlayer insulating film 120 covering the preliminary stepped mold structure 115 can be formed.

The channel holes 125a, the first dummy holes 141, and the second dummy holes 142 may be formed by anisotropically etching the insulating films and the sacrificial films of the preliminary stepped mold structure 115. [ That is, the channel hole 125a, the first dummy hole 141, and the second dummy hole 142 may be simultaneously formed through the anisotropic etching process.

Referring to FIG. 37, the semiconductor pattern 127 may be formed by performing a selective epitaxial growth process on the bottom surface of the channel hole 125a. At this time, the wiring region may be blocked so that the semiconductor pattern is not formed on the bottom surfaces of the first dummy hole 141 and the second dummy hole 142.

Thereafter, the processes described with reference to Figs. 11 to 13 are performed in the same manner. Accordingly, first connection portions (FIGS. 13 and 142c) for connecting the lower portions of the second dummy holes 142 to each other can be formed.

When the above processes are performed, concavo-convex portions may be formed on the side walls of the first and second dummy holes 142, respectively. In addition, the insulating pattern and the sacrificial pattern exposed on the sidewall of the channel hole 125a may be etched by a certain thickness. Therefore, the concavo-convex portion can also be formed on the side wall of the channel hole 125a.

Referring to FIGS. 38 and 39, a filler structure 138 may be formed in the channel hole. The filler structure 138 may include a semiconductor pattern 127, a channel structure 136a, and a pad pattern 137. [ In addition, a dummy channel structure and a first insulation structure 136b may be formed in the first and second dummy holes, respectively. The first insulating structure 136b, the dummy channel structure, and the channel structure 136a may be formed through the same process, and may include substantially the same material.

Specifically, the channel structure may include a first dielectric layer structure 130a, a first channel 132a, and a first buried insulation pattern 134a. The dummy channel structure and the first insulation structure 136b may include a second dielectric structure 130b, a second channel 132b, and a second embedded insulation pattern 134b. Since the first dielectric structure includes a second dielectric layer structure 130b formed on the sidewall of the second dummy hole and including an insulating material, the first dielectric structure may be provided as an insulating structure. In the channel hole, a pad pattern 137 may be formed on the channel structure 136a.

The channel structure 136a, the dummy channel structure, and the first insulation structure 136b may be formed with concavities and convexities on the sidewalls by the channel hole, the concave and convex portions of the first and second dummy holes, and the like.

Thereafter, the same processes as those described with reference to FIGS. 15 to 23 are performed to manufacture a vertical type memory device.

In the vertical memory device, the channel structure, the dummy channel structure, and the first insulation structure may have the irregularities on the side walls, and the same materials may be stacked on each other. Otherwise, it may be substantially the same as the vertical memory element shown in Figs. 22 to 25.

In some embodiments, the vertical memory element may not be recessed in the substrate.

40 and 47 are a plan view and a cross-sectional view for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Referring to Figures 40 to 42, the same process as described with reference to Figures 1 and 2 is performed.

Subsequently, insulating films 112a, 112b, 112c, 112d, 112e, 112f, and 112g and sacrificial films 114a, 114b, 114c, 114d, 114e, and 114f are alternately repeatedly stacked on the substrate 100 Thereby forming a mold structure. Then, the first preliminary stepped mold structure 115a may be formed by stepwise etching the edge portions of the mold structure. That is, the first preliminary stepped mold structure 115b may have a stepped shape at each corner portion located in the wiring region and the peripheral region.

At this time, the lower insulating layer 112a, the lower sacrificial layer 114a, and the insulating layer 112b formed on the lower sacrificial layer 114a included in the first preliminary stepped mold structure 115a are not etched have. Therefore, the first preliminary stepped mold structure 115b may not have a single step at the lowermost part thereof.

Next, a first interlayer insulating film 120 covering the first preliminary stepped mold structure 115b may be formed.

Referring to FIG. 43, the filler structures 138 may be formed through the first preliminary stepped mold structure 115b located in the cell region A. FIG.

The process may be substantially the same as that described with reference to Figs.

44 to 46, the insulating films, the sacrificial films, and the first and second interlayer insulating films 120 and 140 of the first preliminary stepped mold structure 115b located in the wiring region are subjected to anisotropic etching 1 dummy holes 141 and second dummy holes 142, respectively. Further, in the etching step, a step of one layer may be formed at the lowermost part of the first preliminary stepped mold structure 115b. Therefore, a second preliminary stepped mold structure 115c can be formed.

That is, in the etching process for forming the first and second dummy holes, the first and second interlayer insulating films 120 and 140 and the lower insulating film 112a, the lower sacrificial film 114a, The lowest step can be formed by etching the insulating film 112b formed on the insulating film 114a. That is, the first and second interlayer insulating films 120 and 140 and the insulating film 112b formed on the lower insulating film 112a, the lower sacrificial film 114a, and the lower sacrificial film 114a, The first opening 161 may have a ring shape that surrounds the outside of the cell region A. As shown in FIG.

The lower insulating layers 112a and 111a and the lower sacrificial layers 114a and 113a and the lower insulating layers 114b and 111b may be exposed on the sidewalls of the first opening 161.

Referring to FIG. 47, the processes described with reference to FIGS. 11 to 14 can be performed in the same manner.

The first insulation structure 146 filling the inside of the second dummy hole 142 and the first connection portion 142c is formed and the dummy channel structure 14 and 147 may be formed.

The insulating layer and / or the sacrificial layer on the sidewalls of the first opening 161 may be partly etched to slightly enlarge the width of the first opening 161. Referring to FIG. In addition, the first opening 161 is filled with an insulating material, and the second insulating structure 162 may be formed in the first opening 161.

Thereafter, the same processes as those described with reference to FIGS. 15 to 23 are performed to manufacture a vertical type memory device.

The vertical memory device may include a ring-shaped second insulating structure 162 surrounding the wiring region. Otherwise, it may be substantially the same as the vertical memory element shown in Figs. 22 to 25.

48 is a cross-sectional view for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments.

The vertical memory element may be substantially the same as the vertical memory element shown in FIG. 47 except for the second insulating structure.

The same process as described with reference to Figs. 40 to 46 is performed to form the first opening.

Referring to FIG. 48, the processes described with reference to FIGS. 11 to 13 can be performed in the same manner. Accordingly, a first connection portion 142c connecting the lower portions of the second dummy holes 142 may be formed.

Thereafter, a first insulation structure 146 filling the inside of the second dummy hole 142 and the first connection portion 142c is formed, and a dummy channel structure (Fig. 15, 147) is formed in the first dummy hole 141 ) Can be formed.

An insulating material may also be deposited in the first opening 161 to form a second insulating structure 162a in the first opening 161. Referring to FIG.

At this time, the second insulation structure 162a may be formed along the sidewalls and the bottom of the first opening 161. Therefore, a space can be left inside the first opening 161.

Thereafter, a third interlayer insulating film 166 covering the upper portion of the first opening 161 may be formed on the second interlayer insulating film 140. Thus, an air gap 164 may be created within the first opening.

Thereafter, the same processes as those described with reference to FIGS. 15 to 23 are performed to manufacture a vertical type memory device.

The vertical memory device includes a ring-shaped second insulating structure 162b surrounding the wiring region, and the second insulating structure 162b may include an air gap 164. Otherwise, it may be substantially the same as the vertical memory element shown in Figs. 22 to 25.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

A vertical memory device can be manufactured by a method according to exemplary embodiments of the present invention.

100: substrate 102: mask pattern
104: sacrificial area 105: preliminary stepped mold structure
120: first interlayer insulating film 112a:
114a: Lower sacrificial membrane
112b, 112c, 112d, 112e, 112f, and 112g:
114b, 114c, 114d, 114e, 114f:
136, 136a: channel structure
136b: first insulation structure
147: dummy channel structure
138: Pillar structures 140: Second interlayer insulating film
125: channel hole 143a: first connection part
143b: second dummy hole 146: first insulation structure
161: first opening portion 160: gate pattern

Claims (10)

A plurality of gate patterns stacked in a first direction perpendicular to the substrate and extending in a second direction parallel to the substrate;
A conductive connection pattern connecting the gate patterns provided as word lines in a third direction perpendicular to the second direction;
And a bridge pattern disposed on both sides in the third direction of the conductive connection pattern and connected to the lower portion of the pillar portion while filling the gap between the pillar portion passing through the gate pattern in the first direction and the third direction of the lowermost gate pattern The semiconductor device comprising: a semiconductor substrate; The vertical semiconductor device according to claim 1, wherein the bridge pattern is disposed below the conductive connection pattern. The vertical semiconductor device according to claim 1, wherein the side walls of the pillar portions of the insulating structure have irregularities. The semiconductor device according to claim 1, wherein edge portions of the gate patterns in the second direction have a stepped shape, and the insulating structure and the conductive connection pattern are located at edge portions in a second direction having the step shape, . Sequentially forming a lower insulating film and a lower sacrificial layer on a substrate;
Forming a sacrificial region in at least one of the substrate, the lower insulating film, and the lower sacrificial layer located in the pattern cut region;
Alternately and repeatedly stacking an insulating film and a sacrificial film on the lower sacrificial film;
Etching the insulating film, the sacrificial layer, the lower insulating layer, and the lower sacrificial layer to expose the surface of the substrate and form dummy holes each exposing both ends in the third direction of the sacrificial region;
Removing the lower sacrificial layer disposed between the sacrificial region and the dummy holes through the dummy holes to form a connecting portion connected to the dummy holes and a lower sacrificial pattern cut by the connecting portion;
And replacing the lower sacrificial patterns and the sacrificial layers with a gate pattern. 6. The method of claim 5, wherein the sacrificial region is formed by plasma-treating at least one surface of the substrate, the lower insulating film, and the lower sacrificial layer. 6. The vertical semiconductor device according to claim 5, further comprising: alternately and repeatedly stacking the insulating film and the sacrifice layer, and then etching the edge portions of the lower insulating layer, the lower sacrificial layer, the insulating layer, and the sacrifice layer so as to have a stepped shape Gt; The semiconductor device according to claim 5, further comprising forming an insulating structure including an insulating material having an etch selectivity with the sacrificial layer, after forming the connecting portion and the lower sacrificial patterns, Gt; The method according to claim 5, further comprising forming the connection portion and the lower sacrificial patterns, and then forming the lower insulating film, the lower sacrificial film, the insulating film, and the sacrificial film located on both sides in the second direction perpendicular to the third direction, And forming a stepped mold structure extending in the second direction and a connection pattern connecting the stepped mold structure to each other. 6. The method of claim 5, wherein in the step of removing the sacrificial layer and the sacrificial layer disposed between the sacrificial region and the dummy holes through the dummy holes, the sidewall of the dummy holes At least one of which is partially etched.

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