KR102643050B1 - Methods of manufacturing vertical memory devices - Google Patents

Abstract

The vertical semiconductor device includes a plurality of gate patterns that are stacked and spaced apart in a first direction perpendicular to the substrate and extend in a second direction horizontal to the substrate. It includes a conductive connection pattern connecting the gate patterns provided as word lines in a third direction perpendicular to the second direction, disposed on both sides of the third direction of the conductive connection pattern, and connecting the gate pattern to the first direction. It may include an insulating structure including a bridge pattern connected to a lower part of the pillar part and filling a space between a pillar part penetrating in one direction and a third direction of the lowermost gate pattern. In the vertical semiconductor device, the gate patterns may have no curves on each upper surface and each upper surface may be flat.

Description

Manufacturing method of vertical memory device {METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES}

The present invention relates to a method of manufacturing a vertical memory device. More specifically, it relates to a vertical NAND flash memory device and a method of manufacturing the same.

Recently, vertical memory devices in which memory cells are stacked vertically from the substrate surface have been developed. As memory cells are stacked in multiple layers in the vertical direction, it may not be easy to manufacture a vertical memory device.

One object of the present invention is to provide a method of manufacturing the vertical memory device.

In order to achieve the object of the present invention, the vertical memory elements according to embodiments of the present invention are stacked while being spaced apart in a first direction perpendicular to the substrate, and a plurality of devices extending in a second direction horizontal to the substrate. Gate patterns are provided. A conductive connection pattern is provided to connect the gate patterns provided as word lines in a third direction perpendicular to the second direction, and is disposed on both sides of the third direction of the conductive connection pattern, and connects the gate pattern to the first direction. and an insulating structure including a bridge pattern connected to a lower portion of the pillar portion and filling a space between a pillar portion penetrating in one direction and a third direction of the lowermost gate pattern.

In order to achieve the object of the present invention, a lower insulating film and a lower sacrificial film are sequentially formed on a substrate in a method of manufacturing a vertical memory device according to embodiments of the present invention. A sacrificial region is formed on at least one of the substrate, the lower insulating layer, and the lower sacrificial layer located in the pattern cutting area. An insulating layer and a sacrificial layer are alternately and repeatedly stacked on the lower sacrificial layer. The insulating layer, the sacrificial layer, the lower insulating layer, and the lower sacrificial layer are etched to expose the substrate surface, and dummy holes are formed to expose both ends of the sacrificial region in the third direction, respectively. The lower sacrificial film disposed between the sacrificial area and the dummy holes is removed through the dummy holes to form a connection portion connected to the dummy holes and lower sacrificial patterns cut by the connection portion. The lower sacrificial patterns and sacrificial layers are replaced with gate patterns.

According to the vertical memory device according to example embodiments, a process of etching the lower sacrificial layer to separate the gate pattern (GSL) of the ground selection transistor may be performed after forming the stepped preliminary mold structure. Accordingly, the upper surfaces of each sacrificial layer and insulating layer included in the stepped mold structure may be flat.

Therefore, when the lower sacrificial film is etched in advance to form an opening, and a sacrificial film and an insulating film are formed thereon to form a mold structure, it is possible to prevent the films stacked over the opening from being curved.

Additionally, when performing the dummy channel hole forming processes, for example, a step pattern of the lower sacrificial layer can be formed together, thereby reducing manufacturing process steps.

1 to 25 are plan views, cross-sectional views, and perspective views showing a method of manufacturing a semiconductor device according to example embodiments.
Figure 26 is a plan view for explaining a method of manufacturing a semiconductor device according to example embodiments.
27 to 31 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
32 and 35 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
36 and 39 are plan and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
FIGS. 40 and 47 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
Figure 48 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

1 to 25 are plan views, cross-sectional views, and perspective views showing a method of manufacturing a semiconductor device according to example embodiments.

Specifically, Figures 1, 3, 5, 9, 15, 22 and 24 are plan views, and Figures 2, 4, 6 to 8, 10 to 14, 16 to 21 and 23 are cross-sectional views. Figure 25 is a perspective view showing a partial area of a vertical memory device.

Figures 3, 5, 9, 15, 22 and 24 show portions of the cell area and wiring area in the substrate.

Figures 4, 6, and 17 are cross-sectional views cut along line II_I' of Figure 3, Figures 7, 16, 18, 20, and 23 are cross-sectional views cut along line II_II' of Figure 3, and Figures 2, 8, and 10 , 11, 12, 13, 14, 19 and 21 are cross-sectional views cut along line III_III'.

Hereinafter, the direction perpendicular to the upper surface of the substrate is referred to as the first direction. Additionally, directions parallel to the upper surface of the substrate and perpendicular to each other are referred to as the second direction and the third direction.

1 and 2, a mask pattern 102 is formed on the substrate 100, and a substrate treatment process is performed on the surface of the substrate 100 exposed by the mask pattern 102 to form the substrate 100. ) A sacrificial area 104 may be formed at the top. The upper surface of the substrate including the sacrificial area may be flat.

The substrate 100 may include a cell area (A), a wiring area (B), and a peripheral area (C). The cell area (A) may be an area where memory cells are formed. The wiring area B may be an area where wiring electrically connected to the memory cells is formed. The peripheral area (C) may be an area other than the cell area (A) and the wiring area (B). The wiring area (B) and the peripheral area (C) may have a shape surrounding the cell area (A).

The wiring area B may include a first area where the ground selection line GSL is to be cut. Although not shown, the first portion may be repeatedly arranged at regular intervals in the wiring area B.

The mask pattern 102 may selectively expose a portion of the substrate 100 corresponding to the first portion. Accordingly, the mask pattern 102 can cover both the cell area (A) and the peripheral area (C). The mask pattern 102 may include, for example, a photoresist pattern.

In an exemplary embodiment, the first portion may overlap one end of the uppermost word line in the wiring area B in the first direction. Additionally, the first region may correspond to a region between a pair of neighboring gate patterns in the third direction.

The sacrificial region 104 may be formed to have high etch selectivity with respect to parts of the substrate 100 other than the sacrificial region 104.

In an exemplary embodiment, the substrate processing process may include an ion implantation process or a plasma treatment process.

For example, when the ion implantation process is performed, a sacrificial region 104 doped with impurities may be formed on the upper part of the substrate 100. Accordingly, the sacrificial region 104 can be etched faster than an undoped portion of the substrate. In contrast, when the plasma treatment process is performed, a sacrificial area 104 in which plasma damage occurs may be formed on the upper part of the substrate 100. Accordingly, the sacrificial region 104 can be etched faster than the portion of the substrate where the damage has not occurred.

In some other exemplary embodiments, the substrate treatment process may include an etching process of the substrate and a process of forming a buried film on the etched area. Specifically, the portion of the substrate 100 exposed by the mask pattern 102 is etched to form a recess, and the sacrificial region 104 can be formed by forming a buried film within the recess. The buried film may include a material that has high etch selectivity with respect to the substrate 100, and may include, for example, silicon germanium, polysilicon, etc.

Referring to FIGS. 3 and 4 , a preliminary stepped mold structure 115 may be formed on the substrate 100. A first interlayer insulating film 120 may be formed covering the preliminary stepped mold structure 115.

Specifically, a lower insulating layer 112a and a lower sacrificial layer 114a are sequentially formed on the substrate 100. The lower sacrificial layer may have a flat upper surface. A mold structure may be formed by alternately and repeatedly stacking insulating films 112b, 112c, 112d, 112e, 112f, 112g and sacrificial films 114b, 114c, 114d, 114e, 114f on the lower sacrificial film. . The insulating layers 112b, 112c, 112d, 112e, 112f, and 112g and the sacrificial layers 114b, 114c, 114d, 114e, and 114f formed on the lower sacrificial layer may have a flat upper surface.

For example, the lower insulating film and the insulating films 112a, 112b, 112c, 112d, 112e, 112f, and 112g may be formed using an oxide-based material such as silicon oxide, silicon carbonate, or silicon fluoride. For example, the lower sacrificial film and sacrificial films 114a, 114b, 114c, 114d, 114e, and 114f may be formed using a nitride-based material such as silicon nitride (SiN) or silicon boronitride (SiBN). there is.

Thereafter, the edge portion of the mold structure may be etched step by step to form the preliminary stepped mold structure 115. That is, the preliminary stepped mold structure 115 may have a stepped shape at each corner located in the wiring area B and the peripheral area C.

The lower sacrificial film and sacrificial films 114a, 114b, 114c, 114d, 114e, and 114f may be removed through a subsequent process to provide a space in which gate patterns are formed. The gate patterns may include GSL, word lines, and SSL. In an exemplary embodiment, the lower sacrificial layer 114a may be provided as a GSL, and at least one sacrificial layer (eg, 114f) formed at the top may be provided as an SSL. Additionally, sacrificial layers (eg, 114b, 114c, 114d, 114e) located between the sacrificial layers formed of the GSL and SSL may be provided as word lines. In an exemplary embodiment, the lower sacrificial layer may have two or more layers, and thus, two or more GSLs may be formed.

Hereinafter, the description will be limited to the fact that one GSL and one SSL are provided in one string, and word lines are provided between the GSL and SSL, but the present invention is not limited to this.

The first interlayer insulating film 120 may be formed using an insulating material such as silicon oxide.

Referring to FIGS. 5 to 8 , filler structures 138 may be formed by penetrating the preliminary stepped mold structure 115 located in the cell area (A). The pillar structures 138 may include a semiconductor pattern 127, a channel structure 136, and a pad pattern 137. Additionally, a second interlayer insulating film 140 may be further formed to cover the first interlayer insulating film 120, the preliminary stepped mold structure 115, and the filler structure 138.

Specifically, the channel hole 125 may be formed by anisotropically etching the insulating films and sacrificial films of the preliminary stepped mold structure 115 located in the cell region. The surface of the substrate 100 may be exposed through the channel hole 125. In an exemplary embodiment, the semiconductor pattern 127 may be formed on the bottom of the channel hole 125 by performing a selective epitaxial growth process. A channel structure 136 may be formed on the semiconductor pattern 127 to fill the inside of the channel hole 125. The channel structure 136 may include a dielectric film structure 130, a channel 132, and a buried insulating pattern 134. The dielectric layer structure 130 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. For example, the pad pattern 137 including polysilicon may be formed on the channel structure 136.

The second interlayer insulating film 140 may be formed using an insulating material such as silicon oxide. In an exemplary embodiment, the second interlayer insulating film 140 may be formed of substantially the same material as the first interlayer insulating film 120. Therefore, they may be merged into one interlayer insulating film.

9 and 10, the insulating films, sacrificial films, and first and second interlayer insulating films 120 and 140 of the preliminary stepped mold structure 115 located in the wiring area are anisotropically etched to form a first dummy. A hole 141 and a second dummy hole 142 may be formed, respectively. The first and second dummy holes 141 and 142 may expose the surface of the substrate 100.

A dummy channel structure 147 may be formed inside the first dummy hole 141 through a subsequent process. The dummy channel structure 147 may be provided as a support pattern to support the gate patterns.

The second dummy hole 142 may be formed at both edges of the first portion. That is, the sacrificial area 104 may be located between the second dummy holes 142, and the edge of the sacrificial area 104 may be partially exposed on the bottom of the second dummy hole 142. there is. The second dummy hole 142 may be provided to form an opening for cutting the GSL in a subsequent process.

Referring to FIG. 11, the substrate 100 in the sacrificial area 104 is selectively removed. The removal process can be performed through an isotropic etching process.

The isotropic etching process may include a wet etching process, a dry isotropic etching process, etc. The etchant used in the etching process may be provided through the second dummy hole 142.

When the isotropic etching process is performed, a preliminary first connection portion 142a may be formed in the lower portion of the second dummy holes 142 to connect the lower portions of the second dummy holes 142 to each other. The second dummy holes 142 and the preliminary first connection portion 142a may have a U-shape.

Referring to FIG. 12, an isotropic etching process is performed to remove the lower insulating film 114a exposed on the preliminary first connection portion 142a. Accordingly, a preliminary second connection portion 142b exposing the bottom surface of the lowermost sacrificial layer may be formed.

The lower insulating film 114a exposed on the preliminary first connection part 142a is more dense than the other insulating film exposed on the sidewall of the second dummy hole 142 because etchants are transmitted through the first preliminary connection part 142a. The area in contact with the etchants is larger. Therefore, the lower insulating film 112a exposed on the first preliminary connection portion 142a may be etched faster than the other insulating film exposed on the sidewall of the second dummy hole 142. The insulating film exposed on the sidewall of the second dummy hole 142 may be etched to a certain thickness, and as a result, uneven portions may be created on the sidewall of the second dummy hole 142.

Meanwhile, although not shown, in the etching process, the insulating film exposed on the sidewall of the first dummy hole 141 may also be partially thick. Accordingly, the uneven portion may be created on the sidewall of the first dummy hole 141.

Referring to FIG. 13, an isotropic etching process is performed to remove the lower sacrificial layer 114a exposed on the second preliminary connection portion 142b. Accordingly, a first connection portion 142c may be formed to connect the lower portions of the first dummy holes 142 to each other.

Since etchants are delivered to the lower sacrificial film 114a exposed on the preliminary second connection part 142b through the preliminary second connection part 142b, other sacrificial layers exposed on the sidewall of the second dummy hole 142 The area in contact with the etchants is larger than that of the film. Therefore, the lower sacrificial layer 114a exposed on the second preliminary connection portion 142b may be etched faster than the other sacrificial layer exposed on the sidewall of the second dummy hole 142. Accordingly, the sacrificial film exposed on the sidewall of the second dummy hole 142 may be etched to a partial thickness. In an exemplary embodiment, the etch thickness of the sacrificial film exposed on the sidewall of the second dummy hole 142 may be different from the etch thickness of the insulating film exposed on the sidewall of the second dummy hole 142. Accordingly, uneven portions may be created on the sidewall of the second dummy hole 142.

Meanwhile, although not shown, the sacrificial film exposed on the sidewall of the first dummy hole 141 may also be etched to a certain thickness. Accordingly, the uneven portion may be created on the sidewall of the first dummy hole 141.

When the above process is performed, only the lowermost insulating film and the lowermost sacrificial film located on the substrate 100 in the first region are selectively removed.

In a general method, after depositing the lowermost insulating layer and the lowermost sacrificial layer, the lowermost insulating layer and the lowermost sacrificial layer in the first portion are etched to form an opening for GSL cutting. Afterwards, an insulating film and a sacrificial film are continuously deposited on the lowermost sacrificial film and the cut portion substrate to form a preliminary mold structure. In this case, the height of the upper surface of the insulating film and the sacrificial film formed inside the cut portion may be lower than the height of the upper surface of the other insulating film and the sacrificial film formed on the lowermost sacrificial film. That is, the insulating film and the sacrificial film have a step at the opening area, and as a result, a curved area may be created in the insulating film and the sacrificial film at the opening area. The bent portion may cause defects in subsequent processes.

However, according to exemplary embodiments, an opening for GSL cutting is not formed in the lowermost insulating layer and the sacrificial layer, but the preliminary stepped mold structure 115 is formed by sequentially and repeatedly stacking the insulating layer and the sacrificial layer. Therefore, the insulating film and the sacrificial film in the preliminary stepped mold structure 115 may not be curved due to the lower step. Additionally, after forming the preliminary stepped mold structure 115, the lowermost insulating film and the lowermost sacrificial film located in the first portion can be selectively removed. Therefore, the GSL of the ground selection transistor can be cut at the first portion through a subsequent process.

Referring to FIG. 14, a first insulating structure 146 is formed to fill the inside of the second dummy hole 142 and the first connection portion 142c, and a dummy channel structure (FIG. 15, 147) can be formed.

In an exemplary embodiment, the first insulating structure 146 and the dummy channel structure 147 may be formed using a material having a high etch selectivity with the material provided as the sacrificial layer. For example, the first insulating structure 146 and the dummy channel structure 147 may include silicon oxide.

In an exemplary embodiment, the first insulating structure 146 and the dummy channel structure 147 include an insulating film that completely fills the second dummy hole 142, the first connection portion 142c, and the first dummy hole 141. It can be formed by forming and flattening the insulating film. The planarization process may be performed so that the upper surface of the second interlayer insulating film 140 is exposed. Alternatively, the planarization process may be performed so that the upper surface of the first interlayer insulating film 120 is exposed. In this case, the first insulating structure 146 includes an insulating pattern that completely fills the second dummy hole 142 and the first connection portion 142c, and the dummy channel structure 147 includes the first dummy hole 142. It may include an insulating pattern that completely fills (141).

In some embodiments, the first insulating structure 146 and the dummy channel structure 147 are conformal along the surfaces of the second dummy hole 142, the first connection portion 142c, and the first dummy hole 141. forming an insulating film, forming a buried film on the insulating film to completely fill the second dummy hole 142, the first connection portion 142c, and the first dummy hole 141, and planarizing the filling film and the insulating film. can do. In this case, the first insulating structure 146 includes an insulating pattern conformally formed along the surface of the second dummy hole 142 and the first connection portion 142c, and the second dummy hole ( 142) and a buried pattern that completely fills the first connection portion 142c. In addition, the dummy channel structure 147 includes an insulating pattern conformally formed along the surface of the first dummy hole 141 and a buried pattern that completely fills the first dummy hole 141 on the insulating pattern. You may.

The first insulating structure 146 may have a U-shape when viewed in cross section. That is, the first insulating structure 146 is located at both ends of the first portion and includes a filler portion extending through the preliminary stepped mold structure 115 and the first interlayer insulating film 120 to the substrate surface, and the filler portion. It may include a bridge pattern connecting the lower parts to each other.

Referring to FIGS. 15 and 16 , an opening 150a extending in the second direction may be formed by cutting the preliminary stepped mold structure 115 in at least the cell region. Through the above process, the preliminary stepped mold structure 115 in the cell area may be formed as stepped mold structures 115a spaced apart from each other in the third direction. An insulating pattern 116 and a sacrificial pattern 118 may be stacked on the stepped mold structure 115a.

In the etching process to form the opening 150a, the preliminary stepped mold structure 115 in the first portion may not be etched. Additionally, the preliminary stepped mold structure 115 may be etched on both sides of the first portion in the second direction. Accordingly, the portion that is not etched may be provided as a connection pattern 150b connecting the stepped mold structures 115a to each other.

In an exemplary embodiment, openings 150a including the connection pattern 150b and openings 150a not including the connection pattern 150b may be formed alternately in the third direction. Accordingly, the pair of adjacent stepped mold structures 115a may be connected to each other by the connection pattern 150b at the first portion.

The first portion may overlap with a sacrificial pattern (eg, 118e) corresponding to an end of the uppermost word line in the second direction. Accordingly, the uppermost sacrificial pattern (eg, 118f) provided as the SSL may have a cut shape. On the other hand, the sacrificial patterns (eg, 118b to 118e) provided to the word line located below may have a shape connected to each other in the third direction by the connection pattern 150b. Additionally, the lowermost sacrificial pattern 118a provided to the GSL may have a shape cut by a previous process. That is, in the first portion, the sacrificial patterns provided by the SSL and GSL may not be provided.

Referring to FIGS. 17 to 19 , the sacrificial patterns 118 whose sidewalls are exposed through the opening 150a may be removed. According to example embodiments, the sacrificial patterns 118 may be removed through an isotropic etching process.

As the sacrificial patterns 118 are removed, a gap 152 may be formed between the insulating patterns 116 of each layer. At this time, as shown in FIG. 20, the sacrificial patterns 118 remaining in the first portion are also removed, thereby forming the gap 152.

Referring to FIGS. 20 and 21 , gate patterns 160 can be formed by filling the inside of the gap 152 of each layer with a conductive material. That is, the sacrificial patterns 118 of each layer may be replaced with gate patterns 160, respectively. According to example embodiments, the gate pattern 160 may be formed using metal or metal nitride.

As described, the lowest gate pattern 160a is provided as a GSL, the uppermost gate pattern 160f is provided as an SSL, and the gate patterns 160b, 160c, 160d, and 160e between the GSL and SSL are word lines. can be provided.

However, the inside of the gap 152 in the first portion is also filled with the conductive material, and this can be provided as a conductive connection pattern 161 that connects two adjacent word lines in the third direction. Accordingly, two neighboring word lines in the third direction may be electrically connected.

However, since the gap 152 is not formed in the portion corresponding to the SSL and GSL in the first portion and is filled with an insulating material, the conductive connection pattern 161 is not formed. Accordingly, the SSLs and GSLs neighboring in the third direction may be electrically insulated.

Referring to FIGS. 22 and 23, an ion implantation process may be performed to form an impurity region 105 on the upper part of the substrate 100 exposed through the opening 150a. An insulating pattern 155 and a common source line 157 may be formed on the impurity region 105 to fill the opening 150a.

Subsequently, although not shown, an upper interlayer insulating film may be formed on the second interlayer insulating film, contacts may be formed penetrating the interlayer insulating films located in the wiring region, and interconnections connected to the contacts may be formed. .

A vertical memory device can be manufactured through the above process.

FIG. 24 is a plan view of a vertical memory device, and FIG. 25 is a perspective view showing a connection pattern portion of the vertical memory device.

Referring to FIGS. 22 to 25 , the vertical memory device may be provided with gate patterns 160 that extend in the second direction and are stacked while being spaced apart from each other in the first direction. Edges of the gate patterns 160 are located in the wiring area, and the edges may have a step shape.

Channel structures 136 are provided through the gate patterns 160 located in the cell region, and a dummy layer is provided through the gate patterns 160 and the first interlayer insulating layer 120 located in the wiring region. Channel structures 147 may be provided. Additionally, a first insulating structure 146 may be provided at a first portion in the wiring area where the GSL is cut. The first insulating structure 146 may include substantially the same material as the dummy channel structure 147.

The first insulating structure 146 includes the pillar portion and a bridge pattern, and the GSLs neighboring in the third direction may be cut from each other by the bridge pattern.

As shown in FIG. 21, the side wall of the pillar portion of the first insulating structure 146 may have irregularities.

On the bridge pattern, the conductive connection pattern 161 is provided in a portion corresponding to the pillar portion, and the conductive connection pattern 161 is provided as a pair of gate patterns 160 provided as word lines. They can be electrically connected to each other in three directions.

The gate patterns 160 may be formed to have flat upper surfaces without any curves.

Figure 26 is a plan view for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 26 , the process described with reference to FIGS. 1 to 4 is performed in the same manner to form the preliminary stepped mold structure 115 and the first interlayer insulating film on the substrate.

Thereafter, the same process as described with reference to FIGS. 9 to 14 is performed to form a first insulating structure and a dummy channel structure 147 on the preliminary stepped mold structure 115.

Afterwards, the process described with reference to FIGS. 5 to 8 is performed to form the filler structure.

That is, the first insulating structure and the dummy channel structure 147 can be formed in the preliminary stepped mold structure 115 without forming a filler structure in the cell region. Then, the filler structure is formed in the cell region.

Subsequently, the vertical memory device can be manufactured by performing the process described with reference to FIGS. 15 to 23. The vertical memory device may be substantially the same as the vertical memory device shown in FIGS. 22 to 25.

27 to 31 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 27, a lower insulating layer 112a and a lower sacrificial layer 114a are formed on the substrate 100.

A mask pattern 102 is formed on the lower sacrificial layer 114a. The mask pattern 102 may selectively expose a portion of the lower sacrificial layer 114a corresponding to a first portion of the wiring region B where the ground selection line GSL is to be cut.

A substrate treatment process is performed on the surface of the lower sacrificial layer 114a exposed by the mask pattern 102 to form a sacrificial region 104a in a portion of the lower sacrificial layer 114a.

The substrate processing process may include an ion implantation process or a plasma treatment process. The sacrificial region 104a may have high etch selectivity with the lower sacrificial layer 114a and the sacrificial layer formed thereafter. That is, when the same etching process is performed, the sacrificial region 104a can be removed faster than the lower sacrificial layer and other sacrificial layers.

After this, the mask pattern is removed.

Referring to FIG. 28, insulating films 112b, 112c, 112d, 112e, 112f and sacrificial films 114b, 114c, 114d, 114e, 114f are formed on the lower sacrificial film 114a and the sacrificial region 104a. A mold structure is formed by alternately and repeatedly stacking.

Afterwards, the ends of the mold structure are gradually etched to form a preliminary stepped mold structure 115 (see FIGS. 3 and 4). The process of forming the preliminary stepped mold structure may be substantially the same as that described with reference to FIGS. 3 and 4.

Continuing, by performing the same process as described with reference to FIGS. 5 to 8, filler structures 138 (see FIG. 5) are formed through the preliminary stepped mold structure 115 located in the cell area (A). can be formed.

Referring to FIG. 29, the insulating films 112, sacrificial films 114, and first and second interlayer insulating films of the preliminary stepped mold structure 115 located in the wiring area are anisotropically etched to form a first dummy hole and Second dummy holes 143 may be formed, respectively. The process of forming the first and second dummy holes 143 may be the same as that described with reference to FIGS. 9 and 10 .

A sacrificial region 104a formed in the lower sacrificial layer 114a may be exposed on the lower sidewall of the second dummy hole 143.

Referring to FIG. 30, the sacrificial region 104a is removed through an isotropic etching process. The sacrificial region 104a may be etched faster than the lower sacrificial layer 114a and the other sacrificial layers 114b, 114c, 114d, and 114e. Accordingly, a first connection portion 143a that connects the lower side walls of the second dummy hole 142 to each other can be formed. The first connection portion 143a may be a portion where the GSL of the ground selection transistor formed in a subsequent process is cut. The lower sacrificial layer 114a on both sides of the first connection portion 143a may be replaced with a gate pattern through a subsequent process and provided to the GSL.

In the process of etching the sacrificial region 104a, the lower sacrificial layer 114a and the other sacrificial layers 114b, 114c, 114d, and 114e may also be etched to a certain thickness. Accordingly, uneven portions may be created on the sidewall of the second dummy hole 143.

Referring to FIG. 31, a vertical memory device can be manufactured by performing the same processes described with reference to FIGS. 14 to 23.

That is, a first insulating structure 146 is formed to fill the inside of the second dummy hole 143 and the first connection portion 143a (FIG. 30), and a dummy channel structure (FIG. 15) is formed inside the first dummy hole 141. , 147) can be formed.

At this time, the first insulating structure 146 connects the filler part extending through the preliminary stepped mold structure 115 and the first interlayer insulating film 120 to the surface of the substrate 100 and the lower part of the pillar part. It may include a bridge pattern. The heights of the upper and lower surfaces of the bridge pattern may be the same as the heights of the upper and lower surfaces of the lowermost sacrificial pattern, respectively.

In an exemplary embodiment, the bridge pattern and the lower insulating layer 112a may include the same insulating material. In this case, the bridge pattern and the lower insulating layer 112a may be merged into one layer.

Afterwards, an opening extending in the second direction (FIG. 22, 150a) may be formed while cutting the preliminary stepped mold structure 115 in at least the cell region. The sacrificial patterns can be replaced with gate patterns 160.

The vertical memory device is a vertical memory device shown in FIGS. 22 to 25, except that no recess is created in the substrate and the bridge pattern of the first insulating structure 146 is provided to be spaced apart from the upper surface of the substrate. It may be substantially the same as the type memory device.

32 and 35 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 32, a lower insulating film 112a is formed on the substrate 100.

A mask pattern 102 is formed on the lower insulating film 112a. The mask pattern 102 may selectively expose a portion of the lower insulating film 112a corresponding to a first portion in the wiring region B, where the ground selection line GSL is to be cut.

A substrate treatment process is performed on the surface of the lower insulating layer 112a exposed by the mask pattern 102 to form a sacrificial region 104b in the lower insulating layer 112a.

The substrate processing process may include an ion implantation process or a plasma treatment process. The sacrificial region 104b may have high etch selectivity with the lower insulating layer 112a and insulating layers formed thereafter. That is, when the same etching process is performed, the sacrificial region 104b can be removed faster than the lower insulating layer 112a and other insulating layers.

After this, the mask pattern 102 is removed.

Referring to FIG. 33, a lower sacrificial layer 114a is formed on the lower insulating layer 112a and the sacrificial region 104b. The insulating films 112b, 112c, 112d, 112e, and 112f and the sacrificial films 114b, 114c, 114d, and 114e are alternately and repeatedly stacked on the lower sacrificial film 114a to form a mold structure. Afterwards, the ends of the mold structure are gradually etched to form a preliminary stepped mold structure 115 (see FIGS. 3 and 4). The process of forming the preliminary stepped mold structure 115 may be substantially the same as that described with reference to FIGS. 3 and 4 .

Continuing, the same process as described with reference to FIGS. 5 to 8 is performed to form filler structures 138 (FIG. 5) by penetrating the preliminary stepped mold structure 115 located in the cell area (A). can do.

Thereafter, the insulating films, sacrificial films, lower insulating film, lower sacrificial film, and first and second interlayer insulating films of the preliminary stepped mold structure 115 located in the wiring area are anisotropically etched to form the first dummy hole and the second interlayer insulating film. Dummy holes 143b are formed respectively. The process of forming the first and second dummy holes 143b may be the same as that described with reference to FIGS. 9 and 10 . A sacrificial region 104b formed in the lowermost insulating layer 112a may be exposed on the sidewall of the second dummy hole 143b.

Referring to FIG. 34, the sacrificial region 104b is removed through an isotropic etching process. The sacrificial region may be etched faster than the lower insulating layer 112a and the other insulating layers 112b, 112c, 112d, 112e, and 112f. Accordingly, it is possible to form a preliminary first connection portion 143c that connects the lower side walls of the second dummy hole 143b to each other. The substrate surface and the bottom surface of the lower sacrificial layer may be exposed by the preliminary first connection portion 143c, respectively.

In the process of etching the sacrificial region, the lowermost insulating layer and other insulating layers may also be etched to a certain thickness. Accordingly, uneven portions may be created on the sidewall of the second dummy hole 143b.

Referring to FIG. 35, an isotropic etching process is performed to remove the lower sacrificial layer 114a exposed by the preliminary first connection portion 143c. Accordingly, a first connection portion 143d may be formed to connect the lower portions of the second dummy holes 143b to each other.

The lower sacrificial film 114a exposed on the preliminary first connection portion 143c is etched faster than the other sacrificial films 114b, 114c, 114d, and 114e exposed on the sidewall of the second dummy hole 143b. You can. Accordingly, through the etching process, uneven portions may be created on the sidewall of the second dummy hole 143b.

Afterwards, substantially the same process as described with reference to FIGS. 14 to 23 is performed to manufacture a vertical memory device.

In the vertical memory device, the first insulating structure 146b may include a pillar part extending to the surface of the substrate 100 and a bridge pattern connecting the lower part of the pillar part to each other. The height of the upper surface of the bridge pattern may be substantially equal to the height of the upper surface of the lowermost gate pattern 118a. Additionally, the bridge pattern may be in contact with the upper surface of the substrate 100.

The vertical memory device may be substantially the same as the vertical memory device shown in FIGS. 22 to 25, except that no recess is created in the substrate.

36 and 39 are plan and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to Figure 36, the same process as described with reference to Figures 1 to 4 is performed. Accordingly, a preliminary stepped mold structure (FIG. 4, 115) can be formed on the substrate 100. A first interlayer insulating film 120 may be formed to cover the preliminary stepped mold structure 115.

The channel hole 125a, the first dummy hole 141, and the second dummy hole 142 may be formed by anisotropically etching the insulating films and sacrificial films of the preliminary stepped mold structure 115. That is, the channel hole 125a, the first dummy hole 141, and the second dummy hole 142 can be formed simultaneously through the anisotropic etching process.

Referring to FIG. 37, a semiconductor pattern 127 may be formed on the bottom of the channel hole 125a by performing a selective epitaxial growth process. At this time, the wiring area may be blocked so that the semiconductor pattern is not formed on the bottom surfaces of the first dummy hole 141 and the second dummy hole 142.

Afterwards, the processes described with reference to FIGS. 11 to 13 are performed in the same manner. Accordingly, a first connection portion (FIG. 13, 142c) connecting the lower portions of the second dummy holes 142 to each other can be formed.

When the above processes are performed, uneven portions may be created on the side walls of the first and second dummy holes 142, respectively. Additionally, the insulating pattern and sacrificial pattern exposed on the sidewall of the channel hole 125a may be etched to a certain thickness. Therefore, the uneven portion may be created on the sidewall of the channel hole 125a.

Referring to FIGS. 38 and 39, a pillar structure 138 may be formed inside the channel hole. The pillar structure 138 may include a semiconductor pattern 127, a channel structure 136a, and a pad pattern 137. Additionally, a dummy channel structure and a first insulating structure 136b may be formed inside the first and second dummy holes, respectively. The first insulating structure 136b, the dummy channel structure, and the channel structure 136a may be formed through the same process and may include substantially the same material.

Specifically, the channel structure may include a first dielectric layer structure 130a, a first channel 132a, and a first buried insulating pattern 134a. The dummy channel structure and the first insulating structure 136b may include a second dielectric film structure 130b, a second channel 132b, and a second buried insulating pattern 134b. The first insulating structure is formed on a sidewall of the second dummy hole and includes a second dielectric film structure 130b made of an insulating material, and thus may be provided as an insulating structure. Within the channel hole, a pad pattern 137 may be formed on the channel structure 136a.

The channel structure 136a, the dummy channel structure, and the first insulating structure 136b may have uneven portions formed on side walls by the uneven portions of the channel hole and the first and second dummy holes.

Afterwards, the same process as described with reference to FIGS. 15 to 23 is performed to manufacture a vertical memory device.

In the vertical memory device, the channel structure, the dummy channel structure, and the first insulating structure have uneven sidewalls, and the same materials may be stacked on each other. Other than that, it may be substantially the same as the vertical memory device shown in FIGS. 22 to 25.

In some embodiments, the vertical memory device may not have a recess created in the substrate.

FIGS. 40 and 47 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIGS. 40 to 42, the same process as described with reference to FIGS. 1 and 2 is performed.

Afterwards, insulating films 112a, 112b, 112c, 112d, 112e, 112f, 112g and sacrificial films 114a, 114b, 114c, 114d, 114e, 114f are alternately and repeatedly stacked on the substrate 100. Thus, a mold structure can be formed. Thereafter, the edge portion of the mold structure may be etched step by step to form the first preliminary stepped mold structure 115a. That is, each corner of the first preliminary stepped mold structure 115b located in the wiring area and the surrounding area may have a stepped shape.

At this time, the lower insulating film 112a, the lower sacrificial film 114a included in the first preliminary stepped mold structure 115a, and the insulating film 112b formed on the lower sacrificial film 114a may not be etched. there is. Accordingly, the first preliminary staircase mold structure 115b may not have a first floor staircase formed at the bottom.

Next, a first interlayer insulating film 120 may be formed to cover the first preliminary stepped mold structure 115b.

Referring to FIG. 43, filler structures 138 may be formed through the first preliminary stepped mold structure 115b located in the cell area A.

The process may be substantially the same as that described with reference to FIGS. 5 to 8.

Referring to FIGS. 44 to 46, the insulating films, sacrificial films, and first and second interlayer insulating films 120 and 140 of the first preliminary stepped mold structure 115b located in the wiring area are anisotropically etched to form a first layer. One dummy hole 141 and a second dummy hole 142 can be formed, respectively. Additionally, in the etching process, a first-floor staircase may be formed at the bottom of the first preliminary stepped mold structure 115b. Therefore, the second preliminary stepped mold structure 115c can be formed.

That is, in the etching process for forming the first and second dummy holes, the first and second interlayer insulating films 120 and 140, the lower insulating film 112a, the lower sacrificial film 114a, and the lower sacrificial film. The lowest step can be formed by etching the insulating film 112b formed on (114a). That is, the first and second interlayer insulating films 120 and 140, the lower insulating film 112a, the lower sacrificial film 114a, and the first insulating film 112b formed on the lower sacrificial film 114a. An opening 161 may be formed, and when viewed in plan view, the first opening 161 may have a ring shape surrounding the outside of the cell area A.

Parts of the lower insulating films 112a and 111a, the lower sacrificial films 114a and 113a, and the upper insulating films 114b and 111b may be exposed on the side walls of the first opening 161, respectively.

Referring to Figure 47, the processes described with reference to Figures 11 to 14 can be performed in the same manner.

When the above processes are performed, a first insulating structure 146 is formed that fills the inside of the second dummy hole 142 and the first connection portion 142c, and a dummy channel structure (FIG. 14, 147) can be formed.

When the process is performed, the insulating film and/or sacrificial film on the sidewall of the first opening 161 may be partially etched, thereby slightly expanding the width of the first opening 161. Additionally, the inside of the first opening 161 may be filled with an insulating material, so that a second insulating structure 162 may be formed inside the first opening 161.

Afterwards, the same process as described with reference to FIGS. 15 to 23 is performed to manufacture a vertical memory device.

The vertical memory device may include a ring-shaped second insulating structure 162 surrounding the wiring area. Other than that, it may be substantially the same as the vertical memory device shown in FIGS. 22 to 25.

Figure 48 is a cross-sectional view for explaining a method of manufacturing a vertical memory device according to example embodiments.

The vertical memory device may be substantially the same as the vertical memory device shown in FIG. 47 except for the second insulating structure.

The first opening is formed by performing the same process as described with reference to FIGS. 40 to 46.

Referring to Figure 48, the processes described with reference to Figures 11 to 13 can be performed in the same manner. Accordingly, a first connection portion 142c may be formed to connect the lower portions of the second dummy holes 142 to each other.

Afterwards, a first insulating structure 146 is formed to fill the inside of the second dummy hole 142 and the first connection portion 142c, and a dummy channel structure (FIGS. 15, 147) is formed inside the first dummy hole 141. ) can be formed.

Additionally, an insulating material may be deposited inside the first opening 161 to form a second insulating structure 162a inside the first opening 161.

At this time, the second insulating structure 162a may be formed along the sidewall and bottom of the first opening 161. Accordingly, space can remain inside the first opening 161.

Afterwards, a third interlayer insulating film 166 may be formed on the second interlayer insulating film 140 to cover the top of the first opening 161. Accordingly, an air gap 164 may be created inside the first opening.

Afterwards, the same process as described with reference to FIGS. 15 to 23 is performed to manufacture a vertical memory device.

The vertical memory device includes a ring-shaped second insulating structure 162b surrounding the wiring area, and the second insulating structure 162b may include an air gap 164. Other than that, it may be substantially the same as the vertical memory device shown in FIGS. 22 to 25.

As described above, the present invention has been described with reference to preferred embodiments, but those skilled in the art can make various modifications and modifications to the present invention without departing from the spirit and scope of the present invention as set forth in the patent claims. You will understand that you can change it.

A vertical memory device can be manufactured by a method according to exemplary embodiments of the present invention.

100: substrate 102: mask pattern
104: Sacrificial area 105: Preliminary stepped mold structure
120: first interlayer insulating film 112a: lower insulating film
114a: lower sacrificial film
112b, 112c, 112d, 112e, 112f, 112g: insulating films
114b, 114c, 114d, 114e, 114f: sacrificial films
136, 136a: Channel structure
136b: first insulating structure
147: Dummy channel structure
138: Filler structures 140: Second interlayer insulating film
125: channel hole 143a: first connection part
143b: second dummy hole 146: first insulating structure
161: first opening 160: gate pattern

Claims (10)

a plurality of gate patterns stacked and spaced apart in a first direction perpendicular to the substrate, extending in a second direction horizontal to the substrate, and including a lowermost gate pattern and gate patterns provided as a word line;
Among the gate patterns of each layer provided as the word line, a conductive connection pattern that directly connects the gate patterns of each layer adjacent to each other in a third direction perpendicular to the second direction and is made of the same conductive material as the gate patterns. ; and
A filler portion disposed on both sides of the third direction of the conductive connection pattern, penetrating the gate pattern in the first direction, and including an insulating material, and interposed between the third direction of the lowermost gate pattern and extending in the third direction. A vertical semiconductor device comprising an insulating structure that electrically insulates neighboring lowermost gate patterns, is connected to a lower part of the pillar part, and includes a bridge pattern containing an insulating material. The vertical semiconductor device of claim 1, wherein the bridge pattern is disposed below the lowest conductive connection pattern. The vertical semiconductor device of claim 1, wherein a side wall of the pillar portion of the insulating structure has irregularities. The vertical semiconductor device of claim 1, wherein edge portions of the gate patterns in the second direction have a step shape, and the insulating structure and the conductive connection pattern are located at edge portions in the second direction having the step shape. . sequentially forming a lower insulating film and a lower sacrificial film on the substrate;
forming a sacrificial region on at least one of the substrate, a lower insulating film, and a lower sacrificial film located in a pattern cutting area;
repeatedly stacking an insulating layer and a sacrificial layer alternately on the lower sacrificial layer;
exposing the surface of the substrate by etching the insulating layer, the sacrificial layer, the lower insulating layer, and the lower sacrificial layer, and forming dummy holes exposing both ends of the sacrificial region in a third direction, respectively;
The lower sacrificial layer disposed between the sacrificial area and the dummy holes is removed through the dummy holes to form a connection portion communicating with lower portions of the dummy holes and a lower sacrificial pattern cut in the third direction by the connection portion. do;
Replacing the lower sacrificial patterns and sacrificial films with a conductive material to form a lowermost gate pattern cut in the third direction and gate patterns disposed thereon,
An insulating structure that fills the dummy holes and the connection portion with an insulating material and includes a bridge pattern that is interposed between the filler portion and the third direction of the lowermost gate pattern and electrically insulates the lowermost gate pattern adjacent to the third direction. A method of manufacturing a vertical semiconductor device comprising forming a. The method of claim 5, wherein the sacrificial region is formed by plasma treating at least one surface of the substrate, the lower insulating layer, and the lower sacrificial layer. The vertical semiconductor device of claim 5, further comprising etching the lower insulating film, the lower sacrificial film, and each edge of the insulating film and the sacrificial film to have a step shape after repeatedly stacking the insulating film and the sacrificial film alternately. Manufacturing method. The method of claim 5, wherein the insulating material included in the insulating structure includes a material having an etch selectivity with that of the sacrificial layer. 6. The method of claim 5, wherein after forming the connection portion and the lower sacrificial patterns, the lower insulating film, the lower sacrificial film, the insulating film, and the sacrificial film are formed on both sides of the second direction perpendicular to the third direction in the pattern cut area. A method of manufacturing a vertical semiconductor device by etching in the second direction to form a stepped mold structure extending in the second direction and a connection pattern connecting the stepped mold structure to each other. 6. The method of claim 5, wherein in the process of removing the lower sacrificial layer disposed between the sacrificial area and the dummy holes through the dummy holes, the lower sacrificial layer, the sacrificial layer, and the insulating layer are formed so that side walls of the dummy holes have irregularities. A method of manufacturing a vertical semiconductor device in which at least one is partially etched.

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