KR20130115777A - Methods of manufacturing vertical memory devices - Google Patents

Abstract

PURPOSE: A method for manufacturing a vertical memory device is provided to easily perform a semiconductor pattern formation process by extending the inlet of an opening part. CONSTITUTION: An opening part having an expanded inlet is formed. A charge trapping pattern (116a) and an insulating layer pattern (118a) are formed on the sidewall of the opening part. A channel layer is formed in the opening part. The channel layer is electrically connected to a semiconductor substrate. Memory cells and the gate electrodes of a selection transistor are formed on the lateral surface of the channel layer.

Description

Method of manufacturing vertical memory device {METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES}

The present invention relates to a method of manufacturing a vertical memory device. More particularly, the present invention relates to a method of manufacturing a vertical nonvolatile memory device.

Recently, vertical memory devices in which memory cells are stacked in a horizontal direction on a substrate have been developed. In addition, the number of memory cells stacked in a vertical direction on the substrate is continuously increasing in the vertical memory device, and the intervals in which the memory cells are spaced in the horizontal direction are also very narrow. Therefore, each unit process for manufacturing the highly integrated vertical memory device has become difficult.

One object of the present invention is to provide a method of manufacturing a highly integrated vertical memory device.

In order to achieve the above object of the present invention, in the method of manufacturing a vertical memory device according to the embodiments of the present invention, a plurality of sacrificial and interlayer insulating films are made of different materials on a semiconductor substrate repeatedly stacked. One preliminary hard mask pattern and a second hard mask pattern are formed. The sacrificial layers and the interlayer insulating layers are etched using the second hard mask pattern and the first preliminary hard mask pattern as an etch mask to relatively protrude a sidewall portion of the first preliminary hard mask pattern and to form a substrate. It forms a preliminary opening through which the surface is exposed. A portion of the sidewall of the first preliminary hard mask pattern exposed to the preliminary opening is selectively isotropically etched to form an opening having an extended inlet. A charge trapping pattern and a tunnel insulation pattern are formed on sidewalls of the opening. A channel film electrically connected to the semiconductor substrate is formed in the opening. In addition, gate electrodes of memory cells and a selection transistor are formed on side surfaces of the channel layer.

In one embodiment of the present invention, the first preliminary hard mask pattern may include polysilicon.

In one embodiment of the present invention, the step of selectively isotropically etching part of the sidewalls of the first preliminary hard mask pattern may be performed by introducing an etching gas containing a halogen element at a temperature of 300 to 500 degrees.

The etching gas may include a Cl ₂ gas or an NF ₃ gas.

In one embodiment of the present invention, the cross section of the first hard mask pattern at the opening portion has a trapezoidal shape, and the lower width of the first hard mask pattern is formed to be equal to or narrower than the width of the uppermost interlayer insulating film. A portion of the sidewalls of the first preliminary hard mask pattern may be selectively isotropically etched.

In one embodiment of the present invention, after selectively isotropically etching a portion of the first preliminary hard mask pattern sidewall, a portion of the sidewall of the second hard mask pattern may be selectively selected.

The process of selectively etching a portion of the sidewalls of the second hard mask pattern may be performed by introducing an etching gas including HF or NH ₃ at a temperature of 50 to 300 degrees.

In an embodiment of the present disclosure, after the opening is formed, a semiconductor pattern may be formed to fill the lower portion of the opening.

In one embodiment of the present invention, the channel film may be formed in direct contact with the sidewall of the opening and the top surface of the semiconductor pattern.

In one embodiment, the charge trapping pattern and the tunnel insulation pattern form a charge trapping layer and the tunnel insulation layer along sidewalls and bottom surfaces of the openings. Next, the charge trapping film and the tunnel insulating film formed on the bottom surface of the opening are etched.

According to the embodiments of the present invention, the opening of the opening may be expanded because the opening of the opening does not protrude by the hard mask pattern. Therefore, in the subsequent steps, processes such as semiconductor pattern formation, charge trapping film pattern, tunnel insulating film pattern, and first channel film pattern formation can be easily performed.

1 to 9 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to Embodiment 1 of the present invention.
10 and 11 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to Embodiment 2 of the present invention.
12 to 14 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to a third embodiment of the present invention.

Hereinafter, a method of manufacturing a vertical type memory device according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, It will be understood by those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. In the accompanying drawings, dimensions of a substrate, a layer (film), an area, patterns or structures are enlarged in actuality for clarity of the present invention. In the present invention, each layer (film), region, electrode, pattern or structure is referred to as being "on", "on", or " Means that each layer (film), region, electrode, pattern, or structure is directly formed or positioned below a substrate, each layer (film), region, structure, or pattern, A layer (film), another region, another electrode, other patterns or other structure may be additionally formed on the substrate. It will also be understood that when a material, layer, area, electrode, pattern or structure is referred to as a "first", "second" and / or " Regions, electrodes, patterns, or structures. ≪ RTI ID = 0.0 > Thus, "first "," second "and / or" reserve "may be used, respectively, selectively or interchangeably for each layer (membrane), region, electrode, patterns or structures.

Example 1

1 to 9 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to Embodiment 1 of the present invention.

Referring to FIG. 1, a plurality of interlayer insulating films 102 and a sacrificial film 104 are alternately repeatedly stacked on a substrate 100. The first hard mask film 106 and the second hard mask film 108 are sequentially formed on the interlayer insulating film 102 formed on the uppermost layer. In FIG. 1, seven layers of interlayer insulating film 102 and six layers of sacrificial film 104 are formed, but the number of stacked layers may be increased or decreased.

The substrate 100 may include a single crystal semiconductor material. The substrate is used as a seed for growing a single crystal semiconductor material through a selective epitaxial process in a subsequent process. Therefore, the substrate 100 may be a substrate including single crystal silicon on at least an upper surface thereof.

The plurality of interlayer insulating layers 102 function to insulate each of the memory cells and the selection transistors stacked vertically. The interlayer insulating film 102 may be formed using an insulating oxide. For example, the interlayer insulating layer 102 may be formed of silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF).

The sacrificial layer 104 is formed by depositing a material having an etch selectivity with the interlayer insulating layers 102. In addition, the sacrificial layer 104 must be formed of a material having an etching selectivity with respect to the substrate. For example, the sacrificial layer 104 may be formed using a nitride such as silicon nitride (SiN), silicon borosilicate (SiBN), or the like.

The sacrificial film 104 is provided as a film for forming gates constituting each of the memory cells and the selection transistors in a subsequent process. Therefore, the thickness of the sacrificial film 104 formed in each layer may be the same as the target thickness of the gate electrodes formed in each layer.

The gate electrode of the selection transistor may have a gate length longer than that of the cell transistor. Therefore, although not shown, the sacrificial film 104 provided as the gate of the selection transistor may be formed thicker than the sacrificial film of another layer.

Subsequent processes must be performed on the structure in which the interlayer insulating layer 102 and the sacrificial layer 104 are stacked. In order to reduce damage to the interlayer insulating film and the sacrificial film by subsequent processes, the interlayer insulating film formed on the top may be formed thicker than other interlayer insulating films formed on the bottom.

The first hard mask layer 106 may serve as a main etching mask for forming a channel hole by etching part of the stacked structure of the interlayer insulating layers 102 and the sacrificial layers 104. Therefore, a material having an etch selectivity is formed by depositing the interlayer insulating film and the sacrificial film, respectively. For example, the first hard mask layer 106 is formed by depositing polysilicon.

The second hard mask layer 108 is provided as a sub-etching mask to suppress damage or wear of the first hard mask layer 106 during an etching process. The second hard mask layer 108 may be formed of a material having excellent adhesive properties with the first hard mask layer 108 and having almost no stress at an interface. For example, the second hard mask layer 108 may be formed by depositing silicon oxide.

Referring to FIG. 2, a photoresist pattern is formed on the second hard mask layer 108 and then patterned with an etching mask to form a second hard mask pattern 108a. Subsequently, the first hard mask layer 106 is etched to form a first preliminary hard mask pattern 106a.

By using the first preliminary hard mask pattern 106a and the second hard mask pattern 108a as an etch mask, the preliminary openings exposing the substrate surface on the bottom surface by etching the interlayer insulating layer 102 and the sacrificial layer 104 ( 110).

The preliminary opening 110 may be formed through a dry etching process. The preliminary opening 110 may have a vertical inclination with respect to the substrate 100, and may have a shape in which the width thereof becomes narrower toward the lower portion of the substrate 100.

The etching process is performed under the condition that the interlayer insulating film 102 made of oxide is etched. Therefore, a portion of the second hard mask pattern 108a formed of silicon oxide may also be removed in the etching process. In addition, when the etching process is performed, the second hard mask pattern 108a formed of silicon oxide may be etched faster than the first preliminary hard mask pattern 106a formed of polysilicon. Therefore, when the etching process is completed to form the preliminary opening 110, the first preliminary hard mask pattern 106a protrudes from the sidewall of the preliminary opening 110 than the second hard mask pattern 108a. Has

The inner side of the preliminary opening 110 may be narrower to protrude toward the lower sidewall of the first preliminary hard mask pattern 106a. That is, the cross-section of the first preliminary hard mask pattern 106a at the preliminary opening 110 has a wide trapezoidal shape at a lower portion thereof, and a lower width of the preliminary first hard mask pattern 106a has the uppermost interlayer insulating film. It can be formed wider than the width of. As such, the protruding portion of the first preliminary hard mask pattern 106a may narrow the inner width of the inlet portion of the preliminary opening 110.

In addition, the inner width W1 of the preliminary opening 110 between the first preliminary hard mask patterns 106a is smaller than the inner width W2 of the preliminary opening 110 between the second hard mask patterns 108a.

Referring to FIG. 3, an isotropic etching process of selectively etching only sidewalls of the first preliminary hard mask pattern 106a exposed to the sidewalls of the preliminary opening 110 may be performed to form a first hard mask pattern 106b. The isotropic etching process may be performed to remove the protruding portion of the first preliminary hard mask pattern 106a. When the isotropic etching process is performed, the first opening 110a having the inner width of the inlet portion is expanded.

The cross section of the first hard mask pattern 106b has a trapezoidal shape at a portion of the first opening 110a. By isotropic etching, the lower width W3 of the first hard mask pattern 106b is equal to or narrower than the width W4 of the uppermost interlayer insulating layer 102. Therefore, as illustrated, the inner sidewall of the first opening 110a does not protrude from the portion of the first hard mask pattern 106b.

In the isotropic etching process, the lower interlayer insulating layer 102 and the sacrificial layer 104 should be hardly removed. That is, the isotropic etching process requires that only polysilicon provided as the first preliminary hard mask pattern 106a is etched while almost no silicon oxide and silicon nitride are etched. In addition, when performing the isotropic etching process, the surface of the substrate 100 exposed on the bottom surface of the preliminary opening 110 should be hardly damaged.

To this end, the isotropic etching process uses an etching gas containing a halogen element. For example, the etching gas may be Cl ₂ gas, NF ₃ gas, etc., which may be used alone or in combination.

The plasma is not used in the isotropic etching process. Using plasma in the etching process is not preferable because plasma damage occurs on the exposed substrate surface. In addition, when the plasma is used, since the etching gas has a straightness, sidewall portions of the first preliminary hard mask pattern 106a are hard to be etched.

When the process temperature in the isotropic etching process is 300 ° C. or less, the sidewall of the first preliminary hard mask pattern 106a may be hardly etched. When the process temperature during the etching process is 500 ° C. or more, the exposed surface of the substrate 100 may also be partially etched to damage the surface of the substrate 100. Therefore, the etching process temperature may be performed under 300 to 500 ℃.

Referring to FIG. 4, spacers 112 are formed on sidewalls of the first and second hard mask patterns 106b and 108a. The spacer 112 may be formed by selectively depositing an oxide on an upper sidewall portion of the first opening 110a. For example, the spacer 112 may be formed of medium temperature oxide (MTO), high temperature oxide (HTO), or ALD oxide.

The semiconductor pattern 114 filling the lower portion of the first opening 110a is formed. The semiconductor pattern 114 may be single crystal silicon.

For example, the first opening 110a may be partially formed by performing a selective epitaxial growth (SEG) using a portion of the substrate 100 exposed by the first opening 110a as a seed. The filling semiconductor pattern 114 may be formed. The upper surface of the semiconductor pattern 114 may be positioned on the sidewall of the interlayer insulating layer 102 positioned between the ground select line and the word lines in a subsequent process.

Although the first hard mask pattern 106b is formed of polysilicon, the surface of the first hard mask pattern 106b is not exposed because it is covered by the spacer 112. Therefore, even when the selective epitaxial process is performed, no semiconductor film is grown on the sidewall of the first hard mask pattern 106b.

Referring to FIG. 5, the charge trapping layer 116, the tunnel insulation layer 118, and the first channel layer 120 are sequentially formed on the sidewalls of the first opening 110a and the semiconductor pattern 114. The charge trapping film 116, the tunnel insulating film 118, and the first channel film 120 are conformally formed.

The charge trapping layer 116 may be formed using a nitride or a metal oxide such as silicon nitride.

The tunnel insulating layer 118 may be formed using silicon oxide.

The first channel layer 120 may be formed using polysilicon, single crystal silicon, or amorphous silicon doped with impurities.

By forming the charge trapping layer 116, the tunnel insulating layer 118, and the first channel layer 120, the inner width of the first opening 110a is greatly reduced. However, since the first hard mask pattern 106b does not protrude from the inside of the first opening 110a, the entrance portion of the first opening 110a has a sufficiently wide width.

Referring to FIG. 6, the charge trapping layer 116, the tunnel insulation layer 118, and the first channel layer 120 formed on the bottom surface of the first opening 110a are etched through an anisotropic etching process, thereby trapping charge. The film pattern 116a, the tunnel insulating film pattern 118a, and the first channel film pattern 120a are formed. When the etching process is performed, an upper surface of the semiconductor pattern 114 is exposed on a bottom surface of the first opening 110a.

Since the depth of the first opening 110a is very deep, it may be difficult for the etching gas to flow into the bottom surface of the first opening 110a during the etching process. Therefore, the charge trapping layer 116, the tunnel insulation layer 118, and the first channel layer 120 are not normally etched, so that the top surface of the semiconductor pattern 114 may not be exposed.

However, according to the present exemplary embodiment, since the sidewall portion of the first hard mask pattern 106b does not protrude and the inlet of the first opening 110a is extended to have a wide width, an etching gas is generated during the etching process. It may be easily introduced to the bottom portion of the first opening (110a). Therefore, a defect in which the upper surface of the semiconductor pattern 114 is not exposed in the etching process can be suppressed.

Referring to FIG. 7, a preliminary second channel layer may be formed along the upper surfaces of the first channel layer pattern 120a and the semiconductor pattern 114. The preliminary second channel layer may be formed using polysilicon, single crystal silicon, or amorphous silicon doped with impurities. When the first channel layer pattern 120a and the preliminary second channel layer 122 are formed using amorphous silicon, a process of crystallizing the first channel layer pattern 120a may be additionally performed.

A pre-filling insulating layer may be formed on the preliminary second channel layer to fill the inside of the first opening 110a. The prefilled insulating layer may be formed of silicon oxide.

The planarization process is performed to remove upper surfaces of the prefilled insulating layer and the preliminary second channel layer. Therefore, the second channel layer 120a is formed along the upper surface of the first channel layer pattern 120a and the semiconductor pattern 114. In addition, a buried insulating layer filling the inside of the first opening 110a is formed on the second channel layer 120a.

As shown, in the planarization process, the first and second hard mask patterns 106b and 108a may also be removed.

As described above, since the semiconductor pattern 114 is exposed in the bottom surface of the first opening 110a, the second channel layer 122 is in direct contact with the upper surface of the semiconductor pattern 114. Therefore, the defect that the second channel layer 122 is not in contact with the semiconductor pattern 114 or the resistance between the second channel layer 122 and the semiconductor pattern 114 is increased can be reduced.

Referring to FIG. 8, a portion of an upper portion of the buried insulating layer 124 is removed to form a buried insulating layer pattern 124a. Thereafter, a conductive material is embedded in a portion where the buried insulating layer 124 is removed to form a pad pattern 126.

Subsequently, some regions of the interlayer insulating layers 102 and the sacrificial layers 104 are dry-etched to form second openings (not shown). The second opening may have a trench shape extending in one direction.

The sacrificial layers 104 exposed on the sidewalls of the second openings are removed to form recesses 127 between the interlayer insulating layers 102 of each layer. The charge trapping layer pattern 116a is exposed at each recess 127. The removal process may be performed through a wet etching process.

Referring to FIG. 9, a blocking dielectric layer 128 is formed on the charge trapping layer pattern 116a exposed on the sidewall of the recess 127. The blocking dielectric layer 128 may be conformally formed along the surfaces of the interlayer insulating layer 102, the substrate 100, and the charge trapping layer pattern 116a. The blocking dielectric layer 128 may be formed using silicon oxide or metal oxide. The metal oxide may include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, and the like. According to an embodiment, the blocking dielectric layer 128 may be formed as a multilayer film in which a silicon oxide film and a metal oxide film are stacked.

A gate electrode film is formed to fill the inside of the recess. In addition, a portion of the gate electrode film is etched to form a third opening (not shown) so that the gate electrode film is separated for each layer. Through the etching process, the gate electrodes 130 stacked for each layer are formed. The gate electrode 130 may be provided as a ground select line GSL, a word line, and a string select line SSL, respectively.

An impurity region is formed by implanting impurities into the substrate exposed on the bottom of the third opening. The impurity region may be provided to the common source line CSL. Subsequently, an insulating film pattern (not shown) filling the inside of the third opening is formed.

Thereafter, an upper interlayer insulating layer 132 covering the pad pattern 126 is formed. The bit line contact 134 and the bit line 136 connected to the pad pattern 126 are formed through the upper interlayer insulating layer 132. The bit line 136 may extend perpendicular to the direction in which the gate electrodes of each layer extend.

According to the present exemplary embodiment, since the first hard mask pattern 106b does not protrude into the first opening, the inner width of the inlet portion of the first opening 110a may be extended. As a result, etching gases may be easily introduced into the lower portion of the first opening 110a. Therefore, the second channel layer 122 formed in the first opening 110a and the lower semiconductor pattern 114 are not connected, or the resistance between the second channel layer 122 and the semiconductor pattern 114 is reduced. Problems such as increase can be suppressed.

Example 2

10 and 11 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to Embodiment 2 of the present invention.

The method of manufacturing the vertical memory device of the present embodiment is the same as the method of manufacturing the vertical memory device of Embodiment 1, except that the etching process is further performed.

First, the first opening 110a having the shape in which the first hard mask pattern 106b does not protrude is formed by performing the process described with reference to FIGS. 1 to 3.

Referring to FIG. 10, the third hard mask pattern 108b having the reduced width between the neighboring first openings 110a may be further etched by further etching the upper and sidewall portions of the second hard mask pattern 108a. Form. When the etching process is performed, the inner width of the inlet portion of the first opening 110a is further extended.

For example, the width W6 of the third hard mask pattern 108b provided between the neighboring first openings 110a may be equal to or narrower than the width W5 of the first hard mask pattern 106a. You can do that.

In the process of etching a part of the second hard mask pattern 108a, process conditions must be adjusted so that the lower interlayer insulating layers 102 are not removed. In addition, when performing the etching process, the surface of the substrate 100 exposed on the bottom surface of the preliminary opening 110 should be hardly damaged.

The etching gas used in the etching process may include HF or NH 3. It may be used alone or in combination.

When the process temperature is lower than 50 ° C. in the etching process, the second hard mask pattern may not be etched. When the etching process temperature is higher than 300 ° C., the interlayer insulating layers below may be removed. Therefore, in order to partially etch only the second hard mask pattern 108a, an etching process should be performed at a temperature of 50 to 300 ° C.

The etching process does not use plasma. Using plasma in the etching process is not preferable because plasma damage occurs on the exposed surface of the substrate 100.

Thereafter, the process described with reference to FIGS. 4 to 6 is performed. By performing the above processes, a structure as shown in FIG. 11 is formed.

As shown in FIG. 11, in the vertical memory device of the present exemplary embodiment, the first and third hard mask patterns 106b and 108b positioned between the first openings 110a have a narrow width. 1 The inner width of the inlet portion of the opening 110a is expanded. As a result, etching gases may be easily introduced into the lower portion of the first opening 110a. Therefore, the charge trapping layer 116, the tunnel insulating layer 118, and the first channel layer 120 may be easily etched. Therefore, defects caused by the charge trapping layer 116, the tunnel insulating layer 118, and the first channel layer 120 not being etched normally may be suppressed.

Subsequently, the same process as described with reference to FIGS. 7 to 9 is performed. By performing the above processes, a vertical memory device having the same shape as shown in FIG. 9 is manufactured.

Example 3

12 to 14 are cross-sectional views illustrating a method of manufacturing a vertical memory device according to a third embodiment of the present invention.

The method of manufacturing the vertical memory device of the present embodiment is the same as the method of manufacturing the vertical memory device of Embodiment 1, except that the step of forming the semiconductor pattern inside the first opening is omitted.

First, the first opening 110a having the shape in which the first hard mask pattern does not protrude is formed by performing the process described with reference to FIGS. 1 to 3.

Referring to FIG. 12, the charge trapping layer 140, the tunnel insulation layer 142, and the first channel layer 144 are sequentially formed along the sidewalls of the first opening 110a and the surface of the semiconductor substrate 100. . The charge trapping layer 140, the tunnel insulating layer 142, and the first channel layer 144 are formed conformally.

Referring to FIG. 13, the charge trapping layer 140, the tunnel insulation layer 142, and the first channel layer 144 formed on the bottom surface of the first opening 110a are etched through an anisotropic etching process, thereby trapping charge. The film pattern 140a, the tunnel insulating film pattern 142a, and the first channel film pattern 144a are formed. When the etching process is performed, an upper surface of the semiconductor substrate 100 is exposed on a bottom surface of the first opening 110a.

Subsequently, the same process as described with reference to FIGS. 7 to 9 is performed. By performing the above processes, a vertical memory device as shown in Fig. 14 is manufactured.

According to the said process, the internal width of the inlet part of the 1st opening part 110a can be expanded. Therefore, the second channel layer 146 and the lower semiconductor substrate 100 may not be connected or the resistance between the second channel layer 146 and the semiconductor substrate 100 may be suppressed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

According to embodiments of the present invention, openings having a wide width may be formed in the inlet portion. The above-described processes may be applied to various semiconductor processes including openings as well as fabricating vertical nonvolatile memory devices.

100 substrate 102 interlayer insulating film
104: sacrificial film 106b: first hard mask
108a: second hard mask 110a: first opening
114: semiconductor pattern 116a: charge trapping film pattern
118a: tunnel insulating film pattern 20a: first channel film pattern
122: second channel film 124a: buried insulating film pattern

Claims (10)

Forming a first preliminary hard mask pattern and a second hard mask pattern made of different materials on a semiconductor substrate on which a plurality of sacrificial films and interlayer insulating films are repeatedly stacked;
The sacrificial layers and the interlayer insulating layers are etched using the second hard mask pattern and the first preliminary hard mask pattern as an etch mask to relatively protrude a sidewall portion of the first preliminary hard mask pattern and to form a substrate. Forming a preliminary opening to which the surface is exposed;
Selectively isotropically etching a portion of the first preliminary hard mask pattern sidewall exposed to the preliminary opening to form an opening having an extended inlet portion;
Forming a charge trapping pattern and a tunnel insulation pattern on sidewalls of the opening;
Forming a channel film in the opening to be electrically connected to the semiconductor substrate; And
And forming gate electrodes of memory cells and a selection transistor on side surfaces of the channel film. The method of claim 1, wherein the first preliminary hard mask pattern comprises polysilicon. The method of claim 1, wherein the isotropic etching of a portion of the sidewalls of the first preliminary hard mask pattern is performed by introducing an etching gas containing a halogen element at a temperature of 300 to 500 degrees. Manufacturing method. The method of claim 3, wherein the etching gas comprises a Cl ₂ gas or an NF ₃ gas. The method of claim 1, wherein the cross section of the first hard mask pattern at the opening portion has a trapezoidal shape, and the lower width of the first hard mask pattern is equal to or smaller than the width of the uppermost interlayer insulating layer. A method of manufacturing a vertical memory device to selectively isotropically etch a portion of the first preliminary hard mask pattern sidewall. The method of claim 1, further comprising, after selectively isotropically etching the sidewalls of the first preliminary hard mask pattern, selectively etching the sidewalls of the second hard mask pattern. . The method of claim 6, wherein the etching of a portion of the sidewalls of the second hard mask pattern is performed by introducing an etching gas including HF or NH ₃ at a temperature of 50 to 300 degrees. Manufacturing method. The method of claim 1, further comprising forming a semiconductor pattern filling the lower portion of the opening after forming the opening. The method of claim 1, wherein the channel layer is in direct contact with a sidewall of the opening and an upper surface of the semiconductor pattern. The method of claim 1, wherein the charge trapping pattern and the tunnel insulating film pattern,
Forming a charge trapping film and a tunnel insulating film along sidewalls and bottom surfaces of the openings; And
And etching the charge trapping film and the tunnel insulating film formed on the bottom of the opening.

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