KR20180046833A - Digital frequency measuring apparatus - Google Patents

Abstract

According to an embodiment of the present invention, a digital frequency measuring apparatus includes: a frequency divider for dividing an input signal and providing a divided signal; a periodic counter for counting the period of the divided signal from the frequency divider by using a clock signal and providing a period count value for each period; and a digital filter for amplifying the period count value to an accumulated gain and converting the amplified period count value to a frequency to provide a first digital output value. The digital filter determines the accumulated gain as a predetermined stage degree and a decimator factor. It is possible to increase resolution and a sampling rate.

Description

[0001] DIGITAL FREQUENCY MEASURING APPARATUS [0002]

The present invention relates to a digital frequency measuring apparatus.

Currently, there are various methods of frequency measurement, but it is not easy to satisfy high frequency resolution and fast sampling rate at the same time.

For example, in the case of high frequency resolution in frequency measurement, the higher the frequency resolution, the more precise control and discrimination becomes possible, and the accurate measurement can be performed by applying it to the measurement of impedance and the like. In addition, for fast sampling rates in frequency measurements, more control is possible on the control side.

However, if the sampling rate is increased, the frequency resolution can be deteriorated. On the other hand, if the frequency resolution is increased, the frequency measurement time becomes longer and the sampling rate can be lowered. These points should be considered in the development of frequency measurement devices.

Conventional digital frequency measurement technology measures frequency through a method such as an integrator using a counter.

In the conventional digital frequency measurement technique, there is no restriction on the frequency input and it is possible to use it in a wide frequency band. However, there is a disadvantage that an internal oscillator having a high frequency is required to increase the frequency resolution, Rate is slowed down.

Among the existing digital frequency measurement techniques, the frequency measurement technique using counters is the most commonly used frequency counting method, and the input frequency is counted by the internal main oscillator.

In such conventional frequency measurement techniques, it is difficult to discriminate the frequency when the input frequency is equal to or more than the main oscillator.

For example, when the input frequencies of 10 MHz and 9.8 MHz are counted by a main oscillator of 20 MHz, the counter value becomes 2 in both cases, and it is not distinguished from each other.

In this case, in order to increase the frequency resolution capability, the input frequency is divided into a predetermined value and the frequency is lowered so that the frequency can be discriminated from each other. However, since the counting time becomes long according to frequency division, the sampling rate is slowed down.

As described above, when the conventional frequency measurement method is used, there is a problem that it is difficult to satisfy both the frequency resolution and the sampling rate in the trade off relationship.

Accordingly, a structure for satisfying a wide frequency input range is required to improve both the frequency resolution and the sampling rate.

Korean Patent Publication No. 2013-0060756

An embodiment of the present invention provides a digital frequency measurement device capable of improving a resolution and a sampling rate with a digital frequency measurement technique superior in noise characteristic to an analog method.

According to an embodiment of the present invention, there is provided a frequency divider that divides an input signal and provides a divided signal; A period counter for counting periods of the divided signals from the frequency divider by using a clock signal and providing a period count value for each period; And a digital filter for amplifying the period count value to an accumulated gain, converting the amplified period count value to a frequency to provide a first digital output value, Wherein the digital filter determines the accumulated gain as a predetermined stage order and a decimator factor.

In the solution of this task, one of several concepts described in the following detailed description is provided. The subject matter of the present invention is not intended to identify the core or essential technology of the claimed subject matter, but merely one of the claimed subject matter is described, each of which is specifically set forth in the following detailed description.

According to an embodiment of the present invention, it is possible to apply a high-precision frequency resolution in an input environment in which the frequency of a measurement object signal changes precisely, thereby achieving a high sampling rate while maintaining high accuracy, It can be applied to sensors to improve the precision and speed of control. In addition, it has superior noise characteristics compared with analog method because it adopts digital method.

1 is a diagram illustrating an example of a digital frequency measuring apparatus according to an embodiment of the present invention.
2 is a diagram illustrating another example of a digital frequency measuring apparatus according to an embodiment of the present invention.
3 is an exemplary view of an input signal, a frequency-divided signal, and a clock signal according to an embodiment of the present invention.
4 is a diagram illustrating an example of a digital filter according to an embodiment of the present invention.
5 is another example of a digital filter according to an embodiment of the present invention.
6 is an example of an integrator I according to an embodiment of the present invention.
7 is an exemplary view of a comb C according to an embodiment of the present invention.
8 is a graph showing a digital output value according to an embodiment of the present invention.
9 is a graph showing frequency measurement values according to an embodiment of the present invention.
10 is a diagram illustrating an example of a digital frequency measurement method according to an embodiment of the present invention.

It should be understood that the present invention is not limited to the embodiments described and that various changes may be made without departing from the spirit and scope of the present invention.

In addition, in each embodiment of the present invention, the structure, shape, and numerical values described as an example are merely examples for helping understanding of the technical matters of the present invention, so that the spirit and scope of the present invention are not limited thereto. It should be understood that various changes may be made without departing from the spirit of the invention. The embodiments of the present invention may be combined with one another to form various new embodiments.

In the drawings referred to in the present invention, components having substantially the same configuration and function as those of the present invention will be denoted by the same reference numerals.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

FIG. 1 is a diagram illustrating an example of a digital frequency measuring apparatus according to an embodiment of the present invention, and FIG. 2 is another example of a digital frequency measuring apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a digital frequency measuring apparatus according to an embodiment of the present invention includes a frequency divider 100, a period counter 200, and a digital filter 300.

Referring to FIG. 2, a digital frequency measuring apparatus according to an embodiment of the present invention includes a frequency divider 100, a period counter 200, a digital filter 300, and a frequency calculator 400.

1 and 2, the frequency divider 100 divides an analog input signal Sin having a frequency Fin by a predetermined division value N and outputs a frequency (for example, 10 MHz to 100 MHz) And provide the divided signals (DSin = Sin / N, DFin = Fin / N) to the period counter 200. [

The frequency resolution of the frequency divider 100 may be configured such that the clock frequency Fclk of the clock signal Sclk and the total sampling number Total (Fclk * TSN) of the number of samples (TSN), and thus the resolution can be improved as the frequency (Fclk) of the clock signal is higher or the total number of samples (TSN) is larger.

Here, the clock frequency Fclk may be approximately 50 MHz, and the total sampling number TSN may be determined as a product of the division value N and the cumulative gain GAIN of the digital filter 300, For example, if the division value N is 100 and the cumulative gain GAIN of the digital filter 300 is 256, then the total number of samples TSN may be 25600.

In addition, when the frequency division number N is 100 and the frequency Fin of the analog input signal Sin is 100 MHz, the frequency Fin / N of the divided signal DSin may be 1 MHz.

The period counter 200 counts the periods of the divided signals DSin and DFin from the frequency divider 100 using the clock signal Sclk and outputs the period counts per cycle of the divided signals PCV ) To the digital filter (300).

For example, when the clock frequency Fclk is 50 MHz and the frequency DFin of the divided signal DSin is 1 MHz, the period count value PCV is counted from 0 to 49 (Fclk / DFin-1) . In this case, the period counter 200 may provide a count value PCV for each period of the divided signal DSin (Fin / N) of the frequency divider 100.

The digital filter 300 amplifies the period count value PCV from the period counter 200 to a predetermined cumulative gain GAIN and outputs the amplified period count value APCV as a first digital output value Dout1). Here, the digital filter 300 may be a digital filter such as a Cascade Integrator Comb (CIC).

The digital filter 300 may determine the accumulated gain (GAIN) as a predetermined stage order (SN) and a decimator factor (R). For example, the digital filter 300 may determine the cumulative gain GAIN as the multiplier of the stage order (SN) for the decimator factor R as a multiplier.

In the drawings of the present invention, unnecessary redundant explanations may be omitted for the same reference numerals and components having the same function.

2, the frequency calculator 400 converts the amplified period count value APCV from the digital filter 300 into an output frequency Fout and outputs the output frequency Fout as a second digital output value (Dout2).

The amplified period count value APCV may be converted into an output frequency Fout according to Equation (1).

Where Fclk is the clock frequency of the clock signal Sclk of the period counter 200 and TSN is the product of the division value N and the cumulative gain GAIN of the digital filter 300 N * GAIN), GAIN is the cumulative gain of the digital filter 300, APCV is an amplified period determined by the product of the period count value (PCV) and the cumulative gain (GAIN) (PCV * GAIN) Count value.

Each of the frequency divider 100, the period counter 200, the digital filter 300, and the frequency calculator 400 includes hardware such as a microprocessor and the like, May be implemented as a combination of software programmed to perform.

The hardware may include at least one processing unit and a memory. Herein, the processing unit may include, for example, a signal processor, a microprocessor, a central processing unit (CPU), an application specific integrated circuit (ASIC), and a field programmable gate array And may include at least one.

The memory may include at least one of volatile memory (e.g., RAM) and non-volatile memory (e.g., ROM, flash memory, etc.).

The digital frequency measurement apparatus according to an embodiment of the present invention may be implemented as shown in FIG. 1 to provide the amplified period count value as a first digital output value, or may be implemented as shown in FIG. 1, As a second digital output value. This can be determined according to the values required by the device and application to which it is applied.

3 is an exemplary view of an input signal, a frequency-divided signal, and a clock signal according to an embodiment of the present invention.

3, Sin is an analog input signal that is input to the frequency divider 100 as a frequency measurement object, DSin is a signal divided in the period counter 200, and Sclk is a clock signal used in the period counter 200. [

Referring to FIG. 3, if the input frequency Fin of the input signal Sin is 100 MHz and the divided value N is 100, the divided frequency DFin of the divided signal DSin is 1 MHz . The frequency Fclk of the clock signal Sclk may be 50 MHz which is higher than the divided frequency DFin of the divided signal DSin.

FIG. 4 is a diagram illustrating an example of a digital filter according to an embodiment of the present invention, and FIG. 5 is another example of a digital filter according to an embodiment of the present invention.

Referring to FIG. 4, the digital filter 300 may include a decimator CIC filter 310.

4, the decimator CIC filter 310 amplifies the period count value PCV from the period counter 200 by the accumulated gain determined by the stage order SN and the decimator factor R, And convert the amplified period count value APCV into a frequency to provide the first digital output value Dout1.

Referring to FIG. 5, the digital filter 300 may include a decimator CIC filter 310 and a moving average filter 320.

5, the decimator CIC filter 310 amplifies the period count value PCV from the period counter 200 by the accumulated gain determined by the stage order SN and the decimator factor R, And provide the amplified period count value (APCV).

The moving average filter 320 calculates a moving average value of the amplified period count value from the decimator CIC filter 310 and provides a moving average value of the amplified period count as the first digital output value Dout1 can do.

In one embodiment of the present invention, the first digital output value Dout1 may be the amplified period count value APCV or may be a moving average value for the amplified period count value APCV.

4 and 5, the decimator CIC filter 310 may include an integrating circuit 311, a decimator 312, and a comb circuit 313.

The integration circuit 311 includes a plurality of integrators I cascaded by the number corresponding to the stage order SN and sequentially accumulates period count values PCV from the period counter 200, It is possible to provide a star accumulation value.

The decimator 312 may provide an accumulation value that is sampled one by one for each period corresponding to the decimator factor R from the cumulative values for each cycle from the integrating circuit 311 and downsampled.

The comb circuit 313 includes a plurality of combs C cascaded in the number corresponding to the stage order SN so that the current downsampled accumulation value from the decimator 312 is multiplied by the previous downsampled accumulation value And provide a subtraction cumulative value for a period corresponding to the decimator factor R. [

For example, when the decimator factor R is 4, the decimator CIC digital filter 310 outputs a 4-order 4 decimator CIC (Cascaded Integrator-Comb) ) Digital filter. At this time, the cumulative gain GAIN can be 4 ^ 4 (= 256). Here, the stage order SN and the decimator factor R are not limited thereto.

In this case, the integrating circuit 311 includes four integrators I to sequentially accumulate the period count value PCV from the period counter 200 with a delayed value of four cycles, have.

For example, when the integrating circuit 311 includes four integrators I, the first integrator inputs the count value Vcont for each period of the period counter 200, And the second integrator accumulates the first accumulative value as a sum by adding the sum to the accumulative value. Likewise, the third and fourth integrators accumulate the values by inputting the integrator output of the previous stage.

Since the decimator 312 samples one sample every four periods corresponding to the decimator factor (R = 4) from the cumulative values of the respective cycles from the integration circuit 311, the decimator 312 performs down sampling An accumulation value can be provided.

The comb circuit 313 may include four combs C in which case the current downsampled accumulation value from the decimator 312 is subtracted from the downsampled accumulation value four cycles earlier , So that it is possible to provide cumulative cumulative cumulative values during the last four cycles.

For example, if the degree of the CIC (Cascaded Integrator-Comb) filter is 4, four cascaded combs C may be included. In this case, the first comb comb subtracts the current downsampled cumulative value Cin from the decimator 312 from the downsampled cumulative value Cin 'before four cycles. The second comb comb subtracts the result C1 of the first comb before 4 cycles by inputting the result C1 of the first comb Comb and outputs the result C2 to the third comb Comb ). Similarly, in the third and fourth combs, the subtraction cumulative value (APCV), which is the final output value by subtracting the previous results (Cin ', C1', C2 ', and C3' - C2 '- C3' ".

Here, Cin is the current cumulative value, Cin 'is the cumulative value before four cycles, C1' is the result of the previous first comb, C2 'is the result of the previous second comb, Comb), the C3 may be "Cin-Cin '-C1'-C2'.

For example, in the digital filter 300, as described above, if the period count value PCV is 49 and the accumulated gain GAIN is 256, the amplified period count value APCV is a period count value PCV ) 49 and the cumulative gain (GAIN) 256 to obtain 49 * 256 (= 12544).

The digital filter 300 amplifies the period count value (PCV) for a signal obtained by dividing the input signal to an accumulated gain (GAIN), thereby achieving the same effect as obtaining a large number of sampling values even if a small divided value is used .

As a result, the frequency division value for the desired frequency resolution can be reduced to 1 / GAIN with respect to the conventional counter method by the accumulated gain (GAIN) of the digital filter 300. [ This has the effect of amplifying the output speed of the count value every cycle of the period counter 200 by an accumulated gain (GAIN), and also has the effect of increasing the sampling speed by the cumulative gain.

5, when the moving average filter 320 is a 16 moving average filter, a moving average value is obtained in 16 frequency units from the decimator CIC filter 310, And provides the moving average value to the count value as the first digital output value Dout1.

For example, the 16 moving average filter 320 calculates an average by taking a moving sum of 16 pieces of data with respect to the output value of the fourth-order 4 decimator CIC digital filter 310, It stabilizes the shaking. For example, the moving average filter 320 may be a half band digital filter or the like.

The resolution of the digital frequency measurement device outputting the first digital output may be a product of a clock frequency Fclk and a total sample number TSN and the first digital output Digital output may be converted into a frequency according to Equation (1) and provided as a second digital output.

6 is an example of an integrator I according to an embodiment of the present invention.

4, 5 and 6, the integration circuit 311 may include four integrators I, for example.

The integrator I integrator integrates the current period count value PCV and the previous period count value PCV and amplifies the value by accumulating the period count value PCV, Here, the stage order number (SN) value of four cascaded structures has a four-order effect.

7 is an exemplary view of a comb C according to an embodiment of the present invention.

4, 5 and 7, the comb circuit 313 includes four combs C, for example.

The comb C subtracts the current downsampled accumulation value from the currently input decimator 312 to provide a subtraction cumulative value for the four periods corresponding to the decimator factor R So that an unlimited accumulated value can be prevented from being provided.

For example, the comb C subtracts the cumulative value of four cycles before the cumulative value currently input so that the integrated value has the cumulative value of four cycles.

In the digital filter 300, when the differential delay order M is 1, the cumulative gain GAIN is expressed by (RM) ^ SN (R: decimator factor, M: differential delay) Order, and SN = stage degree). Thus, the digital filter 300 has an amplification effect of 256 times.

FIG. 8 is a graph showing digital output values according to an embodiment of the present invention, and FIG. 9 is a graph showing frequency measurement values according to an embodiment of the present invention.

8, the vertical length is a first digital output value Dout1 which is the amplified period count value, and the horizontal length represents time. The first digital output value Dout1 is calculated according to the frequency variation of the input signal (14.888 Mhz to 14.846 MHz) Dout1).

Referring to the graph of FIG. 8, the first digital output value Dout1, which is the amplified period count value APCV, increases as the frequency of the input signal decreases from 14.888 MHz to 14.846 MHz.

In the graph shown in Fig. 9, the vertical is the second digital output value Dout2, which is the measurement frequency value, and the horizontal is the time, which is obtained by converting the first digital output value Dout1 shown in Fig. Graph.

Referring to the graph of FIG. 9, it can be seen that the second digital output value Dout2, which is a measurement frequency value, decreases as the frequency of the input signal gradually decreases from 14.888 MHz to 14.846 MHz.

Referring to FIG. 8 and FIG. 9, it can be seen that according to the digital frequency measuring apparatus according to the embodiment of the present invention, the frequency gradually decreasing from 14.888 MHz to 14.846 MHz can be accurately counted.

Hereinafter, a digital frequency measurement method will be described with reference to Figs. 1 to 10. Fig. In the present application, the description of the digital frequency measuring device and the description of the digital frequency measuring method can be complementarily applied to each other, unless otherwise specified.

10 is a diagram illustrating an example of a digital frequency measurement method according to an embodiment of the present invention. A digital frequency measurement method according to an embodiment of the present invention will be described with reference to FIG.

In step S100, the frequency divider 100 divides the input signal Sin and provides the divided signal DSin.

In step S200, the cycle of the divided signal DSin from the frequency divider 100 is counted by the period counter 200 using the clock signal Sclk, and the cycle count value PCV for each cycle is Can be provided.

In step S300, the digital filter 300 amplifies the period count value PCV to an accumulated gain GAIN, and the amplified period count value may be provided as a first digital output value Dout1.

In step S400, the frequency calculator 400 converts the amplified period count value into a frequency according to Equation (1) to provide a second digital output value Dout2.

The digital frequency measurement device according to an embodiment of the present invention as described above can be applied to a camera module mounted on a mobile device such as a mobile phone, and in this case, the frequency corresponding to the movement of the lens can be measured. In this case, It can be applied to a detection sensor to improve the precision and speed of control.

100: frequency divider
200: Cycle counter
300: Digital filter
310; Decimator CIC filter
311: Integrating circuit
312: decimator
313: Com circuit
320; Moving average filter
400: Frequency calculator
Sin: Input signal
DSin: Diverted signal
Sclk: clock signal
PCV; Period count value
GAIN; Cumulative gain
Dout1; The first digital output value
Dout2: second digital output value

Claims (14)

A frequency divider that divides the input signal to provide a divided signal;
A period counter for counting periods of the divided signals from the frequency divider by using a clock signal and providing a period count value for each period; And
A digital filter for amplifying the period count value to an accumulated gain and providing the amplified period count value as a first digital output value; Lt; / RTI >
Wherein the digital filter determines the cumulative gain as a predetermined stage degree and a decimator factor
Digital frequency measuring device.
The digital filter according to claim 1, wherein the digital filter
And determines the accumulated gain as the multiplier of the stage for the decimator factor as a multiplier.
The digital filter according to claim 1, wherein the digital filter
A decimator CIC filter that amplifies the period count value from the period counter by the accumulated gain determined by the stage order and the decimator factor, converts the amplified period count value into a frequency and provides the frequency as the first digital output value;
The digital frequency measurement device comprising:
4. The apparatus of claim 3, wherein the decimator CIC filter comprises:
An integrating circuit including a plurality of integrators cascaded by the number corresponding to the stage order, sequentially accumulating period count values from the period counter to provide cumulative values for each period;
A decimator for sampling one of the accumulation values for each cycle from the integration circuit for each period corresponding to the decimator factor and providing a downsampled accumulation value; And
And a subtracter for subtracting the current downsampled accumulative value from the decimator from the decimated cumulative value for the period corresponding to the decimator factor by including a plurality of combs cascaded by the number corresponding to the stage order, Providing comb circuits;
The digital frequency measurement device comprising:
The digital filter according to claim 1, wherein the digital filter
A decimator CIC filter for amplifying a period count value from the period counter by the accumulated gain determined by the stage order and a decimator factor and for converting the amplified period count value into a frequency to provide a frequency value; And
A moving average filter for obtaining a moving average value of the amplified period count value from the decimator CIC filter and providing a moving average value for the amplified period count as the first digital output value;
The digital frequency measurement device comprising:
6. The apparatus of claim 5, wherein the decimator CIC filter comprises:
An integrating circuit including a plurality of integrators cascaded by the number corresponding to the stage order, sequentially accumulating period count values from the period counter to provide cumulative values for each period;
A decimator for sampling one of the accumulation values for each cycle from the integration circuit for each period corresponding to the decimator factor and providing a downsampled accumulation value; And
A comb circuit for subtracting a current downsampled accumulation value from the decimator to provide a subtraction accumulation value for a period corresponding to the decimator factor;
The digital frequency measurement device comprising:
6. The apparatus of claim 5, wherein the moving average filter
16 moving average filter,
Wherein the 16 moving average filter obtains a moving average value of the frequency value from the decimator CIC filter in units of 16 and provides a moving average value of the amplified period count value as the first digital output value.
A frequency divider that divides the input signal to provide a divided signal;
A period counter for counting periods of the divided signals from the frequency divider by using a clock signal and providing a period count value for each period;
A digital filter for amplifying the period count value to an accumulated gain and providing the amplified period count value as a first digital output value; And
A frequency calculator for converting the amplified period count value into an output frequency and providing the output frequency as a second digital output value; Lt; / RTI >
Wherein the digital filter determines the cumulative gain as a predetermined stage degree and a decimator factor
Digital frequency measuring device.
The digital filter according to claim 8, wherein the digital filter
And determines the accumulated gain as the multiplier of the stage for the decimator factor as a multiplier.
The digital filter according to claim 8, wherein the digital filter
A decimator CIC filter that amplifies the period count value from the period counter by the accumulated gain determined by the stage order and the decimator factor, converts the amplified period count value into a frequency and provides the frequency as the first digital output value;
The digital frequency measurement device comprising:
11. The apparatus of claim 10, wherein the decimator CIC filter comprises:
An integrating circuit including a plurality of integrators cascaded by the number corresponding to the stage order, sequentially accumulating period count values from the period counter to provide cumulative values for each period;
A decimator for sampling one of the accumulation values for each cycle from the integration circuit for each period corresponding to the decimator factor and providing a downsampled accumulation value; And
And a subtracter for subtracting the current downsampled accumulative value from the decimator from the decimated cumulative value for the period corresponding to the decimator factor by including a plurality of combs cascaded by the number corresponding to the stage order, Providing comb circuits;
The digital frequency measurement device comprising:
The digital filter according to claim 8, wherein the digital filter
Further comprising a moving average filter,
Wherein the decimator CIC filter amplifies the period count value from the period counter with the accumulated gain determined by the stage order and the decimator factor, converts the amplified period count value into a frequency to provide a frequency value,
Wherein the moving average filter obtains a moving average value for the amplified period count value from the decimator CIC filter and provides a moving average value for the amplified period count as the first digital output value
Digital frequency measuring device.
13. The apparatus of claim 12, wherein the moving average filter
16 moving average filter,
Wherein the 16 moving average filter obtains a moving average value of the frequency value from the decimator CIC filter in units of 16 and provides a moving average value of the amplified period count value as the first digital output value.
9. The apparatus of claim 8,
The amplified period count value is expressed by the following equation

Wherein Fout is an output frequency, Fclk is a clock frequency of the clock signal of the period counter, TSN is a total sampling number determined by a product of the division value N and GAIN, and GAIN Is the cumulative gain of the digital filter, and APCV is an amplified period count value determined by multiplying the period count value PCV and GAIN.

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