KR20180039507A - Display device and its driving method - Google Patents

Abstract

One embodiment of the present invention provides a display device, which detects a case in which an excessive voltage compared with a rated voltage is input to a timing controller in a test, and a driving method thereof. According to one embodiment of the present invention, the timing controller has a core input voltage and a driving input voltage, received from a power management integrated circuit, wherein both of the core input voltage and the driving input voltage are set values. If a reset signal received from the power management integrated circuit is a high logic level, a first reset signal among data driving unit control signals is generated as a high logic level. Since the present invention can detect abnormality of an input voltage input in the timing controller in a test step, problems can be detected before a product is delivered to a customer. That is, the present invention can solve problems that quality problems are detected after a product is delivered to a customer, or that deterioration happens because an abnormal voltage is continuously supplied to the timing controller, and then the problem is recognized and fixed.

Description

DISPLAY DEVICE AND ITS DRIVING METHOD [0002]

One example of the present invention relates to a display device and a driving method thereof.

BACKGROUND ART [0002] A lot of related technologies are being developed in the field of display devices for displaying visual information as images or images in an information society. The display device includes a display panel having a display area provided with pixels for displaying an image and a non-display area disposed at a periphery of the display area and not displaying an image, a gate driver for inputting a gate signal to the pixels, A timing controller for inputting a signal for controlling a plurality of source drive ICs (hereinafter referred to as " IC "), a gate driver, and a plurality of source drive ICs to be input; And a power management integrated circuit (PMIC) that generates various kinds of voltages for driving the timing controller using input power.

The timing controller receives the core input voltage Vcore and the drive input voltage Vcc from the power management integrated circuit. There are various types of core input voltage depending on the input terminal. It has the rated voltage level set at 1.0V, 1.1V, 1.2V, 1.8V, and the driving input voltage is two rated voltage set at 1.8V and 3.3V Level.

As the timing controller uses various input voltages, an excessive voltage may be input to the timing controller due to internal or external factors in the power management control circuit, human errors, or the like. However, since the timing controller is an internal semiconductor integrated circuit or an element, even if there is an error in the input voltage, it can not be immediately recognized as an image. As the display device is driven for a long period of time (for example, 1,500 hours or more), abnormal driving can be confirmed as an image only after the deterioration of the timing controller proceeds. Accordingly, even when a voltage exceeding the rated voltage is input to the timing controller, there is a problem that the voltage can not be detected during the inspection and can be confirmed only after the display device product is presented to the customer.

One example of the present invention is to provide a display apparatus and a method of driving the same that can detect when a voltage of an excessive magnitude relative to a rated voltage is input to a timing controller.

A display device according to an example of the present invention includes a display panel for displaying an image, a plurality of source drive ICs for supplying data voltages to the display panel, a timing controller for supplying data driver control signals to the plurality of source drive ICs, And a power management integrated circuit that receives input power from the external set and generates a core input voltage, a drive input voltage, and a reset signal for driving the timing controller using the input power.

A method of driving a display device according to an embodiment of the present invention includes a timing controller supplying data drive control signals to a plurality of source drive ICs, supplying a plurality of source drive ICs with a data voltage to a display panel, And displaying the image on the panel.

The timing controller according to an exemplary embodiment of the present invention may be configured such that when the core input voltage and the drive input voltage received from the power management integrated circuit are both set values and the reset signal received from the power management integrated circuit is a high logic level, To a high logic level.

A display device and a driving method thereof according to an exemplary embodiment of the present invention can directly detect a wrong input voltage among input voltages in a timing controller. Particularly, since the first reset signal is generated by the logic gate in the timing controller and is included in the data driver control signal, when the information is displayed on the display panel, the presence or absence of the voltage input to the timing controller It can be easily detected.

As a result, it is possible to detect an abnormality in the input voltage inputted to the timing controller in the inspection step, so that the customer can find the problem before the product is delivered. As a result, it is possible to solve the problem of recognizing a problem in quality after the product is delivered to the customer, or recognizing and repairing the problem only after the abnormal voltage is continuously supplied to the timing controller and deterioration occurs.

1 is a plan view of a liquid crystal display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram showing a pixel in a case where the display device according to an exemplary embodiment of the present invention is a liquid crystal display device in detail.
3 is a block diagram of a display device according to an exemplary embodiment of the present invention.
4 is a circuit diagram showing a pixel in detail when the display device according to an exemplary embodiment of the present invention is an organic light emitting display device.
5 is a block diagram illustrating input and output signals between a source drive IC, a timing controller, a power management integrated circuit, and an external set in accordance with one example of the present invention.
6 is a detailed block diagram of a timing controller according to an exemplary embodiment of the present invention.
7 is a block diagram illustrating input and output signals of a logic gate in accordance with one example of the present invention.
8 is a table showing the logic levels of the input and output signals of a logic gate according to an example of the present invention.
9 is a flowchart of a method of driving a timing controller in a display device according to an example of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display device according to an exemplary embodiment of the present invention may be implemented in various ways such as a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoresis display have.

1 is a plan view of a liquid crystal display device according to an exemplary embodiment of the present invention. 1, the first horizontal axis direction X is a direction parallel to the gate lines, the second horizontal axis direction Y is a direction parallel to the data lines, and the vertical axis direction Z is a direction Thickness (or height) direction. A display device according to an exemplary embodiment of the present invention includes a display panel 110, a gate driver 120, a source driver IC 131, a flexible circuit film 140, a control printed circuit board (C-PCB) (150), and a timing controller (Tcon) (160).

The display panel 110 includes a thin film transistor substrate 111, a counter substrate 112 and a liquid crystal layer interposed between the thin film transistor substrate 111 and the counter substrate 112. The thin film transistor substrate 111 includes a plurality of gate lines and a plurality of data lines arranged to cross each other.

The plurality of gate lines extend along the first horizontal axis direction X of the thin film transistor substrate 111 and extend at regular intervals along the second horizontal axis direction Y crossing the first horizontal axis direction X . The plurality of data lines intersect the plurality of gate lines, extend long along the second horizontal axis direction Y, and are spaced apart at regular intervals along the first horizontal axis direction X. [

2 is a circuit diagram showing a pixel P in detail when the display device according to an exemplary embodiment of the present invention is a liquid crystal display device. In FIG. 2, only the data line DLj and the pixel P connected to the j-th common line Lj are shown for j (j is a positive integer satisfying 1? J? Q) for convenience of explanation.

The pixels P are arranged at the intersections of the data lines DLj and the gate lines GLk, respectively. Each of the pixels P is connected to the data line DLj and the gate line GLk. Each of the pixels P includes a thin film transistor T, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and a storage capacitor Cst. The thin film transistor T is turned on by the gate signal of the gate line GLk. The turn-on thin film transistor T supplies the data voltage of the data line DLj to the pixel electrode PE. The common electrodes CE are connected to the common line Lj and are supplied with a common voltage from the common line Lj.

Each of the pixels P drives the liquid crystal of the liquid crystal layer LC by an electric field generated by a potential difference between a data voltage supplied to the pixel electrode PE and a common voltage supplied to the common electrode CE. The arrangement of liquid crystals changes according to the presence or absence of an electric field and the intensity of an electric field, and the amount of light transmitted from the backlight unit can be adjusted. As a result, the pixels P can display an image having a gradation corresponding to the data voltage. The storage capacitor Cst is disposed between the pixel electrode PE and the common electrode CE. The storage capacitor Cst maintains a constant potential difference between the pixel electrode PE and the common electrode CE.

The common electrode CE is disposed on the counter substrate 112 in a vertical field driving system such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The common electrode is disposed on the thin film transistor substrate 111 together with the pixel electrode PE in a horizontal electric field driving method such as an IPS (In Plane Switching) mode or an FFS (Fringe Field Switching) mode. The liquid crystal mode of the display panel 110 may be implemented in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above.

The thin film transistor substrate 111 includes a display region DA and a non-display region. In the display area DA, the gate lines and the data lines are arranged to cross each other. The intersection regions of the gate lines and the data lines define a pixel region, respectively.

The non-display area is disposed at the outer periphery of the display area DA. More specifically, the non-display region means the remaining region of the thin film transistor substrate 111 excluding the display region DA. For example, the non-display region may be the upper, lower, left, and right edge portions of the thin film transistor substrate 111. The counter substrate 112 includes a black matrix, a color filter, and the like. The color filters may be disposed in openings that are not covered by the black matrix. When the display panel 110 has a color filter on TFT (COT) structure, the black matrix and the color filters may be disposed on the thin film transistor substrate 111.

An alignment film may be provided on each of the thin film transistor substrate 111 and the counter substrate 112 to attach a polarizing plate and set a pre-tilt angle of the liquid crystal. A spacer may be provided between the thin film transistor substrate 111 and the counter substrate 112 to maintain a cell gap of the liquid crystal layer.

In the case where the display device according to an exemplary embodiment of the present invention is an organic light emitting display, the counter substrate 112 is bonded to the TFT substrate 111 so as to serve as a sealing substrate for preventing penetration of oxygen or foreign substances from the outside.

2 is a block diagram of a display device according to an exemplary embodiment of the present invention. The display panel 110 is provided with gate lines GL1 to GLp, p is a positive integer of 2 or more, data lines DL1 to DLq, q is a positive integer of 2 or more, and sensing lines L1 to Lq do. The data lines DL1 to DLq and the sensing lines L1 to Lq may intersect the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines L1 to Lq may be parallel to each other.

Each of the pixels P may be connected to any one of the gate lines GL1 to GLp and one of the data lines DL1 to DLq and the sensing lines L1 to Lq.

Each of the pixels P may include an organic light emitting diode (OLED) as shown in FIG. 4 and a pixel driver PD for supplying a current to the organic light emitting diode OLED. In FIG. 4, for convenience of explanation, the data line DLj, j-th sensing line Lj, k (k is 1? K? P) Only the pixels P connected to the scan line GLk and the kth sensing signal line SSk are shown. The pixel P includes an organic light emitting diode OLED and a pixel driver PD for supplying current to the organic light emitting diode OLED and the jth sensing line Lj.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT and the cathode electrode can be connected to the low potential voltage line ELVSL to which a low potential voltage lower than the high potential voltage is supplied.

The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The pixel driver PD includes a driving transistor DT, a first transistor ST1 controlled by a scan signal of the scan line GLk, and a second transistor ST1 controlled by a sensing signal of the sensing signal line SSk. A transistor ST2, and a capacitor C as shown in Fig. The pixel driving part PD is supplied with the data voltage VDATA of the data line DLj connected to the pixel P when a scan signal is supplied from the scan line GLk connected to the pixel P in the display mode, And supplies the current of the driving transistor DT to the organic light emitting diode OLED according to the data voltage VDATA. The pixel driving part PD is supplied with the sensing voltage of the data line DLj connected to the pixel P when a scan signal is supplied from the scan line Sk connected to the pixel P in the sensing mode, DT to the sensing line Lj connected to the pixel P.

The driving transistor DT is provided between the high potential voltage line ELVDDL and the organic light emitting diode OLED. The driving transistor DT adjusts the current flowing from the high potential voltage line ELVDDL to the organic light emitting diode OLED according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1, the source electrode thereof is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode thereof is connected to the high potential And may be connected to the voltage line ELVDDL.

The first transistor ST1 is turned on by the kth scan signal of the kth scan line Sk to supply the voltage of the jth data line DLj to the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 is connected to the kth scan line GLk, the first electrode thereof is connected to the gate electrode of the driving transistor DT, and the second electrode thereof is connected to the jth data line DLj . The first transistor ST1 may be referred to as a scan transistor.

The second transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SSk to connect the jth sensing line Lj to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the kth sensing signal line SSk and the first electrode thereof is connected to the jth sensing line Lj and the second electrode of the second transistor ST2 is connected to the source electrode of the driving transistor DT. Can be connected. The second transistor ST2 may be referred to as a sensing transistor.

The capacitor C is provided between the gate electrode and the source electrode of the driving transistor DT. The capacitor C stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

4, the driving transistor DT and the first and second transistors ST1 and ST2 are formed of an N-type MOSFET (metal oxide semiconductor field effect transistor). However, it should be noted that the driving transistor DT and the first and second transistors ST1 and ST2 are not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. It should be noted that the first electrode may be a source electrode and the second electrode may be a drain electrode, but the present invention is not limited thereto. That is, the first electrode may be a drain electrode and the second electrode may be a source electrode.

In the display mode, when the scan signal is supplied to the kth scan line GLk, the data voltage VDATA of the jth data line DLj is supplied to the gate electrode of the drive transistor DT, The initializing voltage of the j-th sensing line Lj is supplied to the source electrode of the driving transistor DT. The current of the driving transistor DT flowing in accordance with the voltage difference between the voltage of the gate electrode of the driving transistor DT and the voltage of the source electrode is supplied to the organic light emitting diode OLED in the display mode, Emits light in accordance with the current of the driving transistor DT. At this time, since the data voltage VDATA is a voltage compensated for the threshold voltage and electron mobility of the driving transistor DT, the current of the driving transistor DT does not depend on the threshold voltage and the electron mobility of the driving transistor DT .

In the sensing mode, when a scan signal is supplied to the kth scan line GLk, a sensing voltage of the jth data line is supplied to the gate electrode of the driving transistor DT, and a sensing signal is applied to the kth sensing signal line SSk The initializing voltage of the jth sensing line Lj is supplied to the source electrode of the driving transistor DT. Further, when the sensing signal is supplied to the kth sensing signal line SSk, the second transistor ST2 is turned on to drive the driving transistor DT in accordance with the voltage difference between the voltage of the gate electrode of the driving transistor DT and the voltage of the source electrode So that the current of the transistor DT flows to the jth sensing line Lj.

The gate driver 120 generates a gate signal according to the gate driver control signal GCS input from the timing controller 160 and supplies the gate signal to the gate line. The gate driver 120 according to an embodiment of the present invention is provided with a gate in panel (GIP) circuit in a non-display region of the TFT substrate 111. The GIP circuit is embedded in the non-display region of the thin film transistor substrate 111 together with the transistor of the pixel. For example, the circuit portion 120 formed of the GIP circuit may be provided on one side or the other non-display region of the display region DA, or on both non-display regions of the display region DA, but not limited thereto , And is provided in an arbitrary non-display area capable of supplying a gate signal to the gate line.

The data driver 130 generates data voltages according to the data driver control signal DCS input from the timing controller 160 and supplies the data voltages to the data lines. The data driver 130 may be implemented as a plurality of source driver integrated circuits (ICs) 130. Each of the plurality of source drive ICs 131 is mounted on the flexible circuit film 140 and receives the digital video data DATA and the data driver control signal DCS supplied from the timing controller 160, Converts the digital video data (DATA) into an analog data voltage according to a signal (DCS) and supplies it to the data lines. In the case where the source drive IC 131 is fabricated from a drive chip, each of the source drive ICs 131 is connected to a flexible circuit film (COF) by a chip on film (COF) or a chip on plastic 140, respectively. The chip-on film may include a base film such as polyimide and a plurality of conductive lead wires provided on the base film.

Each of the plurality of flexible circuit films 140 may be attached to the thin film transistor substrate 111 and the control printed circuit board 150. Specifically, each of the plurality of flexible circuit films 140 is attached to a pad portion provided on the thin film transistor substrate 111. At this time, each of the plurality of flexible circuit films 140 is attached to the pads using an anisotropic conductive film (ACF). As a result, the source drive ICs 131 can be connected to the data lines DL1 to DLq. Each of the plurality of flexible circuit films 140 supplies a data voltage supplied from the source drive ICs 131 to the data line through the pad portion. At least one of the plurality of flexible circuit films 140 supplies the gate driver control signal GCS supplied from the timing controller 160 to the gate driver 120. [ Each of the flexible circuit films 140 may be bent or bent.

The control printed circuit board 150 is connected to a plurality of flexible circuit films 140. The control printed circuit board 150 supports a plurality of circuits implemented with driving chips. For example, a timing controller 160 may be mounted on the control printed circuit board 150. [ The control printed circuit board 150 may be a printed circuit board (PCB) or a flexible printed circuit board (FPCB).

The timing controller 160 is mounted on the control printed circuit board 150 and receives digital video data and timing synchronization signals (Timing Signals) from an external system board. Here, the timing synchronization signals include a vertical synchronization signal (Vsync) defining one frame period, a horizontal synchronization signal (Hsync) defining one horizontal period, a data enable signal (Data Enable Signal, DE), and a dot clock (Dot Clock, DCLK) which is a clock signal having a predetermined period.

The timing controller 160 generates a gate driver control signal GCS for controlling the operation timing of the gate driver 120 and a data driver control signal DCS for controlling the source driver ICs 131 based on the timing synchronization signals. . The timing controller 160 supplies the gate driver control signal GCS to the gate driver 120 and the data driver control signal DCS to the plurality of source driver ICs 131.

5 is a block diagram of an exemplary embodiment of an input and output signal between a source drive IC 131, a timing controller 160, a power management integrated circuit (PMIC) 200, and an external set 300, Fig. In FIG. 5, only one source drive IC 131 of a plurality of source drive ICs 131 is shown.

The source drive IC 131 supplies the data voltages to the pixels P provided in the display panel 110 for displaying an image as described above. The source drive IC 131 can supply the data voltages corresponding to the respective pixels P based on the data driver control signal DCS input from the timing controller 160. [

The data driver control signal DCS may be transmitted using an EPI packet protocol. The EPI packet protocol is a communication protocol used when the timing controller 160 transmits digital video data (DATA) to the source drive IC 131. The EPI packet protocol is used in the first to third steps (Phase 1 to 3) depending on whether the EPI packet protocol is used in an active area which is an area for displaying an image on a display panel, in a non- 1 to 3).

The source drive IC 131 receives the timing controller 160 and the EPI voltage (Vepi) for performing the EPI packet protocol from the power management integrated circuit 200. The source drive IC 131 also includes a source drive power supply voltage VDD as a reference voltage for generating a data voltage and a half source drive power supply voltage HVDD having a logic level of half the source drive power supply voltage VDD. Is supplied from the power management integrated circuit (200).

The timing controller 160 supplies the data driver control signals DCS to the plurality of source drive ICs 131 as described above. The data driver control signal DCS is generated by using the digital video data DATA and the timing synchronization signal TS received from the external set 300 having the system board.

The timing controller 160 receives the core input voltage Vcore from the power management integrated circuit 200. The core input voltage Vcore is a voltage for generating various signals of the driving chip on which the timing controller 160 is mounted. The voltage core input voltage Vcore varies according to the input terminal of the driving chip on which the timing controller 160 is mounted, and has a rated voltage level set at 1.0V, 1.1V, 1.2V, and 1.8V.

The timing controller 160 is supplied with the drive input voltage Vcc from the power management integrated circuit 200. The driving input voltage Vcc serves as a reference power source for driving the timing controller 160. [ The drive input voltage (Vcc) has two nominal voltage levels set at 1.8V and 3.3V.

The timing controller 160 receives a reset signal RESET from the power management integrated circuit 200. The reset signal RESET serves to determine whether the timing controller 160 outputs or does not output the data driver control signal DCS. The timing controller 160 does not output the data driver control signal DCS to the source driver IC 131 when the reset signal RESET of the low logic level is supplied. The timing controller 160 outputs the data driver control signal DCS to the source driver IC 131 when receiving a reset signal RESET of a high logic level.

The power management integrated circuit 200 receives the input power Vin from the external set 300. The input power supply (Vin) is a direct current (DC) voltage having a magnitude of 12V and adjusted from an externally supplied power supply voltage to a rated size that can be used in a display device.

The power management integrated circuit 200 generates a core input voltage Vcore, a drive input voltage Vcc, and a reset signal RESET for driving the timing controller 160 using the input power supply Vin. The power management integrated circuit 200 supplies the generated core input voltage Vcore, the drive input voltage Vcc, and the reset signal RESET to the timing controller 160. [

The power management integrated circuit 200 uses the input power supply Vin to control the source drive power supply voltage VDD which is a reference voltage for generating the data voltage by the source drive IC 131 and the half of the source drive power supply voltage VDD Source drive power supply voltage (HVDD) having a logic level of magnitude that is the same as the magnitude of the source drive voltage. The power management integrated circuit 200 also generates the EPI voltage Vepi for performing the EPI packet protocol between the source drive IC 131 and the timing controller 160. [ The power management integrated circuit 200 supplies the source drive power supply voltage VDD, the half source drive power supply voltage HVDD and the EPI voltage Vepi to the source drive IC 131.

The external set 300 includes a system board. The external set 300 supplies digital video data (DATA) and timing synchronization signals (TS) to the timing controller 160. The external set 300 supplies the input power supply Vin to the power management integrated circuit 200.

The most important feature of the present invention is that the timing controller 160 stores the set values of the core input voltage Vcore and the drive input voltage Vcc. Accordingly, the timing controller 160 can determine whether the core input voltage Vcore and the drive input voltage Vcc input from the power management integrated circuit 200 are set values. The timing controller 160 receives a reset signal RESET input from the power management integrated circuit 200 and outputs the reset signal RESET to the power management integrated circuit 200. [ The first reset signal RESET_1 of the data driver control signals DCS is set to a high logic level (High, 1).

The first reset signal RESET_1 is a signal included in the data driver control signal DCS. The first reset signal RESET_1 is supplied to the timing controller 160 and the source drive IC 131 to determine whether all of the input voltages of the timing controller 160 are supplied with the set values, Al is a signal newly introduced in the present invention.

There has been no method of detecting abnormality until abnormality occurs on the display panel 110 even when the magnitude of the voltage input to the timing controller 160 differs from that of the rated voltage. This is because there is no signal that the logic level varies depending on whether all of the input voltages of the timing controller 160 have been supplied with the set values or the input voltage with the error among the input voltages such as the first reset signal RESET_1 to be.

The timing controller 160 according to an exemplary embodiment of the present invention is configured such that the core input voltage Vcore and the drive input voltage Vcc are both set values and the reset signal RESET input from the power management integrated circuit 200 has a high logic Level, the first reset signal RESET_1 of the high logic level (High, 1) is generated. Accordingly, the present invention can detect whether all of the input voltages of the timing controller 160 are supplied with a predetermined value or whether there is an input voltage with an error among the input voltages. In addition, the present invention can start the driving of the timing controller 160 after confirming that all the input voltages of the timing controller 160 are supplied at a set value, thereby enabling the stable display device to be driven.

When the core input voltage Vcore or the driving input voltage Vcc includes an error, the timing controller 160 according to an exemplary embodiment of the present invention sets the first reset signal RESET_1 to a low logic level (Low, 0). When the core input voltage Vcore and the driving input voltage Vcc input from the power management integrated circuit 200 are higher or lower than a predetermined voltage level by a predetermined voltage level or higher The voltage difference is 0.5 V or more), it is judged as a value including an error.

The timing controller 160 generates the first reset signal RESET_1 as a low logic level (Low, 0) when the core input voltage Vcore and the drive input voltage Vcc are abnormally higher or lower than the set value. When the first reset signal RESET_1 is at a low logic level (Low, 0), the timing controller 160 stops supplying the drive voltage to the source drive IC 131. [ Thus, it is possible to prevent breakage due to deterioration of the abnormal timing controller 160.

Preferably, the timing controller 160 sets the first reset signal RESET_1 to a low logic level (Low, 0) when the core input voltage Vcore and the drive input voltage Vcc are abnormally higher or lower than the set value, , It can be indicated that the core input voltage Vcore and the driving input voltage Vcc are abnormally higher or lower than a set value on the display panel 110. [ Accordingly, when the voltage inputted to the timing controller 160 is different from the rated voltage in the process of checking before the display device comes out to the product, it is possible to easily detect an abnormality and solve the problem in advance. Further, even if a failure occurs after the display device comes out to the product, it is known that the voltage input to the timing controller 160 before the deterioration on the display panel 110 due to the abnormal input voltage is different from the rated voltage And the problem can be recognized before deterioration occurs.

The timing controller 160 according to an exemplary embodiment of the present invention generates the first reset signal RESET_1 to a low logic level when the reset signal RESET is a low logic level. When the reset signal RESET is at a low logic level, the first reset signal RESET_1 is generated to a low logic level even when both the core input voltage Vcore and the drive input voltage Vcc are normal.

Accordingly, the first reset signal RESET_1 can be adjusted by the presence or absence of the input voltages inputted to the timing controller 160, but the first reset signal RESET_1 can be adjusted by using an independent signal. Accordingly, the first reset signal RESET_1 can be set to a low logic level, and the timing of driving the timing controller 160 can be artificially adjusted.

In addition, the timing controller 160 according to an exemplary embodiment of the present invention maintains a screen-idle state in which the display panel 110 does not display an image when the reset signal RESET is at a low logic level. That is, the reset signal RESET can be set to a low logic level to control whether the display panel 110 displays an image.

Maintaining the screen-idle state using the reset signal (RESET) can be applied as an alternative to cope with an unexpected situation. For example, if an error occurs in the set value information about the input voltages stored in the timing controller 160, the timing controller 160 determines whether the input voltage is erroneous based on the erroneous set value. Therefore, the timing controller 160 is driven for a long time with a wrong input voltage. In this case, the timing controller 160 can be forced to maintain the screen-idle state by using the reset signal RESET.

6 is a detailed block diagram of a timing controller 160 according to an exemplary embodiment of the present invention. The timing controller 160 according to an exemplary embodiment of the present invention includes a core input voltage determination unit 161, a driving input voltage determination unit 162, and a logic gate 163.

The core input voltage determination unit 161 stores information on the rated core voltage magnitude which is a set value of the core input voltage Vcore. The core input voltage determination unit 161 determines whether the core input voltage Vcore supplied from the power management integrated circuit 200 is a set value. The core input voltage determination unit 161 generates the first core voltage Vcore_1 based on the determination result.

The drive input voltage determination unit 162 stores information about a rated drive voltage magnitude that is a set value of the drive input voltage Vcc. The drive input voltage determination unit 162 determines whether the drive input voltage Vcc supplied from the power management integrated circuit 200 is a set value. The drive input voltage determination unit 162 generates the first drive voltage Vcc_1 based on the determination result.

The logic gate 163 receives the first core voltage Vcore_ 1 from the core input voltage determination unit 161. The logic gate 163 receives the first driving voltage Vcc_ 1 from the driving input voltage determining unit 162. The logic gate 163 supplies the reset signal RESET from the power management integrated circuit 200. The logic gate 163 generates and outputs the first reset signal RESET_1 based on the values of the first core voltage Vcore_1, the first driving voltage Vcc_1, and the reset signal RESET.

The timing controller 160 of the present invention may store information on the rated core voltage magnitude and the rated driving voltage magnitude and compare the input core voltage Vcore and the driving input voltage Vcc. The timing controller 160 of the present invention also uses the logic gate 163 to perform a first reset operation based on the values of the first core voltage Vcore_1, the first drive voltage Vcc_1, and the reset signal RESET, Which can generate and output a signal RESET_1 by adding a simple logic circuit and notifying the abnormality of the core input voltage Vcore and the drive input voltage Vcc input to the timing controller 160, (RESET_1).

More specifically, the core input voltage determination unit 161 generates the first core voltage Vcore_1 of the high logic level when the core input voltage Vcore inputted from the power management integrated circuit 200 is a set value. The core input voltage determination unit 161 generates the first core voltage Vcore_1 of the low logic level when the core input voltage Vcore input from the power management integrated circuit 200 includes a value of error.

The driving input voltage determining unit 162 generates the first driving voltage Vcc_1 of the high logic level when the driving input voltage Vcc input from the power management integrated circuit 200 is a set value. The drive input voltage determination unit 162 generates the first drive voltage Vcc_ 1 of the low logic level when the drive input voltage Vcc input from the power management integrated circuit 200 includes a value including an error.

In addition, the logic gate 163 is a three-input one-output AND gate. 7 is a block diagram illustrating input and output signals of a logic gate 163 in accordance with one example of the present invention.

7, when the logic gate 163 according to an exemplary embodiment of the present invention is a 3-input 1-output AND gate, the first core voltage Vcore_1, the first driving voltage Vcc_1, and the reset signal RESET, Is input to the input terminals of the logic gate 163, and the first reset signal RESET_1 is output from the output terminal of the AND gate.

8 is a table showing the logic levels of the input and output signals of logic gate 163 in accordance with an example of the present invention. In the case of a 3-input 1-output AND gate, it has an output value of a high logic level (High, 1) only when all three input values are at a high logic level (High, If the value is a low logic level (Low, 0), it has an output value of a low logic level (Low, 0).

Accordingly, when the first core voltage Vcore_1, the first driving voltage Vcc_1, and the reset signal RESET are all at the high logic level (High, 1), the logic gate 163 according to the exemplary embodiment of the present invention And outputs the first reset signal RESET_1 of the high logic level (High, 1) only.

Also, at least one of the first core voltage Vcore_1, the first driving voltage Vcc_1, and the reset signal RESET is at a low logic level (Low, 0), and the logic gate 163 according to an exemplary embodiment of the present invention, , It outputs a first reset signal RESET_1 of a low logic level (Low, 0). In particular, as described above, when the reset signal RESET of the low logic level (Low, 0) is inputted, the timing controller 160 controls the display panel 110 to maintain the picture-inactive state The data driver control signal DCS is not supplied to the source drive IC 131. [

In the present invention, only when the first core voltage Vcore_1, the first driving voltage Vcc_1, and the reset signal RESET are all at the high logic level (High, 1), the first reset of the high logic level (High, Since the purpose is to output the signal RESET_1, the most suitable logic gate for the purpose of the present invention is a 3-input 1-output AND gate. Also, when the logic gate 163 according to an exemplary embodiment of the present invention is a 3-input 1-output AND gate, three signals can be input using only one logic gate.

A method of driving a display device according to an exemplary embodiment of the present invention includes a timing controller 160 supplying data driving unit control signals DCS to a plurality of source drive ICs 131, Supplying a data voltage to the display panel 110, and displaying the image on the display panel 110.

The step of the timing controller 160 of the present invention supplying the data driver control signals DCS to the plurality of source drive ICs 131 may include receiving the core input voltage Vcore ) And the driving input voltage Vcc are all set and the reset signal RESET input from the power management integrated circuit 200 is at a high logic level, the first reset signal RTI ID = 0.0 > RESET_1 < / RTI > to a high logic level.

9 is a flowchart of a method of driving the timing controller 160 in a display device according to an exemplary embodiment of the present invention.

First, the power management integrated circuit 200 inputs the driving input voltage Vcc and the core input voltage Vcore to the timing controller 160. More specifically, the core input voltage Vcore is input to the core input voltage determination unit 161 and the drive input voltage Vcc is input to the drive input voltage determination unit 162. (S1 in Fig. 9)

Second, the timing controller 160 checks the input voltage and outputs 1 when it is a set value and 0 when it is an error value. (S2 in Fig. 9)

More specifically, the core input voltage determination unit 161 determines whether the core input voltage Vcore input from the power management integrated circuit 200 is greater than the core input voltage reference value stored in the core input voltage determination unit 161 and a predetermined voltage level And outputs a first core voltage Vcore_1 having a high logic level (High, 1) when a difference of 0.5 V or less is generated. The core input voltage determination unit 161 determines whether the core input voltage Vcore inputted from the power management integrated circuit 200 exceeds the core input voltage reference value and the predetermined voltage level, (Vcore_1) having the first core voltage Vcore_1.

The drive input voltage determination unit 162 determines whether the drive input voltage Vcc input from the power management integrated circuit 200 is greater than the drive input voltage reference value stored in the drive input voltage determination unit 162 and a predetermined voltage level (High, 1) when a difference of less than a predetermined value (typically, 0.5 V) is generated. The drive input voltage determination unit 162 determines whether the drive input voltage Vcc input from the power management integrated circuit 200 exceeds the drive input voltage reference value and the predetermined voltage level at a low logic level The first driving voltage Vcc_ 1 having the first driving voltage Vcc_ 1.

Third, when both the first driving voltage Vcc_1 and the first core voltage Vcore_1 are 1, the reset signal RESET is confirmed. (S3 in Fig. 9)

More specifically, when the first driving voltage Vcc_1 and the first core voltage Vcore_1 are both 1, the voltages input to the timing controller 160 are the rated voltages. If at least one of the first driving voltage Vcc_1 and the first core voltage Vcore_1 is 0, at least one of the voltages inputted to the timing controller 160 is not normal. Therefore, the timing controller The logic gate 163 in the memory 160 informs the timing controller 160 and the source drive IC 131 of the supply of the abnormal voltage through the first reset signal RESET_1.

It is possible to control whether or not the timing controller 160 is output in accordance with the reset signal RESET even if the first drive voltage Vcc_1 and the first core voltage Vcore_1 are both 1. [ As described above, even if the first drive voltage Vcc_1 and the first core voltage Vcore_1 are both 1, the timing controller 160 maintains the idle state in which no image is displayed on the display panel 110 If necessary, the reset signal RESET is used to maintain the idle state.

Fourth, when the reset signal RESET is 1, the logic gate 163 in the timing controller 160 outputs the first reset signal RESET_1 at a high logic level (High, 1). (S4 in Fig. 9)

More specifically, when the logic gate 163 is a 3-input 1-output AND gate, only one logic gate 163 can achieve a desired result.

As described above, the core input voltage determining unit 161 determines whether the core input voltage Vcore is a predetermined value and generates the core input voltage Vcore when generating the first core voltage Vcore_1 based on the determination result. And generates a first core voltage Vcore_1 of a high logic level (High, 1) when the first core voltage Vcore is a set value, and generates a first core voltage Vcore_1 of a low logic level (Low, 0) (Vcore).

Further, in the same principle as described above, the drive input voltage determining unit 162 determines whether the drive input voltage Vcc is a set value, and when generating the first drive voltage Vcc_1 based on the determination result, Generates a first drive voltage Vcc_1 of a high logic level (High, 1) when the input voltage Vcc is a set value and generates a first logic level (Low, 0) when the drive input voltage Vcc includes a value of error, The first driving voltage Vcc_l of the first transistor Q1 is generated.

The method of driving a display device according to an exemplary embodiment of the present invention can detect an input voltage erroneously input from among the input voltages in the timing controller 160. [ In particular, since the first reset signal RESET_ 1 is generated by the logic gate 163 in the timing controller 160 and is included in the data driver control signal DCS, the information is displayed on the display panel 110 The presence or absence of abnormality of the voltage input to the timing controller 160 can be easily detected with the naked eye.

Accordingly, it is possible to detect the presence or absence of an abnormality in the input voltage input to the timing controller 160 in the inspecting step, so that the user can find the problem before the product is delivered. As a result, it is possible to solve the problem of recognizing a problem in quality after the product is delivered to the customer, or recognizing the problem and repairing the trouble only after the abnormal voltage is continuously supplied to the timing controller 160 and deterioration occurs.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Accordingly, it should be understood that the above-described embodiments are illustrative and non-restrictive in every respect. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: display panel 111: thin film transistor substrate
112: opposing substrate 120: gate driver
130: Data driver 131: Source drive IC
140: flexible circuit film 150: control printed circuit board
160: Timing controller 161: Core input voltage judging unit
162: driving input voltage determination unit 163: logic gate
200: power management integrated circuit 300: external set

Claims (10)

A display panel for displaying an image;
A plurality of source drive ICs for supplying data voltages to the display panel;
A timing controller for supplying data driver control signals to the plurality of source drive ICs; And
And a power management integrated circuit that receives input power from an external set and generates a core input voltage, a drive input voltage, and a reset signal for driving the timing controller using the input power,
Wherein the timing controller is configured such that when both the core input voltage and the drive input voltage received from the power management integrated circuit are set and the reset signal received from the power management integrated circuit is at a high logic level, 1 < / RTI > reset signal to a high logic level. The apparatus according to claim 1,
And generates the first reset signal to a low logic level when the core input voltage or the drive input voltage is a value including an error. The apparatus according to claim 1,
And generates the first reset signal to a low logic level when the reset signal is a low logic level, and maintains a screen-idle state in which the display panel does not display an image. The apparatus according to claim 1,
A core input voltage determination unit for determining whether the core input voltage is a preset value and generating a first core voltage based on a determination result;
A drive input voltage determination unit for determining whether the drive input voltage is a preset value and generating a first drive voltage based on a determination result; And
A first core voltage supplied from the core input voltage determination unit, a first drive voltage supplied from the drive input voltage determination unit, and a second reset signal supplied from the drive input voltage determination unit, And a logic gate connected to the gate. 5. The method of claim 4,
Wherein the core input voltage determination unit includes:
Generates a first core voltage of a high logic level when the core input voltage is a set value and generates a first core voltage of a low logic level when the core input voltage is a value including an error,
Wherein the drive input voltage determination unit comprises:
Generates a first drive voltage of a high logic level when the drive input voltage is a set value and generates a first drive voltage of a low logic level when the drive input voltage is a value including an error,
Wherein the logic gate is a 3-input, 1-output AND gate. The timing controller supplying data driver control signals to a plurality of source drive ICs;
The plurality of source drive ICs supplying a data voltage to a display panel; And
Wherein the display panel displays an image,
Wherein the timing controller supplies the data driver control signals to the plurality of source driver ICs,
When the core input voltage and the drive input voltage supplied from the power management integrated circuit are both set values and the reset signal received from the power management integrated circuit is at a high logic level, And generating a high logic level signal. 7. The timing controller according to claim 6,
And generates the first reset signal to a low logic level when the core input voltage or the drive input voltage includes a value including an error. 7. The timing controller according to claim 6,
And generates the first reset signal to a low logic level when the reset signal is a low logic level, and maintains a screen-idle state in which the display panel does not display an image. 7. The method of claim 6, wherein the timing controller supplies data driver control signals to a plurality of source driver ICs,
Determining whether the core input voltage is a set value, and generating a first core voltage based on the determination result;
Determining whether the driving input voltage is a preset value, and generating a first driving voltage based on a determination result; And
Receiving the first core voltage and the first driving voltage, receiving the reset signal, generating the first reset signal according to the reset signal, and outputting the first reset signal to the timing controller. 10. The method of claim 9,
Determining whether the core input voltage is a set value, and generating a first core voltage based on a determination result,
Generates a first core voltage of a high logic level when the core input voltage is a set value and generates a first core voltage of a low logic level when the core input voltage is a value including an error,
Determining whether the driving input voltage is a set value, and generating a first driving voltage based on a determination result,
Generates a first drive voltage of a high logic level when the drive input voltage is a set value and generates a first drive voltage of a low logic level when the drive input voltage is a value including an error,
Wherein the first reset signal is generated using a 3-input 1-output AND gate.

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