KR20180005026A - Semiconductor device - Google Patents

Abstract

A semiconductor device with improved sensitivity is provided. According to an embodiment of the present invention, the semiconductor device comprises: a substrate; first and second semiconductor layers arranged on the substrate; a third semiconductor layer arranged between the first and second semiconductor layers; a first electrode arranged in at least one recess exposing the first semiconductor layer by passing through the second and third semiconductor layers so as to be connected to the first semiconductor layer; and a second electrode connected to the second semiconductor layer. The third semiconductor layer has a plane shape surrounding the at least one recess.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

Embodiments relate to semiconductor devices.

A semiconductor device including a compound such as GaN or AlGaN has many advantages such as a wide and easily adjustable band gap energy, and thus can be used variously as a light emitting device, a light receiving device, and various diodes.

Particularly, a light emitting device such as a light emitting diode or a laser diode using a semiconductor material of Group 3-5 or 2-6 group semiconductors can be applied to various devices such as a red, Blue, or ultraviolet light. By using fluorescent materials or combining colors, it is possible to realize white light with high efficiency. Also, compared with conventional light sources such as fluorescent lamps and incandescent lamps, low power consumption, Speed, safety and environmental friendliness.

In addition, when a light-receiving element such as a photodetector or a solar cell is manufactured using a semiconductor material of Group 3-5 or Group 2-6 compound semiconductor, development of a device material absorbs light of various wavelength regions to generate a photocurrent So that light of various wavelength ranges from the gamma ray to the radio wave range can be detected. In addition, such a light receiving element has advantages of fast response speed, safety, environment friendliness and easy control of element materials, so that power control or a module for high-frequency circuit or communication, gas detection, ultraviolet (UV) It can be easily used for various sensors.

Accordingly, the semiconductor device can be replaced with a transmission module of an optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, White LED lightings, automotive headlights, traffic lights and sensors for gas and fire detection. In addition, semiconductor devices can be applied to high frequency application circuits, other power control devices, and communication modules.

In the case of the above-described semiconductor element, which is a light-receiving element, continuous research for improving the sensing sensitivity of light is underway.

An embodiment is to provide a semiconductor device with improved sensing sensitivity.

A semiconductor device according to an embodiment includes a substrate; First and second semiconductor layers disposed on the substrate; A third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer; A first electrode disposed in at least one recess through the second semiconductor layer and the third semiconductor layer to expose the first semiconductor layer and connected to the first semiconductor layer; And a second electrode connected to the second semiconductor layer, wherein the third semiconductor layer may have a planar shape surrounding the at least one recess.

For example, the ratio of the first planar portion of the third semiconductor layer to the entire planar portion of the first semiconductor layer may be greater than 64.87%.

For example, the at least one recess includes a plurality of recesses, and the plurality of recesses may be spaced apart from one another in a symmetrical shape on a plane.

For example, the semiconductor device may operate in a photovoltaic mode.

For example, the at least one recess may have a circular, elliptical or polygonal planar shape.

For example, the light receiving structure including the first, second, and third semiconductor layers may include a central region between the third semiconductor layers in the recess located inside the edge of the light receiving structure; And a peripheral region in which the third semiconductor layer is disposed, the peripheral region protruding from the central region and having a planar shape larger than the central region.

For example, the first electrode may be disposed on the front or a portion of the first semiconductor layer exposed in the at least one recess.

For example, the semiconductor device may include: a first insulating layer disposed between the first electrode and the side of each of the second semiconductor layer and the third semiconductor layer exposed in the recess; A first cover metal layer surrounding the first electrode; And a second cover metal layer disposed to surround the second electrode.

For example, the semiconductor device may include a first pad connected to the first electrode through the first cover metal layer; A second pad connected to the second electrode through the second cover metal layer; And a second cover metal layer disposed between the first pad and the second cover metal layer to open upper portions of the first and second cover metal layers respectively connected to the first pad and the second pad, And may further include a second insulating layer.

For example, the first cover metal layer that is not covered by the second insulating layer has a circular planar shape and may have a diameter of 10 mu m to 150 mu m on a plane.

For example, the first semiconductor layer may be n-type and the second semiconductor layer may be p-type.

The semiconductor device according to the embodiment has a higher sensing current because the photocurrent is higher than that of the comparative example at the same chip area, and has a high degree of design freedom.

1 shows a plan view of a semiconductor device according to an embodiment.
2 is a cross-sectional view of a semiconductor device cut along a line I-I 'shown in FIG.
3 is a plan view of a semiconductor device according to another embodiment.
4 shows a plan view of a semiconductor device according to another embodiment.
5 shows a cross-sectional view of a semiconductor device according to an embodiment having a flip chip bonding structure.
6A to 6F show process cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment.
7 shows a plan view of a semiconductor device according to a comparative example.
8 is a cross-sectional view of a semiconductor device according to a comparative example cut along the line II-II 'shown in FIG.
9 is a plan view of a semiconductor device according to another comparative example.
10 shows a plan view of a semiconductor device according to another comparative example.
11 is a graph showing changes in photocurrent with respect to wavelength in a semiconductor device according to a comparative example.
12 is a graph showing the peak response rate according to the activation ratio.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

The semiconductor device may include various electronic devices such as a light emitting device and a light receiving device. Each of the light emitting device and the light receiving device includes first and second semiconductor layers having different conductivity types, and a second semiconductor layer disposed between the first and second semiconductor layers And a third semiconductor layer (or an active layer).

The light emitting device emits light by recombination of electrons and holes, and the wavelength of the light is determined by the energy band gap inherent to the material. Therefore, the emitted light may vary depending on the composition of the material.

The above-described light emitting device is constituted by a light emitting device package and can be used as a light source of an illumination system, for example, as a light source of an image display device or a light source of an illumination device.

When used as a backlight unit of a video display device, it can be used as an edge-type backlight unit or as a direct-type backlight unit. When used as a light source of a lighting device, it can be used as a regulator or bulb type. It is possible.

As the light emitting element, there are a light emitting diode or a laser diode.

The light emitting diode may include a first semiconductor layer, a second semiconductor layer and a third semiconductor layer of the above-described structure. The second semiconductor layer, which is a p-type semiconductor layer, is bonded to the first semiconductor layer, which is an n-type semiconductor layer, and then an electro-luminescence phenomenon in which light is emitted when current flows is used. In the phase, the light emitting diode and the laser diode have a difference from each other. That is, the laser diode can emit light having one specific wavelength (monochromatic beam) with the same phase and in the same direction by using a phenomenon called stimulated emission and a constructive interference phenomenon. It can be used for optical communication, medical equipment and semiconductor processing equipment.

On the other hand, as the light receiving element, a photodetector, which is a kind of transducer that detects light and converts the intensity of the light into an electric signal, is exemplified. As such a photodetector, a photodiode (e.g., a PD with a peak wavelength in a visible blind spectral region or a true blind spectral region), a photodiode (e.g., a photodiode such as a photodiode (silicon, selenium), a photoconductive element (cadmium sulfide, cadmium selenide) , Photomultiplier tube, phototube (vacuum, gas-filled), IR (Infra-Red) detector, and the like.

In addition, a semiconductor device such as a photodetector may be fabricated using a direct bandgap semiconductor, which is generally excellent in photo-conversion efficiency. Alternatively, the photodetector has a variety of structures, and the most general structure includes a pinned photodetector using a pn junction, a Schottky photodetector using a Schottky junction, and a metal-semiconductor metal (MSM) photodetector have.

The light receiving element, such as a photodiode, may include a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer (or an active layer) having the above-described structure, and may have a pn junction or a pin structure . The photodiode operates by applying reverse bias or zero bias. When light is incident on the photodiode, electrons and holes are generated and a current flows. At this time, the magnitude of the current may be approximately proportional to the intensity of the light incident on the photodiode.

A photocell or a solar cell is a type of photodiode that can convert light into current. The solar cell includes, similarly to the light emitting device, a first semiconductor layer having a first conductivity type having the above-described structure, a second semiconductor layer having a second conductivity type, and a second semiconductor layer disposed between the first and second semiconductor layers And a second semiconductor layer formed on the first semiconductor layer.

In addition, it can be used as a rectifier of an electronic circuit through a rectifying characteristic of a general diode using a p-n junction, and can be applied to an oscillation circuit or the like by being applied to a microwave circuit.

In addition, the above-described semiconductor element is not necessarily implemented as a semiconductor, and may further include a metal material as the case may be. For example, a semiconductor device such as a light receiving element may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, Or may be implemented using a doped semiconductor material or an intrinsic semiconductor material.

Hereinafter, the semiconductor devices 100A to 100C according to the embodiments will be described using the orthogonal coordinate system (x, y, z), but the embodiments are not limited thereto. That is, the embodiment can be explained using other coordinate systems. In the drawings, the x-axis, the y-axis, and the z-axis are described as being orthogonal to each other, but the embodiments are not limited thereto. That is, the x-axis, the y-axis, and the z-axis may not intersect at right angles with each other.

The semiconductor devices 100A, 100B, and 100C according to the embodiments described below refer to light receiving elements, but the embodiments are not limited thereto.

FIG. 1 shows a plan view of a semiconductor device 100A according to an embodiment, and FIG. 2 shows a cross-sectional view of a semiconductor device 100A cut along a line I-I 'shown in FIG.

1 and 2, a light receiving device 100A according to an embodiment includes a substrate 110, a light receiving structure 120, a first insulating layer 132, a second insulating layer 134, a first electrode 142, a second electrode 144, a first cover metal layer 152, and a second cover metal layer 154.

The light receiving structure 120 is disposed on the substrate 110. For example, the light receiving structure 120 may be formed on the (0001) plane of the sapphire substrate 110. The substrate 110 may comprise a conductive material or a non-conductive material. For example, the substrate 110 may comprise at least one of sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, GaP, InP, Ga ₂ O ₃ , GaAs and Si, ). ≪ / RTI >

A buffer layer (not shown) is formed between the substrate 110 and the first semiconductor layer 122 of the light receiving structure 120 in order to improve the difference in thermal expansion coefficient between the substrate 110 and the light receiving structure 120 and the lattice mismatching. May be further disposed. The buffer layer may include, but is not limited to, at least one material selected from the group consisting of Al, In, N, and Ga, for example. Further, the buffer layer may have a single layer or a multi-layer structure. For example, the buffer layer may be made of AlN and may have a thickness of 100 nm, but the embodiment is not limited thereto. As illustrated in FIG. 2, the buffer layer may be omitted.

The light receiving structure 120 may include a first semiconductor layer 122, a second semiconductor layer 126, and a third semiconductor layer (or active layer)

The first semiconductor layer 122 and the second semiconductor layer 126 may have different conductivity types. For example, the first semiconductor layer 122 is a first conductive type semiconductor layer doped with a first conductive type dopant, and the second semiconductor layer 126 is a second conductive type semiconductor layer doped with a second conductive type dopant . The first conductive type dopant may include Si, Ge, Sn, Se, and Te as an n-type dopant, but is not limited thereto. The second conductivity type dopant may include, but is not limited to, Mg, Zn, Ca, Sr, and Ba as a p-type dopant. According to another embodiment, the first conductivity type dopant may be a p-type dopant and the second conductivity type dopant may be an n-type dopant.

The first semiconductor layer 122 may be disposed on the substrate 110 and have a first thickness T1 of 250 nm, but embodiments are not limited in this respect. The second semiconductor layer 126 may have a second thickness T2 of 30 nm, but embodiments are not limited thereto.

The third semiconductor layer 124 may be disposed between the first semiconductor layer 122 and the second semiconductor layer 126. For example, the third thickness T3 of the third semiconductor layer 124 may be between 10 A and several tens of micrometers, but the embodiment is not limited to a specific value of the third thickness T3.

Further, although not shown, a fourth semiconductor layer is further disposed between the second semiconductor layer 126 and the third semiconductor layer 124, so that a boundary between the third semiconductor layer 124 and the fourth semiconductor layer, A strong electric field is generated in the fourth semiconductor layer near the boundary, and a carrier (for example, electrons) is multiplied and aberrated by the fourth semiconductor layer owing to the strong electric field, whereby the gain of the semiconductor element 100A may be improved have.

Each of the first semiconductor layer 122, the second semiconductor layer 126, the third semiconductor layer 124, and the fourth semiconductor layer may be formed of a semiconductor compound. For example, each of the first semiconductor layer 122, the second semiconductor layer 126, the third semiconductor layer 124, and the fourth semiconductor layer may include a nitride semiconductor, and may be implemented with heavily doped GaN . For example, the first semiconductor layer 122, the second semiconductor layer 126, the third semiconductor layer 124 and the fourth semiconductor layers each of _{In x Al y Ga 1 -x- y} N (0≤x≤ GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, and InGaAs, AlGaP, InGaP, AlInGaP, and InP.

For example, the first semiconductor layer 122 may include n-type AlGaN, the second semiconductor layer 126 may include p-type AlGaN, and the third semiconductor layer 124 may include i-AlGaN .

Alternatively, the first semiconductor layer 122 may include n-type InP, the second semiconductor layer 126 may include p-type InP, and the third semiconductor layer 124 may include undoped InGaAs.

A photon of light incident on the light receiving element 100A generates electron and hole pairs in the third semiconductor layer 124. [ The generated electrons and holes can be detected as a current, respectively, by moving in opposite directions due to the electric field across the third semiconductor layer 124, and meeting the first and second electrodes 142 and 144, respectively. Although not shown, the negative terminal and the positive terminal of an ammeter (not shown) are connected to the first electrode 142 and the second electrode 144, respectively, to measure the current generated in the light receiving element 100A have.

According to the embodiment, the entirety of the third semiconductor layer 124 may be a depletion region. The third semiconductor layer 124 can absorb light in the deep ultraviolet wavelength band. For example, the third semiconductor layer 124 can absorb light having a wavelength band of 280 nm or less. However, the embodiment is not limited to a specific wavelength band of light absorbed in the third semiconductor layer 124. [

Alternatively, the third semiconductor layer 124 may comprise a PIN structure. The PIN structure may include an n-type fifth semiconductor layer (not shown), an intrinsic semiconductor layer (not shown) and a p-type sixth semiconductor layer (not shown). The intrinsic semiconductor layer may be disposed between the n-type fifth semiconductor layer and the p-type sixth semiconductor layer. The intrinsic semiconductor layer may be an undoped semiconductor layer or an unintentionally doped semiconductor layer. Unintentional semiconductor layer means that N-vacancy occurs without doping an n-type dopant such as a silicon (Si) atom in a dopant, for example, in a process of growing a semiconductor layer. At this time, if the N vacancy increases, the concentration of the surplus electrons becomes large, so that it can have electrical characteristics similar to those doped with the n-type dopant, unintentionally in the manufacturing process. a fifth semiconductor layer n-type _{Al x Ga (1-x)} N can include a semiconductor material, the sixth semiconductor layer p-type having a composition formula of (0 = x = 1) is Al _y Ga _(1-y) The semiconductor layer may include a semiconductor material having a composition formula of N (0 = y = 1), and the intrinsic semiconductor layer may include a semiconductor material having a composition formula of Al _z Ga _(1-z) N have.

The semiconductor element 100A serving as a light receiving element may be of the back illumination type in which the photon is incident on the substrate 110 side or may be a forward illumination type incident on the second semiconductor layer 126 side.

If the semiconductor device 100A is of the forward irradiation type and the energy band gaps of the p-type sixth semiconductor layer and the intrinsic semiconductor layer are equal to each other, the carrier is excited in the p-type sixth semiconductor layer and absorbed to form the intrinsic semiconductor layer It may be difficult to provide. Therefore, when aluminum (Al) is added to the intrinsic semiconductor layer, the phenomenon that carriers are absorbed in the p-type sixth semiconductor layer may be further intensified. In order to prevent this, the energy band gap of the sixth p-type semiconductor layer may be increased to prevent carriers from being absorbed in the p-type sixth semiconductor layer. Therefore, in order to increase the energy band gap of the sixth p-type semiconductor layer more than the energy band gap of the intrinsic semiconductor layer, Al may be added to the sixth p-type semiconductor layer. That is, the content (z) of aluminum contained in the intrinsic semiconductor layer may be not less than the content (y) of aluminum contained in the p-type sixth semiconductor layer. However, the energy band gap between the p-type sixth semiconductor layer and the intrinsic semiconductor layer is not limited to this. This is because, if the thickness of the p-type sixth semiconductor layer is made sufficiently thin, the carrier may not be absorbed in the p-type sixth semiconductor layer.

For example, the n-type fifth semiconductor layer may include GaN, and the p-type sixth semiconductor layer and the intrinsic semiconductor layer may each include a semiconductor material having a composition formula of Al _{0 .45} Ga _{0 .55} N. Further, the thickness of the sixth p-type semiconductor layer may be much thinner than the thickness of the intrinsic semiconductor layer.

Further, depending on whether the semiconductor element 100A is a forward irradiation type backward irradiation type, the size or thickness of the energy band gap between the n-type fifth semiconductor layer, the intrinsic semiconductor layer and the p-type sixth semiconductor layer can be determined, Examples are not limited to the relative sizes of such energy band gaps and to specific values of thickness.

At least one of the n-type fifth semiconductor layer, the intrinsic semiconductor layer or the p-type sixth semiconductor layer may be a super lattice (SL) layer (or a super junction (SL) , The intrinsic semiconductor layer, and the p-type sixth semiconductor layer may be 50 Å, 50 Å, and 10 Å, respectively, but the embodiments are not limited thereto.

The first electrode 142 may include at least one recess that exposes the first semiconductor layer 122 through the third semiconductor layer 126 and the second semiconductor layer 124 ) CH1 on the first semiconductor layer 122 and may be electrically connected to the first semiconductor layer 122. [

According to one embodiment, as illustrated in FIG. 2, the first electrode 142 may be disposed at a portion of the first semiconductor layer 122 exposed in at least one recess CH1. In this case, the first width W1 of the first electrode 142 in the second direction, which is different from the first direction, in which the substrate 110 is viewed from the light emitting structure 120, 2 < / RTI > width W2. Here, the second direction may be orthogonal to the first direction. For example, the first direction may be the x-axis direction and the second direction may be the y-axis direction.

2, the first electrode 142 may be disposed on the entire surface of the first semiconductor layer 122 exposed in the at least one recess CH1 . In this case, the first width W1 may be equal to the second width W2.

The first electrode 142 may have a single layer or a multi-layer structure. For example, the first electrode 142 may include a first layer (not shown) and a second layer (not shown). The first layer may include Ti and be disposed on the first semiconductor layer 122 exposed in the recess CH1. The second layer includes Al and may be disposed on the first layer.

Referring to FIG. 1, at least one recess (CHE11) is illustrated as having a circular planar shape, but the embodiment is not limited thereto. That is, according to another embodiment, the contact hole CHE11 may have an elliptical or polygonal planar shape. Here, CHE11 denotes the edge of the recess (CH1).

Referring to FIGS. 1 and 2, when the recess CH11 has a circular plan shape, the diameter of the first cover metal layer 152 exposed on the plane without being covered by the second insulating layer 134 Or the diameter of the recess) (PHI ₀ ) may be between 10 μm and 150 μm, but the embodiment is not limited thereto.

The second electrode 144 may be disposed over the second semiconductor layer 126 and may be electrically connected to the second semiconductor layer 126. The second electrode 144 may have a single-layer or multi-layer structure. For example, the second electrode 144 may include a first layer (not shown) and a second layer (not shown). The first layer includes Ni and is disposed on the second semiconductor layer 126, and the second layer includes Au and may be disposed on the p-type first layer.

Each of the first electrode 142 and the second electrode 144 shown in FIG. 2 may be formed of a metal such as Ag, Ni, Ti, Al, Rh, Pd, Ir, Ru, Mg, , Hf, Cr, and combinations thereof.

When the second electrode 144 includes a material that is in ohmic contact, a separate ohmic layer may be omitted as illustrated in FIG. 2, but the embodiment is not limited thereto. That is, according to another embodiment, when the second electrode 144 does not include an ohmic contact material, a separate ohmic layer (not shown) performing an ohmic function different from that illustrated in FIG. 2 is formed on the second electrode 144 and the second semiconductor layer 126. In this case, The ohmic layer may be a transparent conductive oxide (TCO). For example, the ohmic layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO) ZnO, ZnO, IrOx, ZnO, AlGaO, AZO, ATO, GZO, IZO, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, , Au, and Hf, and is not limited to such a material.

In the case of the embodiment, the third semiconductor layer 124 has a planar shape surrounding at least one recess CH1.

2, the light receiving structure 120 may include a central area CA and a peripheral area PA. The central region CA refers to a region between the third semiconductor layers 124 in the recess CH1 located at the center of the inner side of the light receiving structure 120, May be referred to as an area in which the light guide plate 124 is disposed. According to the embodiment, the peripheral area PA may have a cross-sectional shape protruding from the central area CA.

Fig. 3 shows a plan view of the semiconductor element 100B according to another embodiment, and Fig. 4 shows a plan view of the semiconductor element 100C according to still another embodiment. For convenience of explanation, the illustration of the second electrode 154 in Figs. 3 and 4 is omitted.

In the case of FIGS. 1 and 2, the semiconductor device 100A includes only one recess (CH1, CHE11), but the embodiment is not limited thereto. That is, at least one recess may comprise a plurality of recesses.

As illustrated in FIG. 3, semiconductor device 100B may include four recesses (CH21, CH22, CH23, CH24). In FIG. 3, CHE21, CHE22, CHE23, and CHE24 represent the edges of four recesses (CH21, CH22, CH23, and CH24), as CHE11 shown in FIG. 2 represents the edge of the recess CH1 .

Alternatively, as illustrated in FIG. 4, the semiconductor device 100C may include nine recesses (CH31 to CH39). In FIG. 4, CHE31 to CHE39 represent the edges of nine recesses (CH31 to CH39), as CHE11 shown in FIG. 2 represents the edge of the recess CH1.

The sectional shapes of the semiconductor elements 100B and 100C shown in Figs. 3 and 4 are the same as those of Figs. 1 and 2 except that the recesses [(CH21 to CH24) or (CH31 to CH39) The semiconductor device 100A shown in Fig. Therefore, the sectional shapes of the semiconductor elements 100B and 100C shown in Figs. 3 and 4 are as shown in Fig. The semiconductor elements 100B and 100C shown in FIG. 3 and FIG. 4 are the same as the semiconductor elements 100A and 100B shown in FIGS. 1 and 2 except that the positions and the number of the recesses CH are different from each other. The description of the semiconductor elements 100B and 100C shown in Figs. 3 and 4 is replaced by a description of the semiconductor element 100A shown in Figs. 1 and 2.

Further, when the semiconductor elements 100B and 100C include a plurality of recesses, as illustrated in FIGS. 3 and 4, a plurality of recesses may be spaced apart from each other in a symmetrical shape on a plane, It is not limited.

1 and 2, the first insulating layer 132 is formed on the side of each of the second semiconductor layer 126 and the third semiconductor layer 124 exposed in the recess CH1, The first cover metal layer 142 and the first cover metal layer 152. [ The first electrode 142 and the first cover metal layer 152 and the sides of the second and third semiconductor layers 124 and 126 can be electrically separated from each other by disposing the first insulating layer 132. [

The first cover metal layer 152 may be disposed to surround the first electrode 142. The second cover metal layer 154 may be disposed around the second electrode 144.

Each of the first and second cover metal layers 152 and 154 may be made of a material having excellent electrical conductivity. For example, each of the first and second cover metal layers 152 and 154 may be formed of Ti, Au, Ni, In, Co, W, Fe. Rh, Cr, Al, and the like, but is not limited thereto.

Optionally, the first and second cover metal layers 152,154 may be omitted.

As shown in FIGS. 1 to 4, the semiconductor devices 100A, 100B, and 100C may have a horizontal bonding structure, but the embodiments are not limited thereto.

Hereinafter, the semiconductor device 200 having a flip chip bonding structure will be described as follows.

5 shows a cross-sectional view of a semiconductor device 200 according to an embodiment having a flip chip bonding structure.

The semiconductor device 200 shown in FIG. 5 includes the semiconductor device 100A, the first and second pads 172 and 174, the first and second electrode pads 182 and 184, Second lead frames 202, 204, first and second insulation portions 212, 214, respectively. Here, the first and second electrode pads 182 and 184 may be omitted.

Since the semiconductor device 100A included in the semiconductor device 200 shown in FIG. 5 is the same as the semiconductor device shown in FIG. 2, the same reference numerals are used, and a duplicate description thereof will be omitted.

The first pad 172 is electrically connected to the first electrode 142 through the first cover metal layer 152 and the second pad 174 is electrically connected to the second electrode 144 through the second cover metal layer 154. [ As shown in FIG.

The first pad 172 electrically connects the first electrode 142 to the first lead frame 202 and the second pad 174 electrically connects the second electrode 144 to the second lead frame 204. [ As shown in FIG.

The first and second insulating portions 212 and 214 are disposed between the first and second lead frames 202 and 204 to electrically isolate the first and second lead frames 202 and 204 from each other.

The second insulating layer 134 may be disposed between the first pad 172 and the second cover metal layer 154 to electrically isolate the first pad 172 and the second cover metal layer 154 from each other.

The second insulating layer 134 exposes the upper portion of the first cover metal layer 152 to which the first pad 172 is connected and the upper portion of the second cover metal layer 154 to which the second pads 174 are connected And may be disposed on the entire surface of the light receiving structure 120 while exposing the light receiving structure 120. Accordingly, in FIG. 1, it can be seen that a part of the first cover metal layer 152 and the second cover metal layer 152 are exposed by the second insulating layer 134. 3, part of the first cover metal layers 152-1 to 152-4 is exposed by the second insulating layer 134, and in the case of FIG. 4, the first cover metal layers 152-1 to 152-9 ) Is exposed by the second insulating layer 134. [0064] As shown in FIG.

The first and second insulating layers 132 and 134 and the first and second insulating portions 212 and 214 may be the same material or different materials. Each of the first and second insulating layers 132 and 134 and the first and second insulating portions 212 and 214 may be made of a nonconductive oxide or a nitride. For example, a silicon oxide (SiO ₂ ) layer , An oxynitride layer, Al ₂ O ₃ , or an aluminum oxide layer, but the embodiment is not limited thereto.

Unlike the semiconductor device 100A shown in FIG. 2, which is a horizontal bonding structure, the semiconductor device 200 shown in FIG. 5 is a flip chip bonding structure, so that light from the outside is incident on the substrate 110 and the first semiconductor layer 122 to the third semiconductor layer 124. The first semiconductor layer 122 and the second semiconductor layer 126 are formed of a material having light transmittance and the second semiconductor layer 126, the first electrode 142, and the second electrode 144 are made of a light- And the like.

Hereinafter, the manufacturing method according to the embodiment of the semiconductor element 100A shown in Figs. 1 and 2 will be described with reference to Figs. 6A to 6F, but the embodiments are not limited thereto. That is, the semiconductor device 100A shown in Figs. 1 and 2 may be manufactured by a method different from the manufacturing method shown in Figs. 6A to 6F. Further, the semiconductor devices 100B and 100C shown in Figs. 3 and 4 can be manufactured by the method illustrated in Figs. 6A to 6F, except that the position and the number of the recesses are different.

6A to 6F show process cross-sectional views for explaining a method of manufacturing the semiconductor device 100A according to the embodiment.

First, referring to FIG. 6A, a light receiving structure 120 is formed on a substrate 110. Specifically, a first semiconductor layer 122 is formed on a substrate 110, and a third semiconductor layer 124 is formed on a first semiconductor layer 122. Thereafter, the second semiconductor layer 126 is formed on the third semiconductor layer 124.

Referring to FIG. 6B, a first recess CH1 is formed through the second and third semiconductor layers 126 and 124 to expose the first semiconductor layer 122. Referring to FIG. 6B can be performed by a conventional photolithography process. That is, after an etching mask (not shown) is disposed in an area other than the area where the first recess CH1 is to be formed, the light receiving structure 120 is etched using an etching mask to form a recess CH1, By stripping the etch mask, the recess CH1 illustrated in Fig. 6B can be formed.

Referring to FIG. 6C, a region in which the first electrode 142 is to be disposed in the recess CH1 is exposed, and a region on the second semiconductor layer 126 where the second electrode 144 is to be disposed is exposed The first insulating layer 132 is formed on the entire surface of the light receiving structure 120.

6D, a first electrode 142 is formed on the exposed first semiconductor layer 122 in the recess CH1 without being covered by the first insulating layer 132. Referring to FIG.

6E, a second electrode 144 is formed on the exposed second semiconductor layer 126 without being covered by the first insulating layer 132. Referring to FIG.

6F, a first cover metal layer 152 that surrounds the first electrode 142 and a second cover metal layer 154 that surrounds the second electrode 144 are formed.

Hereinafter, a semiconductor device according to a comparative example and a semiconductor device according to an embodiment will be described with reference to the accompanying drawings.

FIG. 7 shows a plan view of a semiconductor device according to a comparative example, and FIG. 8 shows a cross-sectional view of a semiconductor device according to a comparative example cut along the line II-II 'shown in FIG.

The semiconductor device according to the comparative example shown in Figs. 7 and 8 includes a substrate 10, a light receiving structure 20, a second insulating layer 34, first and second electrodes 42 and 44, 2 cover metal layers 52,54. Here, the substrate 10, the light receiving structure 20, the second insulating layer 34, the first and second electrodes 42 and 44, and the first and second cover metal layers 52 and 54 are shown in FIG. The first and second electrodes 142 and 144 and the first and second cover metal layers 152 and 154, respectively, of the substrate 110, the light receiving structure 120, the second insulating layer 134, Therefore, redundant description will be omitted. That is, the first semiconductor layer 22, the second semiconductor layer 26, and the third semiconductor layer 24 included in the light receiving structure 20 have the first semiconductor layer 122, the second semiconductor layer 126 and the third semiconductor layer 124, respectively.

In the case of the semiconductor devices 100A, 100B, 100C, and 200 according to the embodiments shown in FIGS. 1 to 5, the third semiconductor layer 124 has a planar shape that surrounds the first electrode 142. On the other hand, in the case of the semiconductor device according to the comparative example shown in FIGS. 7 and 8, the first electrode 42 has a planar shape that surrounds the third semiconductor layer 24. Except for these differences, the semiconductor device according to the comparative example shown in FIG. 7 and FIG. 8 is the same as the semiconductor device 100A, 100B, and 100C according to the embodiment, and thus duplicate description will be omitted.

In the semiconductor device according to the comparative example shown in Figs. 7 and 8, the first electrode 42 has a planar shape surrounding the third semiconductor layer 24. In this case, the third planar area A3 of the third semiconductor layer 24 may be smaller than the fourth planar area A4 excluding the third planar area A3 in the entire planar area of the first semiconductor layer 22. [ Here, the third planar area A3 can be expressed by the following equation (1), and the fourth planar area A4 can be expressed by the following equation (2).

₂ represents the diameter of the third semiconductor layer 24 having a circular planar shape, WT represents the width of the first semiconductor layer 22 in the second direction, LT represents the width of the first semiconductor layer 22, In the third direction. Here, the third direction may be a direction different from the first and second directions, and may be a direction orthogonal to the first and second directions. For example, when the first direction is the x-axis direction and the second direction is the y-axis direction, the third direction may be the z-axis direction.

The first plane area A1 can be expressed by the following equation (3), and the second plane area A2 can be expressed by the following equation (4).

Here, φ ₁ represents the distance between the third semiconductor layers 124 in the recess having a circular planar shape, WT represents the width of the first semiconductor layer 122 in the second direction, LT represents the width of the first semiconductor layer Represents the length of the semiconductor layer 122 in the third direction.

9 and 10 show a plan view of a semiconductor device according to another comparative example.

The diameter φ ₂ of the third semiconductor layer 24 shown in FIG. 9 is smaller than the diameter φ ₂ of the third semiconductor layer 24 shown in FIG. 10, and the third semiconductor layer 24 24) the diameter of the (φ ₂₎ is smaller than the diameter (φ ₂₎ of the third semiconductor layer 24 shown in Fig. 9 and 10, except that the number and position of the second cover metal layer 54 are different from the diameter ( ₂ ) of the third semiconductor layer 24 as described above, the semiconductor device shown in Figs. 7 and 8 The same reference numerals are used for the same portions, and redundant description of the semiconductor elements shown in FIGS. 9 and 10 will be omitted.

11 is a graph showing changes in photocurrent by wavelength in a semiconductor device according to a comparative example, in which the abscissa indicates a wavelength and the ordinate indicates a photocurrent.

The present applicant has found that the semiconductor device having the width W in the second direction and the length L in the third direction of 1100 mu m in each of Figs. 7, 9, and 10 has the diameter of the third semiconductor layer 24 (φ ₂ ), and the results as shown in FIG. 11 were obtained. At this time, the width WT of the first semiconductor layer 22 in the second direction and the length LT in the third direction of the first semiconductor layer 22 were set to 1100 mu m, respectively. In this case, the third and fourth planar areas A3 and A4 according to the change of the diameter (φ ₂ ) are shown in the following Table 1.

division 7 9 10 Diameter (φ ₂ ) (cm) 0.1 0.04 0.07 A3 (cm2) 7.85 x 10 ^-3 1.26 x 10 ^-3 3.85 x 10 ^-3 A4 (㎠) 4.25 x 10 ^-3 10.84 x 10 ^-3 8.25 x 10 ^-3

Referring to Fig. 11, at a wavelength of about 270 nm, the photocurrent (C2) of the semiconductor device shown in Fig. 10 is larger than the photocurrent (C3) of the semiconductor device shown in Fig. 9, It can be seen that the photocurrent C1 of the semiconductor device shown in Fig. 7 is larger than the photocurrent C2 of the device. That is, it can be seen that the larger the diameter? ₂ of the third semiconductor layer 24, the larger the photocurrent. The increase in the photocurrent can mean that the sensing sensitivity of the semiconductor device increases.

The applicant of the present application has found that in the semiconductor elements 100A and 100B having the width W in the second direction and the length L in the third direction 1100 m respectively in Figs. 1 and 4, The first and second planar areas A1 and A2 were obtained as shown in the following Table 2 while varying the distance ₁ between the first and third semiconductor layers 124. [ At this time, the width WT of the first semiconductor layer 122 in the second direction and the length LT in the third direction of the first semiconductor layer 122 were set to 1100 mu m, respectively. In this case, the diameter? ₀ of the first cover metal layer 152 that was exposed without being covered by the second insulating layer 134 was regarded as the diameter? ₁ .

division 1 4 Diameter (Φ ₁ ) (㎝) 0.001 0.015 A1 (cm2) 12.1 x 10 ^-3 -0.785 x 10 ^-6 10.51 x 10 ^-3 A2 (cm2) 0.785 x 10 ^-6 1.59 x 10 ^-3

FIG. 12 is a graph showing a peak response rate according to an active ratio, and shows values of other peak response rates 304, 306, 308 and 310 on the basis of the lowest peak response rate 302. That is, the peak response rates 304 to 310 correspond to the peak response rates when the peak response rate 302 is '1'.

Referring to FIG. 12, as shown in FIG. 9, the peak response rate 302 when the third planar area A3 of the third semiconductor layer 24 is the smallest is the smallest, and as shown in FIG. 10, The peak response rate 304 slightly increases when the third planar area A3 of the semiconductor layer 24 increases and the third planar area A3 of the third semiconductor layer 24 increases further as shown in Fig. The peak response rate 306 is further increased. In addition, as in the embodiment 100C shown in FIG. 4, when the first planar area A1 of the third semiconductor layer 124 increases, the peak response rate 308 is higher than the peak response rates 302, 304, 306 And the peak response rate 310 is maximized when the first planar area A1 of the third semiconductor layer 124 further rises as in the embodiment 100A shown in FIG.

Referring to Table 1, in the case of the semiconductor device according to the comparative example, the maximum third planar area A3 of the third semiconductor layer 24 is 7.85.times.10.sup.- ³ cm.sup.2, LT x WT), which is about 64.87% of 12.1 cm < 2 >. On the other hand, in the case of the embodiment, it can be seen that the first plane area A1 of the third semiconductor layer 124 is larger than 64.87%. For example, referring to Table 2, the first planar area A1 shown in FIG. 4 is about 86.85% of the entire planar area 12.1 cm 2 of the first semiconductor layer 122, which is 10.51 cm 2. As described above, in the embodiment, the ratio of the first planar area A1 of the third semiconductor layer 124 to the entire planar area of the first semiconductor layer 122 can be larger than 64.87%.

As a result, in the same chip area (LxW), the semiconductor devices 100A, 100B, and 100C according to the embodiments have a higher photocurrent than the comparative example as the planarity of the third semiconductor layer 124 increases. That is, the sensing sensitivity of the semiconductor devices 100A, 100B, and 100C according to the embodiment is higher than that of the semiconductor devices according to the comparative example. This is the case where the semiconductor devices 100A, 100B, and 100C according to the embodiment operate in a photovoltaic mode.

Further, as compared with the case of manufacturing a semiconductor device according to a comparative example in which the first electrode 42 has a planar shape surrounding the third semiconductor layer 24, the third semiconductor layer 124 has a recess The degree of freedom of designing the semiconductor devices 100A, 100B, and 100C increases. That is, the arrangement (or position) and / or the number of recesses can be designed in various ways.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100A, 100B, 100C, 100D, 200: semiconductor device 110: substrate
120: light receiving structure 122: first semiconductor layer
124: third semiconductor layer 126: second semiconductor layer
132: first insulation layer 134: second insulation layer
142: first electrode 144: second electrode
152: first cover metal layer 154: second cover metal layer

Claims (12)

Board;
First and second semiconductor layers disposed on the substrate;
A third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer;
A first electrode disposed in at least one recess through the second semiconductor layer and the third semiconductor layer to expose the first semiconductor layer and connected to the first semiconductor layer; And
And a second electrode connected to the second semiconductor layer,
And the third semiconductor layer has a planar shape surrounding the at least one recess. 2. The semiconductor device according to claim 1, wherein the ratio of the first planar portion of the third semiconductor layer to the entire planar portion of the first semiconductor layer is larger than 64.87%. 2. The method of claim 1, wherein the at least one recess comprises a plurality of recesses,
Wherein the plurality of recesses are spaced apart from each other in a symmetrical shape on a plane. The semiconductor device according to claim 1, which operates in a photovoltaic mode. The semiconductor device of claim 1, wherein the at least one recess has a circular, elliptical or polygonal planar shape. The light-receiving structure according to claim 1, wherein the light-receiving structure including the first, second,
A central region between the third semiconductor layers in the recess located inside the edge of the light receiving structure; And
Wherein the third semiconductor layer is disposed and includes a peripheral region protruding from the central region and having a planar shape larger than that of the central region. 2. The semiconductor device of claim 1, wherein the first electrode is disposed on a front surface of the first semiconductor layer exposed in the at least one recess. 2. The semiconductor device of claim 1, wherein the first electrode is disposed at a portion of the first semiconductor layer exposed at the at least one recess. The semiconductor device according to claim 6, wherein the semiconductor element
A first insulating layer disposed between the side of each of the second semiconductor layer and the third semiconductor layer exposed in the recess and the first electrode;
A first cover metal layer surrounding the first electrode; And
And a second cover metal layer surrounding the second electrode. 10. The semiconductor device according to claim 9, wherein the semiconductor element
A first pad connected to the first electrode through the first cover metal layer;
A second pad connected to the second electrode through the second cover metal layer; And
And a second cover metal layer disposed between the first pad and the second cover metal layer and opening the upper portions of the first and second cover metal layers to which the first pad and the second pad are respectively connected, 2 < / RTI > insulation layer. 11. The semiconductor device according to claim 10, wherein the first cover metal layer that is not covered by the second insulating layer has a circular planar shape and has a diameter of 10 mu m to 150 mu m on a plane. 12. The semiconductor device according to any one of claims 1 to 11, wherein the first semiconductor layer is n-type and the second semiconductor layer is p-type.

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