KR20180004690A - Multilayer ceramic electronic component - Google Patents

Abstract

The present invention relates to a multilayer ceramic electronic component. According to an embodiment of the present invention, the multilayer ceramic electronic component comprises: a multilayer body including a dielectric layer; and a plurality of internal electrode layers formed in the multilayer body, and having an end thereof exposed to one or more surfaces of the multilayer body. When the thickness of a capacitance forming unit formed by overlapping the internal electrode layers is defined as T1, and the distance between one surface of the multilayer body having the end of an internal electrode exposed therein and an end of the internal electrode disposed at the outermost side is defined as T2, a ratio of T2 to T1 (T2/T1) is 0.70 to 0.95. Also, the thickness of the multilayer body having the capacitance forming unit formed thereon may be greater than that of one surface of the multilayer body having the end of the internal electrode exposed therein.

Description

[0001] The present invention relates to a multilayer ceramic electronic component,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic electronic component, and more particularly, to a multilayer ceramic electronic component having excellent reliability.

In general, an electronic component using a ceramic material such as a capacitor, an inductor, a piezoelectric element, a varistor or a thermistor includes a ceramic body made of a ceramic material, internal electrodes formed inside the body, and external electrodes provided on the surface of the ceramic body to be connected to the internal electrodes Respectively.

A multilayer ceramic capacitor in a ceramic electronic device includes a plurality of laminated dielectric layers, an inner electrode disposed opposite to the dielectric layer with one dielectric layer interposed therebetween, and an outer electrode electrically connected to the inner electrode.

The multilayer ceramic capacitor is widely used as a component of a mobile communication device such as a computer, a PDA, and a mobile phone due to its small size, high capacity, and ease of mounting.

In recent years, miniaturization and multifunctionalization of electronic products have led to the tendency of miniaturization and high functioning of chip components. Therefore, a multilayer ceramic capacitor is required to have a small-sized and high capacity high-capacity product.

In order to increase the capacity of the multilayer ceramic capacitor, the thickness of the dielectric layer and the internal electrode layer must be made thinner and the number of stacked layers must be increased. However, as dielectric layers and internal electrodes are thinned and the number of stacked layers increases, the possibility of dielectric breakdown increases, and interlayer delamination and cracks may occur, thereby decreasing the reliability of the multilayer ceramic capacitor. As a result, miniaturization and high capacity of the multilayer ceramic capacitor are limited.

An object of the present invention is to provide a multilayer ceramic electronic component having excellent reliability.

One embodiment of the present invention relates to a laminated body including a dielectric layer; And a plurality of internal electrode layers formed inside the laminate body and having ends exposed at one or more surfaces of at least one of the laminate bodies, wherein the thickness of the capacitance forming part formed by overlapping the plurality of internal electrode layers is T1, (T2 / T1) of T1 to T1 is 0.70 to 0.95, where T2 is a distance between the ends of the internal electrodes disposed on the outermost side of one side of the laminated body in which the ends of the internal electrodes are exposed, Wherein the thickness of the laminated body on which the forming portion is formed is larger than the thickness of one surface of the laminated body on which the ends of the internal electrodes are exposed.

The thickness of the laminate body on which the capacitance forming portion is formed may form the maximum thickness of the laminate body.

The thickness T1 of the capacitance forming portion may be a distance between the internal electrodes disposed at the outermost portion in the center portion of the laminate body.

The thickness T1 of the capacitance-forming portion can be measured by a distance between an inner electrode disposed on the uppermost layer and an inner electrode disposed on the lowermost layer on an intersection line of two cross sections perpendicular to each other at the central portion of the laminate body.

The distance (T2) between the thickness (T1) of the capacitance-forming portion and the internal electrodes disposed on the outermost one surface of the laminate body where the ends of the internal electrodes are exposed may be formed in the same cross section of the laminate body.

The distance (T2) between the inner electrodes disposed at the outermost one of the surfaces of the laminated body in which the ends of the inner electrodes are exposed may be formed at a central portion of one surface of the laminated body.

The ratio of the thickness of the surface of the laminated body where the end of the internal electrode is exposed to the thickness of the laminated body formed with the capacitance forming portion may be 0.75 to 0.97.

The thickness of the laminate body on which the capacitance-forming portion is formed may be 310 to 320 mu m.

The thickness of the laminated body formed with the capacitance-forming portion may be greater than the thickness of the surface of the laminated body where the ends of the internal electrodes are not exposed.

The thickness T1 of the capacitance-forming portion may be 270 to 280 mu m.

The ratio of the minimum thickness of one surface of the layered body to the maximum thickness of one surface of the layered body where the ends of the internal electrodes are exposed may be 0.78 to 0.95.

The minimum thickness of one surface of the lamination body may be formed in a margin portion where the internal electrode is not formed.

The thickness of the dielectric layer disposed between the internal electrode layers may be less than 0.65 mu m.

The thickness of the one internal electrode layer may be 0.7 탆 or less.

Another embodiment of the present invention is a laminated body including first and second side faces; And a plurality of first and second internal electrode layers formed inside the stack body and each having ends exposed at the first and second sides, respectively, and the plurality of first and second internal electrode layers are formed by overlapping When the distance between the first internal electrode terminal or the second internal electrode terminal disposed at the outermost side in the first side surface or the second side surface of the laminate body is T2 and the thickness of the capacitance forming portion is T1, Wherein the distance between the first and second internal electrode layers adjacent to each other in the capacitance forming portion is less than 0.65 mu m, and the thickness of the laminate main body having the capacitance forming portion formed thereon is smaller than the thickness of the laminate main body Wherein the thickness of the first or second side is greater than the thickness of the first side or the second side.

The thickness T1 of the capacitance forming portion may be a distance between the internal electrodes disposed at the outermost portion in the center portion of the laminate body.

The distance (T2) between the first internal electrode terminal or the second internal electrode terminal disposed at the outermost side in the first side surface or the second side surface of the laminate body is equal to the thickness (T1) of the capacitance- Directional cross-section.

In the width direction of the laminate body, the thickness of the center portion of the laminate body may be larger than the thickness of the end portion of the laminate body.

According to still another embodiment of the present invention, there is provided a semiconductor device comprising: a laminated body having three pairs of surfaces facing each other; A plurality of first and second internal electrode layers formed in the laminated body and each having a terminal end exposed on at least one surface of the laminated body; And a plurality of dielectric layers disposed between the first and second internal electrode layers and having a thickness of less than 0.65 mu m,

Wherein a thickness of the capacitance forming portion formed by overlapping the plurality of first and second internal electrode layers is T 1 and a thickness of the first internal electrode terminal or the second internal electrode terminal disposed at the outermost portion of one side of the laminated body, (T2 / T1) of T1 to T1 is 0.70 to 0.95 when the distance between the ends of the internal electrodes is T2, the thickness of the laminated body having the capacitance-formed portion formed thereon is D1, The ratio (D2 / D1) of D2 to D1 is 0.75 to 0.97, where D2 is the thickness of one surface of the laminate body where the ends of the electrodes are exposed.

The thickness of the laminated body formed with the capacitance-forming portion may be greater than the thickness of the surface of the laminated body where the ends of the internal electrodes are not exposed.

According to the embodiment of the present invention, even when the dielectric layer and the internal electrode layer are made thin, it is possible to prevent the electric field from concentrating in a specific region by controlling the compression ratio of the capacitance forming portion and the electrode lead portion, Can be lowered.

According to one embodiment of the present invention, it is possible to prevent the electric field from concentrating on a specific region by controlling the ratio of the thickness of the capacitor forming portion and the thickness between the internal electrodes drawn to the side surface of the laminate body, .

According to an embodiment of the present invention, it is possible to prevent the electric field from concentrating on a specific region by controlling the thickness of the laminate body on which the capacitor forming portion is formed and the thickness ratio of the side surface of the laminate body, and the possibility of delamination and cracking Can be lowered.

According to the embodiment of the present invention, it is possible to prevent the electric field from concentrating in a specific region by controlling the thickness ratio of the center portion and the end portion of the lamination body in the width direction of the lamination body, Can be lowered.

 According to one embodiment of the present invention, the possibility of dielectric breakdown is lowered, the dielectric breakdown voltage characteristic is excellent, and the characteristics under high temperature and humidity conditions can be excellent.

1 is a schematic perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a schematic perspective view showing a laminated body according to an embodiment of the present invention.
3 is a schematic side view showing one side of the laminate body.
4 is a sectional view taken along the line A-A 'in Fig.
5 is a cross-sectional view taken along the line B-B 'of FIG.
6 is a schematic exploded sectional view showing the laminate body.
7A and 7B are top plan views showing a dielectric layer in which an internal electrode layer is formed.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

1 is a schematic perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 2 is a schematic perspective view showing a laminate body according to an embodiment of the present invention, and Fig. 3 is a schematic side view showing one side face of the laminate body. 4 is a sectional view taken along the line A-A 'of FIG. 1, and FIG. 5 is a sectional view taken along the line B-B' of FIG. 6 is a schematic exploded cross-sectional view showing a laminate body, and Figs. 7A and 7B are top plan views showing a dielectric layer on which an internal electrode layer is formed.

Examples of the multilayer ceramic electronic component include a capacitor, an inductor, a piezoelectric element, a varistor or a thermistor. The ceramic body includes a ceramic body made of a ceramic material, internal electrodes formed inside the body, and external electrodes provided on the surface of the ceramic body to be connected to the internal electrodes can do. Hereinafter, with reference to Figs. 1 to 6, a multilayer ceramic capacitor among the multilayer ceramic electronic components will be described as an example.

1 to 6, a multilayer ceramic capacitor according to an embodiment of the present invention includes a laminate body 110; And outer electrodes 131 and 132 formed on both side surfaces of the laminate body.

In the present embodiment, the 'longitudinal direction' of the multilayer ceramic capacitor may be defined as 'L' direction, 'width direction', and 'T' directions in FIG. The 'thickness direction' can be used in the same sense as the direction in which the dielectric layers are stacked, that is, the 'lamination direction'.

FIG. 2 is a schematic perspective view showing a laminated body 110 excluding the external electrodes 131 and 132 in the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a schematic side view showing one side of the laminated body, Is a schematic exploded sectional view showing a laminated body.

As shown in the figure, according to one embodiment of the present invention, the laminate body 110 may be formed by stacking a plurality of dielectric layers 111 in the thickness direction. The plurality of dielectric layers constituting the laminate body 110 may be integrated in a sintered state such that boundaries between adjacent dielectric layers can not be confirmed.

The dielectric layer may be formed of a ceramic powder having a high dielectric constant, and the ceramic powder is not limited thereto. For example, a barium titanate (BaTiO ₃ ) powder or a strontium titanate (SrTiO ₃ ) powder may be used.

Though not limited thereto, the thickness of the single dielectric layer 111 may be less than 0.65 mu m. Alternatively, the thickness of the one dielectric layer 111 may be 0.55 m or less. The thickness of the one dielectric layer 111 may be from 0.4 mu m or more to less than 0.65 mu m. Or the thickness of the single dielectric layer 111 may be 0.45 to 0.55 mu m.

In one embodiment of the present invention, the thickness of the one dielectric layer may mean an average thickness of one dielectric layer disposed between the internal electrode layers 121 and 122. The average thickness of the dielectric layer can be measured by scanning an image with a Scanning Electron Microscope (SEM) at a magnification of 10,000 in the longitudinal direction of the laminate body 110 as shown in FIG. More specifically, the average value can be measured by measuring the thickness of one dielectric layer at 30 points in the longitudinal direction of the scanned image. Thirty points, which are equivalent prices, may be designated in the capacity forming section E. As shown in FIG. 4, the capacitance forming portion E may mean a region where the first and second internal electrodes are overlapped. When the average value is measured by extending the average value measurement to ten dielectric layers, The average thickness can be further generalized.

The thickness of the dielectric layer may be defined as an average distance between adjacent internal electrode layers 121 and 122 in the capacitance forming portion E. For example, the average distance may be calculated by measuring distances between adjacent internal electrode layers at 30 points at even intervals in the longitudinal direction of the internal electrode layer in the scanned image. When the average distance between adjacent internal electrode layers is extended to 10 pairs of internal electrode layers arranged in the capacitance forming portion E, the average distance between the adjacent internal electrode layers can be further generalized. The distance between the first internal electrode layers 121 and the second internal electrode layers 122 adjacent to each other in the capacitance forming portion E may be less than 0.65 mu m, although not limited thereto. Or the distance between the adjacent first internal electrode layers 121 and the second internal electrode layers 122 may be 0.55 占 퐉 or less. The distance between the first internal electrode layers 121 and the second internal electrode layers 122 adjacent to each other may be 0.4 μm or more and less than 0.65 μm. Or the distance between the first internal electrode layers 121 and the second internal electrode layers 122 adjacent to each other may be 0.45 to 0.55 mu m.

According to one embodiment of the present invention, the laminate body 110 may have a hexahedral shape and may have three pairs of side faces facing each other. More specifically, the thickness of the central portion of the laminated body may be greater than the lengthwise end of the laminated body, and the central portion of the laminated body may be convex.

A plurality of internal electrodes 121 and 122 may be formed in the laminated body 110. The internal electrodes 121 and 122 may be formed on the dielectric layer 111 and may be disposed opposite to each other in a stacking direction of the dielectric layers with a single dielectric layer interposed therebetween by sintering. The internal electrode layer may be formed of a conductive metal such as Ni, Cu, Pd, etc., but the thickness of the internal electrode layer may be 0.7 탆 or less.

According to an embodiment of the present invention, the dielectric layer having the internal electrode layers may be stacked with 200 layers or more.

The plurality of internal electrodes 121 and 122 may have a pair of first internal electrodes 121 and second internal electrodes 122 having different polarities. 7A and 7B, according to an embodiment of the present invention, the first and second internal electrodes 121 and 122 may be in a rectangular or rectangular shape.

7A and 7B, a lengthwise margin L 1 in which the first internal electrode 121 or the second internal electrode 122 is not formed is formed in the longitudinal direction L of one dielectric layer 111 Widthwise margin portions W1 and W2 in which the first internal electrode 121 or the second internal electrode 122 is not formed may be formed in the width direction W of the dielectric layer 111. [

Referring to FIG. 4, one ends of the first and second internal electrodes 121 and 122 are formed at predetermined intervals from one side of the laminate body by the longitudinal margin L1, The other ends of the second internal electrodes 121 and 122 may be exposed to one side of the laminate body, respectively.

Fig. 2 is a schematic perspective view showing the laminate body 110, and Fig. 3 is a schematic side view showing the first side surface S1 of the laminate body. One side of the laminated body in which the other end of the first internal electrode 121 is exposed may be defined as a first side S1 and one side of the laminated body in which the other end of the second internal electrode 122 is exposed, Can be defined as a second side (S2).

According to an embodiment of the present invention, the end of the internal electrode may be exposed to at least one surface of the laminate body.

Although not shown, the first or second internal electrode may be exposed to the same side of the laminate body. Or the end of the first or second internal electrode may be exposed to two or more surfaces of the laminate body.

The other ends of the first and second internal electrodes 121 and 122 exposed to the first and second side faces S1 and S2 of the laminate body 110 are respectively formed on both sides of the laminate body, 2 external electrodes 131 and 132, respectively.

4 is a cross-sectional view taken along the line A-A 'of FIG. 1, and is a cross-sectional view of the multilayer ceramic capacitor taken along the longitudinal direction (or the L direction). 5 is a cross-sectional view taken along the line B-B 'of FIG. 1, and is a cross-sectional view of the multilayer ceramic capacitor taken along the width direction (W direction).

In a region where the first and second internal electrodes 121 and 122 overlap with each other in the laminated body 110, a capacitance may be formed when an electric field is applied. In the present invention, a region in which the first and second internal electrodes 121 and 122 overlap is referred to as a capacitance forming portion E. Also, an area where the first and second internal electrodes are not overlapped with each other and only the first internal electrode or the second internal electrode is formed in the laminated body is referred to as an electrode lead-out portion. The electrode withdrawing portion may be formed by a longitudinal margin L1.

According to an embodiment of the present invention, the thickness of the capacitor forming portion E in which the plurality of internal electrodes 121 and 122 are stacked may be defined as T1. The thickness T1 of the capacitance forming portion E may be formed at the center of the laminate body and may be a distance between the internal electrodes disposed at the outermost of the laminate body. More specifically, the thickness T1 of the capacitance-forming portion E may be the distance between the inner electrode disposed at the outermost portion, for example, the uppermost layer and the lowermost layer in the region where the first and second inner electrodes overlap . The thickness T1 of the capacitance forming portion E may be defined on the intersection line of two cross sections perpendicular to each other at the central portion of the laminate body. 5 is a cross-sectional view taken along the line A-A 'and a cross-sectional view taken along the line B-B' of the laminate body. 'Direction cross-section may be the thickness T1 of the capacitance-forming portion E, as shown in FIG.

The distance between the ends of the internal electrodes disposed at the outermost one side of the laminated body may be defined as T2. More specifically, T2 is a distance between an outermost edge of the first internal electrode or an edge of the second internal electrode exposed on the outermost surface, for example, an inner electrode disposed on the uppermost layer and an inner electrode disposed on the lowermost layer, Lt; / RTI >

3, the end of the first internal electrode 121 can be exposed to the first side S1 of the laminate body, and the first internal electrode 121 disposed on the uppermost layer on the first side, The distance between the first internal electrodes 121 to be arranged may be defined as T2.

In addition, a distance (T2) between the inner electrodes disposed on the outermost side of one side of the laminated body in which the ends of the inner electrodes are exposed may be formed at a central portion of one surface of the laminated body. The distance T2 may be a distance between the center of the first internal electrode 121 disposed on the uppermost layer and the center of the first internal electrode 121 disposed on the lowermost layer on the first side.

4, the distance (T2) between the thickness T1 of the capacitance-forming portion and the internal electrodes disposed on the outermost side of one side of the laminated body in which the ends of the internal electrodes are exposed, In the same cross section. The same cross-section may be a cross-section including a surface on which the end of the internal electrode is exposed, and may be a longitudinal cross-section of the multilayer ceramic capacitor in the present embodiment.

The ratio of T2 to T1 (T2 / T1) may be 0.70 to 0.95. Though not limited thereto, the thickness T1 of the capacitance-forming portion may be 270 to 280 mu m.

A density difference is generated between the capacitor forming portion in which the first and second internal electrodes overlap with each other and the electrode withdrawing portion in which only the first internal electrode or the second internal electrode is formed. When the difference in density between the capacity-forming portion and the electrode lead-out portion increases, delamination or cracking may occur in the electrode lead-out portion. The penetration of the plating solution occurs through the interlayer peeling or cracking site, and the reliability of the multilayer ceramic capacitor may be deteriorated.

According to one embodiment of the present invention, the difference in density can be reduced by pressure-bonding the capacitance forming portion and the electrode lead portion in a differential manner. The thickness ratio of the capacitance forming portion and the electrode lead portion can be adjusted to lower the interlayer separation or cracking rate of the multilayer ceramic capacitor and increase the dielectric breakdown voltage.

If the ratio of T 2 to T 1 (T 2 / T 1) is less than 0.70, the possibility of delamination or cracking of the electrode lead-out portion is low, but the electrode lead-out portion is excessively compressed and the end portion of the internal electrode may be excessively bent. As a result, the distance between the adjacent internal electrodes becomes shorter, the dielectric layer located therebetween becomes thinner, and the electric field can be concentrated in this area. In such a case, the dielectric breakdown voltage characteristic may be deteriorated, and the characteristics under high temperature and humidity conditions may be deteriorated.

If the ratio of T 2 to T 1 (T 2 / T 1) is more than 0.95, the degree of compression of the electrode withdrawing portion is low, and there is a high possibility that delamination or cracking occurs, and the characteristics under high temperature and humidity conditions may deteriorate.

As described above, in order to reduce the size and increase the capacity of the multilayer ceramic capacitor, the thicknesses of the dielectric layer and the internal electrode layer must be made thinner and the number of stacked layers must be increased. However, as the dielectric layer and the internal electrode layer are made thinner and the number of stacked layers is increased, the difference in density between the capacitor forming portion and the electrode lead-out portion where the internal electrodes are overlapped becomes larger. As a result, delamination or cracking occurs in the electrode lead-out portion.

In addition, when the electrode withdrawing portion is excessively compressed in order to increase the density of the electrode withdrawing portion, the end of the inner electrode is excessively bent and the distance between the adjacent upper and lower inner electrodes becomes narrow. The electric field is concentrated in the region where the distance between the internal electrodes is narrowed, and in this region, there is a high possibility that insulation breakdown occurs even at a low voltage.

However, according to one embodiment of the present invention, the thickness of one dielectric layer 111 may be less than 0.65 mu m. According to an embodiment of the present invention, the thickness of one internal electrode layer may be 0.7 m or less. In addition, the dielectric layer on which the internal electrode layers are formed can be stacked by 200 layers or more.

As described above, according to the embodiment of the present invention, even if the dielectric layer and the internal electrode layer are made thin, it is possible to prevent the electric field from concentrating in a specific region by controlling the compression ratio between the capacitance forming portion and the electrode lead portion, It is possible to reduce the possibility of occurrence of cracks.

4 and 5, according to an embodiment of the present invention, the thickness D1 of the laminate body in which the capacitance forming portion E is formed may be larger than the thickness D2 of the side surface of the laminate body. The side surface of the laminate body may be a side surface in the longitudinal direction and the first side surface S1 or the second side surface S2 (see FIG. 1), in which the ends of the first internal electrode 121 or the second internal electrode 122 are exposed, ).

The thickness D1 of the laminate body on which the capacitance forming portion E is formed can form the maximum thickness of the laminate body. The thickness D2 of the side surface of the laminate body may be measured in a region where the first internal electrode or the second internal electrode exists. As shown in FIG. 3, widthwise margin portions W1 and W2 in which the first internal electrode 121 is not formed are present on the side surface of the laminated body, and the thickness D2 of the side surface of the laminated body is larger than the width- (D2) of the side surface of the laminated body in the region where the first internal electrode 121 is present rather than the first internal electrode (W1, W2).

The thickness D1 of the laminated body in which the capacitance forming portion E is formed is not limited to this, but may be 310 to 320 탆.

The thickness ratio (D2 / D1) of the side surface of the lamination body to the thickness of the lamination body having the capacity-formed portion may be 0.75 to 0.97.

If the thickness ratio (D2 / D1) of the side surface of the laminated body to the thickness of the laminate body having the capacitor forming portion is less than 0.75, the possibility of occurrence of delamination or cracking of the electrode leading portion is low. However, And there is a possibility that the characteristics under high temperature and humidity conditions may be deteriorated.

If the thickness ratio (D2 / D1) of the side surface of the laminated body to the thickness of the laminated body having the capacity-formed portion is more than 0.97, there is a high possibility that delamination or cracking will occur and the properties under high- have.

3 and 5, the thickness of the central portion of the laminate body in the width direction of the laminate body may be greater than the thickness of the end portion of the laminate body. The thickness of the central portion of the laminate body can be measured in the region where the internal electrode is present and the thickness of the end portion of the laminate body can be measured in the widthwise margin portion in which the internal electrode is not formed.

According to one embodiment of the present invention, the end of the laminate body may mean one side of the laminate body where the end of the internal electrode is not exposed.

According to an embodiment of the present invention, as shown in FIG. 3, the first inner electrode 121 (the first inner electrode 121) may be formed to have a maximum thickness D3 of the first side surface S1 of the laminate body, (D4 / D3) of the minimum thickness (D4) of the first side surface of the laminate body from which the ends of the first side faces are exposed is 0.78 to 0.95.

The maximum thickness D3 of the side surface of the lamination body may be formed in a region where the first internal electrode 121 is present and the minimum thickness D4 of the side surface of the lamination body may be a width (W1, W2).

Although not limited thereto, the maximum thickness D3 of the side surface on which the end of the first internal electrode 121 is exposed may be 200 to 300 mu m.

Although not shown, the ratio of the minimum thickness of the side surface of the second internal electrode exposed to the end of the second internal electrode to the maximum thickness of the second side surface of the laminate body where the end of the second internal electrode is exposed may be 0.78 to 0.95.

If the ratio of D4 to D3 is less than 0.78, the ends of the internal electrodes in the width direction (W direction) are excessively bent, and the interval between adjacent upper and lower internal electrodes can be reduced. As a result, an electric field is concentrated at the terminal end in the width direction of the internal electrode, so that the breakdown voltage may be lowered, and the characteristics under high temperature and humidity conditions may be deteriorated.

If the ratio of D4 to D3 exceeds 0.95, there is a high possibility that delamination or cracking will occur, and the properties under high temperature and humidity conditions may be deteriorated.

Hereinafter, a method of manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention will be described.

First, an internal electrode pattern can be formed on a plurality of ceramic green sheets. The ceramic green sheet may be formed of a ceramic paste including a ceramic powder, an organic solvent, and an organic binder.

The ceramic powder may be a material having a high dielectric constant, but not limited thereto, a barium titanate (BaTiO ₃ ) -based material, a strontium titanate (SrTiO ₃ ) -based material, or the like can be used. When the ceramic green sheet is fired, it may be a dielectric layer 111 constituting a laminated body.

The internal electrode pattern may be formed by an internal electrode paste containing a conductive metal. The conductive metal may be, but is not limited to, Ni, Cu, Pd, or an alloy thereof.

The method for forming the internal electrode pattern on the ceramic green sheet is not particularly limited, but may be formed through a printing method such as screen printing or gravure printing.

The ceramic green sheet laminate can be formed by laminating the internal electrode patterns formed on the ceramic green sheet so that the internal electrode patterns formed on the ceramic green sheet can be exposed to different sides by the subsequent cutting process. The ceramic green sheet laminate may be pressed to adjust the thickness ratio of the laminate body. As described above, according to the embodiment of the present invention, the electrode withdrawing portion can be more strongly compressed than the capacity forming portion. Further, the side surfaces and the end portions of the laminate body can be pressed more strongly than the central portion.

The pressing may be performed at a predetermined pressure. The compression may be performed by isostatic pressing, although not limited thereto. It is to be limited but are, the compression may be performed at 500 to 1500kgf / cm ² pressure condition. The subsidiary material can be applied to the upper and lower surfaces of the ceramic green sheet laminate during the compression so as to separately press the capacitance forming portion and the electrode lead portion of the laminate body during the isostatic pressing. The auxiliary material is not limited thereto, but a polyethylene terephthalate (PET) film, a vinyl film, a rubber, or the like can be used.

6 is a schematic view of the compression process in a state in which the internal electrode pattern formed on the ceramic green sheet is cut. The auxiliary material (P) may be disposed on the upper and lower portions of the ceramic green sheet laminate to press them. Further, the present invention is not limited to this, and the auxiliary material can be disposed only on the upper or lower portion of the ceramic green sheet and can be compressed.

In addition, the pressing may be performed at a predetermined temperature, but is not limited thereto, and may be performed at 50 to 100 ° C.

The ceramic green sheet laminate may be cut to form the ceramic green chip so that the lengthwise ends of the internal electrodes are exposed through the side surfaces. The ceramic green chip may be calcined and fired to form a laminated body.

The plasticizing process may be performed for the binder removal, but is not limited thereto, and may be performed in an atmospheric environment.

The firing step may be fired in a reducing atmosphere so that the internal electrodes are not oxidized. The firing may be performed at a temperature ranging from 900 to 1300 ° C.

Next, the external electrode may be formed to be electrically connected to the end of the internal electrode exposed at the side surface of the laminate body. Thereafter, plating of nickel, tin, or the like can be performed on the surface of the external electrode.

Hereinafter, the present invention will be described in more detail with reference to examples and comparative examples, but the scope of the present invention is not limited by the examples in order to facilitate a specific understanding of the invention.

[Example]

The internal electrode paste was printed on a ceramic green sheet having a thickness of 1.27 mu m, 1.20 mu m, 1.00 mu m, 0.90 mu m and 0.80 mu m, respectively, before baking, and then 220 to 270 layers were laminated to produce a ceramic laminate. The ceramic laminate was subjected to isostatic pressing at 85 DEG C under a pressure of 1000 kgf / cm < ² >. At this time, a PET film, a vinyl film, and a rubber auxiliary material were separately applied to the upper and lower surfaces of the ceramic laminate in order to strengthen the compression of the electrode lead-out portion, and the thickness of the laminate main body formed with the capacity forming portion was formed larger than the thickness of the side surface of the laminate body.

The pressed ceramic laminate was cut into individual chips, and the cut chips were maintained at 230 DEG C for 60 hours in an atmospheric environment to carry out the binder removal. Then, at 1200 ° C, the internal electrodes were fired in a reducing atmosphere under an oxygen partial pressure of 10 ^-11 atm to 10 ^-10 atm, which is lower than the Ni / NiO equilibrium oxygen partial pressure. The average thickness of the dielectric layers after firing was 0.45 to 0.70 mu m, and the average thickness of the internal electrode layers was 0.65 mu m. The fired chip size was 0.6 ± 0.09 mm × 0.3 ± 0.09 mm × 0.3 ± 0.09 mm (L × W × T).

The properties of the fired chip were evaluated, and the results are shown in Tables 1 and 2 below.

The thickness of one dielectric layer after firing was measured as the average thickness of one dielectric layer disposed between the internal electrode layers. As shown in FIG. 4, the average thickness of the one dielectric layer was measured by scanning an image with a Scanning Electron Microscope (SEM) at a magnification of 10,000 at a longitudinal cross section of the laminate body, The thickness was measured at 30 points and the average value was measured. Thirty points, which are the equidistant intervals, are designated in the capacity forming section.

The peeling or cracking rate of the fired chip was examined on one side of 100 plastic chips, and the occurrence rate of peeling and cracking was expressed as a percentage.

The Breakdown Voltage (BDV) characteristics were evaluated by applying a DC voltage at a rate of 10 V / sec. The high temperature acceleration characteristics were evaluated by the NG rate according to the high temperature acceleration test. For 200 fired chips, 9.45 V DC voltage was applied, and the number of plastic chips in which the insulation resistance dropped to 10 ⁴ Ω or less within 48 hours was expressed as a percentage.

Humidity load characteristics were evaluated by the NG rate according to the humidity resistance load test. The number of plastic chips with insulation resistance of less than 10 ⁴ Ω within 100 hours after application of 6.3 V DC voltage at 40 ° C. and 95% As a percentage.

Dielectric Thickness (um) T1 T2 T2 / T1 D1 D2 D2 / D1 D3 D4 D4 / D3 Comparative Example 1 0.70 275 267 0.97 315 309 0.98 309 299 0.97 Comparative Example 2 0.70 276 235 0.85 313 272 0.87 272 234 0.86 Comparative Example 3 0.70 274 200 0.73 316 237 0.75 237 175 0.74 Comparative Example 4 0.70 274 170 0.62 314 204 0.65 204 137 0.67 Comparative Example 5 0.65 276 270 0.98 316 313 0.99 313 310 0.99 Comparative Example 6 0.65 275 237 0.86 314 276 0.88 276 240 0.87 Comparative Example 7 0.65 275 204 0.74 315 239 0.76 239 184 0.77 Comparative Example 8 0.65 273 177 0.65 312 212 0.68 212 138 0.65 Comparative Example 9 0.55 275 270 0.98 315 312 0.99 312 309 0.99 Example 1 0.55 276 262 0.95 316 307 0.97 307 291 0.95 Example 2 0.55 274 227 0.83 313 269 0.86 269 229 0.85 Example 3 0.55 276 204 0.74 314 245 0.78 245 196 0.80 Example 4 0.55 275 193 0.70 315 236 0.75 236 184 0.78 Comparative Example 10 0.55 274 178 0.65 314 220 0.70 220 169 0.77 Comparative Example 11 0.55 277 161 0.58 314 198 0.63 198 138 0.70 Comparative Example 12 0.50 275 267 0.97 313 310 0.99 310 304 0.98 Example 5 0.50 273 259 0.95 314 305 0.97 305 292 0.96 Example 6 0.50 274 238 0.87 312 281 0.90 281 256 0.91 Example 7 0.50 275 212 0.77 314 242 0.77 242 181 0.75 Comparative Example 13 0.50 276 188 0.68 315 224 0.71 224 161 0.72 Comparative Example 14 0.50 273 161 0.59 312 197 0.63 197 128 0.65 Comparative Example 15 0.45 270 265 0.98 310 307 0.99 307 301 0.98 Example 8 0.45 272 253 0.93 314 298 0.95 298 277 0.93 Example 9 0.45 271 233 0.86 313 275 0.88 275 240 0.87 Example 10 0.45 270 197 0.73 312 234 0.75 234 171 0.73 Comparative Example 16 0.45 270 186 0.69 310 226 0.73 226 163 0.72 Comparative Example 17 0.45 272 163 0.60 311 202 0.65 202 135 0.67

Number of layers Delam / Crack incidence (%) BDV (V) NG rate of high-temperature acceleration test (%) Humidity load test NG rate (%) Comparative Example 1 220 0 85 0 0 Comparative Example 2 220 0 83 0 0 Comparative Example 3 220 0 83 0 0 Comparative Example 4 220 0 85 0 0 Comparative Example 5 230 0 76 0 0 Comparative Example 6 230 0 78 0 0 Comparative Example 7 230 0 79 0 0 Comparative Example 8 230 0 77 0 0 Comparative Example 9 250 18 73 12.5 24.5 Example 1 250 0 75 0 0 Example 2 250 0 72 0 0 Example 3 250 0 71 0 0 Example 4 250 0 72 0 0  Comparative Example 10 250 0 32 24.5 10.5 Comparative Example 11 250 0 24 32.5 12.0  Comparative Example 12 260 20 68 10.5 20.5 Example 5 260 0 67 0 0 Example 6 260 0 68 0 0 Example 7 260 0 63 0 0  Comparative Example 13 260 0 30 36.5 20.0  Comparative Example 14 260 0 25 32.0 21.5 Comparative Example 15 270 23 62 15.5 28.5 Example 8 270 0 62 0 0 Example 9 270 0 61 0 0 Example 10 270 0 60 0 0  Comparative Example 16 270 0 27 42.5 25.5 Comparative Example 17 270 0 18 43 29

D1 is the thickness of the laminated body formed with the capacitor forming portion; D2 is the thickness of the laminated body on which the end of the internal electrode is exposed; D3 is the maximum thickness of one side of the laminated body in which the ends of the internal electrodes are exposed, and D4 is the minimum thickness of one side of the laminated body in which the ends of the internal electrodes are exposed.

As shown in FIG. 4, T1, T2, D1, and D2 are measured in a longitudinal cross-sectional view of the center portion of the laminated body in which the ends of the internal electrodes are exposed. D3 and D4 are measured, Respectively.

Referring to Tables 1 and 2, in Comparative Examples 1 to 8 in which the thickness of the dielectric layer after firing was not less than 0.65 탆, peeling and cracks did not occur regardless of the ratio of T1 and T2, BDV was high, And the humidity load NG rate did not occur.

On the contrary, in Comparative Example 9, Comparative Example 12 and Comparative Example 15 in which the thickness of the dielectric layer after firing was 0.65 탆 or less, the compressibility of the electrode lead-out portion was small and the occurrence rate of peeling or cracking was high, and the high temperature acceleration property and moisture resistance load characteristic were deteriorated. In Comparative Example 10, Comparative Example 11, Comparative Example 13, Comparative Example 14, Comparative Example 16, and Comparative Example 17, the compressibility of the electrode withdrawing portion was large and no peeling or crack occurred. However, BDV characteristics were degraded due to excessive compression, The NG rate of the high temperature acceleration test and the NG rate of the humidity resistance load test were high. It is judged that the electric field concentration occurs as the lengthwise end of the internal electrode is bent and the dielectric layer is thinned.

In Examples 1 to 10, the compression ratio of the capacitor forming portion and the electrode leading portion was adjusted, so that peeling or cracking did not occur. There was no phenomenon that the end of the internal electrode bends toward the width direction or the longitudinal direction margin portion, . As a result, the BDV characteristics did not deteriorate, the high-temperature acceleration characteristics and the moisture-proof load characteristics were excellent, and the reliability was not deteriorated by penetration of the plating solution.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

110: laminated body 111: dielectric layer
121, 122: first and second inner electrodes 131, 132: first and second outer electrodes
E: Capacitor forming portion W1, W2: width direction margin portion
L1: longitudinal margin portion

Claims (22)

A laminated body including a dielectric layer; And
And a plurality of internal electrode layers formed inside the laminate body and having ends exposed at at least one surface of the laminate body,
And a distance between the end of the internal electrode layer disposed on the outermost side of one side of the laminated body in which the end of the internal electrode layer is exposed is T2, the thickness of the capacitance forming portion formed by overlapping the plurality of internal electrode layers is T1, T1 is a distance between the internal electrode layers disposed at the outermost portion in the center portion of the laminate body, a ratio (T2 / T1) of T2 to T1 is not less than 0.70,
The maximum thickness of the laminate body having the capacitor forming portion formed thereon is D1 and the thickness of one surface of the laminate body where the ends of the internal electrodes are exposed is D2, D1 is larger than D2 and D2 / D1 ) Of 0.75 or more.
The method according to claim 1,
And a ratio of T2 to T1 (T2 / T1) is 0.95 or less.
The multilayer ceramic electronic part according to claim 1, wherein a ratio (D2 / D1) of D2 to D1 is 0.97 or less.
The method according to claim 1,
Wherein a thickness T1 of the capacitance forming portion is measured as a distance between an internal electrode layer disposed on the uppermost layer and an internal electrode layer disposed on the lowermost layer on the intersection line of two cross sections perpendicular to each other at the central portion of the laminated body.
The method according to claim 1,
The distance (T2) between the thickness (T1) of the capacitance forming portion and the internal electrode layers disposed on the outermost side of one side of the laminate main body in which the ends of the internal electrode layers are exposed is smaller than a distance (T2) .
The method according to claim 1,
Wherein the distance (T2) between the inner electrode layers disposed on the outermost side of one side of the laminated body in which the ends of the internal electrode layers are exposed is formed at a central portion of one surface of the laminated body.
The method according to claim 1,
Wherein the thickness of the laminate body on which the capacitance forming portion is formed is 310 to 320 mu m.
The method according to claim 1,
Wherein the thickness of the laminate body having the capacitance-forming portions formed therein is larger than the thickness of one surface of the laminate body where the ends of the internal electrode layers are not exposed.
The method according to claim 1,
And the thickness (T1) of the capacitance-forming portion is 270 to 280 mu m.
The method according to claim 1,
Wherein a ratio of a minimum thickness of the one surface of the layered body to a maximum thickness of one surface of the layered body where ends of the internal electrode layers are exposed is 0.78 to 0.95.
11. The method of claim 10,
Wherein a minimum thickness of one surface of the laminate body is formed in a margin portion in which the internal electrode layer is not formed.
The method according to claim 1,
Wherein a thickness of the dielectric layer disposed between the internal electrode layers is less than 0.65 mu m.
The method according to claim 1,
Wherein the one internal electrode layer has a thickness of 0.7 mu m or less.
A laminated body having first and second side faces; And
And a plurality of first and second internal electrode layers formed inside the stack body and each having ends exposed to the first and second sides,
The thickness of the capacitance forming portion formed by overlapping the plurality of first and second internal electrode layers is T1 and the thickness of the first internal electrode layer end or the second internal electrode layer disposed at the outermost portion of the first side surface or the second side surface of the laminate body (T2 / T1) of T1 with respect to T1 is not less than 0.70, and T1 is a distance between the end portions of the internal electrode layers, The distance between the adjacent first and second internal electrode layers is less than 0.65 mu m,
D3 is the maximum thickness of the first side face of the laminated body in which the end of the first internal electrode layer is exposed and D3 is the minimum thickness of the first side face of the laminated body in which the end of the first internal electrode is exposed, And the ratio (D4 / D3) of D4 to D3 is 0.78 or more.
15. The method of claim 14,
And a ratio (T2 / T1) of T2 to the T1 is 0.70 or less.
15. The method of claim 14,
And the ratio (D4 / D3) of D4 to D3 is 0.95 or less.
15. The method of claim 14,
The distance (T2) between the thickness (T1) of the capacitance forming portion and the end of the first internal electrode layer or the end of the second internal electrode layer disposed at the outermost side in the first side surface or the second side surface of the laminate body, Lt; RTI ID = 0.0 > cross-section < / RTI >
15. The method of claim 14,
Wherein a thickness of the center portion of the lamination body is greater than a thickness of the end portion of the lamination body in the width direction of the lamination body.
A laminated body having three pairs of faces facing each other;
A plurality of first and second internal electrode layers formed in the laminated body and each having a terminal end exposed on at least one surface of the laminated body; And
And a plurality of dielectric layers disposed between the first and second internal electrode layers and having a thickness of less than 0.65 mu m,
The thickness of the capacitance forming portion in which the plurality of first and second internal electrode layers are superimposed is T1 and the thickness of the first internal electrode layer or the second internal electrode layer disposed at the outermost portion of one side of the laminated body, And T1 is the distance between the inner electrode layers disposed at the outermost portion in the center portion of the laminate body and the ratio of T2 to T1 (T2 / T1) is not less than 0.70,
D2 is the thickness of one side of the laminate body where the ends of the first and second internal electrode layers are exposed, D2 is greater than D2, And a ratio (D2 / D1) of 0.75 or more.
20. The method of claim 19,
Wherein the thickness of the laminate body having the capacitor forming portion is greater than the thickness of one surface of the laminate body where the end of the internal electrode layer is not exposed.
20. The method of claim 19,
And the ratio of T2 to T1 (T2 / T1) is 0.95 or less.
20. The method of claim 19,
And a ratio (D2 / D1) of D2 to D1 is 0.97 or less.

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