KR20170126505A - Method for coating semiconductor wafers - Google Patents

Abstract

The present invention relates to a method for coating each of semiconductor wafers 120 with an epitaxially deposited layer in an epitaxy reactor (100). In the coating process, at least one semiconductor wafer 120 is arranged on each susceptor 110 in the epitaxy reactor 100, and a first deposition gas for coating at least one semiconductor wafer 120 is deposited on the epitaxial reactor 100, A cleaning process is performed in each of the plurality of coating processes after passing through the taxi reactor 100. In the cleaning process, the first etching gas and then the second deposition gas are passed through the epitaxy reactor 100, Between two successive scrubbing processes, at least one intermediate scrubbing process is now performed, and in the intermediate scrubbing process, between two immediate sequential coating processes, the deposition gas does not pass through the epitaxy reactor 100 2 etch gas passes through the epitaxy reactor 100.

Description

Method for coating semiconductor wafers

The present invention relates to a method of coating each of semiconductor wafers with an epitaxially deposited layer in an epitaxy reactor.

Epitaxially coated semiconductor wafers, in particular silicon wafers, are suitable for use in, for example, the semiconductor industry, and are particularly suitable for the manufacture of high-density integrated electronic components, such as microprocessors or memory chips. In the case of modern microelectronics, a starting material with stringent requirements for global and local planarity, edge geometry, thickness distribution, one-sided local planarity, so-called nanotopology, and integrity, A substrate is required.

For epitaxial coating of a semiconductor wafer in an epitaxy reactor, deposition gas is passed through the epitaxial reactor so that the epitaxial material can be deposited on the surface of the semiconductor wafer. However, the epitaxial material is deposited not only on the semiconductor wafer, but also inside the epitaxial reactor. For this reason, it is generally necessary to periodically remove these residues accumulated on these surfaces from the surfaces in the epitaxial reactor in an uncontrolled manner during deposition.

For example, DE 10 2010 006 725 A1 discloses that in a cleaning process, each of which is repeated after a certain number of coated semiconductor wafers while the dummy wafers are arranged on the susceptor of the epitaxy reactor, Lt; RTI ID = 0.0 > epitaxy < / RTI > reactor through a reactor and then a deposition gas for deposition of silicon.

For example, to prevent impurities diffusing from the surfaces into the epitaxial layer from reaching the semiconductor wafer to be coated later, through the etching gas, such as, for example, hydrogen chloride, the residue of the previous coating processes is removed And through the deposition gas, the interior of the epitaxial reactor can be sealed.

However, nonetheless, during coating of the semiconductor wafers, a geometric change occurs between the individual semiconductor wafers. In particular, in the edge regions of the coating, there are significant differences, which are detrimental to the quality of the coated semiconductor wafers. For example, the edge area can not be used accordingly, or can only be used in applications with low quality requirements.

For example, US 2009/0252942 A1 discloses a method in which an attempt is made to coat the edge regions of semiconductor wafers in a controlled manner by controlled setting of the gas flow rate of the deposition gas for depositing the epitaxial layer.

Thus, it is desirable to provide the possibility of avoiding or at least reducing the geometric variation of epitaxially coated semiconductor wafers.

According to the present invention, a method of coating semiconductor wafers having the features of claim 1 is proposed. Advantageous embodiments of the invention are dependent claims and the following inventions.

A suitable method is proposed for coating semiconductor wafers with epitaxially deposited layers within an epitaxy reactor, respectively. In this case, in the coating process, at least one semiconductor wafer is arranged on each susceptor in the epitaxy reactor, and a first deposition gas for coating at least one semiconductor wafer is passed through the epitaxy reactor. After each of the plurality of coating processes, after the removal of the coated semiconductor wafer (s), a cleaning process is performed, wherein a first etching gas and then a dummy wafer are arranged on each susceptor Respectively, a second deposition gas passes through the epitaxy reactor. In this case, a protective layer is deposited on the susceptor, in particular in the region around the bearing surface of the dummy wafer. The protective layer is preferably a thickness of 5 탆 to 15 탆, particularly preferably about 10 탆. The dummy wafer preferably comprises a semiconductor material or other material of the semiconductor wafer. According to the present invention, between two successive scrubbing processes, at least one intermediate scrubbing process is now carried out, wherein, between two immediate sequential coating processes, the deposition gas does not pass through the epitaxial reactor, The etching gas passes through the epitaxy reactor. In other words, at least one intermediate cleaning process is comparable to the cleaning process, but the deposition gas is not passed. In addition, the period of time during which the etching gas passes during the intermediate cleaning process can sometimes be significantly different from that of the cleaning process, and can be particularly degraded.

In this case, it has been found that the geometric change in the coated semiconductor wafers, especially in the edge region, is caused by the modified thermal and / or flow conditions of the deposition gas. The reason for the deformed conditions in this case lies in the material deposited during the coating processes, especially in the region around the bearing surface of the semiconductor wafers on the susceptor. As each new semiconductor wafer is coated, the thickness of the deposited material in the area around the semiconductor wafer increases, while each newly arranged semiconductor wafer is always the same in thickness. Through at least one intermediate cleaning process, the material in question can now be reduced in a defined manner, or preferably even entirely, so that the conditions for the individual coating processes become similar to each other. A defined reduction in the material in question is intended to mean a reduction of more than 50%, in particular a reduction of more than 70% to more than 90%. In this way, the change in the geometry of the semiconductor wafers can be significantly reduced. In this case, it is preferred that at least one intermediate cleaning step is performed without a dummy wafer, since the area around the bearing surface of the semiconductor wafer on the susceptor can be particularly effectively cleaned.

In this case, it is also advantageous that the dummy wafers are arranged on the respective susceptors while the first etching gas passes during each cleaning process. These dummy wafers may then remain, for example, arranged on the susceptor as the second deposition gas is subsequently passed through. Thus, during the cleaning process it is possible to ensure, on each susceptor, that each of the bearing surfaces, on which the semiconductor wafers are respectively placed during the coating process, remain as unchanged as possible in terms of removal and / or deposition of the material . Thus, the maximally optimized conditions in the coating processes can be achieved.

Preferably, between two successive cleaning processes, an intermediate cleaning process is performed after each coating process. In this way, the same starting conditions can be established for each coating process, so that changes in the geometry of the semiconductor wafers are prevented or at least greatly reduced. In this case, for example, an intermediate cleaning process may also be performed only after each second coding step or every third coating step, thereby allowing fine changes in the geometry of the semiconductor wafers, It should be noted that a higher throughput of semiconductor wafers to be achieved may nevertheless be achieved.

Preferably, during the at least one intermediate cleaning process, the second etching gas is introduced into the epitaxial reactor in a manner such that the material deposited by passage of the deposition gas inside the epitaxial reactor after the previous intermediate cleaning process is reduced or preferably eliminated. It passes through the taxi reactor. In this way, the protective layer, which is preferably produced to reach about 10 mu m during the cleaning process, is preserved in the epitaxy reactor and only the material of the problem deposited during the coating processes is reduced or preferably eliminated. This can be done advantageously by setting the duration of the passage of the etching gas and / or by setting the gas flow rate of the etching gas. This duration depends on the frequency of the intermediate cleaning processes, in this case, or the number of semiconductor wafers coated after the last cleaning or intermediate cleaning process. In this case, the gas flow rate is intended to mean, in particular, the volume of gas per unit time expressed in volumetric flow rate, i.e., standard liters per minute (slm). Generally, the gas flow rate is in the range of 5 slm to 30 slm, and the duration is in the range of 20 s to 40 s.

In this case, in particular, at least one material deposited in the region around the bearing surface for the semiconductor wafers on each susceptor is reduced or preferably removed because the material deposited in this region is predominantly on the edge of the semiconductor wafers Because it changes the thermal and / or flow conditions of the deposited gases in the region, which causes the geometry change of the problem of the semiconductor wafers. In this case, the area around the bearing surface for semiconductor wafers can be understood as an annular area on the susceptor outside the bearing surface for semiconductor wafers, e.g., 10 mm radius or 20 mm radius.

During the coating process, it is advantageous when 1 占 퐉 to 10 占 퐉, particularly 2 占 퐉 to 5 占 퐉, layers are deposited on at least one semiconductor wafer, respectively. These are desirable values for the thickness of the epitaxial layers on semiconductor wafers.

Preferably, the cleaning process is carried out after 8 to 30 coating processes, respectively, especially after 10 to 15 coating processes, respectively. This corresponds, for example, to an average thickness of 30 to 70 mu m of the deposited material inside the epitaxy reactor, if no intermediate cleaning process is performed. The frequency of cleaning processes can be selected according to the epitaxial reactor used, to enable the precise flow of the deposition gas across all coating processes. In this case, it should be noted that the reduction and preferably the removal of the deposited material in the region around the bearing surface of the semiconductor wafers on each susceptor is the main objective of intermediate cleaning processes. In this regard, a quantity of material similar to that without an intermediate cleaning process may possibly be deposited in other areas of the epitaxy reactor. On the other hand, shorter cleaning processes may be possible as a result of vast number of intermediate cleaning processes.

Advantageously, hydrogen chloride is used as the first etching gas and / or the second etching gas. In this way, the material deposited inside the epitaxy reactor can be particularly efficiently removed. The etching gas may pass through the epitaxial reactor by itself or with a carrier gas, for example, hydrogen. In this case, the volumetric flow rate of the carrier gas is preferably 5 slm to 8 slm.

It is advantageous for silicon wafers to be used as semiconductor wafers because they are preferred materials for conventional semiconductor applications. Preferably, then other gases of trichlorosilane or silicon compounds are used as the first deposition gas and / or as the second deposition gas.

Other advantages and configurations of the invention can be found in the detailed description and the accompanying drawings.

It is to be understood that the above-described features and features described below may be utilized in different combinations, or individually, as well as in each indicated combination, without departing from the scope of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated schematically with the aid of an exemplary embodiment of the drawings, and will be described below with reference to the drawings.

Figure 1 schematically shows an epitaxy reactor in which the process according to the invention can be carried out.
Figure 2 schematically shows details of a coated semiconductor wafer on a susceptor of an epitaxy reactor.
Fig. 3 diagrammatically illustrates the difference in edge roll-off Δ of the series of semiconductor wafers of silicon that have not been coated by the method according to the invention, before and after each coating process.
Figure 4 shows diagrammatically the difference Δ of the edge roll-off before and after each coating process for a series of semiconductor wafers of silicon that had been coated by the method according to the preferred embodiment of the present invention.

Figure 1 schematically shows, by way of example, an epitaxial reactor 100 in which the method according to the present invention can be carried out, in cross section, for example. In the middle of the epitaxy reactor 100, there is a susceptor 110 on which semiconductor wafers 120 to be coated, for example, silicon wafers, can be arranged, i.e., disposed. In this case, depending on the size of the epitaxy reactor, the semiconductor wafers may have diameters up to, for example, 450 mm. In this case, the susceptor 110 has a center concave portion such that the semiconductor wafer 120 is supported on the susceptor 110 only in the area of several millimeters from the edge of the susceptor 110, for example.

In this example, gas may pass through the epitaxy reactor 100 from the left opening to the right opening of the epitaxy reactor 100, as indicated by the two arrows. (For example, by way of example, reference is provided to one of these) of heating means, for example, heating lamps 130 on the top and bottom surfaces of the epitaxy reactor 100, The gas can, if necessary, be brought to the desired temperature.

A first deposition gas, e. G., Trichlorosilane, optionally mixed with hydrogen, is passed through the epitaxy reactor 100 to coat the semiconductor wafer 120. In this case, the gas flow rate, the period of time through which the gas passes, and the temperature can be adjusted, for example, according to the desired thickness of the layer to be epitaxially deposited on the semiconductor wafer 120. A thickness often desired for the epitaxial layer is, for example, 4 占 퐉. Generally, for this layer, a gas flow rate of about 15 slm of trichlorosilane is desired for a duration of about 100 s. Further, the susceptor 110 in which the semiconductor wafers 120 are arranged can be rotated about an axis as shown in the figure. In this way, uniform deposition of the epitaxial layer can be achieved.

This coating process is repeated for additional semiconductor wafers. After a plurality of, for example, 10 to 12 coating processes (each having an epitaxial layer of 4 [mu] m on each semiconductor wafer), a total of about 40 [mu] m to 50 [ And similarly deposited within the epitaxy reactor 100.

A cleaning process is performed to clean the epitaxy reactor 100, i.e., to remove or at least reduce undesired material, e.g., after 10 or 12 coating processes, during which the first etch Gas, such as hydrogen chloride, initially passes through the epitaxy reactor 100. In this manner, unwanted materials within the epitaxy reactor 100 can be removed or at least reduced. Through proper adjustment of the duration and the gas flow rate, this material can be completely removed.

Subsequently, within the epitaxy reactor 100, to deposit a defined material layer, for example a silicon layer, within the range of the cleaning process and in the presence of a dummy wafer lying on the susceptor, A gas, such as trichlorosilane, also passes through the epitaxy reactor 100. This layer is used for sealing to prevent impurities diffusing from the surfaces inside the epitaxy reactor 100 from entering the epitaxial layer on later semiconductor wafers to be coated. To achieve this sealing layer having a thickness of about 10 microns, trichlorosilane can pass through the epitaxy reactor at a gas flow rate of 29 slm (standard liters per minute), for example, for a duration of 200 seconds . A dummy wafer is arranged on the susceptor 110 instead of the semiconductor wafer 120 while the second deposition gas is passed through so that no deposited material remains on the bearing surface for the semiconductor wafers and a protective layer is formed. Alternatively, the dummy wafer may also be arranged on the susceptor 110 during the passage of the first etching gas.

FIG. 2 schematically shows details of a semiconductor wafer 120 on a susceptor 110 of an epitaxy reactor 100. On the semiconductor wafer 120 is an epitaxially deposited layer 121. It should be noted that the dimensional ratios shown here are not real scale.

Here, it can be seen that the thickness of the epitaxial layer 121 decreases at the edge (left side in the drawing). The reason for this is the flow conditions of the deposition gas during the coating of the semiconductor wafer, for example, the flow conditions at the edge of the semiconductor wafer and the flow conditions on the surface of the semiconductor wafer are different. In addition, there is an unwanted material (140) on the susceptor (110) in the region around the bearing surface of the semiconductor wafer (120). As already mentioned, this material 140 is deposited during coating processes.

However, from now on, while the new semiconductor wafer 120 is arranged on the susceptor 110 during each coating process, the thickness of the deposited material 140 increases with each coating process. This increase in material 140 is indicated by dashed lines in the figure. During each coating process, this leads to deformed temperature fields and strained flow conditions of the deposition gas, particularly at the edge regions of the semiconductor wafer 120. Thus, as indicated by, for example, the dashed lines, more material 140 causes a larger edge roll-off of epitaxial layer 121. [

In a preferred embodiment of the method according to the present invention, a second etching gas, for example hydrogen chloride, is now passed through the epitaxy reactor 100 between the two cleaning processes, after each coating process, So that the deposited material 140 during the last coating process is reduced and preferably removed again. In this case, neither the dummy wafer nor the semiconductor wafer is arranged on the susceptor 110. In this case, care should be taken to ensure that the protective layer applied in the previous cleaning process is preserved and, as far as possible, only the material deposited during the last coating process is removed, for example by appropriately selecting the duration and the gas flow rate. In this case, since the deposition gas is during the cleaning process, it is not passed before coating the next semiconductor wafer.

In this way, the starting situation during coating of semiconductor wafers is the same for each coating process. Thus, geometric changes in semiconductor wafers, particularly edge regions, are avoided or at least substantially reduced. For completeness, it should also be mentioned that no intermediate cleaning process is logically required prior to the cleaning process after the last coating process.

3, in a diagram for a series of n consecutive coating processes, the edge roll-off difference? (Nm / mm ² units) of the coated semiconductor wafers, when the intermediate cleaning process is not performed between successive coating processes ZDD, i. E., Expressed in the form of a difference in the amount of the measurement describing the curvature of the edge region) is tabulated for the number of times n of the coating processes. In this case, the edge rolloff decreases from the first coating process (after the cleaning process) (left in the figure) to the coating process (from the right in the drawing), thus showing considerable variation.

4, in the diagram for a series of n consecutive coating processes, the edge of the nm / mm ² unit of coated semiconductor wafers, when the procedure is carried out according to the method according to the above described preferred embodiment of the present invention The roll-off difference Δ (expressed as the difference in ZDD) is tabulated for the number of times n of the coating processes. In this case, the edge rolloff is relatively constant from the first coating process after the cleaning process (on the left in the figure) to the coating processes (on the right in the figure), thus seeing a much lower variation than without the intermediate cleaning processes .

Claims (11)

A method for coating semiconductor wafers (120) with an epitaxially deposited layer (121) within an epitaxy reactor (100), the method comprising:
In the coating process, at least one semiconductor wafer 120 is arranged on each susceptor 110 in the epitaxy reactor 100, and a first deposition gas (not shown) for coating the at least one semiconductor wafer 120 Passes through the epitaxy reactor 100,
In each of the plurality of coating processes subsequent to the cleaning process, a cleaning process is performed, wherein the cleaning process passes a first etching gas and then a second deposition gas through the epitaxy reactor 100,
Between two successive scrubbing processes, at least one intermediate scrubbing process is carried out, in which the intermediate scrubbing process, between two immediate sequential coating processes, is carried out without the deposition gas passing through the epitaxy reactor 100 Wherein a second etch gas is passed through the epitaxial reactor (100). ≪ Desc / Clms Page number 19 > The method according to claim 1,
Wherein during each cleaning process a dummy wafer is arranged on each susceptor while the first etching gas and / or the second etching gas are being passed, with the epitaxially deposited layer (121) (120). ≪ / RTI > 3. The method according to claim 1 or 2,
A method for coating semiconductor wafers (120) with an epitaxially deposited layer (121), wherein an intermediate cleaning process is performed between two successive cleaning processes, after each coating process. 4. The method according to any one of claims 1 to 3,
Wherein during the at least one intermediate cleaning process the material deposited 140 by the passage of a deposition gas inside the epitaxy reactor 100 after the previous intermediate cleaning process is reduced or removed, Is passed through the epitaxial reactor (100). ≪ RTI ID = 0.0 > [0002] < / RTI > 5. The method of claim 4,
Wherein at least one material (140) deposited in a region around a bearing surface for each of the semiconductor wafers (120) on the susceptor (110) is reduced or removed, the epitaxially deposited layer 121). ≪ / RTI > The method according to claim 4 or 5,
Wherein the deposited material (140) is reduced or removed by setting a passage duration of the second etching gas and / or by setting a gas flow rate of the second etching gas. (121). ≪ / RTI > 7. The method according to any one of claims 1 to 6,
During the coating process, a layer 121 of 1 占 퐉 to 10 占 퐉, in particular 2 占 퐉 to 5 占 퐉, is deposited on the at least one semiconductor wafer 120, respectively, with the epitaxially deposited layer 121, (120). ≪ / RTI > 8. The method according to any one of claims 1 to 7,
The cleaning process is performed after 8 to 30 coating processes, respectively, in particular after 10 to 15 coating processes, respectively, coating the semiconductor wafers 120 with the epitaxially deposited layer 121, respectively Way. 9. The method according to any one of claims 1 to 8,
Wherein hydrogen chloride is used as said first etch gas and / or said second etch gas. ≪ Desc / Clms Page number 24 > 10. The method according to any one of claims 1 to 9,
Wherein the silicon wafers are used as the semiconductor wafers (120). ≪ Desc / Clms Page number 19 > 10. The method of claim 9,
Wherein the first deposition gas and / or the second deposition gas comprises trichlorosilane. ≪ RTI ID = 0.0 > 11. < / RTI >

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