TW202022174A - Process for producing an epitaxially coated semiconductor wafer - Google Patents

Abstract

A process for producing an epitaxially coated semiconductor wafer, wherein the surface roughness of the epitaxially deposited layer is adjusted during the cooling operation in the reactor chamber specifically through the introduced hydrogen flow and simultaneously through the cooling rate during cooling.

Description

Method for manufacturing epitaxially coated semiconductor wafer

The present invention relates to a method for manufacturing an epitaxially coated semiconductor wafer having an epitaxially deposited layer with a defined surface roughness (haze).

The fields of electronics, microelectronics and microelectromechanics require global and local planarity (global and local planarity), one-sided local planarity (nanotopography), roughness Semiconductor wafers (wafers) that have extreme requirements for cleanliness and other aspects are used as starting materials (substrates). Semiconductor wafers are wafers of semiconductor materials, especially compound semiconductors (such as gallium arsenide) and predominantly elemental semiconductors (such as silicon and occasionally germanium).

According to the prior art, semiconductor wafers are manufactured in a number of continuous process steps, which can generally be classified into the following groups: a) Manufacturing single crystal semiconductor rods (crystal growth); b) Cut the rod into individual wafers; c) Mechanical treatment; d) Chemical treatment; e) Chemical-mechanical treatment; f) Manufacture of layer structure as required.

Semiconductor wafers are usually provided with an epitaxial layer, that is, a monocrystalline overlayer with the same crystal orientation, on which semiconductor components are subsequently applied. If the covering layer is composed of the same material as the substrate, it is homoepitaxy, otherwise, it is heteroepitaxy. Such epitaxially coated semiconductor wafers exhibit some advantages over semiconductor wafers composed of homogeneous materials, such as preventing charge reversal in bipolar CMOS circuits and subsequent short circuits of components ("Latch “Latch-up” issues), low defect density (such as reduced number of COPs (“crystal-originated particles”), and no significant oxygen content, which makes it possible to exclude areas related to parts The risk of short circuit caused by oxygen deposition in.

The application of the epitaxial layer on the surface of the semiconductor wafer is carried out in an epitaxial reactor, and usually includes the following steps: Passing the etching gas through the epitaxial reactor to remove residues on the surface in the epitaxial reactor by the action of the etching gas; Passing the first deposition gas through the epitaxial reactor to deposit, for example, silicon on the surface in the epitaxial reactor; Place a substrate wafer made of, for example, silicon on the susceptor of the epitaxial reactor; and Pass the second deposition gas to deposit the epitaxial layer on the substrate wafer.

For example, EP 1 533 836 A1 and US 2012/0104565 A1 describe processes for epitaxial coating of wafers.

The epitaxial process also affects the surface roughness of the substrate wafer. Roughness (haze) can be measured by optical or electronic methods, such as electron scattering methods. Optical methods usually use scattered light to measure, and the surface roughness has a decisive influence on the measurement. Compared with a smooth surface that reflects only in the main direction, a rough surface has higher diffuse reflection in all directions.

According to DE 697 02 620 T2, the temperature of the substrate wafer during epitaxial deposition should be 900°C to 1100°C. When it is lower than 900°C, the surface roughness of the epitaxial deposition layer will appear, and when it is higher than 1100°C, the amount of particles formed by side reactions increases, thereby reducing the quality of the epitaxial deposition layer.

Patent specification US 6,217,650 B1 teaches a method for manufacturing epitaxial silicon wafers with low surface roughness. For silicon wafers with <100> orientation, when the deposition temperature is 50°C to 100°C lower than the normal temperature, the roughness of the epitaxial deposition layer is reduced. The normal temperature is, for example, for dichloride Dichlorosilane as the source gas is 950°C to 1050°C.

However, the deposition temperature/growth temperature of the epitaxial layer is an important influencing factor, especially in the temperature range of 900°C to 1100°C, which makes the growth rate and therefore the epitaxial deposition layer at very low deposition temperatures The thickness can only be controlled precisely with great difficulty. In particular, the deposition rate in this temperature range seems to depend significantly on the orientation of the crystal, as a result of which the geometry of the wafer has so-called fourfold symmetry. Therefore, there are regions where the deposition layer is thicker and regions where the deposition layer is thinner.

US 2012/0104565 A1 discloses a method for manufacturing epitaxial-coated silicon wafers with low surface roughness at a deposition temperature of 1000°C to 1100°C, which also describes the effect of deposition temperature on surface roughness Impact. US 2012/0104565 A1 teaches the use of dichlorosilane instead of trichlorosilane as the source gas. Since the decomposition temperature of dichlorosilane is lower than that of trichlorosilane, epitaxial coating can be carried out at a lower temperature (1040 to 1080°C), so that lower surface roughness can be obtained than when using trichlorosilane degree.

The object of the present invention is to provide a method for producing epitaxially coated wafers of semiconductor materials with the lowest possible surface roughness (haze) of the epitaxial deposition layer independently of the source gas, which prevents the fourfold symmetry Anything that happens does not damage the edge geometry of the wafer and at the same time allows a sufficiently high deposition rate.

The object of the present invention is achieved by the following method, which is used to manufacture a semiconductor wafer with a defined surface roughness epitaxial deposition layer. The method includes the following steps in the specified order: 1) Place the semiconductor wafer in the On the susceptor in the chamber of the epitaxial reactor; 2) Heating the reactor chamber; 3) Purging the reactor chamber with hydrogen; 4) Passing the hydrogen/hydrogen chloride mixture into the reactor chamber 5) Epitaxially coat semiconductor wafers through gas decomposition at a deposition temperature T greater than 1100°C; 6) Cool the reactor chamber to an unloading temperature, which is at 1100°C and 1060° cooling rate between C (cooling rate) CR less than 3 K / s, and 7) under hydrogen stream fH ₂ the hydrogen gas into the reactor space, wherein hydrogen flow fH ₂ satisfying the relation fH ₂ <a × CR +B, where A=5.08 and B=8.71.

A method for manufacturing a semiconductor wafer with an epitaxial deposition layer with a defined surface roughness includes the following steps in the specified sequence: 1) Place at least one semiconductor wafer on at least one susceptor set in an epitaxial reactor 2) Heat the reactor space to the desired temperature; 3) Purge the reactor chamber with hydrogen; 4) Pass the hydrogen/hydrogen chloride mixture into the reactor chamber; 5) Decompose via gas at the deposition temperature T To epitaxially coat the at least one semiconductor wafer; 6) cool the reactor chamber to an unloading temperature, where the cooling rate CR between 1100°C and 1060°C is less than 3 K/s; and 7) ₂ fH under a hydrogen stream to hydrogen gas into the reactor space, wherein hydrogen flow fH ₂ satisfying the relation _{fH 2 <A × CR + B} , where A = 5.08 and B = 8.71.

Hereinafter, the present invention and preferred embodiments will be described in detail. The present invention starts with a single crystal of semiconductor material pulled according to the prior art, for example, cuts individual wafers from the single crystal by means of a wire saw.

The semiconductor material wafer (semiconductor wafer, wafer) cut from a single crystal can be, for example, a single crystal silicon wafer or a wafer of another semiconductor material, where the other semiconductor material is a compound semiconductor (such as gallium arsenide), or Elemental semiconductors (such as germanium), or other layer structures (such as silicon-germanium (SiGe) or silicon carbide (SiC) or gallium nitride (GaN)).

The diameter of the semiconductor wafer is preferably 150 to 450 mm, very particularly preferably 300 mm.

Additional steps for manufacturing semiconductor material wafers suitable for epitaxial deposition include edge rounding, grinding or lapping, and etching or cleaning and polishing. For example, the corresponding manufacturing process is described in DE 10 2005 045 337 A1.

The epitaxial reactor according to the prior art is suitable for the process for epitaxial coating of semiconductor wafers (especially silicon wafers) according to the present invention. The epitaxial coating system for semiconductor wafers preferably includes the following steps: 1) placing at least one semiconductor wafer on at least one susceptor provided in the epitaxial reactor; 2) heating the reactor space to a desired temperature ( Ramping); 3) purging the reactor chamber with hydrogen (H ₂ baking); 4) passing the hydrogen/hydrogen chloride mixture into the reactor chamber (etching, HCl baking); 5) via The gas is decomposed to epitaxially coat at least one semiconductor wafer; 6) the reactor chamber is cooled to the unloading temperature and hydrogen is introduced, and at least one semiconductor wafer is taken out.

In order to protect the semiconductor wafer from particle contamination, it is better to perform a hydrophilic cleaning before epitaxial coating. This hydrophilic cleaning system produces very thin (about 0.5 to 2 nanometers, depending on the type of cleaning and measurement) natural oxide (natural oxide) on the surface of the semiconductor wafer.

Usually, in the pretreatment of semiconductor wafers in an epitaxial reactor, the natural oxide is removed again under a hydrogen atmosphere (also called "H ₂ baking").

The H ₂ baking is preferably carried out at a temperature of 1050°C to 1200°C and preferably under a hydrogen flow of 40 to 60 slm (standard liters per minute) for 5 to 20 seconds.

After removing the natural oxide layer and before depositing the epitaxial layer, a second pretreatment step for smoothing the front surface of the substrate wafer is preferred. During this second pretreatment step, the so-called wafer etching, it is preferable to pass a mixture of hydrogen (H ₂ ) and hydrogen chloride gas (HCl) through the processing chamber 5 to 20 at a temperature of 1050°C to 1200°C. second. Preferably, the gas flow for hydrogen is 40 to 60 slm, and the gas flow for hydrogen chloride is 0.5 to 5 slm.

For epitaxial coating, it is preferable to use an epitaxial reactor with the ability to coat a single substrate wafer, such as the Centura single-wafer epitaxial reactor from Applied Materials, Inc. Or Epsilon single-wafer epitaxial reactor from ASM International NV. However, the method according to the invention can also be carried out in a multiwafer reactor. Without limiting the scope of the present invention, the method according to the present invention is described below in a single wafer method.

A susceptor made of, for example, graphite, silicon carbide (SiC) or quartz and arranged in the deposition chamber of the epitaxial reactor serves as a support for the semiconductor wafer during the pretreatment step and during the epitaxial coating (Support).

The semiconductor wafer is preferably located on a silicon carbide ring placed on the susceptor to reduce thermal stress on the semiconductor wafer during the deposition of the epitaxial layer.

As an equally preferred alternative, a one-piece susceptor with a protrusion (protrusion) and a susceptor ledge can also be used as an edge support.

In both cases, the semiconductor wafer only contacts the support in the edge area to ensure uniform heating and protect the backside of the semiconductor wafer on which no layer is normally deposited from the source gas.

The bottom of the base preferably has a gas-permeable structure characterized by open pores or perforation holes. However, it can also be made of gas-impermeable material. It is also preferable to use a base made of gas-permeable porous material, as described in DE 10328842 A1, for example.

In an epitaxial reactor, the semiconductor wafer is heated by means of a heat source, preferably by means of upper and lower heat sources (such as lamps or lamp banks), and then exposed to a source containing silicon compound (silane). A gas mixture composed of gas, carrier gas (for example, hydrogen), and optionally dopant gas (for example, diborane).

The deposition of the epitaxial layer is usually carried out by the CVD method ("chemical vapor deposition"), in which the source gas of silane (for example, trichlorosilane (SiHCl ₃ , TCS)) is passed to the silicon The surface of the wafer, where it decomposes at a temperature of 600°C to 1250°C to provide elemental silicon and volatile by-products and form an epitaxial coating on the silicon wafer.

The epitaxial layer may be undoped, or it may be specially doped with boron, phosphorus, arsenic or antimony using a suitable doping gas to adjust the conductivity type and conductivity.

In principle, the uniformity of the film thickness can be affected by various measures, such as by changing the flow of carrier gas (such as hydrogen) and/or source gas (such as TCS), and by installing a gas inlet device (injector) And adjustment, by changing the deposition temperature or by changing the base.

However, the inventors have found that a relatively high deposition temperature is required to compensate for the influence of the aforementioned four-fold symmetry and the attendant impairment of the edge geometry of the semiconductor wafer. However, higher deposition temperatures also result in higher undesirable surface roughness, which can be measured as the so-called haze.

Therefore, it is particularly preferable to apply a deposition temperature of T>1100°C.

After the epitaxial coating of the semiconductor wafer is terminated, before unloading the wafer from the processing chamber of the epitaxial reactor, the wafer is cooled in a hydrogen atmosphere in the processing chamber.

According to the prior art, passing hydrogen gas into the processing chamber not only provides a cooling effect, but also purges the remaining processing gas.

For example, US-6,217,650 B1 describes the cooling of epitaxial-coated silicon wafers in a hydrogen atmosphere at 1000°C to 800°C.

DE 102015224446 A1 describes a method in which the surface roughness (haze) can be reduced by reducing the hydrogen flow to 10 to 100 slm during cooling in the case of high deposition temperatures. The cooling rate used therein relates to the temperature range between deposition and unloading.

This method shows an improvement in surface roughness (haze) that is still insufficient.

The inventors have discovered that the roughness of the epitaxially deposited layer on the front side of the semiconductor wafer can be very easily adjusted during the cooling operation, particularly by controlling the hydrogen flow within a limited temperature range while controlling the cooling rate.

The cooling of the epitaxially coated wafer of semiconductor material can be achieved by cutting off the heating element in the processing chamber during the introduction of hydrogen into the processing chamber or by controlling the output of the heating element to be reduced within a limited period of time (ramping down )) to implement.

In the method according to the present invention, the cooling system of the epitaxial coated wafer of semiconductor material is preferably performed in a temperature range of 1100°C to 1060°C at an average cooling rate of less than 3 K/s. The temperature at which the epitaxially coated wafer of semiconductor material is removed from the processing chamber is usually 600°C to 800°C.

According to the present invention, the specific surface roughness of the epitaxial deposition layer is obtained by adjusting the hydrogen flow during the cooling operation so that it conforms to the following formula: fH ₂ <5.08 × CR+8.71 where CR is the cooling in K/s The rate, fH ₂ is the flow of hydrogen in slm.

The hydrogen can be circulated into the processing chamber at a constant rate or at a variable flow rate. In the case of a variable flow rate, the hydrogen flow may, for example, be continuously increased or continuously decreased during the cooling operation.

The hydrogen flow preferably conforms to the following formula: fH ₂ <5.08 × CR+1.65 where CR is the cooling rate in K/s, and fH ₂ is the hydrogen flow in slm, and particularly satisfies: fH ₂ <5.08 × CR -5.39 where CR is the cooling rate in K/s, and fH ₂ is the hydrogen flow in slm.

Figure 1 is a schematic diagram of experiments performed with different hydrogen flows fH ₂ and different cooling rates CR. The surface roughness (haze), quadruple symmetry, and edge geometry of the wafers from each experiment were measured, and they were characterized accordingly.

FIG. 2 is a schematic diagram of the measurement results on the surface roughness (haze), in which the gray tone of the area in the figure reflects the reduction of the surface roughness (haze) compared with the prior art. The deeper the area, the more favorable the obtained semiconductor wafer/surface roughness, without presenting the disadvantages of the aforementioned fourfold symmetry and edge geometry.

In measuring the surface roughness (haze), the value obtained is relative, that is, based on a measuring instrument, in this case the measuring instrument is a Surfscan SPx instrument from KLA Tencor. The average surface roughness Dn haze average value determined by scattered laser light measurement is calibrated to a specific value of the roughness of the prior art wafer according to the prior art.

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Figure 1 is a schematic diagram of experiments performed with different hydrogen flows fH ₂ and different cooling rates CR.

Fig. 2 is a schematic diagram of the measurement results of surface roughness (haze).

Claims (3)

A method for manufacturing a semiconductor wafer with an epitaxially deposited layer with a defined surface roughness. The method includes the following steps in the specified sequence: 1) Place the semiconductor wafer in an epitaxial reactor On the susceptor in the chamber; 2) heating the reactor chamber; 3) purging the reactor chamber with hydrogen; 4) passing the hydrogen/hydrogen chloride mixture into the reactor chamber 5) epitaxially coat the semiconductor wafer via gas decomposition at a deposition temperature T greater than 1100°C; 6) cool the reactor chamber to an unloading temperature, where it is at 1100°C The cooling rate CR between 1060°C and 1060°C is less than 3 K/s, and 7) hydrogen is fed into the reactor space under a hydrogen flow fH ₂ , where the hydrogen flow fH ₂ conforms to the relationship fH ₂ <A × CR+B, where A=5.08 and B=8.71. The method according to claim 1, wherein the hydrogen flow fH ₂ conforms to the relationship fH ₂ <A × CR+B, and B=1.65. The method according to claim 1, wherein the hydrogen flow fH ₂ conforms to the relationship fH ₂ <A × CR+B, and B=-5.39.

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