KR20170124062A - Organic Light Emitting Display - Google Patents

Abstract

An organic light emitting display device according to the present invention includes an (n-1)^th pixel and an n^th pixel which are arranged in a row, a transistor array, and a capacitor. The transistor array includes a driving transistor, a sampling transistor, and a first initial transistor. The capacitor is connected between an input terminal of an initial voltage and the sampling transistor. A gate electrode of the first initial transistor for initializing the driving transistor of the n^th pixel is connected to a scan line of the (n-1)^th pixel, thereby securing a sufficient sampling period to improve the accuracy of the compensation of the driving transistor.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an active matrix type organic light emitting display.

An active matrix type organic light emitting diode display includes an organic light emitting diode (OLED) that emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode (OLED), which is a self-luminous element, has a structure as shown in FIG. The organic light emitting device OLED includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, electrons (denoted by - in the drawing) passing through the hole transport layer (HTL) and the electron transport layer (ETL) And the excitons are formed. As a result, the light emitting layer (EML) generates visible light.

The OLED display has advantages such as a high contrast ratio and a color reproducibility. However, the efficiency of the organic light emitting diode may be reduced due to leakage current due to unexpected light emission of the OLED during operation of the compensation circuit.

The pixel structure of the organic light emitting display device may include a driving transistor, a capacitor, and a plurality of transistors. In order to drive the organic light emitting device, initialization, sampling, and emissive steps are performed.

The initialization can be initialized by applying an initial voltage to the gate terminal of the driving transistor and the anode terminal of the organic light emitting element. The gate terminal of the driving transistor is initialized to the initial voltage Vini at the time of initialization and an undesired current flows to the organic light emitting element at this moment to reduce the efficiency of the organic light emitting element. Also, the current may excessively flow toward the input terminal of the initial voltage Vini momentarily, thereby causing an image quality failure due to an instantaneous drop of the initial voltage Vini and damaging circuit components.

In addition, reliability of the driving transistor must be ensured in order to allow a constant current to flow through the organic light emitting element. However, the characteristic of the semiconductor layer of the driving transistor changes with time. That is, the threshold voltage of the driving transistor is shifted to the negative or positive voltage. Therefore, it is necessary to arrange a plurality of transistors and capacitors in the pixel in order to compensate the threshold voltage of the driving transistor in real time and emit the organic light emitting element. That is, as the number of transistors increases and becomes more complicated in a limited pixel region, it is required to reduce unnecessary space and to secure a design margin so that each element can be optimally arranged.

Further, in order to implement a high-resolution display device, the number of pixels to emit light increases, so that one horizontal period (H) becomes shorter and the sampling period is accordingly reduced. The reduced sampling period may be a factor that lowers the accuracy of the threshold voltage compensation of the driving transistor.

Accordingly, an object of the present invention is to provide an organic light emitting diode display capable of blocking a current flowing to an organic light emitting diode during a period other than an emission period and ensuring accuracy of threshold voltage compensation of a driving transistor will be.

Another object of the present invention is to provide an OLED display capable of ensuring a design margin in a pixel region by reducing the number of contact holes for connecting a plurality of transistors and capacitors.

It is another object of the present invention to provide an organic light emitting diode (OLED) display device for improving the accuracy of driving transistor compensation by ensuring a sufficient sampling period.

It is another object of the present invention to provide an organic light emitting diode (OLED) display device for blocking an influence of a mobile charge which may affect a semiconductor layer of a driving transistor.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The OLED display according to an embodiment of the present invention includes a transistor array including n-1-th pixel and n-th pixel, a driving transistor, a sampling transistor, and a first initial transistor arranged in rows, an input terminal of an initial voltage, A gate electrode of the first initial transistor for initializing the driving transistor of the n-th pixel is connected to the gate electrode of the (n-1) th pixel.

The organic light emitting display according to an embodiment of the present invention includes organic light emitting devices arranged in rows and arranged in n-1-th and n-th pixels, pixels, respectively, connected to the (n-1) a sampling transistor included in an nth pixel of the nth pixel and connected to the nth scan signal, an emission transistor included in the nth pixel and connected to the nth emission signal, and a frame for driving the organic light emitting element Includes an initial period, a sampling period, and an emission period. In the initial period, the (n-1) th scan signal is applied to the on level and the n th scan signal and the n th emission signal are applied to the off level. In the sampling period, the nth scan signal is applied to the on level and the (n-1) th scan signal and the nth emission signal are applied to the off level. During the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal are applied at the off level.

Embodiments of the present invention can prevent the leakage current flowing to the organic light emitting element during a period other than the emission period by connecting the emission transistor to the anode electrode of the organic light emitting element.

Also, embodiments of the present invention can improve the lifetime of the organic light emitting device by applying a voltage lower than the low potential driving voltage (ELVSS) at an initial voltage (Vini) during an initial period.

In addition, embodiments of the present invention can prevent a short between the data voltage (Vdata) and the initial voltage (Vini) in the initial period, and the sampling period for compensating the pixel is increased, The ability can be improved.

In the embodiments of the present invention, the gate electrode of the first initializing transistor for initializing the driving transistor of the n-th pixel is connected to the gate electrode of the pixel arranged in the (n-1) th row, The accuracy of the threshold voltage compensation can be improved.

In addition, embodiments of the present invention have an effect of reducing the number of contact holes and securing a pixel design margin by connecting one electrode of the capacitor to the input terminal of the initial voltage, not the input terminal of the high-potential driving voltage.

Further, the embodiments of the present invention have the effect of reducing the influence of mobile charges on the semiconductor layer of the driving transistor by disposing a metal layer below the semiconductor layer of the driving transistor.

Embodiments of the present invention can reduce the influence of a mobile charge on the semiconductor layer of the driving transistor by realizing the electrode of the capacitor to have a larger area than the gate electrode of the driving transistor .

Further, the embodiments of the present invention reduce the influence of mobile charge on the semiconductor layer of the transistor by disposing one electrode of the capacitor in the region corresponding to the semiconductor of the transistor operating in the sampling period There is an effect that can be.

Also, in embodiments of the present invention, at least one of the transistors connected to the capacitor is composed of at least two transistors connected in series, thereby preventing the light emission luminance from being distorted due to the leakage current.

Further, the embodiments of the present invention allow the initial period for initializing the driving transistor or the organic light emitting element to be performed during the sampling period of the pixel arranged in the previous row, thereby enabling the driving period of the driving transistor or the organic light emitting element The pixel can be driven. Therefore, the pixel can be driven even in the existing space of 2/3, so that a Narrow-bezel can be easily implemented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining the principle of light emission of an organic light emitting device and an organic light emitting device. FIG.
2 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
3 is an equivalent circuit diagram showing a one-pixel structure of the present invention.
FIG. 4 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 3. FIG.
5A, 5B, and 5C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 4, respectively.
6 is a diagram showing voltage values for nodes A, B, and C of a pixel in the initial period, the sampling period, and the emission period;
FIG. 7 is an equivalent circuit diagram showing one modification of the pixel structure shown in FIG. 3; FIG.
8 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 7. FIG.
9A, 9B, and 9C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 7, respectively.
10 is a diagram showing voltage values for nodes A, B, and C of a pixel in the initial period, the sampling period, and the emission period;
Fig. 11 is an equivalent circuit diagram showing a modification of the pixel structure shown in Fig. 7. Fig.
FIG. 12 is an equivalent circuit diagram showing one modification of the pixel structure shown in FIG. 3; FIG.
FIG. 13 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 12; FIG.
14A, 14B, and 14C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 12, respectively.
FIG. 15 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 12; FIG.
16 to 18 are diagrams showing various examples in which the shift register of the scan driver and the inverter of the emission driver are implemented as a gate driver circuit.
19 shows an array of regions in which capacitors are formed;
20 is a cross-sectional view showing a cross section cut along II 'in FIG. 19;
21 is a view showing an array of regions where capacitors are formed according to a comparative example;

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, and technically various interlocking and driving, and that the embodiments may be practiced independently of each other,

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the embodiment of the present invention, only the transistors constituting the pixel are implemented as P type. However, the technical idea of the present invention is not limited to this, but may be applied to the case of N type.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 11. FIG.

2 illustrates an organic light emitting display according to an embodiment of the present invention.

2, the OLED display includes a display panel 10 on which pixels PXL are formed, a data driving circuit 12 for driving the data lines 14, A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timings of the data driving circuit 12 and the gate driving circuit 13. [

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and the pixels PXL are arranged in a matrix form for each of the intersection regions. The pixels PXL arranged on the same horizontal line form one pixel row. Pixels PXL arranged in one pixel line are connected to one gate line 15 and one gate line 15 may include at least one scan line and at least one emission line. That is, each pixel PXL may be connected to one data line 14 and at least one scan line and an emission line. The pixels PXL can receive the high and low potential driving voltages ELVDD and ELVSS and the initial voltage Vini from the power generating unit in common. The initial voltage Vini may be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device OLED so that unnecessary light emission of the organic light emitting device OLED is prevented in the initial period and the sampling period. That is, it may be set to be equal to or lower than the low-potential driving voltage ELVSS. Therefore, in the initial period, the initial voltage Vini is applied at a voltage lower than the low-level driving voltage ELVSS to suppress unnecessary light emission of the organic light emitting device OLED, and as a result, the lifetime of the organic light emitting device OLED Can be improved.

The transistors (TFTs) constituting the pixel PXL may be implemented as a transistor including an oxide semiconductor layer. The oxide semiconductor layer is advantageous for large-sized display panel 10 when considering both electron mobility and process variations. When formed of an oxide semiconductor, it may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO). However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor. Each pixel PXL includes a plurality of transistors and a capacitor to compensate for a threshold voltage change of the driving transistor. The present invention includes a method of compensating a threshold voltage of a driving transistor among a plurality of transistors, We propose a pixel structure that can secure a period. This will be described in detail later with reference to FIG. 3 to FIG.

Meanwhile, the transistor having the source electrode or the drain electrode connected to one electrode of the capacitor in each pixel PXL may include at least two transistors connected in series so that the influence of an off current is minimized. At this time, two or more transistors are switched by the same control signal. For example, as in FIG. 3, T3 may be designed as a double gate type transistor that is switched by the same control signal and includes T3A and T3B connected in series with each other. And T5 can be designed as a double gate type transistor which is switched by the same control signal and includes T5A and T5B connected in series with each other. The double gate type transistor described below refers to a structure in which two transistors are connected in series to each other.

In addition to T3 and T5, as in Fig. 7, T6 can also be designed as a double gate type transistor including T6A and T6B. 11, in addition to T3 and T5, T2 may also be designed as a double gate type transistor including T2A and T2B. 12, T2 may also be designed as a double gate type transistor including T2A and T2B.

That is, at least one of the transistors connected to the capacitor is constituted by at least two transistors connected in series, so that the light emission luminance can be prevented from being distorted due to the leakage current.

Referring again to FIG. 2, the timing controller 11 rearranges the digital video data (RGB) input from the outside according to the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12. The timing controller 11 is also connected to the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE, A data control signal DDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC. The gate drive circuit 13 may include a scan driver and an emission driver. The scan driver may generate a scan signal in a row-sequential manner to supply at least one scan line connected to each pixel row to the scan lines. The emission driving unit may generate an emission signal in a row-sequential manner to supply at least one emission line connected to each pixel row to the emission lines.

The gate drive circuit 13 may be formed directly on the non-display area of the display panel 10 in accordance with a GIP (Gate-Driver In Panel) method.

3 is an equivalent circuit diagram showing the one-pixel structure of the present invention. 4 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 3. FIG.

Referring to FIG. 3, each pixel PXL disposed in n (n is a natural number) pixel row includes an organic light emitting diode OLED, a driving transistor DT, a first transistor T1, a second transistor T2, A third transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor Cstg.

The organic light emitting element OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The organic compound layer may include at least one hole transporting layer, an electron transporting layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into the light emitting layer or transmits holes, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer blocking layer, EBL). The electron transport layer is a layer for injecting electrons into the light emitting layer or for transporting electrons, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer blocking layer, HBL). The anode electrode of the organic light emitting element OLED is connected to the node C, and the cathode electrode of the organic light emitting element is connected to the input terminal of the low potential driving voltage ELVSS.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the node A, the source electrode is connected to the node D, and the drain electrode is connected to the node B.

The first transistor T1 is connected between the data line 14 and the node D and turned on / off according to the nth scan signal SCAN (n). The gate electrode of the first transistor T1 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied and the source electrode of the first transistor T1 is connected to the data line 14 And the drain electrode of the first transistor T1 is connected to the node D.

The second transistor T2 is connected between the node D and the input terminal of the high potential driving voltage ELVDD and turned on / off according to the nth emission signal EM (n). The gate electrode of the second transistor T2 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the second transistor T2 is connected to the high potential driving voltage ELVDD, and the drain electrode of the second transistor T2 is connected to the node D.

The third transistor T3 is connected between the node A and the node B and turned on / off according to the n-th scan signal SCAN (n). The gate electrode of the third transistor T3 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied, the source electrode of the third transistor T3 is connected to the node A, And the drain electrode of the third transistor T3 is connected to the node B. Here, the third transistor T3 may be referred to as a sampling transistor.

The fourth transistor T4 is connected between the node B and the node C, and is turned on / off according to the nth emission signal EM (n). The gate electrode of the fourth transistor T4 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the fourth transistor T4 is connected to the node B , And the drain electrode of the fourth transistor T4 is connected to the node C. Here, the fourth transistor T4 may be referred to as an emission transistor.

The fifth transistor T5 is connected between the node A and the input terminal of the initial voltage Vini and is turned on / off according to the (n-1) th scan signal SCAN (n-1). The gate electrode of the fifth transistor T5 is connected to the (n-1) th first scan line to which the n-1th scan signal SCAN (n-1) is applied, the source electrode of the fifth transistor T5 is connected to the A and the drain electrode of the fifth transistor T5 is connected to the input terminal of the initial voltage Vini. Here, the fifth transistor T5 may be referred to as a first initial transistor.

The capacitor Cstg is connected between the node A and the input terminal of the initial voltage Vini.

The pixel operation of FIG. 3 will be described with reference to FIGS. 4 to 6. FIG. 4 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 4 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 3. FIG. 5A, 5B, and 5C are equivalent circuit diagrams of pixels operating in the initial period, the sampling period, and the emission period of FIG. 4, respectively. 6 is a diagram showing the voltage values for the nodes A, B, and C of the pixel in the initial period, the sampling period, and the emission period.

One frame period includes the initial period Pi for initializing the node A as shown in Fig. 4, the sampling period Ps for sampling the threshold voltage of the driving transistor DT and storing it in the node A, and the sampled threshold voltage And an emission period Pe for programming the source-gate voltage of the driving transistor DT and causing the organic light emitting diode OLED to emit light with a drive current corresponding to the programmed source-gate voltage. In FIG. 4, the initialization operation is performed in the (n-1) -th horizontal period Hn-1, so that the n-th horizontal period Hn can be allotted to the sampling operation. Therefore, since the sampling period Ps can be sufficiently secured, there is an effect that the threshold voltage of the driving transistor DT can be more accurately sampled.

In FIG. 5A, the transistor operating in the initial period Pi is shown by a dotted line, and the transistor not operating in the solid line. Referring to FIGS. 4 and 5A, the initial period Pi is included in the (n-1) -th horizontal period Hn-1 allocated to the data writing of the (n-1) th pixel row. In the initial period Pi, the n-1 scan signal SCAN (n-1) is applied at a low level and the nth scan signal SCAN (n) and the nth emission signal EM (n) Is applied at a high level. Here, the low level is the on level and the high level is the off level. Hereinafter, for ease of explanation, the low level is referred to as an on level and the high level is referred to as an off level.

In the initial period Pi, the fifth transistor T5 is turned on in response to the (n-1) th scan signal SCAN (n-1), whereby the node A is initialized to the initial voltage Vini. In this case, the fifth transistor T5 may be referred to as a first initial transistor, and the gate electrode of the first initial transistor may be connected to the gate electrode of the pixel arranged in the (n-1) The sampling period of the voltage Vth can be sufficiently secured and the accuracy of the compensation of the threshold voltage Vth can be improved. By initializing the node A prior to the sampling operation, it is possible to enhance the reliability of sampling and to prevent unnecessary emission of the organic light emitting diode OLED. To this end, the initial voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting diode OLED and is set to be equal to or lower than the low-potential driving voltage ELVSS . In the initial period Pi, the data voltage Vdata (n) of the previous frame is held at the node D.

In Fig. 5B, the transistor operating in the sampling period Ps is indicated by a solid line, and the transistor not operating is indicated by a dotted line. Referring to FIGS. 4 and 5B, the sampling period Ps is included in the n-th horizontal period Hn allocated to the data writing of the n-th pixel row. 1) th scanning signal SCAN (n-1) and the n-th emission signal EM (n) are applied in the on period, in the sampling period Ps, Is applied at an off level. In the sampling period Ps, the first and third transistors T1 and T3 are turned on in response to the n-th scan signal SCAN (n), so that the driving transistor DT is diode- And the drain electrode are short-circuited so that the transistor TFT functions as a diode), and the data voltage Vdata (n) is applied to the node D.

In the sampling period Ps, a current Ids flows between the source and the drain of the driving transistor DT, and the potential of the node A is changed from the initial voltage Vini, which is the initial state, to the data voltage Vdata (n) -Vth obtained by subtracting the threshold voltage of the drive transistor DT from the threshold voltage of the drive transistor DT. The initial voltage Vini is equal to or lower than the low potential driving voltage ELVSS. The voltage value of the node A which is the gate electrode of the driving transistor DT includes the threshold voltage Vth of the driving transistor DT so that the threshold voltage Vth of the driving transistor DT in the emission period Pe Can be generated in the erased state.

In FIG. 5C, the transistor operating in the emission period Pe is indicated by a solid line, and the transistor not operating is indicated by a dotted line. Referring to FIGS. 4 and 5C, the emission period Pe corresponds to the remaining period except for the initial period Pi and the sampling period Ps in one frame period. The nth emission signal EM (n) is applied at the ON level and the n th scan signal SCAN (n-1) and the n th scan signal SCAN (n) are applied in the emission period Pe, Is applied at an off level.

In the emission period Pe, the second transistor T2 is turned on in response to the nth emission signal EM (n) to connect the high potential driving voltage ELVDD to the source electrode of the driving transistor DT do. The fourth transistor T4 is turned on in response to the nth emission signal EM (n) to make the potentials of the nodes B and C equal to the operating voltage Voled of the organic light emitting device OLED .

At this time, the fourth transistor T4 is connected to the anode electrode of the organic light emitting device OLED and is turned off during the initial period Pi and the sampling period Ps other than the emission period Pe, so that the emission period Pe The leakage current flowing to the organic light emitting diode OLED can be cut off. Here, the fourth transistor T4 may be referred to as an emission transistor.

The relational expression for the driving current Ioled flowing in the organic light emitting device OLED in the emission period Pe is as shown in the following equation (1). The organic light emitting device OLED emits light by a driving current to realize a desired display gradation.

[Equation 1]

_{I OLED = k / 2 (Vsg} -Vth) 2 = k / 2 (Vs-Vg-Vth) 2 = k / 2 (VDD-Vdata + Vth - Vth) 2 = k / 2 (VDD-Vdata) 2

In Equation (1), k / 2 represents a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

Since the driving current (Ioled) formula k (Vsg-Vth) ² inde, the threshold voltage (Vth) component of the Vsg programmed with the emission period (Pe), the driving transistor (DT) is already included, equation (1) and The threshold voltage (Vth) component of the driving transistor DT is erased in the driving current Ioled relation. Thus, the influence of the change in the threshold voltage Vth on the driving current Ioled can be minimized.

FIG. 6 is a table showing voltage values input to the node A, the node B, and the node C in the initial period Pi, the sampling period Ps, and the emission period Pe described in FIGS. 5A to 5C. The node A that has passed through the sampling period Ps includes the threshold voltage Vth component of the driving transistor DT so that when the organic light emitting element emits light in the emission period Pe, (Ioled) may cancel the threshold voltage (Vth) component to indicate a desired display gradation.

7 is an equivalent circuit diagram showing a modification of the pixel structure shown in FIG. 8 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 7. FIG. 9A, 9B, and 9C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 7, respectively. 10 is a diagram showing voltage values for node A, node B, and node C of the pixel in the initial period, the sampling period, and the emission period.

The pixel PXL of FIG. 7 further includes a sixth transistor T6 in the pixel PXL of FIG. In the pixel PXL shown in Fig. 7, the sixth transistor T6 is connected between the input terminal of the initial voltage Vini and the node C. The gate electrode of the sixth transistor T6 is connected to the (n-1) th first scan line to which the n-1th scan signal SCAN (n-1) is applied, the source electrode of the sixth transistor T6 is connected to the C, and the drain electrode of the sixth transistor T6 is connected to the input terminal of the initial voltage Vini. The pixel PXL of FIG. 7 further includes the sixth transistor T6, thereby fixing the potential of the node C to improve the accuracy of sampling. Therefore, the operation stability of the circuit can be enhanced. Here, the sixth transistor T6 may be referred to as a second initial transistor.

In FIG. 7, the remaining components except the sixth transistor T6 are substantially the same as those described with reference to FIG.

The pixel operation of Fig. 7 will be described with reference to Figs. 7 to 10. Fig. 8 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 9A, 9B, and 9C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 7, respectively. 10 is a diagram showing the voltage values for the nodes A, B, and C of the pixels in the initial period, the sampling period, and the emission period.

8, one frame period includes a initial period Pi for initializing the node A and the node C, a sampling period Ps for sampling the threshold voltage of the driving transistor DT and storing the sampled threshold voltage in the node A, A source-gate voltage of the driving transistor DT is programmed including a sampled threshold voltage and an emission period Pe for causing the organic light emitting diode OLED to emit light with a driving current corresponding to the programmed source- ≪ / RTI > In Fig. 7, the initialization operation is performed in the (n-1) -th horizontal period (Hn-1), so that the n-th horizontal period Hn can be allotted to the sampling operation. Therefore, since the sampling period Ps can be sufficiently secured, there is an effect that the threshold voltage of the driving transistor DT can be more accurately sampled.

In FIG. 9A, the transistor operating in the initial period Pi is indicated by a solid line and the transistor not operating is indicated by a dotted line. 8 and 9A, in the initial period Pi, the n-1 scan signal SCAN (n-1) is applied at the ON level and the n-th scan signal SCAN (n) The emission signal EM (n) is applied at the off level. In the initial period Pi, the fifth and sixth transistors T5 and T6 are turned on in response to the (n-1) th scan signal SCAN (n-1) ). At this time, the gate electrodes of the fifth and sixth transistors T5 and T6 are connected to the gate electrodes of the pixels arranged in the (n-1) th row, so that the sampling period of the threshold voltage Vth of the driving transistor DT is sufficiently secured So that the accuracy of the threshold voltage compensation can be improved. That is, since the node A and the node C are initialized prior to the sampling operation, reliability of sampling can be improved and unnecessary light emission of the organic light emitting diode OLED can be prevented.

In FIG. 9B, the transistors operating in the sampling period Ps are indicated by solid lines, and the transistors not operating are indicated by broken lines. 8 and 9B, in the sampling period Ps, the n-th scan signal SCAN (n) is applied at the ON level and the n-1 scan signal SCAN (n-1) The emission signal EM (n) is applied at the off level. In the sampling period Ps, the first and third transistors T1 and T3 are turned on in response to the n-th scan signal SCAN (n), so that the driving transistor DT is diode- And the drain electrode are short-circuited so that the transistor acts as a diode), and the data voltage Vdata (n) is applied to the node D.

Therefore, in the sampling period Ps, the current Ids flows between the source and the drain of the driving transistor DT, and the potential of the node A is changed from the initial voltage Vini, which is the initial state, (Vdata (n) -Vth) obtained by subtracting the threshold voltage (Vdata (n)) of the driving transistor DT from the threshold voltage of the driving transistor DT. The initial voltage Vini is equal to or lower than the low potential driving voltage ELVSS. The voltage value of the node A which is the gate electrode of the driving transistor DT includes the threshold voltage Vth of the driving transistor DT so that the threshold voltage Vth of the driving transistor DT in the emission period Pe Can be generated in the erased state.

In Fig. 9C, the transistor operating in the emission period Pe is indicated by a solid line, and the transistor not operating is indicated by a dotted line. 8 and 9C, in the emission period Pe, the nth emission signal EM (n) is applied at the ON level, and the n-1 scan signal SCAN (n-1) And the nth scan signal SCAN (n) is applied at an off level. In the emission period Pe, the second transistor T2 is turned on in response to the nth emission signal EM (n) to connect the high potential driving voltage ELVDD to the source electrode of the driving transistor DT do. The fourth transistor T4 is turned on in response to the nth emission signal EM (n) to make the potentials of the nodes B and C equal to the operating voltage Voled of the organic light emitting device OLED .

At this time, the fourth transistor T4 is connected to the anode electrode of the organic light emitting element and is turned off during the initial period Pi and the sampling period Ps other than the emission period Pe, The relationship between the driving current Ioled flowing in the organic light emitting device OLED in the emission period Pe is expressed by the following equation (2). OLED emits light by a driving current to realize a desired display gradation.

&Quot; (2) "

_{I OLED = k / 2 (Vsg} -Vth) 2 = k / 2 ((Vs-Vg) -Vth) 2 = k / 2 ((VDD-Vdata + Vth) - Vth) 2 = k / 2 (VDD-Vdata ) ²

In Equation (2), k / 2 indicates a proportional constant determined by electron mobility, parasitic capacitance, channel capacitance, and the like of the driving transistor DT.

Since the driving current (Ioled) formula k (Vsg-Vth) ² inde, the threshold voltage (Vth) component of the Vsg programmed with the emission period (Pe), the driving transistor (DT) is already included, equation (2) and Similarly, the threshold voltage (Vth) component of the driving transistor DT is erased in the driving current Ioled relation. Therefore, the influence of the change in the threshold voltage Vth on the drive current Ioled can be minimized.

10 is a table showing voltage values input to the nodes A, B, and C in the initial period Pi, the sampling period Ps, and the emission period Pe described in FIGS. 9A to 9C. The node A that has passed through the sampling period Ps includes the threshold voltage Vth component of the driving transistor DT so that when the organic light emitting element emits light in the emission period Pe, (Ioled) may cancel the threshold voltage (Vth) component to indicate a desired display gradation.

11 is an equivalent circuit diagram showing a modification of the pixel structure shown in FIG. 11 shows a modification of the connection relationship of the second transistor T2, the third transistor T3 and the fifth transistor T5 in comparison with FIG.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the node A, the source electrode of the driving transistor DT is connected to the node D, and the drain electrode of the driving transistor DT is connected to the node B.

The first transistor T1 is connected between the data line 14 and the node D and turned on / off according to the nth scan signal SCAN (n). The gate electrode of the first transistor T1 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied and the source electrode of the first transistor T1 is connected to the data line 14 And the drain electrode of the first transistor T1 is connected to the node D.

The second transistor T2 is connected between the node D and the input terminal of the high potential driving voltage ELVDD and turned on / off according to the nth emission signal EM (n). The gate electrode of the second transistor T2 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the second transistor T2 is connected to the high potential driving voltage ELVDD, and the drain electrode of the second transistor T2 is connected to the node D.

The third transistor T3 is connected between the node A and the node B and turned on / off according to the n-th scan signal SCAN (n). The gate electrode of the third transistor T3 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied, the source electrode of the third transistor T3 is connected to the node B, And the drain electrode of the third transistor T3 is connected to the node A. [

The fourth transistor T4 is connected between the node B and the node C, and is turned on / off according to the nth emission signal EM (n). The gate electrode of the fourth transistor T4 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the fourth transistor T4 is connected to the node B , And the drain electrode of the fourth transistor T4 is connected to the node C.

The fifth transistor T5 is connected between the node A and the input terminal of the initial voltage Vini and is turned on / off according to the (n-1) th scan signal SCAN (n-1). The gate electrode of the fifth transistor T5 is connected to the (n-1) th first scan line to which the n-1th scan signal SCAN (n-1) is applied, the source electrode of the fifth transistor T5 is connected to the A and the drain electrode of the fifth transistor T5 is connected to the input terminal of the initial voltage Vini.

The sixth transistor T6 is connected between the input terminal of the initial voltage Vini and the node C, and is turned on / off according to the nth scan signal SCAN (n). The gate electrode of the sixth transistor T6 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied, the source electrode of the sixth transistor T6 is connected to the node C, The drain electrode of the sixth transistor T6 is connected to the input terminal of the initial voltage Vini.

The capacitor Cstg is connected between the node A and the input terminal of the high potential driving voltage ELVDD.

One frame period includes the initial period Pi for initializing the node A and the node C as shown in Fig. 11, the sampling period Ps for sampling the threshold voltage of the driving transistor DT and storing the sampled threshold voltage in the node A, And an emission period Pe for causing the organic light emitting diode OLED to emit light with a drive current corresponding to the programmed source-to-gate voltage of the driving transistor DT, have. 11, the gate voltage initializing operation of the driving transistor is performed during the (n-1) -th horizontal period Hn-1 and the sampling operation is performed together with the initializing operation of the organic light emitting device OLED during the n-th horizontal period Hn. That is, the initial period Pi and the sampling period Ps are included in the n-th horizontal period Hn.

In the initial period Pi, the n-1 scan signal SCAN (n-1) is applied at the ON level and the nth scan signal SCAN (n) and the nth emission signal EM (n) Is applied at an off level. In the initial period Pi, the fifth transistor T5 is turned on in response to the (n-1) th scan signal SCAN (n-1), whereby the node A is initialized to the initial voltage Vini. Therefore, since the node A is initialized prior to the sampling operation, the reliability of the sampling of the threshold voltage (Vth) of the driving transistor DT can be enhanced.

1) th scanning signal SCAN (n-1) and the n-th emission signal EM (n) are applied in the on period, in the sampling period Ps, Is applied at an off level. In the sampling period Ps, the first, third, and sixth transistors T1, T3, and T6 are turned on in response to the n-th scan signal SCAN (n) (diode connection, the gate electrode and the drain electrode are short-circuited so that the transistor acts as a diode), and the data voltage Vdata (n) is applied to the node D. Therefore, in the sampling period Ps, the current Ids flows between the source and the drain of the driving transistor DT, and the potential of the node A is changed from the initial voltage Vini, which is the initial state, (Vdata (n) -Vth) obtained by subtracting the threshold voltage (Vdata (n)) of the driving transistor DT from the threshold voltage of the driving transistor DT. The initial voltage Vini is equal to or lower than the low potential driving voltage ELVSS. The voltage value of the node A which is the gate electrode of the driving transistor DT includes the threshold voltage Vth of the driving transistor DT so that the threshold voltage Vth of the driving transistor DT in the emission period Pe Can be generated in the erased state. In addition, since the node C is initialized prior to the sampling operation, unnecessary light emission of the organic light emitting diode OLED can be prevented.

The emission period Pe corresponds to the remaining period except for the initial period Pi and the sampling period Ps in one frame period. The nth emission signal EM (n) is applied at the ON level and the n th scan signal SCAN (n-1) and the n th scan signal SCAN (n) are applied in the emission period Pe, Is applied at an off level. In the emission period Pe, the second transistor T2 is turned on in response to the nth emission signal EM (n) to connect the high potential driving voltage ELVDD to the source electrode of the driving transistor DT And the fourth transistor T4 is turned on in response to the nth emission signal EM (n) to make the potentials of the nodes B and C equal to the operating voltage Voled of the organic light emitting device OLED .

At this time, the fourth transistor T4 is connected to the anode electrode of the organic light emitting device OLED and is turned off during the initial period Pi and the sampling period Ps other than the emission period Pe, so that the emission period Pe The leakage current flowing to the organic light emitting element can be cut off.

The relation expression for the driving current Ioled flowing in the organic light emitting diode OLED in the emission period Pe is applied in the same manner as in Equation 2 described in FIG. 9C. Accordingly, the organic light emitting element OLED can emit light by a driving current to realize a desired display gradation. The threshold voltage of the gate between the voltage (Vsg), the driving transistor (DT) - Referring to equation (2), drive current (Ioled) formula k (Vsg-Vth) ² because it is a source program through the emission period (Pe) The threshold voltage (Vth) component of the driving transistor DT is erased in the driving current (Ioled) relation as shown in Equation (2). Therefore, the influence of the change in the threshold voltage Vth on the drive current Ioled can be minimized.

12 is an equivalent circuit diagram showing a modification of the pixel structure shown in FIG. 13 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 12. FIG. 14A, 14B, and 14C are equivalent circuit diagrams of pixels corresponding to the initial period, the sampling period, and the emission period of FIG. 12, respectively.

12, each pixel PXL disposed in n (n is a natural number) pixel row includes an organic light emitting diode OLED, a driving transistor DT, a first transistor T1, a second transistor T2, A third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor Cstg.

The organic light emitting element OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The anode electrode of the organic light emitting element OLED is connected to the node C, and the cathode electrode of the organic light emitting element OLED is connected to the input terminal of the low potential driving voltage ELVSS.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the node A, the source electrode is connected to the input terminal of the high potential driving voltage ELVDD, and the drain electrode is connected to the node B.

The first transistor T1 is connected between the data line 14 and the node D and turned on / off according to the nth scan signal SCAN (n). The gate electrode of the first transistor T1 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied and the source electrode of the first transistor T1 is connected to the data line 14 And the drain electrode of the first transistor T1 is connected to the node D.

The second transistor T2 is connected between the node A and the node B and turned on / off according to the n-th scan signal SCAN (n). The gate electrode of the second transistor T2 is connected to the nth first scan line to which the nth scan signal SCAN (n) is applied, the source electrode of the second transistor T2 is connected to the node D, The drain electrode of the second transistor T2 is connected to the node A.

The third transistor T3 is connected between the node D and the input terminal of the initial voltage Vini and is turned on / off according to the nth emission signal EM (n). The gate electrode of the third transistor T3 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the third transistor T3 is connected to the node D , And the drain electrode of the third transistor T3 is connected to the input terminal of the initial voltage Vini.

The fourth transistor T4 is connected between the node B and the node C, and is turned on / off according to the nth emission signal EM (n). The gate electrode of the fourth transistor T4 is connected to the nth first emission line to which the nth emission signal EM (n) is applied and the source electrode of the fourth transistor T4 is connected to the node B , And the drain electrode of the fourth transistor T4 is connected to the node C.

The fifth transistor T5 is connected between the node A and the input terminal of the initial voltage Vini and is turned on / off according to the (n-1) th scan signal SCAN (n-1). The gate electrode of the fifth transistor T5 is connected to the (n-1) th first scan line to which the n-1th scan signal SCAN (n-1) is applied, the source electrode of the fifth transistor T5 is connected to the A and the drain electrode of the fifth transistor T5 is connected to the input terminal of the initial voltage Vini.

The sixth transistor T6 is connected between the node C and the input terminal of the initial voltage Vini and is turned on / off according to the (n-1) th scan signal SCAN (n-1). The gate electrode of the sixth transistor T6 is connected to the (n-1) th first scan line to which the n-1th scan signal SCAN (n-1) is applied, the source electrode of the sixth transistor T6 is connected to the C, and the drain electrode of the sixth transistor T6 is connected to the input terminal of the initial voltage Vini.

Then, the capacitor Cstg is connected between the node A and the node D.

As described above, the pixel PXL of FIG. 12 includes the capacitor Cstg between the node A and the node D, so that the voltage applied to the node A changes according to the change of the voltage applied to the node D. The driving transistor DT determines the amount of current supplied to the organic light emitting element OLED in response to the voltage changed at the node A. [ Thus, the operation stability of the circuit can be improved and the luminance of the organic light emitting diode OLED can be easily controlled.

In addition, it is possible to prevent a short between the data voltage (Vdata) and the initial voltage (Vini) in the initial period through the pixel (PXL) of FIG. 12, So that the compensation ability can be improved.

The pixel operation of Fig. 12 will be described with reference to Figs. 13 to 14C.

One frame period stores the initial period Pi for initializing the node A and the node C and the data voltage Vdata (n) at the node D so that the source-gate voltage of the driving transistor DT becomes equal to the threshold voltage A sampling period Ps for operating the driving transistor DT and an emission period Pe for emitting the organic light emitting element OLED with the driving current of the driving transistor DT driven in response to the voltage changed at the node A. [ ). ≪ / RTI > In Fig. 13, the initialization operation is performed in the (n-1) -th horizontal period Hn-1, so that the n-th horizontal period Hn can be allotted to the sampling operation. Therefore, since the sampling period Ps can be sufficiently secured, there is an effect that the threshold voltage of the driving transistor DT can be more accurately sampled.

In Fig. 14A, a transistor solid line operating in the initial period Pi and a transistor not operating are shown by dotted lines. 13 and 14A, in the initial period Pi, the n-1 scan signal SCAN (n-1) is applied at the ON level and the n-th scan signal SCAN (n) The emission signal EM (n) is applied at the off level. In the initial period Pi, the fifth and sixth transistors T5 and T6 are turned on in response to the (n-1) th scan signal SCAN (n-1) ).

In the initial period Pi, the fifth and sixth transistors T5 and T6 are turned on in response to the (n-1) th scan signal SCAN (n-1) ). By initializing the node A and the node C prior to the sampling operation, it is possible to increase the reliability of sampling and to prevent unnecessary light emission of the organic light emitting element OLED. To this end, the initial voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting diode OLED and is set to be equal to or lower than the low-potential driving voltage ELVSS .

In Fig. 14B, the transistor operating in the sampling period Ps is indicated by a solid line, and the transistor not operating is indicated by a dotted line. 13 and 14B, in the sampling period Ps, the n-th scan signal SCAN (n) is applied at the ON level and the n-1 scan signal SCAN (n-1) The emission signal EM (n) is applied at the off level. In the sampling period Ps, the first and second transistors T1 and T2 are turned on in response to the n-th scan signal SCAN (n), so that the driving transistor DT is diode- (N) is applied to the node D, and the high potential driving voltage ELVDD is applied to the node A. In this case, Here, since the capacitor Cstg is arranged between the node D and the node A, the node D and the node A can independently receive different voltages.

Therefore, in the sampling period Ps, the driving transistor DT operates until the source-gate voltage becomes equal to the threshold voltage, and the high-potential driving voltage ELVDD is applied to the node A while the driving transistor DT is operating. .

In Fig. 14C, the transistor operating in the emission period Pe is indicated by a solid line, and the transistor not operating is indicated by a dotted line. 13 and 14C, in the emission period Pe, the nth emission signal EM (n) is applied at the ON level, and the n-1 scan signal SCAN (n-1) And the nth scan signal SCAN (n) is applied at an off level. In the emission period Pe, the initialization voltage is applied to the node D by turning on the third transistor T3 in response to the nth emission signal EM (n). The voltage of the capacitor Cstgg with respect to the potential change (Vdata-Vinit) of the node D is reflected to the node A. [ That is, the potential change of the node D is also reflected to the node A, so that the gate-source voltage Vgs of the driving transistor DT is programmed. Thus, the driving transistor DT determines the amount of current supplied to the organic light emitting element OLED in response to the voltage changed at the node A. [

The fourth transistor T4 is turned on in response to the nth emission signal EM (n) to make the potential of the node C equal to the operating voltage Voled of the organic light emitting diode OLED.

The relation for the driving current Ioled flowing in the organic light emitting diode OLED in the emission period Pe is as shown in the following equation (3). The organic light emitting device OLED emits light by a driving current to realize a desired display gradation.

At this time, the fourth transistor T4 is connected to the anode electrode of the organic light emitting element and is turned off during the initial period Pi and the sampling period Ps other than the emission period Pe, The leakage current flowing to the organic light emitting element can be cut off.

&Quot; (3) "

I _OLED = k / 2 Vsg-Vth ² = k / 2 Vs-Vg-Vth ² k / 2 VDD - Vdata Vinit Vth ² = k / 2 (Vdata-Vinit) ²

In Equation (3), k / 2 represents a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

Since the threshold voltage (Vth) component of the driving transistor DT is already included in Vsg programmed through the emission period (Pe), the equation (3) Similarly, the threshold voltage (Vth) component of the driving transistor DT is erased in the driving current Ioled relation. Thus, the influence of the change in the threshold voltage Vth on the drive current Ioled is eliminated.

As described above, although one frame is mainly divided into the initial period Pi, the sampling period Ps, and the emission period Pe, the present invention is not limited thereto. As shown in Fig. 15, A hold period Ph may further be included between the period Pi and the emission period Pe.

1) th scan signal SCAN (n-1) and the n-th emission signal EM (n) are applied in off-level in the hold period Ph, Is applied at an off level.

Thus, during the hold period Ph, the nth emission signal EM (n) is not applied to the ON level while the nth scan signal SCAN (n) is applied at the off level, Level. Thus, it is possible to prevent a noise due to a current change or a voltage change that may be generated when the nth scan signal SCAN (n) and the nth emission signal EM (n) are simultaneously synchronized. The remaining components of Fig. 15 are substantially the same as those described in Fig.

(N) scan signal 1 (SCAN1 (n)), the nth scan signal 2 (SCAN (2 (n)) and the nth emission signal EM (n) The structure of the pixel of the present invention described with reference to Figs. 2 to 15 is the same as that of the first embodiment except that the n-1 scan signal SCAN (n-1), the nth scan signal SCAN (n) the pixel structure of the present specification can drive a pixel with a GIP composed of two blocks. Therefore, since the width of the GIP forming region can be narrowed, Implementation of a narrow bezel may be possible.

16 to 18 are diagrams showing various examples in which the shift register of the scan driver and the inverter of the emission driver are implemented as a gate driver circuit.

FIG. 16 is a diagram showing the gate drive circuit 13 of FIG. 2 in detail. 16, the gate driving circuit may include a scan driver S1 (n) and an emission driver (EM Inv. (N)).

The scan driver may generate a scan signal in a row-sequential manner to supply at least one scan line connected to each pixel row to the scan lines. The scan driver includes a shift register. The shift register includes A stages, S1 (1) to S1 (n + 1), which are connected in a dependent manner. The emission driving unit may generate an emission signal in a row-sequential manner to supply at least one emission line connected to each pixel row to the emission lines. The emission driving unit includes an inverter. The inverter includes the B stages (Bstages, EM Inv (1) to EM Inv (N + 1)) which are connected in a dependent manner.

The A stages S1 (1) to S1 (n + 1) and the B stages EM Inv. (1) to EM Inv. (N + 1) are symmetrically symmetric about the active region Can be disposed on both sides of the region.

The A stages S1 (n-1) simultaneously output the n-1 scan signal SCAN (n-1) in response to the start pulse S1VST. The A stage S1 (n-1) outputs a carry signal different from the n-1 scan signal SCAN (n-1) and outputs a carry signal S1VST as a start pulse S1VST, (n). The carry signal can be input as the next stage single-stage start pulse.

The n-1th scan signal SCAN (n-1) is simultaneously supplied to the n-1th scan line of the (N-1) th pixel and the n-1th scan line of the nth pixel, n) and the A stage S1 (n).

1) th scan signal SCAN (n-1) while being supplied with the n-1 scan signal SCAN (n-1) The nth emission signal EM (n) inverted to the scan signal SCAN (n-1) is simultaneously supplied to the emission line of the n-th pixel.

The A stages S1 (n) are supplied with the n-1 scan signal SCAN (n-1) or the n-1 scan signal SCAN (n-1) The nth scan signal SCAN (n) is simultaneously supplied to the nth scan line of the nth pixel in response to the scan timing control signals such as the scan signal Vst and the clock GCLK.

The nth scan signal SCAN (n) is simultaneously supplied to the nth scan line of the nth pixel and the nth scan line of the (n + 1) th pixel, and the B stage EM Inv. (N + (S1 (n + 1)).

The nth scan signal SCAN (n) is supplied to the B stages EM INV. (N + 1) in synchronization with the nth scan signal SCAN (n) (N + 1) th emission signal EM (n + 1) which is inverted to the (N + 1) -th pixel.

When the n-th scan signal SCAN (n) is supplied or the first scan signal SCAN (n) and the carry signal are supplied, the A-stages S1 (n + 1) (N + 1) th scan line SCAN (n + 1) corresponding to the scan timing control signals of the (n + 1) th scan line,

Conventionally, in order to drive a pixel, a gate drive circuit is composed of a first scan driver, a second scan driver, and an emission driver. Further, the gate driving circuit can drive the pixels only when the A stage to the C stage, which are at least three blocks, are disposed. However, in this embodiment, the pixels can be driven by only the scan driver and the emission driver. Accordingly, the present embodiment can drive a pixel with only the A-stage and the B-stage. Therefore, the present embodiment can easily drive the narrow bezel because the pixel can be driven even in the existing 2/3 space.

17, odd-numbered A stages S1 (1) to S1 (2n-1) among the A stages S1 (1) to S1 (2n) and B stages 1) to EM Inv. (2n) may be disposed on one side of the active region and the even-numbered A stages S1 (1) to S1 (2n) of the A stages S1 2n) and B stages (EM Inv. (2) to EM Inv. (2n)) may be placed on the other side of the active area.

Thereby, the first A stages (S1 (1) to S1 (2n)) and the B stages (EM Inv. (1) to EM Inv. (2n)) arranged on one side of the active region The second A stages (S1 (2) to S1 (2n)) and the B stages (EM Inv. (2) to EM Inv. (2n)) disposed on the other side of the active region can operate. That is, the A stages S1 (1) to S1 (2n) and the B stages (EM Inv. (1) to EM Inv. (N + 1)) can operate sequentially in the zigzag direction.

The A stage S1 (2n-1) arranged on one side of the active region outputs the second n-1 scan signal SCAN (2n-1) in response to the start pulse S1VST and the B stage EM Inv. (2n-1) also outputs the second n-1 emission signal EM (2n-1) in response to the start pulse S1VST. The scan signal SCAN (2n-1) output from the A stage S1 (2n-1) is supplied to the A stage S1 (2n) and the B stage (EM Inv. 2n) And the scan signals SCAN (2n) and Em (2n-1) are input in response to the scan signal SCAN (2n-1) input to the A stage (S1 (2n)) and the B stage (EM Inv (2n + 1) and the B stage (EM (2n + 1)) arranged on one side and the B stage ).

As described above, the present embodiment separately arranges the A-stages and the B-stages arranged at odd-numbered positions and the A-stages and B-stages arranged at even-numbered positions to improve the freedom of space utilization, Narrow-bezel) can be easily implemented.

18, A stages (S1 (1) to S1 (n + 1)) can be disposed on one side of the active area and B stages (EM Inv. 1) may be disposed on the tee side of the active area.

Thus, the B stages (EM Inv. (1) to EM Inv. (N + 1)) disposed on the other side of the active region are A stages (S1 +1)). (1) to EM (n + 1) arranged on one side of the active region and B stages (EM Inv. (1) to EM Inv ) Can operate sequentially.

The A stage S1 (n) and the B stage EM Inv. (N) arranged on both sides of the active region can input signals to the pixels in response to the different start signals VST and EVST.

In the A stage S1 (n), the scan signal SCAN (n) output from the A stage S1 (n) in response to the start signal SVST transfers the signal to the nth pixel, Th pixel and input the start signal of the A stage (S1 (n + 1)). At this time, the B stage (EM Inv. (N)) applies the emission signal EM (n) to the Nth pixel in response to the start signal EVST and the B stage EM Inv. (N + The A stage and the B stage can be operated at the same time in sequence.

As described above, the present embodiment separates and arranges the A stages (S1 (1) to S1 (n + 1)) and the B stages (EM Inv. (1) to EM Inv. Thus, freedom of space utilization or freedom of design can be improved, and a narrow bezel can be easily implemented.

19 is a diagram showing an array arrangement of nodes connected to both electrodes of the capacitor Cstg in the pixel shown in Fig.

19, the fifth transistor T5 includes a semiconductor layer 210, a gate electrode, a drain electrode 221, and a source electrode. The sixth transistor T6 includes a semiconductor layer 210, A source electrode 220, a drain electrode 221, and a source electrode, and the capacitor Cstg includes a first electrode 225 and a second electrode. The first electrode 225 of the capacitor Cstg is connected to the initial voltage line Vini receiving the signal from the initial voltage Vini input terminal and the drain electrode 221 of the fifth transistor T5 and the sixth transistor T6 And the second electrode corresponds to the gate electrode 235 of the driving transistor DT. Therefore, an electrostatic capacity can be formed at the overlapping portion of the first electrode 225 and the second electrode 235. The source electrode of the fifth transistor T5 is connected to the gate electrode 235 of the driving transistor DT through the contact hole 271 and the source electrode of the sixth transistor T6 is connected to the anode of the organic light- Can be connected. The semiconductor layer 250 of the driving transistor DT is formed under the gate electrode 235 and the source contact hole 261 and the drain contact hole 263 can be connected to the source or drain electrode of another transistor, respectively .

The first electrode 225 of the capacitor Cstg is formed to have a larger area than the gate electrode 235 of the driving transistor DT so that the initial voltage Vini is applied to the first electrode 225, It is possible to suppress the influence of the mobile charge formed on the substrate 110. Therefore, the driving current of the driving transistor DT can be prevented from being reduced due to the influence of the mobile charge. Here, the initial voltage Vini may be a negative voltage.

The first electrode 225 of the capacitor Cstg is connected to the gate electrode 235 of the driving transistor DT and disposed in a region corresponding to the semiconductor layer of the third transistor T3 that operates in the sampling period, The effect of the mobile charge on the semiconductor layer of the third transistor T3 can be reduced. The arrangement of the first electrode 225 of the capacitor Cstg is not limited to that shown in Fig. 7, and can be applied to other embodiments.

The metal layer 114 may be disposed below the semiconductor layer 250 of the driving transistor DT so that a mobile charge formed on the substrate 110 affects the semiconductor layer 250 of the driving transistor DT. And the metal layer 114 may be formed to be equal to or larger than the size of the semiconductor layer 250 of the driving transistor DT.

At this time, the metal layer 114 may be formed of a semiconductor such as silicon (Si) or a conductive metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium ), Neodymium (Nd), and copper (Cu), or may be formed of two or more alloys.

The first electrode of the capacitor Cstg may be connected to the initial voltage line Vini without being connected to the high potential line VDD from the input terminal ELVDD of the high potential driving voltage so that the number of the contact holes may be reduced You can do the design.

FIG. 21 is a comparative example in which one electrode of the capacitor Cstg of FIG. 7 is connected to the high potential line VDD without being connected to the initial voltage line Vini.

21, the second transistor T2 is connected to the high potential line VDD through the contact hole 282 and the first electrode 225 of the capacitor Cstg is also connected to the high potential line VDD And is connected through another contact hole 281. Therefore, a contact hole 281 for connecting the capacitor Cstg and the high potential line VDD has been added. However, when one electrode of the capacitor Cstg is connected to the initial voltage line Vini as shown in FIGS. 7 and 19, the first electrode 225 of the capacitor Cstg is connected to the fifth transistor T5 and the sixth transistor T6 and the initial voltage line Vini are connected to each other through one contact hole, the number of contact holes can be reduced as compared with the comparative example of FIG. Therefore, by connecting one electrode of the capacitor to the initial voltage line Vini instead of the high potential line VDD, the number of contact holes can be reduced, thereby ensuring a pixel design margin.

Hereinafter, a section cut along the line I-I 'in FIG. 19 will be described with reference to FIG.

Referring to FIG. 20, a first buffer layer 120 is disposed on a substrate 110. The first buffer layer 120 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The substrate 110 may be an insulating layer of glass, metal, plastic, or polyimide type, and may be formed of two or more layers. When the organic light emitting display is a flexible organic light emitting display, it may be made of a flexible material such as plastic. Further, when the organic light emitting device, which is easy to implement in a flexible manner, is applied to a vehicular illumination device or a vehicle display device, flexibility in designing and designing a vehicle lighting device or a vehicle display device in accordance with the structure of the vehicle or the appearance Can be secured.

A metal layer 114 may be disposed on the first buffer layer 120 and a second buffer layer 130 may be disposed on the metal layer 114. The second buffer layer 130 may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

The semiconductor layer 210 is located on the second buffer layer 130. The semiconductor layer 210 may be formed of a silicon semiconductor or an oxide semiconductor. The semiconductor layer 210 of the sixth transistor T6 includes a drain region 215, a source region, a lightly doped region LDD, and a channel region 211 located therebetween. The impurity of the semiconductor layer 210 may be at least one p-type impurity selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In) The semiconductor layer of the driving transistor DT and the fifth transistor T5 may also be formed in the same process as the semiconductor layer 210 of the sixth transistor T6.

A first insulating layer 140 is formed on the semiconductor layer 210. The first insulating layer 140 may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

The gate electrode 220 of the sixth transistor T6 is located on the channel region 211 of the semiconductor layer 210. [ The gate electrode 220 may be formed of any one or two of Mo, Al, Cr, Au, Ni, Ni, Nd, Or more. The gate electrode 235 of the driving transistor DT and the fifth transistor T5 may be formed in the same process as the gate electrode 220 of the sixth transistor T6.

The second insulating layer 150 is located on the gate electrodes 220 and 235. The second insulating layer 150 may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

A first electrode 225 of a capacitor Cstg connected to the initial voltage line Vini is located on the second insulating layer 150.

That is, the first electrode 225 connected to the initial voltage line Vini and the second electrode 235 connected to the gate electrode 235 of the driving transistor DT are overlapped with each other to form a capacitor Cstg . In addition, since the first electrode 225 has a larger area than the second electrode 235, the influence of mobile charges on the semiconductor layer of the driving transistor can be reduced.

A third insulating film 160 is disposed on the first electrode 225 of the capacitor Cstg. The third insulating layer 160 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

After the third insulating layer 160 is formed, the first to third insulating layers 140, 150 and 160 and the first electrode 225 of the capacitor Cstg are selectively etched to form the contact hole 223. A part of the semiconductor layer 210 of the sixth transistor T6 is exposed by the contact hole 223. [

A drain electrode 221 of the sixth transistor T6 formed in the contact hole 223 is located on the third insulating film 160. [ The drain electrode 221 of the sixth transistor T6 shares the same contact hole 223 with the drain electrode of the fifth transistor T5 and is connected to the initial voltage line Vini 225. The drain electrode 221 may be formed of any one of Mo, Al, Cr, Au, Ni, Ni, Nd, Based alloy. When the drain electrode 221 is a multilayer, it may be formed of a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

A fourth insulating layer 170 is formed on the drain electrode 221. The fourth insulating film 170 may be a planarizing film for alleviating the step difference of the lower structure and may be formed of organic materials such as polyimide, benzocyclobutene series resin, and acrylate.

The source electrode and the drain electrode of the above-mentioned transistors may alternatively be applied. In particular, the present invention can be applied to the first to sixth transistors which serve as on / off functions other than the driving transistor DT.

The organic light emitting display of the present invention can be applied to a display device including a TV, a mobile, a tablet PC, a monitor, a smart watch, a laptop computer, Can be applied. In addition, the present invention can be applied to a display device implemented in various forms such as a flat display, a bandable display, a foldable display, and a rollable display.

The organic light emitting display according to the embodiment of the present invention can be described as follows.

An OLED display according to an exemplary embodiment of the present invention includes a display panel having a plurality of pixels, a gate driving circuit driving scan lines and emission lines of the display panel, and a data driving circuit Each pixel arranged in n (n is a natural number) pixel column among the pixels has an organic light emitting element having an anode electrode connected to a node C and a cathode electrode connected to an input terminal of a low potential driving voltage, A driving transistor for controlling a driving current to be applied to the organic light emitting element, the driving transistor including a connected gate electrode, a source electrode connected to the node D, and a drain electrode connected to the node B; A second transistor connected between the node D and an input terminal of the high potential driving voltage, a third transistor connected between the node A and the node B, a node B and a node C A fifth transistor connected between the node A and the input terminal of the initial voltage, and a capacitor connected between the node A and the input terminal of the initial voltage. Therefore, the threshold voltage sampling period of the driving transistor can be sufficiently secured, and the accuracy of the threshold voltage compensation can be improved.

One frame period includes the initial period for initializing the node A, the sampling period for sampling the threshold voltage of the driving transistor and storing it in the node A, the source-gate voltage of the driving transistor including the sampled threshold voltage, And an emission period in which the organic light emitting element is caused to emit light by a driving current according to the programmed source-gate voltage. The gate electrode of the fifth transistor is connected to the (n-1) th first scan line to which the (n-1) th scan signal is applied, and the gate electrode of each of the first and third transistors is connected to the n- 1 scan line, and the gate electrodes of the second transistor and the fourth transistor may be connected to the nth first emission line to which the nth emission signal is applied. In the initial period, the (n-1) th scan signal may be applied at an on level, and the n th scan signal and the n th emission signal may be applied at an off level. In the sampling period, the nth scan signal is applied to the on level and the (n-1) th scan signal and the nth emission signal may be applied to the off level. In the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal may be applied in off-level.

And a sixth transistor connected between the input terminal of the initial voltage and the node C.

One frame period includes the initial period for initializing the node A and the node C, the sampling period for sampling the threshold voltage of the driving transistor and storing the sampled threshold voltage in the node A, and the sampling-period voltage of the driving transistor including the sampled threshold voltage And an emission period during which the organic light emitting element is caused to emit light by a driving current according to the programmed source-gate voltage. The gate electrodes of the fifth transistor and the sixth transistor are connected to the (n-1) th first scan line to which the (n-1) th scan signal is applied, and the gate electrodes of the first transistor and the third transistor are connected to the And the gate electrode of each of the second transistor and the fourth transistor may be connected to the nth emission line to which the nth emission signal is applied. In the initial period, the (n-1) th scan signal is applied to the on level and the n th scan signal and the n th emission signal may be applied to the off level. In the sampling period, the nth scan signal is applied to the on level, and the (n-1) th scan signal and the nth emission signal are applied to the off level. In the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal may be applied in off-level.

One frame period includes the initial period for initializing the node A and the node C, the sampling period for sampling the threshold voltage of the driving transistor and storing the sampled threshold voltage in the node A, and the sampling-period voltage of the driving transistor including the sampled threshold voltage And an emission period during which the organic light emitting element is caused to emit light by a driving current according to the programmed source-gate voltage. The gate electrode of each of the fifth transistors is connected to the (n-1) th first scan line to which the (n-1) th scan signal is applied, and the gate electrodes of the first transistor, the third transistor, And the gate electrode of each of the second transistor and the fourth transistor may be connected to the nth emission line to which the nth emission signal is applied. In the initial period, the (n-1) th scan signal is applied to the on level, the n th scan signal and the n th emission signal are applied to the off level, the n th scan signal is applied to the on level during the sampling period, the n-1 scan signal and the nth emission signal may be applied in off-level. In the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal may be applied in off-level.

The initial period may be included in the (n-1) -th horizontal period, and the sampling period may be included in the n-th horizontal period.

A transistor having a source electrode or a drain electrode connected to one electrode of a capacitor in each pixel includes at least two transistors connected in series to each other and two or more transistors can be switched by the same control signal.

The first electrode of the capacitor is located between the insulating films located between the semiconductor layer and the source electrode of the fifth transistor and is connected to the first electrode of the capacitor through the drain electrode of the fifth transistor and the drain electrode of the sixth transistor through the contact hole .

The driving transistor may further include a metal layer under the semiconductor layer.

The first electrode of the capacitor which is supplied with the initial voltage at the input terminal of the initial voltage may be arranged corresponding to the gate electrode of the driving transistor.

The first electrode of the capacitor which is supplied with the initial voltage at the input terminal of the initial voltage may be disposed in a region corresponding to the semiconductor layer of the third transistor operating during the sampling period.

The first electrode of the capacitor corresponds to the gate electrode of the driving transistor connected to the node A, the second electrode corresponds to the electrode connected to the input terminal of the initial voltage, the first electrode does not connect to the input terminal of the high- Lt; / RTI >

An OLED display according to an exemplary embodiment of the present invention includes a display panel having a plurality of pixels, a gate driving circuit driving scan lines and emission lines of the display panel, and a data driving circuit Each pixel arranged in n (n is a natural number) pixel column among the pixels has an organic light emitting element having an anode electrode connected to a node C and a cathode electrode connected to an input terminal of a low potential driving voltage, A driving transistor for controlling the driving current applied to the organic light emitting element, including a connected gate electrode, a source electrode connected to the input terminal of the high potential driving voltage, and a drain electrode connected to the node B, A second transistor connected between the node A and the node B, a third transistor connected between the node D and an input terminal of the initial voltage, and a node B A fifth transistor connected between the node A and the input terminal of the initial voltage, a sixth transistor connected between the input terminal of the initial voltage and the node C, and a fourth transistor connected between the node A and the node D, Capacitors. Therefore, the driving transistor determines the amount of current supplied to the organic light emitting element OLED in response to the voltage changed at the node A. [ Thus, the operation stability of the circuit can be improved and the luminance of the organic light emitting diode OLED can be easily controlled. In addition, it is possible to prevent a short between the data voltage (Vdata) and the initial voltage (Vini) in the initial period, and the sampling period for compensating the pixel can be increased to improve the compensation capability.

One frame period includes a initial period for initializing the node A and the node C, a sampling period for sampling the threshold voltage of the driving transistor and storing the sampled threshold voltage in the node A (node D), and a source- And an emission period in which the organic light emitting element is caused to emit light with a drive current corresponding to the programmed source-gate voltage. The gate electrodes of the fifth and sixth transistors are connected to the (n-1) th first scan line to which the (n-1) th scan signal is applied, and the gate electrodes of the first and second transistors are connected to the Th first scanning line, and the gate electrodes of the third and fourth transistors may be connected to the nth first emission line to which the nth emission signal is applied. In the initial period, the (n-1) th scan signal is applied to the on level and the n th scan signal and the n th emission signal may be applied to the off level. In the sampling period, the nth scan signal is applied to the on level and the (n-1) th scan signal and the nth emission signal are applied to the off level. In the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal may be applied in off-level.

The initial period may be included in the (n-1) -th horizontal period, and the sampling period may be included in the n-th horizontal period.

The second transistor includes at least two transistors connected in series to each other, and the two or more transistors can be switched by the same control signal.

The OLED display according to one embodiment of the present invention includes a transistor array including n-1-th and n-th pixels arranged in rows, a driving transistor, a sampling transistor, and a first initial transistor, The gate electrode of the first initial transistor for initializing the driving transistor of the n-th pixel is connected to the gate electrode of the (n-1) -th pixel so that the threshold voltage sampling period of the driving transistor is sufficiently So that the accuracy of the threshold voltage compensation can be improved.

The number of contact holes can be minimized by connecting the capacitors to receive an initial voltage rather than a high potential driving voltage.

The capacitor includes an electrode connected to the input terminal of the initial voltage and one contact hole connecting the input terminal of the initial voltage and the electrode, and a second initial electrode for providing a negative voltage to one electrode of the organic light emitting element through one contact hole. And may be connected to a drain electrode or a source electrode of the transistor.

The capacitor includes a first electrode provided with an initial voltage and a second electrode connected to the transistor, and the first electrode may be formed wider than the second electrode.

And a metal layer disposed under the semiconductor layer of the driving transistor.

The first electrode of the capacitor may be disposed in an area corresponding to the semiconductor layer of the sampling transistor.

The first initial transistor includes at least two transistors connected in series to each other, and at least two transistors can be switched by the same control signal.

The sampling transistor includes at least two transistors connected in series to each other, and at least two transistors can be switched by the same control signal.

An organic light emitting element that emits light by the driving transistor, and an emission transistor that blocks light emission so that the organic light emitting element does not emit light in a period other than the light emitting period.

In the organic light emitting diode display according to an embodiment of the present invention, the organic light emitting elements arranged in the (n-1) th pixel and the (n) A sampling transistor included in an nth pixel connected to the nth scan signal, an emission transistor included in an nth pixel and connected to the nth emission signal, and an organic light emitting diode One frame includes an initial period, a sampling period, and an emission period. In the initial period, the (n-1) th scan signal is applied to the on level and the n th scan signal and the n th emission signal are applied to the off level. In the sampling period, the nth scan signal is applied to the on level and the (n-1) th scan signal and the nth emission signal are applied to the off level. During the emission period, the nth emission signal is applied at the on level, and the (n-1) th scan signal and the (n) th scan signal are applied at the off level.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: Data line 15: Gate line

Claims (11)

An (n-1) -th pixel and an n-th pixel arranged in a row;
A transistor array including a driving transistor, a sampling transistor, and a first initial transistor;
A capacitor implemented to be coupled between an input of the initial voltage and the sampling transistor;
And the gate electrode of the first initial transistor for initializing the driving transistor of the nth pixel is connected to the gate electrode of the (n-1) th pixel. The method according to claim 1,
Wherein the capacitors are connected to receive an initial voltage other than a high potential driving voltage, thereby minimizing the number of contact holes. The method according to claim 1,
An electrode connected to an input terminal of the initial voltage; And
A source electrode and a drain electrode of the second initial transistor for providing a negative voltage to one electrode of the organic light emitting diode through the one contact hole, And an organic light emitting diode (OLED). The method according to claim 1,
Wherein the capacitor includes a first electrode that receives an initial voltage and a second electrode that is connected to the transistor, wherein the first electrode is wider than the second electrode. The method according to claim 1,
And a metal layer disposed under the semiconductor layer of the driving transistor. The method according to claim 1,
Wherein the first electrode of the capacitor is disposed in a region corresponding to the semiconductor layer of the sampling transistor. The method according to claim 1,
Wherein the first initial transistor includes at least two transistors connected in series to each other, and the at least two transistors are switched by the same control signal. The method according to claim 1,
Wherein the sampling transistor includes at least two transistors connected in series to each other, and the two transistors are switched by the same control signal. The method according to claim 1,
An organic light emitting element emitting light by the driving transistor; And
And an emission transistor for blocking light emission so that the organic light emitting element does not emit light in a period other than a light emitting period. 10. The method of claim 9,
The emissive transistor is connected to the anode electrode of the organic light emitting diode. An (n-1) -th pixel and an n-th pixel arranged in a row;
An organic light emitting element disposed in each of the pixels;
An initial transistor of an n-th pixel connected to the (n-1) th scan signal of the (n-1) th pixel;
A sampling transistor included in the n-th pixel and connected to the n-th scan signal;
An emission transistor included in the nth pixel and connected to the nth emission signal; And
One frame for driving the organic light emitting element includes a initial period, a sampling period, and an emission period,
In the initial period, the (n-1) th scan signal is applied to the on level, the n th scan signal and the n th emission signal are applied to the off level,
In the sampling period, the n-th scan signal is applied to the on level, the n-1 scan signal and the n-th emission signal are applied to the off level,
Wherein the n th emission signal is applied at an on level and the n th scan signal and the n th scan signal are applied in an off level in the emission period.

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