KR20170119956A - Display device - Google Patents

Abstract

The present invention relates to a display device capable of preventing image defects due to a regular polarity inversion period of a data voltage. The display device includes: a display panel including a plurality of data lines; A timing controller for generating a plurality of polarity signals; And a data driver receiving the plurality of polarity signals and outputting a plurality of data voltages having different irregular polarity inversion periods to the plurality of data lines.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device capable of preventing image defects due to regular polarity inversion periods of a data voltage.

Flat panel displays (FPDs) have been replaced with conventional cathode ray tube (CRT) display devices to provide a compact and lightweight display device for portable computers such as notebook computers, PDAs, and mobile phone terminals as well as monitors of desktop computers Lt; RTI ID = 0.0 > system. ≪ / RTI > Currently available flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) The device is favored as a display device used for a mobile device, a computer monitor, and an HDTV due to its advantages such as excellent visibility, easy thinning, low power and low heat generation.

1 is a view schematically showing a conventional liquid crystal display device.

1, the liquid crystal display device 10 includes a liquid crystal display panel 12, a gate driver 13, and a data driver 14.

In the liquid crystal display panel 12, a plurality of gate lines GL and a plurality of data lines DL are formed in a matrix form on a substrate (not shown). A plurality of subpixels (R, G, B) are defined at the intersections of the gate lines GL and the data lines DL. More specifically, the first data line DL1 is commonly connected to the red subpixel R in the odd column and green subpixel G in the even column located on both sides. The subpixels R, G and B in one row are alternately connected to the odd gate lines GL1 and GL3 and the even gate lines GL2 and GL4 located on both sides.

In response to a gate control signal (not shown) inputted from a timing control unit (not shown), the gate driving unit 13 sequentially applies a gate voltage to the gate line GL formed in the liquid crystal display panel 12 Output.

The data driver 14 applies a data voltage Vd of the analog waveform to the data line DL through the data line DL in response to a data control signal (not shown) input from the timing controller and digital image data (not shown) To the sub-pixels R, G, and B of the panel 12, respectively. The liquid crystal alignment state of each of the sub-pixels R, G, and B is changed according to the applied data voltage Vd to display an image by adjusting the light transmittance.

Here, characteristic deterioration occurs when a constant DC voltage is applied to the liquid crystal for a long time. Therefore, in order to prevent this, the polarity of the data voltage Vd applied to each of the sub-pixels R, G, and B is periodically changed and driven. This driving method is referred to as an inversion method. These inversion schemes include frame inversion, line inversion, and dot inversion.

The dot inversion method is a driving method in which the polarity of the data voltage Vd between all the adjacent subpixels (R, G, B) is opposite. In particular, the conventional liquid crystal display device 10 is driven by a 4-dot inversion method. Thus, the 2X2 subpixels R, G, and B adjacent to the left and right sides of the picture have the same polarity, and the polarity of the data voltage Vd is inverted in units of four horizontal periods, so that the polarity inversion period of eight horizontal periods is obtained.

2 is a view showing a green subpixel of a conventional liquid crystal display device.

Since image defects are largely influenced by the green subpixel G, the following description is based on the green subpixel G. [

2, when the liquid crystal display device 10 is driven by the 4-dot inversion method, each green subpixel G has a positive polarity and a negative polarity data voltage Vd ), And may be approximately charged when the polarity of the data voltage Vd is reversed. Two problems arise at this time.

First, the green subpixel G filled with the positive polarity data voltage Vd and the green subpixel G filled with the negative polarity data voltage Vd are aggregated in a diagonal shape, so that a constant diagonal pattern is generated do. As a result, diagonal image defects may occur.

Secondly, the green subpixels G in which the data voltage Vd is weakly charged are regularly arranged, and image defects of the horizontal line and the vertical line occur. That is, the data voltage Vd is weakly charged in the green subpixel G of the even-numbered display line (not shown), resulting in a bad image on the horizontal line. Also, the data voltage Vd is weakly charged in the green subpixel G connected to the 3n (n is an integer) data lines DL3 and DL6, and a vertical line image defect occurs.

An object of the present invention is to provide a display device capable of preventing an image defect due to a regular polarity inversion period of a data voltage by making the polarity inversion period of the data voltage irregular.

According to an aspect of the present invention, there is provided a display device including a display panel, a timing controller, and a data driver.

The display panel includes a plurality of data lines.

The timing control section generates a plurality of polarity signals.

The data driver receives the plurality of polarity signals and outputs a plurality of data voltages to the plurality of data lines.

The plurality of data voltages to be output have different irregular polarity inversion periods.

The display device according to the present invention can prevent the image failure due to the regular polarity reversal period of the data voltage by making the charged subpixels and the subpixels of the positive or negative polarity not to form a certain pattern.

1 is a view schematically showing a configuration of a conventional liquid crystal display device.
2 is a view showing a green subpixel of a conventional liquid crystal display device.
3 is a view showing a display device according to the present invention.
4 is a view showing a display panel according to the present invention.
5 is a diagram showing a data driver of a display device according to the present invention.
6A and 6B are waveform diagrams and green subpixels of a data voltage of a display device according to an embodiment of the present invention.
7A and 7B are waveform diagrams and green subpixels of a data voltage of a display device according to another embodiment of the present invention.

Hereinafter, a display device according to the present invention will be described in detail with reference to the accompanying drawings.

The display device 100 of the present invention may include a liquid crystal display device, an organic field display device, and the like. Hereinafter, a liquid crystal display device will be described as an example for convenience of explanation.

3 is a view showing a display device according to the present invention.

3, a display device 100 according to the present invention includes a display panel 120, a timing controller 110, a gate driver 130, and a data driver 140.

The display panel 120 includes a plurality of gate lines GL and a plurality of data lines DL formed in a matrix shape on a substrate (not shown) using glass or plastic. A plurality of pixels PX are defined at the intersections of the gate lines GL and the data lines DL.

Each pixel PX of the display panel 120 is provided with at least one thin film transistor (not shown). The gate electrode of the thin film transistor is connected to the gate line GL, and the source electrode thereof is connected to the data line DL. The drain electrode is connected to a pixel electrode (not shown) opposite to a common electrode (not shown) to control a voltage applied to a liquid crystal (not shown). Thus, the movement of the liquid crystal is controlled to realize the gradation of the liquid crystal display device.

The timing controller 110 receives a timing signal TS transmitted from an external system (not shown) and generates a gate control signal GCS, a data control signal DCS, and a polarity signal POL. The gate control signal GCS is output to the gate driver 130 and the data control signal DCS and the polarity signal POL are output to the data driver 140. Here, the timing signal TS may be a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, and a clock signal CLK. The timing controller 110 generates digital image data RGB from the video signal VS transmitted from the external system and outputs the digital image data RGB to the data driver 140.

The gate driver 130 may sequentially output the gate voltage by one horizontal period through the gate line GL in response to the gate control signal GCS provided from the timing controller 110. [ Accordingly, the thin film transistor connected to each gate line GL turns on every horizontal period. Here, the gate driver 130 may include a plurality of shift registers (not shown) connected to the plurality of gate lines GL, and may be configured as a GIP (Gate In Panel) mounted in the touch display panel 110 .

Here, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE. The gate start pulse GSP is applied to the shift register of the gate driver 130 as a signal for determining when to output the gate voltage to the first gate line GL. The gate shift clock GSC is commonly applied to each shift register and is a clock signal that enables a next shift register (not shown). The gate output enable signal GOE controls the output of the shift register.

The data driver 140 converts the digital image data RGB provided from the timing controller 110 into an analog data voltage Vd according to the data control signal DCS and the polarity signal POL. The data driver 140 applies the analog data voltage Vd to the pixel electrode of each pixel PX through the data line DL.

The data control signal DCS includes a source start pulse SSP, a source shift clock SSC and a source output enable signal SOE. The source start pulse SSP determines the sampling start timing of the video data RGB of the data driver 140. The source shift clock SSC is a clock signal for controlling the data sampling operation in the data driver 140. The source output enable signal SOE controls the output of the data driver 140.

4 is a view showing a display panel according to the present invention.

As shown in Fig. 4, the pixel may be composed of multicolor subpixels. For example, the red subpixel R, the green subpixel G, and the blue subpixel B may be sequentially arranged.

Also, the display panel may be driven by a double rate driving (DRD) method. The display panel 120 includes a plurality of sub-pixels arranged between the odd gate lines GL1, GL3, GL5 and GL7 and the even-numbered gate lines GL2, GL4, GL6 and GL8, Each of the data lines DL is commonly connected to subpixels R, G, and B in an odd column and subpixels R, G, and B in an even column, .

For example, the first data line DL1 is commonly connected to the red subpixel R in the odd column and the green subpixel G in the even column located on both sides. The subpixels R, G and B in one row are alternately connected to the odd gate lines GL1, GL3, GL5 and GL7 located on both sides and the even gate lines GL2, GL4, GL6 and GL8. Due to the above structure, the number of gate lines GL is doubled, but the number of data lines DL is halved.

 One data line DL in the display panel applies a data voltage Vd to subpixels R, G and B in odd columns and subpixels R, G and B in an even column. That is, the data voltage Vd is applied to the green subpixel G by the first data line DL1 at the turn-on time of the first gate line GL1 and the data voltage Vd is applied to the turn-on time of the second gate line GL2 After the data voltage Vd is applied to the red subpixel R by the first data line DL1 and the green subpixel G by the first data line DL1 at the turn-on time of the third gate line GL3, The data voltage Vd is applied. Therefore, the data voltage Vd is sequentially applied to each of the sub-pixels R, G, and B in the left-right inverted Z direction.

5 is a diagram showing a data driver of a display device according to the present invention.

As shown in FIG. 5, the data driver 140 includes a polarity controller 150 and a plurality of data ICs 141, 142, 143, 144,...

The polarity control unit 150 includes a plurality of pairs of buffers and an inverter and receives a plurality of polarity signals POL from the timing control unit 110 and outputs a plurality of polarity signals POL And generates a polarity signal PPOL and a negative polarity signal NPOL. That is, a pair of buffers and an inverter receive a single polarity signal POL, a positive polarity signal PPOL is generated through a buffer, A polarity signal (NPOL) is generated. Here, the positive polarity signal PPOL and the negative polarity signal NPOL are opposite to each other in polarity.

The data integration circuits 141, 142, 143, 144, ... receive the positive polarity signal PPOL and the negative polarity signal NPOL from the polarity controller 150 and output the corresponding data voltage Vd And outputs them to the connected data lines DL. More specifically, the data integrated circuits 141, 142, 143, 144, ... comprise a plurality of odd-numbered data accumulating circuits 141, 143 and odd-numbered data accumulating circuits 142, 144. The odd-numbered data integrated circuits 141 and 143 receive the positive polarity signal PPOL and output positive data voltages PVd to the odd data lines DL1 and DL3, Receives the negative polarity signal NPOL and outputs the sub data voltage NVd to the even data lines DL2 and DL4. Here, the positive data voltage (PVd) and the sub data voltage (NVd) are a kind of the data voltage (Vd), and the polarities are opposite to each other.

For example, the polarity control unit 150 receives the first polarity signal POL1, generates a first positive polarity signal PPOL1 through a buffer, and outputs a first negative polarity signal NPOL1 ). The first data integration circuit 141 receives the first positive polarity signal PPOL1 and outputs the first positive data voltage PVd1 to the first data line DL1. The second data integration circuit 142 receives the first negative polarity signal NPOL1 and outputs the first sub data voltage NVd1 to the second data line DL2. Since the polarities of the first positive polarity signal PPOL1 and the first negative polarity signal NPOL1 are opposite to each other, the polarities of the first positive data voltage PVd1 and the first sub data voltage NVd1 are also opposite to each other.

Hereinafter, the data voltage polarity inversion method of the display device having the above configuration will be described.

Each of the plurality of data voltages Vd may be irregularly reversed in polarity every three horizontal periods, four horizontal periods, or five horizontal periods, and the polarity of the data voltage Vd should be repeated with a period of 16 horizontal periods. That is, the polarity of the data voltage Vd may be inverted every four horizontal periods by dividing the 16 horizontal periods into four horizontal periods. Alternatively, the polarity of the data voltage (Vd) is divided by dividing the 16 horizontal periods into two 3 horizontal periods and two 5 horizontal periods, and divides the 16 horizontal periods into 3 horizontal periods, 5 horizontal periods, and 4 horizontal periods The polarity of the data voltage Vd can be inverted. At this time, the order of each horizontal period can be arbitrarily set.

In addition, the polarity of the data voltage Vd output to the data lines DL adjacent to each other may not be the same for two horizontal periods or more. 5, the first positive data voltage PVd1 and the second positive data voltage PVd2 output to the first and third data lines DL1 and DL2 adjacent to the second data line DL2, Is opposite to the first sub-data voltage NVd1 applied to the second data line DL2, or is the same polarity for only one horizontal period, and is necessarily opposite to the polarity for the next horizontal period.

By making the polarity inversion period of each data voltage Vd irregular, it is possible to relieve image defects due to polarity inversion of the regular data voltage Vd on the display panel 120, as will be described later.

6A and 6B are waveform diagrams and green subpixels of a data voltage of a display device according to an embodiment of the present invention.

As shown in FIG. 6A, the plurality of data lines DL are grouped and driven by four data lines DL. That is, the (4n-2) th data lines DL 4n-1 and the (4n-1) th data lines DL 4n- And the 4n-th data lines DL 4n among the data lines DL 4n output the data voltage Vd of the same polarity. Hereinafter, the data voltages Vd applied to the first to fourth data lines DL1 to DL4 will be referred to.

The first positive data voltage PVd1 applied to the first data line DL1 has a negative polarity for the first three horizontal periods, a positive polarity for the next four horizontal periods, a negative polarity for the next five horizontal periods, to be. By setting the inversion period of the four horizontal periods between the inversion period of the three horizontal periods and the inversion period of the five horizontal periods, the polarity arrangement in the display panel 120 can be effectively made irregular.

The first sub data voltage NVd1 applied to the second data line DL2 is polarity opposite to the first positive data voltage PVd1. That is, the first sub data voltage NVd1 is positive for the first three horizontal periods, negative for the next four horizontal periods, positive for the next five horizontal periods, and negative for the last four horizontal periods.

The second positive data voltage PVd2 applied to the third data line DL3 has the same polarity inversion period as the first positive data voltage PVd1 but has a different inversion time. That is, negative for the first three horizontal periods, positive for the next four horizontal periods, negative for the next five horizontal periods, and positive for the last four horizontal periods, based on eight horizontal periods. By varying the inversion points in this way, the polarity arrangement can be made irregular in the display panel 120 effectively.

The second sub data voltage NVd2 applied to the fourth data line DL4 is polarity opposite to the second positive data voltage PVd2. That is, the second sub data voltage NVd2 has positive polarity for the first three horizontal periods, negative polarity for the next four horizontal periods, positive polarity for the next five horizontal periods, negative polarity for the last four horizontal periods, to be.

When the polarity of the data voltage Vd is reversed in this manner, the polarity of the data voltage Vd output to the adjacent data line DL may not be equal to or more than two horizontal periods.

The effect of the data voltage polarity reversal method will be described with reference to FIG. 6B. Since image defects are largely influenced by the green subpixel G, the following description is based on the green subpixel G. [

First, it can be seen that the subpixels (R, G, B) with the data voltage (Vd) charged roughly are arranged irregularly. When the polarity of the data voltage Vd is inverted, approximately charging of the data voltage Vd occurs. Accordingly, if the subpixels R, G, and B having the data voltage Vd are charged to a certain extent or in a certain pattern, this leads to an image failure. In the case of the embodiment of the present invention, It is difficult to find a certain pattern of the subpixels R, G, and B, so that image defects are alleviated.

Secondly, the subpixels R, G and B charged with the positive polarity data voltage Vd and the subpixels R, G and B charged with the negative polarity data voltage Vd are irregular . As a result, it can be confirmed that the image defect of the diagonal line, which is a conventional problem, does not occur.

7A and 7B are waveform diagrams and green subpixels of a data voltage of a display device according to another embodiment of the present invention.

As shown in FIG. 7A, the plurality of data lines DL are grouped and driven by six data lines DL. That is, the 6n-4 th data line DL 6n-4, the 6n-3 th data line DL 6n-3, (6n-2) th data lines (DL 6n-2), (6n-1) th data lines (DL 6n-1) . Hereinafter, the data voltages Vd applied to the first to sixth data lines DL1 to DL6 will be described.

The first positive data voltage PVd1 applied to the first data line DL1 has a negative polarity for the first three horizontal periods, a positive polarity for the next four horizontal periods, a negative polarity for the next five horizontal periods, to be. By setting the inversion period of the four horizontal periods between the inversion period of the three horizontal periods and the inversion period of the five horizontal periods, the polarity arrangement in the display panel 120 can be effectively made irregular.

The first sub data voltage NVd1 applied to the second data line DL2 is polarity opposite to the first positive data voltage PVd1. That is, the first sub data voltage NVd1 is positive for the first three horizontal periods, negative for the next four horizontal periods, positive for the next five horizontal periods, and negative for the last four horizontal periods.

The second positive data voltage PVd2 applied to the third data line DL3 has the same polarity inversion period as the first positive data voltage PVd1 but has a different inversion time. That is, negative for the first three horizontal periods, positive for the next four horizontal periods, negative for the next five horizontal periods, and positive for the last four horizontal periods, based on eight horizontal periods. By varying the inversion points in this way, the polarity arrangement can be made irregular in the display panel 120 effectively.

The second sub data voltage NVd2 applied to the fourth data line DL4 is polarity opposite to the second positive data voltage PVd2. That is, the second sub data voltage NVd2 has positive polarity for the first three horizontal periods, negative polarity for the next four horizontal periods, positive polarity for the next five horizontal periods, negative polarity for the last four horizontal periods, to be.

The third positive data voltage PVd3 applied to the fifth data line DL5 is inverted every four horizontal periods. More specifically, it is negative for the first 4 horizontal periods based on 7 horizontal periods, positive for the following 4 horizontal periods, negative for 4 subsequent horizontal periods, and positive for the last 4 horizontal periods.

The third sub data voltage NVd3 applied to the sixth data line DL6 is polarity opposite to the third positive data voltage PVd3. That is, positive for the first four horizontal periods relative to seven horizontal periods, negative for the following four horizontal periods, positive for the next four horizontal periods, and negative for the last four horizontal periods. By applying the data voltage Vd having the four horizontal period polarity inversion period in this way, the polarity inversion period of the data voltage Vd can be made more irregular.

When the polarity of the data voltage Vd is reversed in this manner, the polarity of the data voltage Vd output to the adjacent data line DL may not be equal to or more than two horizontal periods.

The effect of the data voltage polarity reversal method will be described with reference to FIG. 7B. Since image defects are largely influenced by the green subpixel G, the following description is based on the green subpixel G. [

First, it can be seen that the subpixels (R, G, B) with the data voltage (Vd) charged roughly are arranged irregularly. When the polarity of the data voltage Vd is inverted, approximately charging of the data voltage Vd occurs. Accordingly, when the sub-pixels R, G, and B having the data voltage Vd are charged to a certain extent or in a certain pattern, this leads to an image failure. In another embodiment of the present invention, It is difficult to find a certain pattern of the sub-pixels R, G, and B, so that image defects are alleviated.

Secondly, the subpixels R, G and B charged with the positive polarity data voltage Vd and the subpixels R, G and B charged with the negative polarity data voltage Vd are irregular . As a result, it can be confirmed that the image defect of the diagonal line, which is a conventional problem, does not occur.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: display device 110: timing controller
120: display panel 130: gate driver
140: Data driver 150: Polarity controller
POL: polarity signal

Claims (8)

A display panel including a plurality of data lines;
A timing controller for generating a plurality of polarity signals; And
And a data driver for receiving the plurality of polarity signals and outputting a plurality of data voltages to the plurality of data lines,
Wherein the plurality of data voltages to be output have different irregular polarity inversion periods. The method according to claim 1,
Wherein the data driver comprises a polarity controller and a plurality of data integrated circuits,
Wherein the polarity control unit receives a plurality of polarity signals from the timing control unit and generates a positive polarity signal and a negative polarity signal having a polarity opposite to that of the positive polarity signal,
Wherein the plurality of data integrated circuits receive the positive polarity signal and the negative polarity signal, respectively, and output the data voltage to the data line. 3. The method of claim 2,
Wherein the plurality of data integrated circuits includes an odd data integrated circuit and a superior data integrated circuit,
Wherein the data voltage includes a positive data voltage, a negative data voltage having polarity opposite to the positive data voltage,
Wherein the odd data integrated circuit receives the positive polarity signal and outputs the positive data voltage to the odd data line,
Wherein the excellent data integration circuit receives the negative polarity signal and outputs the sub data voltage to the excellent data line. The method according to claim 1,
Wherein the data voltage is irregularly reversed in polarity every three horizontal periods, four horizontal periods, or five horizontal periods. The method according to claim 1,
Wherein the polarity of the plurality of data voltages is repeated at intervals of 16 horizontal periods. The method according to claim 1,
Wherein polarities of the data voltages output to the data lines adjacent to each other are not equal to each other over two horizontal periods. The method according to claim 1,
The plurality of data lines are driven by grouping the four data lines,
The polarity of the first positive data voltage applied to the first data line is inverted every three horizontal periods, four horizontal periods, five horizontal periods, and four horizontal periods,
The polarity of the first sub data voltage applied to the second data line is opposite to the polarity of the first positive data voltage,
The polarity of the second positive data voltage applied to the third data line is the same as the polarity inversion period of the first positive data voltage but is inverted at another point in time,
And the polarity of the second sub data voltage applied to the fourth data line is opposite to the polarity of the second positive data voltage. The method according to claim 1,
The plurality of data lines are grouped into six data lines,
The polarity of the first positive data voltage applied to the first data line is inverted every three horizontal periods, four horizontal periods, five horizontal periods, and four horizontal periods,
The polarity of the first sub data voltage applied to the second data line is opposite to the polarity of the first positive data voltage,
The polarity of the second positive data voltage applied to the third data line is the same as the polarity inversion period of the first positive data voltage but is inverted at another point in time,
The polarity of the second sub data voltage applied to the fourth data line is opposite to the polarity of the second positive data voltage,
The polarity of the third positive data voltage applied to the fifth data line is inverted every four horizontal periods,
And the polarity of the third sub data voltage applied to the sixth data line is opposite to the polarity of the third positive data voltage.

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